Semiconductor device

Abstract

An epitaxial layer (2) is formed on a substrate (1). A field effect transistor (3) is formed on the epitaxial layer (2). A drain pad (8) is formed on the epitaxial layer (2). The drain pad (8) is connected to the drain electrode (5) of the field effect transistor (3). The rear surface electrode (13) is formed on the rear surface of the substrate (1) and is connected to the source electrode (6) of the field effect transistor (3). The lead (16) is bonded to the drain pad (8). A cavity (17) is formed in the substrate (1) directly below the drain pad (8). The cavity (17) is not formed directly below the bonding portion of the lead (16).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] In a field-effect transistor, a source pad and a drain pad are formed on the surface side of a substrate, and a back electrode is formed on the back side of the substrate. The back electrode and the source pad are connected by a through-hole. The drain pad of the field-effect transistor used in a high-output amplifier is formed larger because it is connected to multiple leads in order to allow a larger current to flow. A large parasitic capacitance is formed between the drain pad on the surface side and the n-type semiconductor substrate or the back electrode on the back side. In order to reduce this parasitic capacitance, a technology has been proposed to etch the substrate from the back and form a cavity below the drain pad (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-270822.

[0004] However, conventionally, a cavity is formed immediately below the bonding portion of the wire, making it difficult to ensure strength sufficient to withstand the impact of wire bonding. Summary of the Invention

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a semiconductor device that can reduce parasitic capacitance and withstand the impact of wire bonding.

[0006] The semiconductor device disclosed herein is characterized in that it comprises: a substrate; an epitaxial layer formed on the substrate; a field effect transistor formed on the epitaxial layer; a drain pad formed on the epitaxial layer and connected to the drain electrode of the field effect transistor; a back electrode formed on the back side of the substrate and connected to the source electrode of the field effect transistor; and a lead joined to the drain pad, a cavity being formed in the substrate directly below the drain pad, and the cavity being not formed directly below the joining portion of the lead.

[0007] In this disclosure, a cavity is formed in the substrate directly below the drain pad. This reduces parasitic capacitance between the drain pad and the back electrode without reducing the drain pad area. Furthermore, the cavity is not formed directly below the wire bonding portion, thus being able to withstand the impact of wire bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a plan view showing the semiconductor device according to the first embodiment.

[0009] Figure 2 It is along Figure 1 I-II sectional view.

[0010] Figure 3 It is along Figure 1 III-IV cross-sectional view.

[0011] Figure 4 It is along Figure 1 V-VI cross-sectional view.

[0012] Figure 5 3 is a cross-sectional view showing a semiconductor device of Comparative Example 1.

[0013] Figure 6 3 is a cross-sectional view showing a semiconductor device of Comparative Example 2.

[0014] Figure 7 It is a top view showing a semiconductor device according to a second embodiment.

[0015] Figure 8 It is along Figure 7 I-II sectional view.

[0016] Figure 9 It is a top view showing a semiconductor device according to a third embodiment.

[0017] Figure 10 This is a cross-sectional view showing a semiconductor device according to a fourth embodiment.

[0018] Figure 11 This is a cross-sectional view showing a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION

[0019] The semiconductor device according to the embodiment will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and overlapping descriptions may be omitted.

[0020] Implementation Method 1

[0021] Figure 1 This is a plan view showing the semiconductor device according to the first embodiment. Figure 2 It is along Figure 1 I-II sectional view. Figure 3 It is along Figure 1 III-IV cross-sectional view. Figure 4 It is along Figure 1 V-VI cross-sectional view.

[0022] An epitaxial layer 2 is formed on a substrate 1. Substrate 1 is a semi-insulating substrate composed of GaAs, SiC, InP, sapphire, GaN, or diamond. The epitaxial layer 2 is made of, for example, GaAs, GaN, or InP. However, substrate 1 may also be an n-type semiconductor substrate composed of, for example, n-type silicon. In this case, epitaxial layer 2 is also composed of silicon.

[0023] Field effect transistor 3 is formed on epitaxial layer 2. Field effect transistor 3 includes a plurality of gate electrodes 4, a plurality of drain electrodes 5, and a plurality of source electrodes 6. Each gate electrode 4 is arranged between adjacent drain electrodes 5 and source electrodes 6.

[0024] A gate pad 7, a drain pad 8, and a source pad 9 are formed on the epitaxial layer 2. The gate pad 7 is connected to the plurality of gate electrodes 4 via a gate wiring 10. The drain pad 8 is connected to the plurality of drain electrodes 5 via an air bridge wiring 11. The source pad 9 is connected to the plurality of source electrodes 6 via an air bridge wiring 12 that crosses the gate wiring 10.

[0025] Back electrode 13 is formed on the back surface of substrate 1. Back electrode 13 is connected to source pad 9 via through-hole 14 that penetrates substrate 1 and epitaxial layer 2. Wire 15 is bonded to gate pad 7. Multiple wires 16 are bonded to drain pad 8. The bond width of wires 15 and 16 is 50 to 60 μm.

[0026] Substrate 1 is etched from the back side, forming multiple cavities 17 in substrate 1 and epitaxial layer 2 directly below drain pad 8. Each cavity 17 has a width of approximately 80 μm. Cavities 17 are not formed directly below the bonding portions of leads 16.

[0027] Next, the effects of this embodiment will be described in comparison with Comparative Examples 1 and 2. Figure 5 1 is a cross-sectional view showing a semiconductor device of Comparative Example 1. In Comparative Example 1, a cavity 17 is formed immediately below the bonding portion of the wire 16. Therefore, it is difficult to ensure strength to withstand the impact of wire bonding. Figure 6 This is a cross-sectional view of a semiconductor device according to Comparative Example 2. In Comparative Example 2, substrate 1 does not have cavity 17, and a portion of back electrode 13 is removed directly below drain pad 8. However, since the semiconductor device is mounted on package GND 18, parasitic capacitance occurs between drain pad 8 and package GND 18. Therefore, even if a portion of back electrode 13 is removed, the parasitic capacitance remains virtually unchanged.

[0028] In contrast, in this embodiment, a cavity 17 is formed in substrate 1 directly below drain pad 8. The interior of cavity 17 is air or a vacuum, and the dielectric constant of the interior of cavity 17 is lower than that of substrate 1. Therefore, the parasitic capacitance between drain pad 8 and back electrode 13 can be reduced without reducing the area of ​​drain pad 8.

[0029] Furthermore, cavity 17 is not formed directly below the bonded portion of wire 16. Therefore, the thinner drain pad 8 above cavity 17 is not mechanically or physically damaged, and can withstand the impact of wire bonding. Furthermore, even if a portion of the lead material is present above cavity 17, resulting from flattening during wire bonding, drain pad 8 above cavity 17 will not be damaged.

[0030] Furthermore, etching reaches the back surface of drain pad 8, forming cavity 17 not only in substrate 1 but also in epitaxial layer 2. This further reduces parasitic capacitance. However, even with a relatively thin epitaxial layer 2 remaining, parasitic capacitance can be sufficiently reduced.

[0031] Implementation Method 2

[0032] Figure 7 It is a top view showing a semiconductor device according to a second embodiment. Figure 8 It is along Figure 7 Cross-sectional view taken along line I-II. Drain pad 8 is separated into multiple pads by slit 19. Wire 16 crosses slit 19 and is bonded to drain pad 8. Slit 19 is filled with air or a vacuum. This ensures substrate strength for wire bonding and reduces parasitic capacitance between drain pad 8 and back electrode 13. The remaining structure and effects are the same as those of embodiment 1.

[0033] Implementation 3

[0034] Figure 9 This is a top view of a semiconductor device according to Embodiment 3. In Embodiment 2, drain pad 8 is separated into multiple pads. Therefore, multiple probes are required to probe drain pad 8 during electrical characteristic evaluation or wafer testing during wafer processing. In contrast, in this embodiment, the multiple pads of drain pad 8 separated by slit 19 are interconnected by thin wiring 20. This allows probing of drain pad 8 with a single probe, facilitating testing. Other configurations and effects are the same as those of Embodiment 2.

[0035] Implementation 4

[0036] Figure 10 This is a cross-sectional view showing a semiconductor device according to a fourth embodiment. Figure 7 Each drain pad 8 separated by slits 19 has a base portion 8a and a protrusion 8b formed on the outer periphery of base portion 8a. Base portion 8a and protrusion 8b are formed together by Au plating.

[0037] The lead 16 is joined to the protrusion 8b arranged on both sides of the slit 19. The height of the slit 19 is about 10 μm in the second embodiment and about 15 μm in the present embodiment. Therefore, the height of the slit 19 can be increased. The parasitic capacitance is mainly formed by connecting the capacitor of the slit 19 portion in series with the capacitor of the substrate 1 portion. The dielectric constant of the slit 19 is about 1 / 10 of the dielectric constant of the substrate 1, so a significant effect of reducing the capacitance can be expected by only slightly increasing the height of the slit 19. In addition, since only the outer periphery of the pad is thickened, the amount of Au material can be reduced compared to the case where the entire pad is thickened.

[0038] Furthermore, if protrusion 8b is formed simultaneously with the formation of air bridge wiring 11 connecting drain electrode 5 to drain pad 8, plating time can be shortened. In this case, the thickness of the material of protrusion 8b and air bridge wiring 11 in the portion not crushed by wire bonding is the same. Other structures and effects are the same as those of Embodiments 2 or 3.

[0039] Implementation 5

[0040] Figure 11 This is a cross-sectional view showing a semiconductor device according to Embodiment 5. Figure 7 1-2 cross-sectional view. Back electrode 13 is formed on the entire back surface of substrate 1. For example, a wafer-shaped metal plate can be pressed onto the back surface of wafer-shaped substrate 1 using Au particles to form back electrode 13. Back electrode 13 blocks cavity 17, thereby preventing conductive resin or solder from entering cavity 17 during installation. Other structures and effects are the same as those of embodiments 1-4.

[0041] Description of Reference Numerals

[0042] 1…substrate; 2…epitaxial layer; 3…field-effect transistor; 5…drain electrode; 6…source electrode; 8…drain pad; 8a…base portion; 8b…protrusion; 11…air bridge wiring; 13…back electrode; 16…lead; 17…void; 19…slit; 20…wiring.

Claims

1. A semiconductor device, characterized in that: have: substrate; an epitaxial layer formed on the substrate; A field effect transistor formed in the epitaxial layer; a drain pad formed on the epitaxial layer and connected to the drain electrode of the field effect transistor; a back electrode formed on the back side of the substrate and connected to the source electrode of the field effect transistor; as well as a lead wire bonded to the drain pad, A cavity is formed in the substrate directly below the drain pad. The cavity is not formed directly below the bonding portion of the lead.

2. The semiconductor device according to claim 1, wherein: The cavity is formed in the substrate and the epitaxial layer.

3. The semiconductor device according to claim 1 or 2, characterized in that: The drain pad is separated into a plurality of pads by a slit, The lead wire crosses the slit and is bonded to the drain pad.

4. The semiconductor device according to claim 3, wherein: The plurality of pads are connected to each other through wirings.

5. The semiconductor device according to claim 3 or 4, characterized in that: Each of the plurality of pads has a base portion and a protrusion formed on an outer peripheral portion of the base portion. The lead wires are joined to the protrusions disposed on both sides of the slit.

6. The semiconductor device according to claim 5, wherein: further comprising an air bridge wiring connecting the drain electrode and the drain pad, The protrusion portion that is not crushed by wire bonding has the same thickness as the material of the air bridge wiring.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The back electrode blocks the void.

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