Semiconductor device

Abstract

A semiconductor device includes: a first semiconductor element having, in one surface thereof, a pixel region in which a plurality of pixels are arranged; a second semiconductor element mounted in a region outside the pixel region of the one surface, and having a first circuit electrically connected to the pixel; and a third semiconductor element mounted on an opposite side of the second semiconductor element from the first semiconductor element, and having a second circuit electrically connected to the pixel.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Patent Document 1 discloses a semiconductor device as a front-type (front-illuminated) solid-state imaging device. In this semiconductor device, a semiconductor chip is bonded to a semiconductor substrate via bump electrodes. A lens material is formed in an area of ​​the semiconductor substrate outside the area where the bump electrodes are formed. A photoelectric conversion element is arranged on the semiconductor substrate in the area where the lens material is formed. The semiconductor chip also includes peripheral circuitry for processing signals from the photoelectric conversion element. List of citations Patent Literature

[0003] Patent Document 1: Japanese Unexamined Patent Application No. 2016-163011 Summary of the Invention

[0004] In the semiconductor device disclosed in Patent Document 1, the expansion of the light-receiving area where the photoelectric conversion element is arranged often makes it difficult to maintain sufficient packaging area for the semiconductor chip on the semiconductor substrate. Therefore, in semiconductor devices such as those used to construct solid-state imaging devices, achieving a higher packaging density for the semiconductor chips is desired.

[0005] A semiconductor device according to a first embodiment of the present invention includes: a first semiconductor element including a pixel area on one surface of which a plurality of pixels are arranged; a second semiconductor element packaged in an area different from the pixel area on the one surface and including a first circuit electrically connected to the pixels; and a third semiconductor element packaged on the second semiconductor element on a side opposite to the first semiconductor element and including a second circuit electrically connected to the pixels.

[0006] In the semiconductor device according to the second embodiment of the present invention, the thickness of the semiconductor substrate of the second semiconductor element is thinner than the thickness of the semiconductor substrate in the same direction of the third semiconductor element in the semiconductor device according to the first embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a longitudinal sectional structural diagram of a main part of a semiconductor device according to a first embodiment of the invention. Figure 2 yes Figure 1 The planar structure of the semiconductor device shown. Figure 3 1 is a cross-sectional view showing the first step of each step of the method for manufacturing a semiconductor device according to the first embodiment. Figure 4 This is a cross-sectional view of the second step. Figure 5 This is a cross-sectional view of the third step. Figure 6 This is a cross-sectional view of the fourth step. Figure 7 This is a cross-sectional view of the fifth step. Figure 8 This is a cross-sectional view of the sixth step. Figure 9 is a semiconductor device according to a second embodiment of the present invention. Figure 1 Corresponding longitudinal cross-sectional structural diagram. Figure 10 yes Figure 9 The semiconductor device shown is Figure 2 The corresponding plan view. Figure 11 is a semiconductor device according to a third embodiment of the present invention. Figure 2 The corresponding plan view. Figure 12 is a semiconductor device according to a fourth embodiment of the present invention. Figure 1 Corresponding longitudinal cross-sectional structural diagram. Figure 13 yes Figure 12 The semiconductor device shown is Figure 2 The corresponding plan view. Figure 14 is a semiconductor device according to a fifth embodiment of the present invention. Figure 2 The corresponding plan view. Figure 15 is a semiconductor device according to a sixth embodiment of the present invention. Figure 2 The corresponding plan view. Figure 16 is a semiconductor device according to a seventh embodiment of the present invention. Figure 1 Corresponding longitudinal cross-sectional structural diagram. Figure 17 is a semiconductor device according to an eighth embodiment of the present invention. Figure 1 Corresponding longitudinal cross-sectional structural diagram. Figure 18 is a semiconductor device according to a ninth embodiment of the present invention. Figure 1 Corresponding longitudinal cross-sectional structural diagram. Figure 19 is a system configuration diagram of a semiconductor device according to a tenth embodiment of the present invention. Figure 20 is a system configuration diagram of a semiconductor device according to an eleventh embodiment of the present invention. Figure 21 is a schematic perspective view of a semiconductor device according to a twelfth embodiment of the present invention. Figure 22 is a system configuration diagram of a semiconductor device according to a thirteenth embodiment of the present invention. Figure 23 yes Figure 22 The semiconductor device shown is Figure 21 Corresponding schematic stereogram. Figure 24 is a block diagram showing an example of a schematic configuration of a vehicle control system. Figure 25 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0008] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 1. First Implementation Plan The first embodiment describes a first example of applying this technology to a semiconductor device. In the first embodiment, the semiconductor device forms a back-illuminated solid-state imaging device. Furthermore, the first embodiment describes the longitudinal cross-sectional structure, planar structure, and manufacturing method of the semiconductor device. 2. Second Implementation Plan The second embodiment explains a second example in which the package structure of the semiconductor element is changed in the semiconductor device according to the first embodiment. 3. Third Implementation Plan The third embodiment explains a third example of changing the package layout of semiconductor elements in the semiconductor device according to the second embodiment. 4. Fourth Implementation Plan The fourth embodiment explains a fourth example in which the package structure of the semiconductor element is changed in the semiconductor device according to the second embodiment. 5. Fifth Implementation Plan The fifth embodiment explains a fifth example of changing the package layout of semiconductor elements in the semiconductor device according to the first embodiment. 6. Sixth Implementation Plan The sixth embodiment explains a sixth example of changing the package layout of semiconductor elements in the semiconductor device according to the fifth embodiment. 7. Seventh Implementation Plan The seventh embodiment explains a seventh example in which a semiconductor element is further added to the semiconductor device according to the first embodiment. 8. Eighth Implementation Plan The eighth embodiment describes an eighth example in which the semiconductor device according to the first embodiment is applied to a front-illuminated solid-state imaging device. 9. Ninth Implementation Plan The ninth embodiment explains a ninth example in which the package structure of the semiconductor element is changed in the semiconductor device according to the first embodiment. 10. Tenth Implementation Plan The tenth embodiment explains an optimal system configuration of the semiconductor device according to the second embodiment. 11. Eleventh Implementation Plan The eleventh embodiment explains a first application example of the system configuration of the semiconductor device according to the tenth embodiment. 12. Twelfth Implementation Plan The twelfth embodiment explains a second application example of the system configuration of the semiconductor device according to the tenth embodiment. 13. Thirteenth Implementation Plan The thirteenth embodiment explains a third application example of the system configuration of the semiconductor device according to the tenth embodiment. 14. Application Examples of Mobile Objects Application Example An example in which the present technology is applied to a vehicle control system as an example of a mobile body control system is described. 15. Other Implementation Options

[0009] <1. First Implementation Plan> Reference Figures 1 to 8 A semiconductor device 10 according to a first embodiment of the present invention will be described.

[0010] For convenience, the arrow X direction, as shown in the figures, indicates one planar direction of the semiconductor device 10 placed on a plane. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. Furthermore, the arrow Z direction indicates an upward direction perpendicular to the arrow X and arrow Y directions. That is, the arrow X, arrow Y, and arrow Z directions completely coincide with the X-axis, Y-axis, and Z-axis directions of the three-dimensional coordinate system, respectively. It should be noted that these directions are respectively illustrated to help understand the description and are not intended to limit the directions used in the present technology.

[0011] [Structure of Semiconductor Device 10] (1) Overall Structure of Semiconductor Device 10 Figure 1 An example of a longitudinal cross-sectional configuration of the semiconductor device 10 according to the first embodiment is shown. Figure 2 Shown Figure 1 An example of a planar configuration of the semiconductor device 10 is shown. like Figure 1 and Figure 2 As shown, a semiconductor device 10 according to the first embodiment constitutes a back-illuminated solid-state imaging device. To explain this in more detail, semiconductor device 10 is configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. Semiconductor device 10 includes, as main components, a first semiconductor element 1, a second semiconductor element 2, and a third semiconductor element 3.

[0012] (2) Structure of the first semiconductor element 1 like Figure 1 and Figure 2 As shown, the first semiconductor element 1 includes a pixel region 110 on the front side 1A in the arrow Z direction, where a plurality of pixels 100 are arranged. The pixels 100 are arranged, for example, in the arrow X direction and the arrow Y direction. Here, the front side 1A corresponds to "one surface of the first semiconductor element" according to the present technology.

[0013] (2-1) Structure of Supporting Substrate 101 and Semiconductor Substrate 103 To explain this in detail, the first semiconductor element 1 includes a support substrate 101 and a semiconductor substrate 103 . The support substrate 101 is formed of, for example, a single crystal silicon (Si) substrate. The side of the support substrate 101 opposite to the direction of arrow Z is the back surface 1B of the first semiconductor element 1 opposite to the front surface 1A. The semiconductor substrate 103 is stacked on the support substrate 101 in the direction indicated by the arrow Z. The semiconductor substrate 103 is formed of, for example, a single crystal silicon substrate and has a thickness of, for example, 2 μm or more and 13 μm or less. The semiconductor substrate 103 is stacked on the support substrate 101 via an insulator whose reference numeral is omitted. The insulator is formed of a silicon nitride (SiN) film.

[0014] like Figure 2 As shown, support substrate 101 and semiconductor substrate 103 are each formed into a rectangular shape when viewed in the direction of arrow Z (hereinafter referred to as "in plan view") and are formed to have the same planar area (planar dimensions). Specifically, first semiconductor element 1 is formed into semiconductor chips processed as wafers (dies) by dicing a semiconductor wafer during the manufacturing process. Here, the planar shape of first semiconductor element 1 is a rectangle having its longer side in the direction of arrow X and its shorter side in the direction of arrow Y. Here, “as viewed from the thickness direction of the first semiconductor element 1 ” according to the present technology is equivalent to “in a plan view when viewed in the arrow Z direction”.

[0015] (2-2) Structure of Pixel 100 and Pixel Region 110 like Figure 1 and Figure 2 As shown, the pixel region 110 is provided in the central portion of the front surface 1A of the first semiconductor element 1. Each pixel 100 constituting the pixel region 110 includes at least a photoelectric conversion element 107. Each pixel 100 further includes an optical filter 105 and an optical lens 106.

[0016] Although the detailed structure is omitted, Figure 1 As shown, the photoelectric conversion element 107 is provided in the semiconductor substrate 103. The photoelectric conversion element 107 converts incident light L incident in the direction of arrow Z into electric charges. Here, the photoelectric conversion element 107 is formed of, for example, a photodiode.

[0017] The optical filter 105 is provided on the front surface 1A side of the semiconductor substrate 103 via the insulator 104. The optical filter 105 includes three color filters, one for each pixel 100. Specifically, the optical filter 105 includes a red filter (R), a green filter (G), and a blue filter (B) (not shown). The red filter (R) allows light in the red wavelength band to pass through. The green filter (G) allows light in the green wavelength band to pass through. The blue filter (B) allows light in the blue wavelength band to pass through. The optical filter 105 is formed, for example, from a resin material containing a dye.

[0018] The optical lens 106 is provided on the side of the optical filter 105 opposite the photoelectric conversion element 107. In other words, the optical lens 106 is provided on the front surface 1A side of the optical filter 105. Although not shown in the plan view, the optical lens 106 is formed into a circular shape for each pixel 100. Furthermore, when viewed in the direction of arrow Y (hereinafter referred to as "in a side view"), the optical lens 106 is formed into a curved shape that curves toward the light incident side for each pixel 100, thereby converging the incident light L on the photoelectric conversion element 107. The optical lens 106 is formed as a so-called on-chip lens, and is formed for each pixel 100 or integrally across a plurality of pixels 100. The optical lens 106 is formed of, for example, a transparent resin material.

[0019] (2-3) Configuration of Pixel Circuit 108 like Figure 1 As shown, the pixel circuit 108 is electrically connected to one pixel 100 or a plurality of pixels 100 via a transfer transistor not shown. Although the detailed circuit configuration of the pixel circuit 108 and the illustration and description of the vertical cross-sectional configuration of the pixel circuit 108 in the side view are omitted, the pixel circuit 108 includes a plurality of transistors Tr. For example, the pixel circuit 108 includes transistors Tr used as reset transistors, amplifier transistors, selection transistors, etc. The transistors Tr constituting the pixel circuit 108 , including the transfer transistor, are each formed of an n-channel conductive insulated gate field effect transistor (IGFET), for example. The pixel circuit 108 is provided in the main surface portion of the semiconductor substrate 103 on the support substrate 101 side.

[0020] (2-4) Structure of the Wiring Layer 102 The wiring layer 102 is provided on the support substrate 101 side of the semiconductor substrate 103. In other words, the wiring layer 102 is provided between the semiconductor substrate 103 and the support substrate 101. For example, wiring 1021 and wiring 1022 are formed in multiple layers in the wiring layer 102. Wiring 1021 and wiring 1022 connect multiple transistors Tr. Multiple transistors Tr constitute the pixel circuit 108. For example, a metal wiring material such as copper (Cu) is used for wiring 1021. For example, a metal wiring material such as an aluminum (Al)-Cu alloy is used for wiring 1022. Furthermore, plug wiring 1023 is used to connect wiring 1021 and wiring 1022. For example, a metal wiring material such as tungsten (W) or an Al-Cu alloy is used for plug wiring 1023. Although shown in a simplified manner, the insulator 1025 is formed between the wirings 1021 having multiple layers, for example, and between the wiring 1021 and the wiring 1022. The insulator 1025 is formed of, for example, a silicon oxide (SiO2) film.

[0021] (2-5) Structure of the Packaging Area 120 like Figure 1 and Figure 2 As shown, packaging region 120 is provided in the peripheral portion of front surface 1A of first semiconductor element 1 . The peripheral portion surrounds pixel region 110 provided in the central portion of front surface 1A of first semiconductor element 1 . Second semiconductor element 2 and third semiconductor element 3 are packaged in packaging region 120 .

[0022] This will be described in detail. A plurality of terminals 1042 are provided in the packaging region 120. The terminals 1042 are provided in the front portion of the insulator 104 on the side indicated by the arrow Z. The terminals 1042 are configured to mechanically connect to the second semiconductor element 2 for packaging and to electrically connect the pixels 100 of the first semiconductor element 1 to the external terminals of the first circuit 202 of the second semiconductor element 2. Furthermore, the terminals 1042 are also configured to electrically connect the pixels 100 to the external terminals of the second circuit 302 of the third semiconductor element 3. The terminal 1042 is electrically connected to the wiring 1021 of the wiring layer 102 through the wiring 1041 and the through wiring 1031. The wiring 1041 is provided closer to the semiconductor substrate 103 than the terminal 1042. The through wiring 1031 penetrates the semiconductor substrate 103 in the thickness direction. For example, a metal wiring material such as Cu is used for the terminal 1042, the wiring 1041, and the through wiring 1031. In addition, although not described in detail, the insulator 104 is provided between the terminal 1042 and the wiring 1041. The insulator 104 serves as an interlayer insulating film of the packaging region 120. The insulator 104 is formed of, for example, a SiO2 film. Here, the terminal 1042 corresponds to the “first terminal” according to the present technology.

[0023] In practice, the pixel 100 is electrically connected to the first circuit 202 of the second semiconductor element 2 via the pixel circuit 108. The term "electrically connecting the first circuit to the pixel" is used to represent both "indirectly electrically connecting the pixel 100 to the first circuit 202 via the pixel circuit 108" and "directly electrically connecting the pixel 100 to the first circuit 202."

[0024] In addition, if Figure 1 As shown, in the area around the pixel region 110, a terminal 1043 for inspection is provided along the outer edge of the first semiconductor element 1. The terminal 1043 is used for, for example, an electrical characteristic inspection performed during or after the manufacturing steps of the semiconductor device 10. During the inspection, an inspection probe contacts the terminal 1043. The terminal 1043 is formed of, for example, a metal wiring material similar to the wiring 1022 of the wiring layer 102 .

[0025] (3) Structure of the Second Semiconductor Element 2 like Figure 1 and Figure 2 As shown, the second semiconductor element 2 is packaged in the packaging region 120 on the front surface 1A side of the first semiconductor element 1. That is, the second semiconductor element 2 is packaged in a region different from the pixel region 110 of the first semiconductor element 1. The second semiconductor element 2 includes a semiconductor substrate 201 and a first circuit 202 .

[0026] (3-1) Structure of the Semiconductor Substrate 201 Like the semiconductor substrate 103 of the first semiconductor element 1, the semiconductor substrate 201 is formed of, for example, a single crystal silicon substrate. The semiconductor substrate 201 is thinner than the semiconductor substrate 103 of the first semiconductor element 1 and thinner than the semiconductor substrate 301 of the third semiconductor element 3 (described later). The thickness of the semiconductor substrate 201 is, for example, 10 μm or less. The thickness of the semiconductor substrate 201 is set to be between 1 μm and 10 μm.

[0027] (3-2) Configuration of the First Circuit 202 like Figure 1 As shown, the first circuit 202 is provided on the arrow Z direction side (the third semiconductor element 3 side) and the front surface 2A side of the semiconductor substrate 201. The first circuit 202 is indirectly electrically connected to the pixels 100 of the pixel region 110 via the pixel circuit 108. The first circuit 202 includes one or more logic circuits selected from, for example, a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, an output circuit, and a control circuit, which constitute the peripheral circuits of a back-illuminated solid-state imaging device. Like the pixel circuit 108, the first circuit 202 is configured to include transistors Tr, resistors, capacitors, and the like. Note that in the second circuit 302 provided in the third semiconductor element 3 (described later), a logic circuit similar to that of the first circuit 202 may be separated, or the second circuit 302 may include other logic circuits not selected in the first circuit 202.

[0028] Although a detailed description of the logic circuit's circuit configuration is omitted, the control circuit receives an input clock and data indicating operating modes, among other things, and also outputs data such as internal information related to the solid-state imaging device. Specifically, the control circuit generates control signals or clock signals that serve as a reference for the operation of the vertical drive circuit, column signal processing circuit, horizontal drive circuit, and other circuits based on the vertical synchronization signal, horizontal synchronization signal, and master clock. These signals are then input to the vertical drive circuit, column signal processing circuit, horizontal drive circuit, and other circuits.

[0029] The vertical drive circuit includes, for example, a shift register. It selects a pixel drive line and supplies a pulse suitable for driving the pixel 100 to the selected pixel drive line. Pixels 100 are driven in rows. That is, the vertical drive circuit selectively scans each pixel 100 in the pixel area 110 in a vertical direction, row by row. Signal charges generated based on the amount of incident light L received by the photoelectric conversion element 107 of each pixel 100 are supplied as pixel signals to the column signal processing circuit via vertical signal lines.

[0030] For example, a column signal processing circuit is provided for each column of pixels 100. The column signal processing circuit performs signal processing, such as noise removal, on the signals output from a row of pixels 100 for each pixel column. Specifically, the column signal processing circuit performs signal processing such as CDS (correlated double sampling), signal amplification, or analog-to-digital conversion. CDS is suitable for removing fixed pattern noise inherent in pixels 100. A horizontal selection switch (not shown) is connected to the output stage of the column signal processing circuit between the column signal processing circuit and the horizontal signal line.

[0031] The horizontal drive circuit includes, for example, a shift register, and sequentially selects each column signal processing circuit by sequentially outputting horizontal scanning pulses, and outputs pixel signals from each column signal processing circuit to a horizontal signal line.

[0032] The output circuit performs signal processing on the signals sequentially supplied from the column signal processing circuits via horizontal signal lines and outputs the resulting signals. For example, the output circuit may only perform buffering in some cases, and in other cases perform black level adjustment, column deviation correction, and various types of digital signal processing. The logic circuit also includes input / output terminals (not shown). These terminals exchange signals between the back-illuminated solid-state imaging device (semiconductor device 10) and the outside world. Although not shown, these terminals have the same structure as terminals 1043 and are located on the front surface 1A side of the first semiconductor element 1.

[0033] (3-3) Structure of Wiring Layer 203 and Wiring Layer 204 The wiring layer 203 is provided on the front surface 2A side of the semiconductor substrate 201. For example, wiring 2031 and terminals 2032 having multiple layers are formed in the wiring layer 203. The wiring 2031 and terminals 2032 connect, for example, logic circuits together, and connect the logic circuits and the pixel circuit 108 together. For example, a metal wiring material such as Cu is used for the wiring 2031 and the terminal 2032. In addition, a plug wiring 2033 is formed on the wiring 2031. The plug wiring 2033 is electrically connected to the transistor Tr of the first circuit 202. For example, a metal wiring material such as W is used for the plug wiring 2033.

[0034] Although shown in a simplified manner, the insulator 2035 is formed between the wirings 2031 having multiple layers, for example, and between the wiring 2031 and the wiring 2032. The insulator 2035 is formed of, for example, a SiO2 film.

[0035] The front surface of the terminal 2032 is exposed from the insulator 2035. The terminal 3032 of the third semiconductor element 3 described later is bonded to the terminal 2032. That is, the terminal 2032 enables the third semiconductor element 3 to be packaged, and is electrically connected to the terminal 3032. Here, the terminal 2032 corresponds to the “third terminal” according to the present technology. In addition, the terminal 3032 corresponds to the “fourth terminal” according to the present technology.

[0036] Meanwhile, the wiring layer 204 is provided on the back surface 2B side of the semiconductor substrate 201. For example, a plurality of layers of wiring 2041 and terminals 2042 are formed in the wiring layer 204. The wiring 2041 and the terminals 2042 connect, for example, logic circuits together, and connect the logic circuits and the pixel circuit 108 together. For example, a metal wiring material such as Cu is used for the wiring 2041. Also, for example, a metal wiring material such as an Al-Cu alloy is used for the terminal 2042. In addition, the terminal 2042 is electrically connected to the wiring 2041 via a plug wiring 2043. For example, a metal wiring material such as W is used for the plug wiring 2043. Here, the terminal 2042 corresponds to the “second terminal” according to the present technology.

[0037] Furthermore, a terminal 2044 for inspection is provided in the wiring layer 204 of the second semiconductor element 2. Like the terminal 1043, the terminal 2044 is used for, for example, an electrical characteristic inspection performed during or after the manufacturing steps of the semiconductor device 10. The terminal 2044 is formed of, for example, a metal wiring material similar to that of the terminal 2042 of the wiring layer 204 .

[0038] Although shown in a simplified manner, the insulator 2045 is formed between the wirings 2041 having multiple layers, for example, and between the wirings 2041 and the terminals 2042. The insulator 2045 is formed of, for example, a SiO2 film.

[0039] The wiring 2401 of the wiring layer 204 is electrically connected to the wiring 2031 of the wiring layer 203 through the through wiring 2011. The through wiring 2011 is provided to penetrate the semiconductor substrate 201 of the second semiconductor element 2 in the thickness direction. The through wiring 2011 is formed of a metal wiring material similar to the through wiring 1031, for example. In the second semiconductor element 2 , the semiconductor substrate 201 is formed thin, which enables easy provision of the through wiring 2011 . Here, the through-wiring 2011 corresponds to the “first through-wiring” according to the present technology.

[0040] (3-4) Packaging Method of Second Semiconductor Element 2 like Figure 1As shown, the second semiconductor element 2 is packaged in a face-up manner (in which the first circuit 202 faces the same arrow Z direction) in the packaging region 120 on the front surface 2A side of the first semiconductor element 1 . To explain this in detail, the terminals 2042 of the wiring layer 204 of the second semiconductor element 2 are electrically connected to the terminals 1042 provided in the packaging region 120 of the first semiconductor element 1, and the second semiconductor element 2 is packaged on the first semiconductor element 1. Bump electrodes 5 are used for this packaging. Here, microbump electrodes are used for the bump electrodes 5. For example, a Sn-based solder such as a tin (Sn)-silver (Ag) alloy is used for the bump electrodes 5 .

[0041] like Figure 2 As shown, the second semiconductor element 2 is formed into a rectangular shape in a plan view. The planar area (planar dimensions) of the second semiconductor element 2 is smaller than the planar area (planar dimensions) of the first semiconductor element 1. Furthermore, the second semiconductor element 2 is provided within the front surface 1A of the first semiconductor element 1. In other words, the second semiconductor element 2 is encapsulated in the peripheral portion surrounding the pixel region 110 within the front surface 1A of the first semiconductor element 1. In the present technology, it is sufficient as long as the second semiconductor element 2 is packaged along at least one side of the rectangular first semiconductor element 1. In the first embodiment, a total of two second semiconductor elements 2 are packaged along two sides of the first semiconductor element 1 that are opposite to each other in the arrow Y direction.

[0042] (4) Structure of the Third Semiconductor Element 3 like Figure 1 and Figure 2 As shown, the third semiconductor element 3 is packaged on the front surface 2A side of the second semiconductor element 2. That is, like the second semiconductor element 2, the third semiconductor element 3 is packaged in a packaging region 120 different from the pixel region 110 of the first semiconductor element 1. The third semiconductor element 3 includes a semiconductor substrate 301 and a second circuit 302 .

[0043] (4-1) Structure of Semiconductor Substrate 301 Like semiconductor substrate 103 of first semiconductor element 1, semiconductor substrate 301 is formed of, for example, a single crystal silicon substrate. As described above, semiconductor substrate 301 is thinner than semiconductor substrate 103 of first semiconductor element 1 and thicker than semiconductor substrate 201 of second semiconductor element 2. The thickness of semiconductor substrate 301 is, for example, not less than 100 μm and not more than 800 μm. Here, the thickness of semiconductor substrate 301 is, for example, not less than 100 μm and not more than 400 μm.

[0044] (4-2) Configuration of the Second Circuit 302 like Figure 1 As shown, the second circuit 302 is provided on the side opposite to the direction of arrow Z (on the side of the second semiconductor element 2) and on the front surface 3A side of the semiconductor substrate 301. The second circuit 302 is indirectly electrically connected to the pixels 100 in the pixel region 110 via the pixel circuit 108 or the pixel circuit 108 and the first circuit 202. As described above, the second circuit 302 includes a logic circuit. Like the pixel circuit 108, the second circuit 302 is configured to include a transistor Tr, a resistor, a capacitor, and the like.

[0045] (4-3) Structure of the Wiring Layer 303 The wiring layer 303 is provided on the front surface 3A side of the semiconductor substrate 301. For example, multiple layers of wiring 3031 and terminals 3032 are formed in the wiring layer 303. The wiring 3031 and terminals 3032, for example, connect logic circuits. For example, a metal wiring material such as Cu is used for the wiring 3031 and terminals 3032. Furthermore, a plug wiring 3033 is formed on the wiring 3031. The plug wiring 3033 is electrically connected to the transistor Tr of the second circuit 302. For example, a metal wiring material such as W is used for the plug wiring 3033. Note that, in the first embodiment, no wiring layer is provided on the back surface 2B of the semiconductor substrate 301 .

[0046] Although shown in a simplified manner, the insulator 3035 is formed between the wirings 3031 having multiple layers, for example, and between the wirings 3031 and the terminals 3032. The insulator 3035 is formed of, for example, a SiO2 film.

[0047] The front surface of the terminal 3032 is exposed from the insulator 3035. The terminal 2032 of the second semiconductor element 2 is bonded to the terminal 3032. That is, the terminal 3032 allows the third semiconductor element 3 to be packaged on the second semiconductor element 2 and is electrically connected to the terminal 2032.

[0048] (4-4) Packaging Method of Third Semiconductor Element 3 like Figure 1 As shown, the third semiconductor element 3 is packaged face-down (the front surface 3A provided with the second circuit 302 faces the front surface 2A of the second semiconductor element 2 provided with the first circuit 202 ). To explain this in detail, the terminal 3032 electrically connected to the second circuit 302 of the third semiconductor element 3 is bonded to the terminal 2032 electrically connected to the first circuit 202 of the second semiconductor element 2. Here, for example, Cu is used for each of the terminals 2032 and 3032, thus forming a Cu-Cu bond. That is, the terminals 2032 and 3032 are mechanically and electrically connected to each other.

[0049] like Figure 2 As shown, the planar shape of the third semiconductor element 3 is formed into a rectangular shape identical to the planar shape of the second semiconductor element 2 in a plan view. Furthermore, the planar area (planar dimensions) of the third semiconductor element 3 is identical to the planar area (planar dimensions) of the second semiconductor element 2. Furthermore, the third semiconductor element 3 is packaged at the same packaging position as the second semiconductor element 2. That is, in the first embodiment, the third semiconductor element 3 is packaged on each of the two second semiconductor elements 2.

[0050] [Method of Manufacturing Semiconductor Device 10] Next, a method for manufacturing the semiconductor device 10 according to the first embodiment will be described. Specifically, a method for manufacturing the second semiconductor element 2 and the third semiconductor element 3 packaged on the first semiconductor element 1 will be described. Figures 3 to 8 An example of a step cross section for each step for explaining the method for manufacturing the semiconductor device 10 is shown.

[0051] First, if Figure 3 As shown, a semiconductor substrate 301 of the third semiconductor element 3 and a semiconductor substrate 201 of the second semiconductor element 2 are formed. Each of the semiconductor substrate 301 and the semiconductor substrate 201 is in a semiconductor wafer state. The second circuit 302 is formed on the front surface 3A side of the semiconductor substrate 301 , and the wiring layer 303 is also formed. The terminal 3032 is formed on the uppermost layer of the wiring layer 303 . On the other hand, the first circuit 202 is formed on the front surface 2A side of the semiconductor substrate 201, and further formed is a wiring layer 203. On the uppermost layer of the wiring layer 203, a terminal 2032 is formed.

[0052] like Figure 4 As shown, the front surface 3A of the semiconductor substrate 301 and the front surface 2A of the semiconductor substrate 201 are opposed to each other, and the terminal 2032 is bonded to the terminal 3032. That is, the second semiconductor element 2 is packaged on the third semiconductor element 3.

[0053] like Figure 5 As shown, the back surface 2B of the semiconductor substrate 201 of the second semiconductor element 2 is polished to thin the semiconductor substrate 201 .

[0054] like Figure 6 As shown, a wiring layer 204 is formed on the back surface 2B side of the semiconductor substrate 201. Terminals 2042 and 2044 are formed on the uppermost layer of the wiring layer 204. As described above, the terminal 2042 is formed as a terminal for packaging the second semiconductor element 2 on the first semiconductor element 1 (see Figure 1 ). Meanwhile, the terminal 2044 is formed as a terminal for inspection.

[0055] like Figure 7 As shown, the bump electrode 5 is formed on the terminal 2042. On the other hand, the bump electrode 5 is not formed on the terminal 2044.

[0056] like Figure 8 As shown, semiconductor substrate 301 and semiconductor substrate 201 are cut into individual pieces (cut into semiconductor chips) by dicing. Thus, third semiconductor element 3 is formed from semiconductor substrate 301 including wiring layer 303, and second semiconductor element 2 is formed from semiconductor substrate 201 including wiring layers 203 and 204. In this step, third semiconductor element 3 is packaged on second semiconductor element 2.

[0057] Then, as mentioned above Figure 1 and Figure 2 As shown, the second semiconductor element 2 on which the third semiconductor element 3 is packaged is packaged in the packaging region 120 of the first semiconductor element 1 , thereby completing the method for manufacturing the semiconductor device 10 according to the first embodiment and completing the semiconductor device 10 .

[0058] [Function and Effect] As mentioned above, Figure 1 and Figure 2 As shown, the semiconductor device 10 according to the first embodiment includes a first semiconductor element 1 , a second semiconductor element 2 , and a third semiconductor element 3 . First semiconductor element 1 includes a pixel region 110 on front surface 1A. Pixel region 110 includes a plurality of pixels 100. Second semiconductor element 2 is packaged in a region of front surface 1A different from pixel region 110 and includes first circuit 202 electrically connected to pixels 100. Here, the region different from pixel region 110 is package region 120. Third semiconductor element 3 is packaged on second semiconductor element 2 on the side opposite to first semiconductor element 1 and includes second circuit 302 electrically connected to pixels 100. In the semiconductor device 10 having such a configuration, the second semiconductor element 2 and the third semiconductor element 3 are stacked in a region different from the pixel region 110. This makes it possible to increase the packing density in the thickness direction of the first semiconductor element 1. Therefore, it is possible to increase the packing density of the peripheral circuits including the first circuit 202 and the second circuit 302 while expanding the pixel region 110.

[0059] In addition, in the semiconductor device 10, as Figure 2 As shown, when viewed along the thickness direction of the first semiconductor element 1 (in a plan view), the plan area of ​​each of the second semiconductor element 2 and the third semiconductor element 3 is smaller than the plan area of ​​the first semiconductor element 1 . Therefore, the pixel region 110 of the first semiconductor element 1 can be further expanded.

[0060] In addition, in the semiconductor device 10, as Figure 2 As shown, each of the second semiconductor element 2 and the third semiconductor element 3 is provided within the front surface 1A of the first semiconductor element 1 when viewed in the thickness direction of the first semiconductor element (in a plan view). Therefore, it is possible to increase the packaging density while expanding the pixel region 110 in the front surface 1A of the first semiconductor element 1 .

[0061] In addition, in the semiconductor device 10, as Figure 1 As shown, the thickness of the semiconductor substrate 201 of the second semiconductor element 2 is thinner than the thickness of the semiconductor substrate 301 of the third semiconductor element 3 along the same direction. Furthermore, in the semiconductor device 10, the second semiconductor element 2 includes a through-wiring (first through-wiring) 2011 that penetrates along the thickness direction and electrically connects the pixel 100 and the first circuit 202 to each other. To explain this in detail, the through-wiring 2011 is formed so as to penetrate the semiconductor substrate 201 of the second semiconductor element 2 along the thickness direction. In the semiconductor device 10 having such a configuration, the semiconductor substrate 201 of the second semiconductor element 2 is formed thin, which enables easy handling of the semiconductor substrate 201. In the first embodiment, the through wiring 2011 penetrating the semiconductor substrate 201 can be easily formed. Therefore, in the second semiconductor element 2, the wiring layer 203 on the front surface 2A side and the wiring layer 204 on the back surface 2B side of the semiconductor substrate 201 are electrically connected to each other via the through wiring 2011. That is, each of the second semiconductor element 2 and the third semiconductor element 3 can be packaged on the first semiconductor element 1 in a stacked state, which makes it possible to increase the packaging density of the packaging area 120 while expanding the pixel area 110.

[0062] In addition, if Figure 1As shown, the semiconductor device 10 includes a terminal (first terminal) 1042 on the front surface 1A side of the first semiconductor element 1, and a terminal (second terminal) 2042 on the first semiconductor element 1 side of the second semiconductor element 2. The terminal 1042 is electrically connected to the pixel 100. The terminal 2042 is electrically connected to the first circuit 202 or the second circuit 302. In addition, the terminal 2042 is electrically connected to the terminal 1042 via the bump electrode 5. In the semiconductor device 10 having this structure, the second semiconductor element 2 is packaged on the first semiconductor element 1 using the bump electrodes 5. This allows the area occupied by the package region 120 to be reduced compared to the case of packaging using a bonding wire method. Therefore, the packaging density of the package region 120 can be increased while expanding the pixel region 110.

[0063] In addition, if Figure 1 As shown, the semiconductor device 10 includes a terminal (third terminal) 2032 on the third semiconductor element 3 side of the second semiconductor element 2. Terminal 2032 is electrically connected to the first circuit 202. The semiconductor device 10 also includes a terminal (fourth terminal) 3032 on the second semiconductor element 2 side of the third semiconductor element 3. Terminal 3032 is electrically connected to the second circuit 302. Terminal 3032 is opposed to and joined to terminal 2032, and terminals 2032 and 3032 are electrically connected to each other. In the semiconductor device 10 having such a configuration, the third semiconductor element 3 can be packaged within the front surface 2A of the second semiconductor element 2, which reduces the footprint of the package. Therefore, the packaging density of the package area 120 can be increased while expanding the pixel area 110.

[0064] In addition, in the semiconductor device 10, as Figure 1 As shown, the first semiconductor element 1 is constructed as a back-illuminated solid-state imaging device. In the semiconductor device 10 having such a configuration, in the pixels 100 in the pixel region 110 , the incident light L is efficiently absorbed by the photoelectric conversion element 107 , which makes it possible to improve sensitivity characteristics.

[0065] In addition, in the semiconductor device 10, as Figure 1 and Figure 2 As shown, the first circuit 202 of the second semiconductor element 2 and the second circuit 302 of the third semiconductor element 3 are logic circuits. Therefore, it is possible to increase the packaging density of the peripheral circuits in the packaging area 120 while expanding the pixel area 110 .

[0066] Furthermore, in the semiconductor device 10, as Figure 2As shown, the first semiconductor element 1 is formed into a rectangular shape when viewed in the thickness direction (in a plan view). Furthermore, a pixel region 110 is provided in the central portion of the front surface 1A of the first semiconductor element 1, and the second semiconductor element 2 and the third semiconductor element 3 are packaged in a peripheral portion serving as a packaging region 120 along at least one side of the rectangular shape. In the semiconductor device 10 having such a structure, it is possible to increase the packaging density of the peripheral circuits in the packaging region 120 while expanding the pixel region 110 .

[0067] <2. Second Implementation Plan> Reference Figure 9 and Figure 10 A semiconductor device 10 according to a second embodiment of the present invention will be described. Note that, in the second and subsequent embodiments, components that are the same as or substantially the same as those of the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals, and redundant descriptions are omitted.

[0068] [Structure of Semiconductor Device 10] Figure 9 An example of a longitudinal cross-sectional configuration of the semiconductor device 10 according to the second embodiment is shown. Figure 10 Shown Figure 9 An example of a planar configuration of the semiconductor device 10 is shown.

[0069] like Figure 9 and Figure 10 As shown, the semiconductor device 10 according to the second embodiment includes a third semiconductor element 3M including a second circuit 302M in the semiconductor device 10 according to the first embodiment.

[0070] This will be explained in detail. Figure 9 and Figure 10 As shown, the second semiconductor element 2 is packaged in the packaging area 120 along one side of the first semiconductor element 1 in the direction of arrow Y, and the third semiconductor element 3 is packaged on the second semiconductor element 2 (see FIG. Figure 1 and Figure 2 ). As in the first embodiment, the first circuit 202 of the second semiconductor element 2 and the second circuit 302 of the third semiconductor element 3 respectively construct logic circuits.

[0071] Meanwhile, a second semiconductor element 2 is packaged in the package region 120 along the other side of the first semiconductor element 1, opposite to the direction of arrow Y, and a third semiconductor element 3M is packaged on the second semiconductor element 2. As in the first embodiment, the first circuit 202 of the second semiconductor element 2 constitutes a logic circuit. The third semiconductor element 3M includes a second circuit 302M, and the second circuit 302M constitutes a memory circuit. For example, the second circuit 302M is a volatile memory circuit or a nonvolatile memory circuit for accumulating signals obtained in the pixel region 110. Specifically, the second circuit 302M is a shift register that constitutes a vertical drive circuit, a horizontal drive circuit, or the like.

[0072] As with the third semiconductor element 3 of the semiconductor device 10 according to the first embodiment, the third semiconductor element 3M includes a semiconductor substrate 301 and a wiring layer 303. Terminals 3032 are provided in the wiring layer 303. By bonding the terminals 3032 to the terminals 2032 of the second semiconductor element 2 , the third semiconductor element 3M is packaged on the second semiconductor element 2 in a face-down manner.

[0073] Components other than the above-described components are the same or substantially the same as those of the semiconductor device 10 according to the above-described first embodiment.

[0074] [Function and Effect] In the semiconductor device 10 according to the second embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the first embodiment can be obtained.

[0075] Furthermore, the semiconductor device 10 includes a third semiconductor element 3M having a second circuit 302M. In the semiconductor device 10 having such a configuration, the second circuit 302M is a memory circuit, which enables the system configuration of the back-illuminated solid-state imaging device to have a signal accumulation function.

[0076] <3. Third Implementation Plan> Reference Figure 11 A semiconductor device 10 according to a third embodiment of the present invention will be described.

[0077] [Structure of Semiconductor Device 10] Figure 11 An example of a planar configuration of the semiconductor device 10 according to the third embodiment is shown. like Figure 11As shown, the semiconductor device 10 according to the third embodiment includes a third semiconductor element 3M having a second circuit 302M, similar to the semiconductor device 10 according to the second embodiment. To explain this in detail, the second semiconductor element 2 is packaged in the packaging region 120 along one side of the first semiconductor element 1 in the direction of arrow Y, and the third semiconductor element 3M is packaged on the second semiconductor element 2. The first circuit 202 of the second semiconductor element 2 constitutes a logic circuit. The second circuit 302M of the third semiconductor element 3M constitutes a memory circuit.

[0078] Similarly, a second semiconductor element 2 is packaged in the packaging region 120 along the other side of the first semiconductor element 1 opposite to the direction of arrow Y, and a third semiconductor element 3M is packaged on the second semiconductor element 2. The first circuit 202 of the second semiconductor element 2 constitutes a logic circuit. The second circuit 302M of the third semiconductor element 3M constitutes a memory circuit. That is, in the third embodiment, the third semiconductor element 3 is replaced by the third semiconductor element 3M.

[0079] Components other than the above-described components are the same as or substantially the same as those of the semiconductor device 10 according to the second embodiment described above.

[0080] [Function and Effect] In the semiconductor device 10 according to the third embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the second embodiment can be obtained.

[0081] <4. Fourth Implementation Plan> Reference Figure 12 and Figure 13 A semiconductor device 10 according to a fourth embodiment of the present invention will be described.

[0082] [Structure of Semiconductor Device 10] Figure 12 An example of a longitudinal cross-sectional configuration of a semiconductor device 10 according to the fourth embodiment is shown. Figure 13 Shown Figure 12 An example of a planar configuration of the semiconductor device 10 is shown.

[0083] like Figure 12 and Figure 13 As shown, the semiconductor device 10 according to the fourth embodiment has a configuration in which the semiconductor device 10 according to the first embodiment and the semiconductor device 10 according to the second embodiment or the third embodiment are combined.

[0084] This will be explained in detail. Figure 12 and Figure 13As shown, the second semiconductor element 2 is packaged in the packaging region 120 along one side of the first semiconductor element 1 in the direction of arrow Y, and the third semiconductor element 3 is packaged on the second semiconductor element 2. As in the first embodiment, the first circuit 202 of the second semiconductor element 2 and the second circuit 302 of the third semiconductor element 3 each constitute a logic circuit.

[0085] On the other hand, the third semiconductor element 3M is packaged directly and independently in the packaging region 120 along the other side opposite to the arrow Y direction of the first semiconductor element 1. The third semiconductor element 3M includes a second circuit 302M, which constitutes a memory circuit. In the third semiconductor element 3M, the terminal 3032 is mechanically and electrically connected to the terminal 1042 in the package region 120 of the first semiconductor element 1 via the bump electrode 5. The third semiconductor element 3M is packaged in a face-down manner. Here, the third semiconductor element 3M corresponds to the “fifth semiconductor element” according to the present technology. In addition, the second circuit 302M corresponds to the “fourth circuit” according to the present technology.

[0086] Components other than the above-described components are the same or substantially the same as those of the semiconductor device 10 according to any one of the first to third embodiments described above.

[0087] [Function and Effect] In the semiconductor device 10 according to the fourth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the second embodiment or the third embodiment can be obtained.

[0088] <5. Fifth Implementation Plan> Reference Figure 14 A semiconductor device 10 according to a fifth embodiment of the present invention will be described.

[0089] [Structure of Semiconductor Device 10] Figure 14 An example of a planar configuration of the semiconductor device 10 according to the fifth embodiment is shown.

[0090] like Figure 14 As shown, the semiconductor device 10 according to the fifth embodiment has a configuration in which the semiconductor device 10 according to the first embodiment and the semiconductor device 10 according to the fourth embodiment are combined.

[0091] This will be explained in detail. Figure 14As shown, the second semiconductor element 2 is packaged in the packaging region 120 along one side of the first semiconductor element 1 in the direction of arrow Y, and the third semiconductor element 3 is packaged on the second semiconductor element 2. As in the first embodiment, the first circuit 202 of the second semiconductor element 2 and the second circuit 302 of the third semiconductor element 3 each constitute a logic circuit.

[0092] On the other hand, a second semiconductor element 2 is packaged in a packaging region 120 along the other side of the first semiconductor element 1 opposite to the direction of arrow Y, and a third semiconductor element 3 is packaged on the second semiconductor element 2. As in the first embodiment, the first circuit 202 of the second semiconductor element 2 and the second circuit 302 of the third semiconductor element 3 each constitute a logic circuit.

[0093] Furthermore, the third semiconductor element 3M is packaged directly and individually in the packaging region 120 along a side of the first semiconductor element 1 opposite to the direction of arrow X. The third semiconductor element 3M includes a second circuit 302M, and the second circuit 302 constitutes a memory circuit. As with the semiconductor device 10 according to the fourth embodiment, the third semiconductor element 3M is packaged in the package region 120 of the first semiconductor element 1 via the bump electrode 5 .

[0094] Components other than the above-described components are the same as or substantially the same as those of the semiconductor devices 10 according to the above-described first and fourth embodiments.

[0095] [Function and Effect] In the semiconductor device 10 according to the fifth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the fourth embodiment can be obtained.

[0096] <6. Sixth Implementation Plan> Reference Figure 15 A semiconductor device 10 according to a sixth embodiment of the present invention will be described.

[0097] [Structure of Semiconductor Device 10] Figure 15 An example of a planar configuration of the semiconductor device 10 according to the sixth embodiment is shown.

[0098] like Figure 15As shown, the semiconductor device 10 according to the sixth embodiment further includes a third semiconductor element 3M in the packaging region 120 along the other side of the first semiconductor element 1 in the direction of arrow X of the semiconductor device 10 according to the fifth embodiment. That is, the second semiconductor element 2 and the third semiconductor element 3 are packaged in the packaging region 120 on the sides of the first semiconductor element 1 that are opposite to each other in the direction of arrow Y, and the third semiconductor element 3M is packaged in the packaging region 120 on the sides of the first semiconductor element 1 that are opposite to each other in the direction of arrow X.

[0099] Components other than the above-described components are the same or substantially the same as those of the semiconductor devices 10 according to the above-described first and fifth embodiments.

[0100] [Function and Effect] In the semiconductor device 10 according to the sixth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the fifth embodiment can be obtained.

[0101] <7. Seventh Implementation Plan> Reference Figure 16 A semiconductor device 10 according to a sixth embodiment of the present invention will be described.

[0102] [Structure of Semiconductor Device 10] Figure 16 An example of a longitudinal cross-sectional configuration of a semiconductor device 10 according to the seventh embodiment is shown. like Figure 16 As shown, the semiconductor device 10 according to the seventh embodiment further includes a fourth semiconductor element 4 in the semiconductor device 10 according to the first embodiment.

[0103] This will be described in detail. Like the semiconductor device 10 according to the first embodiment, the semiconductor device 10 constitutes a back-illuminated solid-state imaging device. The fourth semiconductor element 4 is packaged on the back surface 2B side of the first semiconductor element 1. The fourth semiconductor element 4 includes a semiconductor substrate 401 and a third circuit 402.

[0104] Like the semiconductor substrate 103 of the first semiconductor element 1 , the semiconductor substrate 401 is formed of, for example, a single crystal silicon substrate. The third circuit 402 is provided on the semiconductor substrate 401 on the front surface 1A side of the first semiconductor element 1. In the third circuit 402, for example, a logic circuit similar to the first circuit 202 or the second circuit 302 is divided, or the third circuit 402 includes other logic circuits not selected in the first circuit 202 or the second circuit 302. Like the pixel circuit 108, the third circuit 402 is configured to include a transistor Tr, a resistor, a capacitor, etc. Alternatively, the third circuit 402 may be the memory circuit described in the semiconductor device 10 according to the second embodiment.

[0105] The wiring layer 403 is provided on the front surface 1A side of the semiconductor substrate 401. Multiple layers of wiring 4031 and terminals 4032 are formed in the wiring layer 403. The wiring 4031 and the terminals 4032, for example, connect logic circuits. For example, a metal wiring material such as Cu is used for the wiring 4031. For example, a metal wiring material such as Cu is used for the terminals 4032. Furthermore, a plug wiring 4033 is formed on the wiring 4031. The plug wiring 4033 is electrically connected to the transistor Tr of the third circuit 402. For example, a metal wiring material such as W is used for the plug wiring 4033.

[0106] Although shown in a simplified manner, the insulator 4035 is formed, for example, between the multilayer wirings 4031 and between the wirings 4031 and the terminals 4032. The insulator 4035 is formed of, for example, a SiO2 film.

[0107] The front surface of the terminal 4032 is exposed from the insulator 4035. The wiring 1022 of the wiring layer 102 of the first semiconductor element 1 is Cu-Cu bonded to the terminal 4032 as a terminal. In other words, the terminal 4032 is mechanically and electrically connected to the wiring 1022, similar to the bonding between the terminal 2032 of the second semiconductor element 2 and the terminal 3032 of the third semiconductor element 3. Here, the fourth semiconductor element 4 corresponds to the “fourth semiconductor element” according to the present technology. In addition, the third circuit 402 corresponds to the “third circuit” according to the present technology.

[0108] Components other than the above-described components are the same or substantially the same as those of the semiconductor device 10 according to the above-described first embodiment.

[0109] [Function and Effect] In the semiconductor device 10 according to the seventh embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the first embodiment can be obtained.

[0110] Furthermore, the semiconductor device 10 includes a fourth semiconductor element 4 having a third circuit 402. In the semiconductor device 10 having this configuration, the addition of the fourth semiconductor element allows for expansion of the system configuration of the back-illuminated solid-state imaging device. Furthermore, the fourth semiconductor element 4 is packaged on the back surface 1B side of the first semiconductor element 1, which allows for expansion of the pixel area 110 of the semiconductor device 10 while further increasing the packaging density.

[0111] <8. Eighth Implementation Plan> Reference Figure 17 A semiconductor device 10 according to an eighth embodiment of the present invention will be described.

[0112] [Structure of Semiconductor Device 10] Figure 17 An example of a longitudinal cross-sectional configuration of a semiconductor device 10 according to the eighth embodiment is shown. like Figure 17 As shown, the semiconductor device 10 according to the eighth embodiment is an application example of the semiconductor device 10 according to the first embodiment.

[0113] This will be described in detail. Unlike the semiconductor device 10 according to the first embodiment, the semiconductor device 10 forms a front-illuminated solid-state imaging device. That is, in the first semiconductor element 1, the pixel circuit 108 is provided on the front surface 1A side of the semiconductor substrate 103. The insulator 104 also serves as a wiring layer, and the wiring 1041 and the terminal 1042 are formed in the insulator 104.

[0114] Furthermore, as with the semiconductor device 10 according to the first embodiment, the second semiconductor element 2 is packaged in the package region 120 of the first semiconductor element 1. In addition, the third semiconductor element 3 is packaged on the second semiconductor element 2.

[0115] Components other than the above-described components are the same or substantially the same as those of the semiconductor device 10 according to the above-described first embodiment.

[0116] [Function and Effect] In the semiconductor device 10 according to the eighth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the first embodiment can be obtained.

[0117] Furthermore, in the semiconductor device 10 , even if the first semiconductor element 1 constitutes a front-illuminated solid-state imaging device, it is possible to increase the packaging density of peripheral circuits while expanding the pixel region 110 .

[0118] <9. Ninth Implementation Plan> Reference Figure 18A semiconductor device 10 according to a ninth embodiment of the present invention will be described.

[0119] [Structure of Semiconductor Device 10] Figure 18 An example of a longitudinal cross-sectional configuration of a semiconductor device 10 according to a ninth embodiment is shown. like Figure 18 As shown, the semiconductor device 10 according to the ninth embodiment includes a through wiring 2012 in the second semiconductor element 2 of the semiconductor device 10 according to the first embodiment. Here, the through wiring 2012 corresponds to a "second through wiring" according to the present technology.

[0120] This will be described in detail. In the second semiconductor element 2 of the semiconductor device 10 , a through wiring 2012 is provided that penetrates the semiconductor substrate 201 and the wiring layer 203 in the thickness direction. One end of the through wiring 2012 is electrically connected to a wiring 2041 provided in the wiring layer 204 of the second semiconductor element 2. The wiring 2041 is electrically connected indirectly to the pixel 100 via the pixel circuit 108 of the first semiconductor element 1. In addition, the other end of the through wiring 2012 is electrically connected to the terminal 3032 of the wiring layer 303 of the third semiconductor element 3. The terminal 3032 is electrically connected to the second circuit 302 via the wiring 3031.

[0121] The through wiring 2012 is formed of a metal wiring material similar to that of the through wiring 2011. In addition, the through wiring 2012 electrically connects the wiring 2014 of the second semiconductor element 2 and the wiring 3031 of the third semiconductor element 3 to each other; therefore, it is not necessary to join the terminal 2032 of the second semiconductor element 2 and the terminal 3032 of the third semiconductor element 3 together.

[0122] Components other than the above-described components are the same or substantially the same as those of the semiconductor device 10 according to the above-described first embodiment.

[0123] [Function and Effect] In the semiconductor device 10 according to the ninth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the first embodiment can be obtained.

[0124] Furthermore, the semiconductor device 10 includes a through wiring 1012 penetrating the second semiconductor element 2. In the semiconductor device 10 having such a configuration, an electrical connection structure between the second semiconductor element 2 and the third semiconductor element 3 can be easily realized.

[0125] <10. Tenth Implementation Plan> Reference Figure 19A semiconductor device 10 according to a tenth embodiment of the present invention will be described. In the semiconductor device 10 according to the tenth embodiment of the present invention to the semiconductor device 10 according to the thirteenth embodiment described later, examples of configuring an optimal system configuration are described.

[0126] [System Configuration of Semiconductor Device 10] Figure 19 An example of a system configuration of the semiconductor device 10 according to the tenth embodiment is shown. like Figure 19 As shown, the semiconductor device 10 according to the tenth embodiment includes a pixel region 110 , a scanning circuit SSC, a readout circuit REC, and a control circuit COC in the first semiconductor element 1 of the semiconductor device 10 according to the second embodiment. The scanning circuit SSC includes, for example, one or more selected from a vertical driving circuit and a horizontal driving circuit. In addition, the readout circuit REC includes a pixel circuit 108 that reads a pixel signal converted from light into electric charge in the pixel 100 .

[0127] The first circuit 202 provided in the second semiconductor element 2 includes an analog-to-digital conversion circuit ADC, an output signal processing circuit OSC, and an output interface circuit OIF. In addition, the second circuit 302M of the third semiconductor element 3M includes a storage circuit.

[0128] In the analog-to-digital conversion circuit ADC, the pixel signal read by the readout circuit REC is converted from an analog signal to a digital signal. The pixel signal converted to a digital signal is temporarily stored in the storage circuit. In other words, the pixel signal is temporarily stored in the storage circuit. The output signal processing circuit OSC reads the pixel signal held by the storage circuit and converts the pixel signal into a predetermined output signal. The output interface circuit OIF outputs the output signal to an external device.

[0129] Components other than the above-described components are the same as or substantially the same as those of the semiconductor device 10 according to the second embodiment described above.

[0130] [Function and Effect] In the semiconductor device 10 according to the tenth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the second embodiment can be obtained.

[0131] In addition, if Figure 19As shown, the semiconductor device 10 includes a pixel region 110, a scanning circuit SSC, a readout circuit REC, and a control circuit COC in the first semiconductor element 1. In addition, the semiconductor device 10 includes an analog-to-digital conversion circuit ADC, an output signal processing circuit OSC, and an output interface circuit OIF in the second semiconductor element 2, and includes a storage circuit in the third semiconductor element 3M. Therefore, the third semiconductor element 3M can be manufactured independently of the first semiconductor element 1 and the second semiconductor element 2 using a process specific to memory devices. To elaborate, the third semiconductor element 3M can be constructed as a semiconductor element using specialized materials, such as high-dielectric-constant materials or magnetic materials, and specialized processes. Specifically, a memory circuit such as a volatile semiconductor memory element (e.g., DRAM), magnetoresistive random access memory (MRAM), or resistive random access memory (RRAM) can be incorporated into the third semiconductor element 3M.

[0132] In the tenth embodiment, providing a memory circuit in the third semiconductor element 3M enables construction of an optimal system configuration. For example, special materials and special processes are used for the memory circuit; therefore, in the third semiconductor element 3M, no through wiring is formed in the semiconductor substrate 301 (see FIG. Figure 9 ). That is, in addition to the special materials and special processes, the through-wiring is also a new structure added. Therefore, it is possible to effectively suppress or prevent the degradation of the characteristics of the memory element of the memory circuit due to the formation of the through-wiring.

[0133] In the semiconductor device 10 having such a structure, the through wiring 2011 is used for connection between the first semiconductor element 1 and the second semiconductor element 2 (for example, see Figure 9 ). In addition, the connection between the terminal 2032 and the terminal 3032 is used for the connection between the second semiconductor element 2 and the third semiconductor element 3M (for example, refer to Figure 9 ). Note that a circuit other than the memory circuit may be appropriately mounted in any one of the first semiconductor element 1 and the second semiconductor element 2 .

[0134] <11. Eleventh Implementation Plan> Reference Figure 20 A semiconductor device 10 according to an eleventh embodiment of the present invention will be described. The semiconductor device 10 according to the eleventh embodiment is an application example of the semiconductor device 10 according to the tenth embodiment.

[0135] [System Configuration of Semiconductor Device 10] Figure 20An example of a system configuration of the semiconductor device 10 according to the eleventh embodiment is shown. like Figure 20 As shown, in the semiconductor device 10 of the eleventh embodiment, the analog-to-digital conversion circuit ADC of the semiconductor device 10 according to the tenth embodiment is divided into a comparator circuit CP and a counter circuit COU. The comparator circuit CP is mounted in the first semiconductor element 1. In addition, the counter circuit COU is mounted as the first circuit 202 in the second semiconductor element 2. In addition, the second semiconductor element 2 includes an output interface circuit OIF as the first circuit 202. Furthermore, the third semiconductor element 3M includes a memory circuit as the second circuit 302M, and further includes an output signal processing circuit OSC.

[0136] Here, the output signal processing circuit OSC is connected to the wiring 3031 (see Figure 9 , hereinafter referred to as “first wiring 1W”) is electrically connected to the memory circuit. The first wiring 1W corresponds to the “first wiring” according to the present technology. The output signal processing circuit OSC operates according to the first clock signal CLK1 supplied from the control circuit COC.

[0137] In addition, the output interface circuit OIF is connected to the wiring 3031 and the wiring 2031 (see Figure 9 ; hereinafter referred to as “second wiring 2W”) is electrically connected to the output signal processing circuit OSC. The second wiring 2W corresponds to the “second wiring” according to the present technology. The output interface circuit OIF operates according to the second clock signal CLK2 supplied from the control circuit COC.

[0138] Here, the number of second wirings 2W is smaller than the number of first wirings 1W. Furthermore, the clock frequency of the second clock signal CLK2 is higher than the clock frequency of the first clock signal CLK1. This allows for parallel processing to transmit a large number of signals between the storage circuit and the output signal processing circuit OSC. High-speed serial transmission of signals is possible between the output signal processing circuit OSC and the output interface circuit OIF.

[0139] Components other than the above-described components are the same as or substantially the same as those of the semiconductor device 10 according to the above-described tenth embodiment.

[0140] [Function and Effect] In the semiconductor device 10 according to the eleventh embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the tenth embodiment can be obtained.

[0141] In addition, in the semiconductor device 10, as Figure 20As shown, the storage circuit and the output signal processing circuit OSC are provided in the third semiconductor element 3. The operation of the storage circuit and the output signal processing circuit OSC is asynchronous with the cycle of a series of row-sequential readout operations in which the pixels 100 are selected row by row by the vertical scanning circuit (refer to FIG. Figure 9 ), reads the pixel signal from the selected pixel 100, and then converts the pixel signal from an analog signal to a digital signal. In other words, the storage circuit and output signal processing circuit OSC operate as random logic circuits. This results in the generation of irregular power supply noise. The generation source of such power supply noise is provided in the third semiconductor element 3 away from the pixel 100, which makes it possible to effectively suppress or prevent the generation of power supply noise. Therefore, as a solid-state imaging device, good image quality can be achieved.

[0142] In addition, in the semiconductor device 10, as Figure 20 As shown, the output interface circuit OIF is provided in the second semiconductor element 2. The second semiconductor element 2 is packaged in a circuit including a terminal 1043 (refer to FIG. Figure 9 ) near the first semiconductor element 1. Therefore, parasitic resistance and capacitance added to the signal output path from the output interface circuit OIF to the external output terminal can be effectively reduced. Furthermore, the output interface circuit OIF operates based on the high-speed second clock signal CLK2. In the semiconductor device 10 having such a structure, a higher signal transmission speed can be achieved.

[0143] Furthermore, in the semiconductor device 10, as Figure 20 As shown, the analog-to-digital conversion circuit ADC is divided into a comparator circuit CP and a counter circuit COU. The comparator circuit CP is an analog circuit and is mounted in the first semiconductor element 1. In addition, the counter circuit COU is a digital circuit and is mounted in the second semiconductor element 2. The second semiconductor element 2 having such a configuration includes only a circuit block of a digital circuit; therefore, no analog circuit elements are required, and the circuit block can be easily implemented. Therefore, the production cost of the second semiconductor element 2 can be reduced.

[0144] <12. Twelfth Implementation Plan> Reference Figure 21 A semiconductor device 10 according to a twelfth embodiment of the present invention will be described. The semiconductor device 10 according to the twelfth embodiment is an application example of the semiconductor device 10 according to the tenth embodiment.

[0145] [System Configuration of Semiconductor Device 10] Figure 21An example of a schematic configuration of a semiconductor device 10 according to a twelfth embodiment is shown. like Figure 21 As shown, in the semiconductor device 10 according to the twelfth embodiment, the readout circuit REC and the analog-to-digital conversion circuit ADC are distributed and mounted in the second semiconductor element 2 and the third semiconductor element 3 of the semiconductor device 10 according to the tenth embodiment. In other words, in a plan view, twice the number of analog-to-digital conversion circuits AD can be mounted within a predetermined area of ​​the package region 120 of the first semiconductor element 1.

[0146] Components other than the above-described components are the same as or substantially the same as those of the semiconductor device 10 according to the above-described tenth embodiment.

[0147] [Function and Effect] In the semiconductor device 10 according to the twelfth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the tenth embodiment can be obtained.

[0148] In addition, in the semiconductor device 10, as Figure 21 As shown, the readout circuit REC and the analog-to-digital conversion circuit ADC are distributed and mounted in both the second semiconductor element 2 and the third semiconductor element 3. Therefore, the readout speed of the pixel signal can be doubled without increasing the chip size of the semiconductor device 10.

[0149] In addition, in the semiconductor device 10, each of the second semiconductor element 2 and the third semiconductor element 3 can be manufactured by the same structure, which makes it possible to reduce production costs. Here, the term "manufactured by the same structure" is used to indicate that each of the second semiconductor element 2 and the third semiconductor element 3 is produced by completely identical design, development, and manufacturing.

[0150] Note that the twelfth embodiment is an example in which the readout circuit REC and the analog-to-digital conversion circuit ADC are provided side by side in the respective second semiconductor element 2 and third semiconductor element 3. In the present technology, the readout circuit REC can be installed in the first semiconductor element 1, and the analog-to-digital conversion circuit ADC can be provided side by side in the respective second semiconductor element 2 and third semiconductor element 3.

[0151] <13. Thirteenth Implementation Plan> Reference Figure 22 and Figure 23 A semiconductor device 10 according to a thirteenth embodiment of the present invention will be described. The semiconductor device 10 according to the thirteenth embodiment is an application example of the eleventh embodiment.

[0152] [System Configuration of Semiconductor Device 10] Figure 22 An example of a system configuration of the semiconductor device 10 according to the thirteenth embodiment is shown.

[0153] like Figure 22 As shown, the semiconductor device 10 according to the thirteenth embodiment includes a first semiconductor element 1 , a second semiconductor element 20 and a second semiconductor element 21 , and a third semiconductor element 3 and a third semiconductor element 3M1 .

[0154] The first semiconductor element 1 includes a pixel region 110 . The current generating circuit CGC, the negative voltage generating circuit NVG, the intermediate voltage generating circuit IVG, and the vertical scanning circuit VSC are mounted in the second semiconductor element 20 as the first circuit 202. The current generating circuit CGC and the like mounted in the second semiconductor element 20 are analog circuits. Furthermore, a constant current source circuit CCS, a comparator circuit CP, and a ramp generating circuit LG are mounted in the second semiconductor element 21 as the first circuit 202. Like the second semiconductor element 20, the constant current source circuit CCS and the like mounted in the second semiconductor element 21 are analog circuits.

[0155] The control signal generation circuit CSG, the clock generation circuit CK, the system circuit SC, and the register circuit RG are mounted in the third semiconductor element 3 as the second circuit 302. The control signal generation circuit CSG and the like mounted in the third semiconductor element 3 are digital circuits. A memory circuit, a counter circuit COU, an output signal processing circuit OSC, and an output interface circuit OIF are mounted in the third semiconductor element 3M1 as the second circuit 302M. The memory circuit and the like mounted in the third semiconductor element 3M1 are digital circuits.

[0156] Here, the control signal generation circuit CSG provides divided clock signals to each of the current generation circuit CGC, the negative voltage generation circuit NVG, and the intermediate voltage generation circuit IVG. Furthermore, the control signal generation circuit CSG supplies a row select signal, a shutter address signal, a read address signal, a latch pulse signal, a reset pulse signal, and the like to the vertical scanning circuit VSC. Furthermore, the control signal generation circuit CSG supplies control pulse signals to each of the constant current source circuit CCS and the comparator circuit CP, and supplies a SYNC signal to the storage circuit. Furthermore, the control signal generation circuit CSG supplies a register reflection signal to the register circuit RG, and supplies an interrupt signal to the system circuit SC through the advanced peripheral bus (APB) and the interface (IF).

[0157] [Structure of Semiconductor Device 10] Figure 23 Shown Figure 22 An example of a schematic configuration of a semiconductor device 10 is shown. like Figure 23 As shown, the second semiconductor element 21 and the third semiconductor element 3M1 are stacked and packaged in respective packaging regions 120 of the first semiconductor element 1 that are opposite to each other in the arrow X direction. Furthermore, a second semiconductor element 20 and a third semiconductor element 3 are stacked and packaged in a packaging region 120 of the first semiconductor element 1 along the arrow Y direction.

[0158] Components other than the above-described components are the same as or substantially the same as those of the semiconductor device 10 according to the above-described eleventh embodiment.

[0159] [Function and Effect] In the semiconductor device 10 according to the thirteenth embodiment, actions and effects similar to those obtained by the semiconductor device 10 according to the eleventh embodiment can be obtained.

[0160] In addition, in the semiconductor device 10, as Figure 22 and Figure 23 As shown, the pixel region 110 is provided in the first semiconductor element 1. Furthermore, analog circuits are provided in the second semiconductor element 20 and the second semiconductor element 21, and digital circuits are provided in the third semiconductor element 3 and the third semiconductor element 3M1. In the thirteenth embodiment, the system circuit SC and the clock generation circuit CK that control the entire semiconductor device 10 are provided in the third semiconductor element 3. Therefore, in order to supply control signals and clock signals to the digital circuits other than the above-mentioned circuits of the third semiconductor element 3, the analog circuits of the second semiconductor element 2, and the like, a structure is required in which the signals temporarily pass from the third semiconductor element 3 through the second semiconductor element 2 and the first semiconductor element 1.

[0161] In the semiconductor device 10 having this configuration, the first semiconductor element 1 has a structure dedicated to pixels and is manufactured using a process dedicated to pixels. Similarly, the second semiconductor elements 20 and 21 each have a structure dedicated to analog circuits and are manufactured using a process dedicated to analog circuits. Furthermore, the third semiconductor element 3 and the third semiconductor element 3M1 each have a structure dedicated to digital circuits and are manufactured using a process dedicated to digital circuits. In other words, the first semiconductor element 1, the second semiconductor element 20 and the second semiconductor element 21, and the third semiconductor element 3 and the third semiconductor element 3M1 have device structures that are completely independent of each other and are produced using completely independent semiconductor manufacturing processes. Therefore, the first semiconductor element 1 can adopt a structure specific to the pixel characteristics and employ a process specific to the pixel characteristics. Furthermore, each of the second semiconductor element 20 and the second semiconductor element 21 can adopt a structure specialized for high withstand voltage and low noise, for example, and employ a process specialized for high withstand voltage and high noise. Furthermore, each of the third semiconductor element 3 and the third semiconductor element 3M1 can adopt a structure specialized for low voltage and miniaturization and employ a process specialized for low voltage and miniaturization. That is, each semiconductor element can be optimized independently, and the performance of the entire semiconductor device 10 can be improved.

[0162] <14. Application Examples of Mobile Objects> The technology according to the present invention (the present technology) is applicable to a variety of products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile object, such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, aircraft, drones, ships, and robots.

[0163] Figure 24 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present invention can be applied.

[0164] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 24 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional components of integrated control unit 12050 include a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0165] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor for generating vehicle drive force, a drive force transmitting mechanism for transmitting drive force to wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating vehicle braking force.

[0166] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, backup lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from a mobile device that replaces a key. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0167] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receive the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can perform object detection processing for objects such as people, vehicles, obstacles, signs, or characters on the road surface, or can perform distance detection processing to detect the distance to such objects.

[0168] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0169] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0170] Microcomputer 12051 can calculate control target values ​​for the driving force generation device, steering mechanism, or braking device based on information about the vehicle's exterior or interior obtained by vehicle exterior information detection unit 12030 or vehicle interior information detection unit 12040, and output control commands to drive system control unit 12010. For example, microcomputer 12051 can perform coordinated control to implement advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, vehicle-to-vehicle distance-based following driving, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0171] In addition, by controlling the driving force generating device, steering mechanism or braking device, etc. based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 is able to perform collaborative control aimed at achieving automatic driving, etc., wherein the automatic driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0172] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, for example, based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0173] The audio and video output unit 12052 sends an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the vehicle's passengers or the outside of the vehicle of information. Figure 24 In the example of FIG, as the output device, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. The display portion 12062 can include, for example, at least one of an in-vehicle display and a head-up display.

[0174] Figure 25 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0175] exist Figure 25 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0176] Camera units 12101, 12102, 12103, 12104, and 12105 are, for example, located on the front nose, rearview mirror, rear bumper, and rear door of vehicle 12100, as well as on the upper portion of the windshield inside the vehicle. Camera unit 12101 located on the front nose and camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located on the rearview mirror primarily capture images on both sides of vehicle 12100. Camera unit 12104 located on the rear bumper or rear door primarily captures images from behind vehicle 12100. Camera unit 12105 located on the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0177] By the way, Figure 25Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located at the rear bumper or rear door. For example, by superimposing image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 viewed from above can be obtained.

[0178] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0179] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can determine the distances and temporal changes in these distances (relative speeds with respect to vehicle 12100) to various three-dimensional objects within imaging ranges 12111 to 12114, thereby identifying the closest three-dimensional object as the preceding vehicle. Specifically, this three-dimensional object is located on the travel path of vehicle 12100 and is traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, microcomputer 12051 can pre-set the desired distance to the preceding vehicle and execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). This enables cooperative control, such as automated driving, designed to enable the vehicle to travel autonomously without relying on driver input.

[0180] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12501 can classify 3D object data of 3D objects into 3D object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating a collision possibility, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and executes forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0181] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can identify pedestrians, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. The audio and video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0182] An example of a vehicle control system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the imaging unit 12031 in the above-described configuration. Applying the technology according to the present invention to the imaging unit 12031 enables the realization of an imaging unit 12031 that can increase the packaging density of peripheral circuits while expanding the pixel area.

[0183] <15. Other Implementation Options> The present technology is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology. For example, in the solid semiconductor devices according to the above-described first to ninth embodiments, semiconductor devices according to two or more embodiments may be combined.

[0184] In addition, in the present technology, three or more semiconductor elements can be stacked and packaged in the packaging region of the first semiconductor element. In this case, the semiconductor substrate of the semiconductor element stacked closer to the first semiconductor element than the semiconductor element stacked on the uppermost layer is thinned. Furthermore, the present technology is applicable to a semiconductor device including a first semiconductor element having a pixel region in which a plurality of pixels, each having a light-emitting source, are arranged. Examples of the light-emitting source include light-emitting diodes (LEDs), lasers, liquid crystals including backlights, organic electroluminescence (EL), and plasma.

[0185] A semiconductor device according to a first aspect of the present invention includes a first semiconductor element, a second semiconductor element, and a third semiconductor element. The first semiconductor element includes a pixel region in which a plurality of pixels are arranged on one surface. The second semiconductor element is packaged in an area on the one surface that is different from the pixel region and includes a first circuit electrically connected to the pixels. The third semiconductor element is packaged on the second semiconductor element on an opposite side of the first semiconductor element and includes a second circuit electrically connected to the pixels. In a semiconductor device having this structure, the second and third semiconductor elements are stacked in a region separate from the pixel region, which increases the packing density along the thickness direction of the first semiconductor element. Consequently, the packing density of the peripheral circuits, including the first and second circuits, can be increased while expanding the pixel region.

[0186] Furthermore, in the semiconductor device according to the second aspect of the present invention, the thickness of the semiconductor substrate of the second semiconductor element is thinner than the thickness of the semiconductor substrate of the third semiconductor element in the semiconductor device according to the first aspect in the same direction. In a semiconductor device having this structure, the semiconductor substrate of the second semiconductor element can be easily processed, which enables the formation of through-wiring that penetrates the semiconductor substrate in the thickness direction, for example. Therefore, the second and third semiconductor elements can be packaged in a stacked state on the first semiconductor element, which increases the packaging density of the packaging area while expanding the pixel area.

[0187] <Structure of this technology> The present technology has the following configuration: According to the present technology having the following configuration, in a semiconductor device, it is possible to increase the packaging density of the packaging region while expanding the pixel region. (1) A semiconductor device comprising: a first semiconductor element having a pixel region in which a plurality of pixels are arranged on one surface; a second semiconductor element packaged in a region different from the pixel region on the one surface and including a first circuit electrically connected to the pixel; and A third semiconductor element is packaged on the second semiconductor element on an opposite side of the first semiconductor element and includes a second circuit electrically connected to the pixel. (2) The semiconductor device according to (1) above, wherein, when viewed along the thickness direction of the first semiconductor element, a planar area of ​​each of the second semiconductor element and the third semiconductor element is smaller than a planar area of ​​the first semiconductor element. (3) The semiconductor device according to the above (2), wherein each of the second semiconductor element and the third semiconductor element is provided within the one surface of the first semiconductor element when viewed along the thickness direction of the first semiconductor element. (4) The semiconductor device according to any one of (1) to (3) above, wherein the thickness of the semiconductor substrate of the second semiconductor element is thinner than the thickness of the semiconductor substrate of the third semiconductor element in the same direction. (5) The semiconductor device according to any one of (1) to (4) above, wherein the second semiconductor element includes a first through-wiring that penetrates in a thickness direction and electrically connects the pixel and the first circuit to each other. (6) The semiconductor device according to any one of (1) to (5) above, wherein the second semiconductor element includes a second through-wiring that penetrates in a thickness direction and electrically connects the pixel and the second circuit to each other. (7) The semiconductor device according to any one of (1) to (6) above, wherein: The first semiconductor element includes a first terminal electrically connected to the pixel on the one surface side thereof, The second semiconductor element includes a second terminal electrically connected to the first circuit or the second circuit on the first semiconductor element side, and The second terminal is electrically connected to the first terminal via a bump electrode. (8) The semiconductor device according to any one of (1) to (5) and (7), wherein: comprising, on the third semiconductor element side of the second semiconductor element, a third terminal electrically connected to the first circuit, comprising a fourth terminal electrically connected to the second circuit on the second semiconductor element side of the third semiconductor element, and The fourth terminal is opposed to and engaged with the third terminal, and the third terminal and the fourth terminal are electrically connected to each other. (9) The semiconductor device according to any one of (1) to (8) above, wherein the first semiconductor element constitutes a front-illuminated solid-state imaging device. (10) The semiconductor device according to any one of (1) to (8) above, wherein the first semiconductor element constitutes a back-illuminated solid-state imaging device. (11) The semiconductor device according to any one of (1) to (8) above, wherein: A fourth semiconductor element is provided on a side of the first semiconductor element opposite to the one surface, the fourth semiconductor element including a third circuit electrically connected to the pixel, and having a planar area equal to that of the first semiconductor element when viewed in a thickness direction of the first semiconductor element, and The first semiconductor element constitutes a back-illuminated solid-state imaging device. (12) The semiconductor device according to any one of (1) to (11) above, wherein the first circuit and the second circuit are logic circuits. (13) The semiconductor device according to any one of (1) to (11) above, wherein: The first circuit is a logic circuit, and The second circuit is a storage circuit. (14) The semiconductor device according to any one of (1) to (13) above, wherein: A fifth semiconductor element is packaged in a region on the one surface of the first semiconductor element that is different from the pixel region and the region where the second semiconductor element is packaged. The fifth semiconductor element includes a fourth circuit electrically connected to the pixel. (15) The semiconductor device according to the above (14), wherein the fourth circuit is a memory circuit. (16) The semiconductor device according to any one of (1) to (15) above, wherein: The first semiconductor element is formed into a rectangular shape when viewed in the thickness direction, and The pixel region is provided in a central portion of the one surface of the first semiconductor element, and the second semiconductor element and the third semiconductor element are packaged in a peripheral portion along at least one side of the rectangular shape. (17) The semiconductor device according to the above (13), wherein the second circuit of the third semiconductor element is a storage circuit that temporarily holds an analog-to-digital conversion result of a pixel signal output from the pixel. (18) The semiconductor device according to (13) or (17) above, further comprising: an output signal processing circuit electrically connected to the storage circuit via a plurality of first wirings and operating with a first clock signal, wherein: The storage circuit and the output signal processing circuit are provided in the third semiconductor element. (19) The semiconductor device according to (18) above further includes: an output interface circuit electrically connected to the output signal processing circuit via a plurality of second wirings and operating with a second clock signal, the number of the second wirings being smaller than the number of the first wirings, and the clock frequency of the second clock signal being higher than the clock frequency of the first clock signal, wherein: The output interface circuit is provided as the first circuit in the second semiconductor element. (20) The semiconductor device according to any one of (1) to (19) above further includes an analog-to-digital conversion circuit provided in each of the first circuit of the second semiconductor element and the second circuit of the third semiconductor element. (twenty one) The semiconductor device according to any one of (1) to (19) above, wherein: An analog circuit is provided in the first circuit of the second semiconductor element, and A digital circuit is provided in the second circuit of the third semiconductor element.

[0188] This application claims priority from Japanese Patent Application JP 2022-167873 filed with the Japan Patent Office on October 19, 2022, the entire contents of which are incorporated herein by reference.

[0189] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made according to design requirements and other factors as long as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A semiconductor device comprising: A first semiconductor element having a pixel region in which a plurality of pixels are arranged on one surface; a second semiconductor element packaged in a region different from the pixel region on the one surface and including a first circuit electrically connected to the pixel; and A third semiconductor element is packaged on the second semiconductor element on an opposite side of the first semiconductor element and includes a second circuit electrically connected to the pixel.

2. The semiconductor device according to claim 1, wherein When viewed along the thickness direction of the first semiconductor element, a planar area of ​​each of the second semiconductor element and the third semiconductor element is smaller than a planar area of ​​the first semiconductor element.

3. The semiconductor device according to claim 2, wherein: Each of the second semiconductor element and the third semiconductor element is provided within the one surface of the first semiconductor element when viewed in the thickness direction of the first semiconductor element.

4. The semiconductor device according to claim 1, wherein The thickness of the semiconductor substrate of the second semiconductor element is thinner than the thickness of the semiconductor substrate of the third semiconductor element in the same direction.

5. The semiconductor device according to claim 4, wherein: The second semiconductor element includes a first through wiring that penetrates in a thickness direction and electrically connects the pixel and the first circuit to each other.

6. The semiconductor device according to claim 4, wherein: The second semiconductor element includes a second through wiring that penetrates in a thickness direction and electrically connects the pixel and the second circuit to each other.

7. The semiconductor device according to claim 1, wherein The first semiconductor element includes, on the one surface side thereof, a first terminal electrically connected to the pixel, The second semiconductor element includes a second terminal electrically connected to the first circuit or the second circuit on the first semiconductor element side of the second semiconductor element, and The second terminal is electrically connected to the first terminal via a bump electrode.

8. The semiconductor device according to claim 1, wherein comprising, on the third semiconductor element side of the second semiconductor element, a third terminal electrically connected to the first circuit, comprising a fourth terminal electrically connected to the second circuit on the second semiconductor element side of the third semiconductor element, and The fourth terminal is opposed to and engaged with the third terminal, and the third terminal and the fourth terminal are electrically connected to each other.

9. The semiconductor device according to claim 1, wherein: The first semiconductor element constitutes a front-illuminated solid-state imaging device.

10. The semiconductor device according to claim 1, wherein The first semiconductor element constitutes a back-illuminated solid-state imaging device.

11. The semiconductor device according to claim 1, wherein A fourth semiconductor element is provided on a side of the first semiconductor element opposite to the one surface, the fourth semiconductor element includes a third circuit electrically connected to the pixel, and when viewed along the thickness direction of the first semiconductor element, the fourth semiconductor element has a plane area equal to that of the first semiconductor element, and The first semiconductor element constitutes a back-illuminated solid-state imaging device.

12. The semiconductor device according to claim 1, wherein The first circuit and the second circuit are logic circuits.

13. The semiconductor device according to claim 1, wherein The first circuit is a logic circuit, and The second circuit is a storage circuit.

14. The semiconductor device according to claim 1, wherein A fifth semiconductor element is packaged in a region on the one surface of the first semiconductor element that is different from the pixel region and the region where the second semiconductor element is packaged, and the fifth semiconductor element includes a fourth circuit electrically connected to the pixel.

15. The semiconductor device according to claim 14, wherein: The fourth circuit is a storage circuit.

16. The semiconductor device according to claim 1, wherein The first semiconductor element is formed in a rectangular shape when viewed in the thickness direction, and The pixel region is provided in a central portion of the one surface of the first semiconductor element, and the second semiconductor element and the third semiconductor element are packaged in a peripheral portion along at least one side of the rectangular shape.

17. The semiconductor device according to claim 13, wherein: The second circuit of the third semiconductor element is a storage circuit that temporarily holds an analog-to-digital conversion result of a pixel signal output from the pixel.

18. The semiconductor device according to claim 13, further comprising: an output signal processing circuit, which is electrically connected to the storage circuit through a plurality of first wirings and operates with a first clock signal, wherein: The storage circuit and the output signal processing circuit are provided in the third semiconductor element.

19. The semiconductor device according to claim 18, further comprising: an output interface circuit electrically connected to the output signal processing circuit via a plurality of second wirings and operating with a second clock signal, the number of the second wirings being less than the number of the first wirings, and the clock frequency of the second clock signal being higher than the clock frequency of the first clock signal, wherein: The output interface circuit is provided as the first circuit in the second semiconductor element. 20 . The semiconductor device according to claim 1 , further comprising an analog-to-digital conversion circuit provided in each of the first circuit of the second semiconductor element and the second circuit of the third semiconductor element.

Images