Storage device and operating method of storage device

Abstract

A storage device and an operating method of the storage device are provided. The storage device includes a non-volatile memory including a virtual block including an L2P pair region storing a pair of logical page number (LPN) and physical page number (PPN) (LPN-PPN pair), and a data region storing data addressed to the PPN; a volatile memory including an L2V table storing a virtual block number (VBN) corresponding to the LPN, an L2P cache storing the LPN-PPN pair, and an LPN range map storing a portion of the LPN stored in an L2P pair region of a virtual block; and a controller configured to control the non-volatile memory and the volatile memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0161032 filed in the Korean Intellectual Property Office on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] The storage device receives a logical page number (LPN) from a host device, determines a physical page number (PPN) corresponding to the LPN, and stores data therein. Therefore, logical page number to physical page number (L2P) conversion is an important operation in the storage device.

[0004] As the demand for storage device capacity increases, the size of the L2P map used for L2P conversion gradually increases. This requires additional DRAM for L2P, but weakens the price competitiveness of storage devices. Summary of the invention

[0005] The present disclosure provides a storage device capable of improving the performance of the storage device while implementing L2P mapping in an on-demand loading manner and an operating method of the storage device. In some embodiments, the storage device has reduced DRAM usage compared to other storage devices. The L2P mapping in the disclosed storage device can be implemented by using an on-demand loading manner that maintains the L2P mapping as the latest L2P mapping garbage collection (GC) to reduce DRAM usage. The present disclosure also provides a method for L2P mapping GC that avoids reducing the random write performance of the storage device.

[0006] In a first general aspect, a storage device includes: a nonvolatile memory including a virtual block including an L2P pair area storing pairs of logical page numbers (LPNs) and physical page numbers (PPNs) (LPN-PPN pairs) and a data area storing data addressed to the PPNs; a volatile memory including a logical page number to virtual block number (L2V) table storing virtual block numbers (VBNs) corresponding to the LPNs, an L2P cache storing the LPN-PPN pairs, and an LPN range map storing a portion of the LPNs stored in the L2P pair area of ​​the virtual block; and a controller configured to control the nonvolatile memory and the volatile memory.

[0007] In a second general aspect, a storage device includes: a nonvolatile memory including a first virtual block and a second virtual block, a volatile memory, and a controller connected to the nonvolatile memory and the volatile memory, wherein when the controller determines garbage collection of the first virtual block, each of the first virtual block and the second virtual block includes an L2P pair area storing a pair of logical page numbers (LPNs) and physical page numbers (PPNs) (LPN-PPN pairs) and a data area storing data addressed to the PPN, and the controller migrates a valid LPN-PPN pair stored in the L2P pair area of ​​the first virtual block to the L2P pair area of ​​the second virtual block, and migrates valid data stored in the data area of ​​the first virtual block to the data area of ​​the second virtual block.

[0008] In a third general aspect, an operating method of a storage device, the storage device comprising a volatile memory, a nonvolatile memory, and a controller, the nonvolatile memory comprising a virtual block, the virtual block having an L2P pair area for storing LPN-PPN pairs and a data area for storing data addressed to the PPN, the controller for controlling the volatile memory and the nonvolatile memory, the operating method comprising: receiving from a host device a write command instructing to write first data in an area addressed to a first LPN, writing a write command instructing to write first data to a location of a first PPN of the virtual block addressed to a first VBN; A method of storing a first data storage device in a virtual block includes determining a location for storing first data, storing a pair of a first LPN and a first VBN in an L2V table of a volatile memory based on a result of the determination, and storing a pair of a first LPN and a first PPN in an L2P cache of the volatile memory, storing the first data in a location of the first PPN addressed to a virtual block, and flushing the LPN-PPN pair stored in the L2P cache to the L2P pair area of ​​the virtual block when it is determined that the virtual block is full based on the LPN-PPN pair stored in the L2P cache and the data stored in the data area of ​​the virtual block.

[0009] In a fourth general aspect, a method of operating a storage device, the storage device comprising a volatile memory, a nonvolatile memory, and a controller, the volatile memory comprising an L2P cache in which a first LPN-PPN pair is stored, the nonvolatile memory comprising a virtual block having an L2P pair area for storing a second LPN-PPN pair and a data area for storing data addressed to the PPN, the controller being configured to control the volatile memory and the nonvolatile memory, the method comprising: receiving a read command from a host device, the read command instructing to read data stored in the LPN-PPN pair addressed to the first LPN; The method comprises: determining a first LPN in a second LPN-PPN pair of the L2P pair region of the virtual block, determining whether the first LPN exists in an L2P cache of the volatile memory, determining a PPN corresponding to the first LPN in the L2P cache in response to the first LPN being present in the L2P cache and returning data stored in a location addressed to the determined PPN to the host device, and determining a PPN corresponding to the first LPN in a second LPN-PPN pair of the L2P pair region of the virtual block in response to the first LPN not being present in the L2P cache and returning data stored in the location addressed to the determined PPN to the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating an example of a memory system.

[0011] Figure 2 It is shown Figure 1 A block diagram of an example of a buffer memory of a memory system.

[0012] Figure 3 It is shown Figure 2 FIG. 1 is a view of an example of an L2V table of a buffer memory.

[0013] Figure 4 It is shown Figure 2 An example view of the buffer memory of the L2P cache.

[0014] Figure 5 It is shown Figure 2 A view of an example of an LPN range map of a buffer memory.

[0015] Figures 6 to 8 It is shown Figure 1 A view of an example of a nonvolatile memory of a memory system.

[0016] Fig. 9 It is shown Figure 1 A view of a storage controller and nonvolatile memory of a storage device being reconfigured.

[0017] Fig.10 It is shown Figure 1A view of a memory controller, memory interface, and nonvolatile memory being reconfigured.

[0018] Fig.11 It is shown Fig.10 An example of a block diagram of a non-volatile memory.

[0019] Fig.12 is a view showing an example of a 3D V-NAND structure applicable to a nonvolatile memory.

[0020] Fig.13 is a flowchart illustrating an example of a write operation of a storage device.

[0021] Fig.14A , Fig. 14B and Fig.15 It is shown Fig.13 A view of an example of the operation of a storage device.

[0022] Fig.16 is a flow chart illustrating an example of a read operation of a storage device.

[0023] Fig.17 is a flow chart illustrating an example of a garbage collection operation of a storage device. and

[0024] Fig.18 is a block diagram illustrating an example of an electronic device. DETAILED DESCRIPTION

[0025] Figure 1 is a diagram showing an example of a memory system.

[0026] refer to Figure 1 , the memory system 10 includes a host device 100 and a storage device 200. In addition, the storage device 200 may include a storage controller 210 and a non-volatile memory (NVM) 220. In some embodiments, the host device 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory for temporarily storing data to be sent to or from the storage device 200.

[0027] The storage device 200 may include a storage medium for storing data according to a request from the host device 100. As an example, the storage device 200 may include at least one of a solid state drive (SSD), an embedded memory, or a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device compliant with the non-volatile memory express (NVMe) standard.

[0028] When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device conforming to the Universal Flash Storage (UFS) standard or the Embedded Multimedia Card (eMMC) standard. Each of the host device 100 and the storage device 200 may generate and transmit packets according to the adopted standard protocol.

[0029] When the non-volatile memory 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include other various types of non-volatile memories. For example, the storage device 200 may include a magnetic random access memory (MRAM), a spin-transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and other various types of memory.

[0030] In some embodiments, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. In addition, in some embodiments, the host controller 110 and the host memory 120 may be integrated in the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules provided in the application processor AP, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory provided in the application processor, or a non-volatile memory or memory module provided outside the application processor.

[0031] The host controller 110 may store data (eg, write data) of the buffer in the nonvolatile memory 220 or may manage an operation of storing data (eg, read data) of the nonvolatile memory 220 in the buffer.

[0032] The storage controller 210 may include a host interface 211, a memory interface 212, and a processor 213. In addition, the storage controller 210 may further include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218.

[0033] The memory controller 210 may further include a working memory in which a flash translation layer (FTL) 214 is loaded, and the flash translation layer 214 may be executed by the processor 213 to control data write and read operations of the nonvolatile memory 220 .

[0034] The host interface 211 may transmit and receive packets to and from the host device 100. The packet transmitted from the host device 100 to the host interface 211 may include a command or data to be written into the nonvolatile memory 220, and the packet transmitted from the host interface 211 to the host device 100 may include a response to a command or data read from the nonvolatile memory 220.

[0035] The memory interface 212 may transmit data to be written in the nonvolatile memory 220 to the nonvolatile memory 220 or receive data read from the nonvolatile memory 220. The memory interface 212 may be implemented to comply with a standard specification such as switching or ONFI.

[0036] The flash translation layer 214 may perform various functions such as address mapping, wear leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from a host into a physical address for actually storing data in the non-volatile memory 220. In some embodiments, the L2P translation operation may be performed with reference to the L2P cache 216b and the LPN range map 216c stored in the buffer memory 216 and the L2P pair area stored in the non-volatile memory 220.

[0037] Wear leveling is a technique for allowing blocks in the nonvolatile memory 220 to be used evenly to prevent a particular block from being excessively degraded, and can be implemented, for example, by a firmware technique for balancing the erase counts of physical blocks. Garbage collection is a technique for ensuring that there is sufficient available capacity in the nonvolatile memory 220 by copying valid data of a block to a new block and then erasing the existing block.

[0038] The packet manager 215 may generate a packet according to a protocol of an interface negotiated with the host device 100 , or parse various information from a packet received from the host device 100 .

[0039] The buffer memory 216 may temporarily store data to be written into or read from the nonvolatile memory 220. The buffer memory 216 may be provided in the memory controller 210, but may be arranged outside the memory controller 210 according to an embodiment. In some embodiments, the buffer memory may include a volatile memory, but the present disclosure is not limited thereto.

[0040] In the following, reference will be made to Figures 2 to 5 Describe in more detail Figure 1 Buffer memory 216 of the example.

[0041] Figure 2 It shows that Figure 1 A block diagram of a buffer memory of the memory system 10 is shown. Figure 3 It is shown Figure 2 A view of the L2V table. Figure 4 It is shown Figure 2 A view of the L2P cache. Figure 5 It is shown Figure 2 A view of the LPN range map.

[0042] First, refer to Figure 2 , the buffer memory 216 includes an L2V table 216a, an L2P cache 216b, and an LPN range map 216c, which constitute an L2P map for L2P translation.

[0043] refer to Figure 3 , the L2V table 216 a includes a virtual block number (VBN) of the nonvolatile memory 220 , which corresponds to the LPN received from the host device 100 .

[0044] The non-volatile memory 220 may include, for example, Figure 6 , and each VBN may indicate each virtual block. Each LPN corresponding to each VBN may be stored in the L2V table 216a, as shown.

[0045] refer to Figure 4 , the L2P cache 216b stores a PPN pair (hereinafter, LPN-PPN pair (LPPA)) corresponding to the LPN received from the host device 100. In this embodiment, the L2P cache 216b may store the LPN-PPN pair LPPA of the virtual block that is not closed. In this case, the closing of the virtual block means that the storage capacity allocated to the virtual block is full.

[0046] As will be described later, LPN-PPN pairs LPPA for closed virtual blocks are stored in the L2P pair area of ​​the virtual blocks, and LPN-PPN pairs LPPA for unclosed virtual blocks may be stored in the L2P cache 216 b.

[0047] refer to Figure 5 , the LPN range map 216c stores a portion of the LPNs stored in the L2P pair area of ​​the closed virtual block. For example, when the LPNs stored in the L2P pair area of ​​the closed virtual block are divided into page-sized portions, the LPN range map 216c may store, for example, the last LPN of each page.

[0048] As will be described later, since LPNs stored in the L2P pair area of ​​the virtual block are aligned and stored according to a predetermined reference (eg, ascending order), the last LPN value of each page may be the maximum value among the LPN values ​​of the page to which the corresponding LPN belongs.

[0049] For example, in Figure 5 In the example shown in , the LPN range map 216c can store LPNa, which is the maximum value among the LPN values ​​stored in the first page of the L2P pair area of ​​the virtual block, and LPNb, which is the maximum value among the LPN values ​​stored in the second page thereof. A detailed method for configuring the LPN range map 216c will be described later.

[0050] Return to reference Figure 1 , the ECC engine 217 may perform an error detection and correction function on the read data read from the nonvolatile memory 220. For example, the ECC engine 217 may generate a parity bit for the write data to be written in the nonvolatile memory 220, and the parity bit generated as described above may be stored in the nonvolatile memory 220 together with the write data. When reading data from the nonvolatile memory 220, the ECC engine 217 may correct an error of the read data by using the parity bit read from the nonvolatile memory 220 together with the read data, and may output the error-corrected read data.

[0051] In some embodiments, the ECC engine 217 may perform error correction by using a low-density parity check (LDPC) code. For example, the ECC engine 217 may perform error correction decoding based on data read from the non-volatile memory 220. The ECC engine 217 may determine whether the error correction decoding is successful and output an indication signal based on the determined result. In some embodiments, the ECC engine 217 may perform error correction by using coded modulation such as Bose-Chaudhuri-Hokungum (BCH) code, Turbo code, Reed-Solomon code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM) and block coded modulation (BCM).

[0052] The AES engine 218 may perform at least one of an encryption operation or a decryption operation on data input to the memory controller 210 by using a symmetric key algorithm.

[0053] In the following, reference will be made to Figures 6 to 8 The configuration of the nonvolatile memory 220 according to the present embodiment is described in more detail.

[0054] Figures 6 to 8 It is shown Figure 1 A view of the nonvolatile memory.

[0055] First, refer to Figure 6 , the nonvolatile memory 220 may include a plurality of virtual blocks VB1 to VB3. As described above, each of the virtual blocks VB1 to VB3 may be indicated by VBN.

[0056] refer to Figure 7In some embodiments, the virtual block VB1 may include a plurality of physical blocks. One of the plurality of physical blocks may be allocated to the L2P pair region L2PR for storing LPN-PPN pairs. Physical blocks not allocated to the L2P pair region L2PR among the plurality of physical blocks included in the virtual block VB1 may be allocated to the data region DR for storing data.

[0057] In some embodiments, the plurality of physical blocks may include an SLC block including a single level cell (SLC) and an MLC block including a multi level cell (MLC). The SLC block may be allocated to the L2P pair region L2PR, and the MLC block may be allocated to the data region DR.

[0058] Next, refer to Figure 8 In some embodiments, the virtual block VB1 may include a plurality of physical blocks. Each physical block may include a first portion connected to an SLC word line and a second portion connected to an MLC word line. The first portion of each physical block may be allocated to an L2P pair region L2PR for storing LPN-PPN pairs, and the second portion of each physical block may be allocated to a data region DR for storing data.

[0059] Moreover, in some embodiments, the virtual block VB1 may include a plurality of physical blocks. Each physical block may include an SLC subblock including an SLC and an MLC subblock including an MLC. The SLC subblock of each physical block may be allocated to an L2P pair area L2PR for storing LPN-PPN pairs, and the MLC subblock of each physical block may be allocated to a data area DR for storing data.

[0060] Fig. 9 yes Figure 1 A block diagram of a storage controller and a nonvolatile memory of a storage device is reconfigured.

[0061] refer to Fig. 9 , the storage device 200 includes a nonvolatile memory 220 and a storage controller 210. The storage device 200 may support a plurality of channels CH1 to CHm, and the nonvolatile memory 220 and the storage controller 210 may be connected to each other through the plurality of channels CH1 to CHm. For example, the storage device 200 may be implemented as a storage device such as a solid state drive (SSD).

[0062] The nonvolatile memory 220 may include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the nonvolatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm in a corresponding manner. For example, the nonvolatile memory devices NVM11 to NVM1n may be connected to the first channel CH1 through the channels W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n may be connected to the second channel CH2 through the channels W21 to W2n. In some embodiments, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented in any memory unit that can be operated according to a separate command from the storage controller 210. For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, but the present disclosure is not limited thereto.

[0063] The memory controller 210 may transmit and receive signals to and from the nonvolatile memory 220 through the plurality of channels CH1 to CHm. For example, the memory controller 210 may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the nonvolatile memory 220 through the channels CH1 to CHm, or may receive data DATAa to DATAm from the nonvolatile memory 220.

[0064] The memory controller 210 may select one of the nonvolatile memory devices connected to the corresponding channel through each channel, and may send and receive signals to and from the selected nonvolatile memory device. For example, the memory controller 210 may select the nonvolatile memory device NVM11 from the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 210 may send a command CMDa, an address ADDRa, and data DATAa to the selected nonvolatile memory device NVM11 through the first channel CH1, or may receive data DATAa from the selected nonvolatile memory device NVM11.

[0065] The memory controller 210 may send and receive signals to and from the nonvolatile memory 220 in parallel through different channels. For example, the memory controller 210 may send a command CMDb to the nonvolatile memory 220 through the second channel CH2 while sending a command CMDa to the nonvolatile memory 220 through the first channel CH1. For example, the memory controller 210 may receive data DATAb from the nonvolatile memory 220 through the second channel CH2 while receiving data DATAa from the nonvolatile memory 220 through the first channel CH1.

[0066] The memory controller 210 may control the overall operation of the nonvolatile memory 220. The memory controller 210 may control each of the nonvolatile memory devices NVM11 to NVMmn connected to the channels CH1 to CHm by sending signals to the channels CH1 to CHm. For example, the memory controller 210 may control a selected one of the nonvolatile memory devices NVM11-NVM1n by sending a command CMDa and an address ADDRa to the first channel CH1.

[0067] Each of the nonvolatile memory devices NVM11 to NVMmn may operate under the control of the memory controller 210. For example, the nonvolatile memory device NVM11 may program (or write) data DATAa according to the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the nonvolatile memory device NVM21 may read data DATAb according to the command CMDb and the address ADDRb provided to the second channel CH2, and may transmit the read data DATAb to the memory controller 210.

[0068] although Fig. 9 It is shown that the nonvolatile memory 220 performs communication with the memory controller 210 through "m" channels, and the nonvolatile memory 220 includes "n" nonvolatile memory devices corresponding to each channel, but various modifications may be made to the number of channels and the number of nonvolatile memory devices connected to one channel.

[0069] Fig.10 It is shown Figure 1 A view of a memory controller, memory interface, and nonvolatile memory being reconfigured. Figure 1 The memory interface 212 may include Fig.10 Controller interface circuit 212a.

[0070] The nonvolatile memory 220 may include first to eighth pins P11 to P18 , a memory interface circuit 212 b , a control logic circuit 510 , and a memory cell array 520 .

[0071] The memory interface circuit 212b may receive a chip enable signal nCE from the memory controller 210 through the first pin P11. The memory interface circuit 212b may send and receive signals to and from the memory controller 210 through the second pin P12 to the eighth pin P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit 212b may send and receive signals to and from the memory controller 210 through the second to eighth pins P12 to P18.

[0072] The memory interface circuit 212b can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 210 through the second to fourth pins P12 to P14. The memory interface circuit 212b can receive a data signal DQ from the memory controller 210 or send a data signal DQ to the memory controller 210 through the seventh pin P17. The command CMD, the address ADDR, and the data DATA can be transmitted through the data signal DQ. For example, the data signal DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals.

[0073] The memory interface circuit 212 b may obtain a command CMD from a data signal DQ received in an enable period (e.g., a high level state) of a command latch enable signal CLE based on a switching timing of a write enable signal nWE. The memory interface circuit 212 b may obtain an address ADDR from a data signal DQ received in an enable period (e.g., a high level state) of an address latch enable signal ALE based on a switching timing of a write enable signal nWE.

[0074] In some embodiments, the write enable signal nWE may maintain a static state (e.g., a high level or a low level) and then switch between a high level and a low level. For example, the write enable signal nWE may switch at a cycle of sending a command CMD or an address ADDR. Therefore, the memory interface circuit 212b may obtain the command CMD or the address ADDR based on the switching timing of the write enable signal nWE.

[0075] The memory interface circuit 212b may receive a read enable signal nRE from the memory controller 210 through a fifth pin P15. The memory interface circuit 212b may receive a data strobe signal DQS from the memory controller 210 or send the data strobe signal DQS to the memory controller 210 through a sixth pin P16.

[0076] In the data DATA output operation of the non-volatile memory 220, the memory interface circuit 212b may generate a read enable signal nRE switch through the fifth pin P15 before outputting the data DATA. The memory interface circuit 212b may generate a data strobe signal DQS switch based on the switch of the write enable signal nRE. For example, the memory interface circuit 212b may generate a data strobe signal DQS that starts switching after a predetermined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The memory interface circuit 212b may send a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Therefore, the data DATA may be aligned at the switching timing of the data strobe signal DQS and then sent to the memory controller 210.

[0077] In the data DATA input operation of the nonvolatile memory 220, when the data signal DQ including the data DATA is received from the memory controller 210, the memory interface circuit 212b may receive the switching of the data strobe signal DQS together with the data DATA from the memory controller 210. The memory interface circuit 212b may obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 212b may obtain the data DATA by sampling the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS.

[0078] The memory interface circuit 212b may send a ready / busy output signal nR / B to the memory controller 210 through the eighth pin P18. The memory interface circuit 212b may send the state information of the nonvolatile memory 220 to the memory controller 210 through the ready / busy output signal nR / B. When the nonvolatile memory 220 is in a busy state (i.e., when the internal operation of the nonvolatile memory 220 is being performed), the memory interface circuit 212b may send the ready / busy output signal nR / B indicating the busy state to the memory controller 210. When the nonvolatile memory 220 is in a ready state (i.e., when the internal operation of the nonvolatile memory 220 is completed or not being performed), the memory interface circuit 212b may send the ready / busy output signal nR / B indicating the ready state to the memory controller 210.

[0079] For example, when the nonvolatile memory 220 reads data DATA from the memory cell array 520 in response to a page read command, the memory interface circuit 212 b may transmit a ready / busy output signal nR / B indicating a busy state (e.g., a low level) to the memory controller 210. For example, when the nonvolatile memory 220 programs data DATA to the memory cell array 520 in response to a program command, the memory interface circuit 212 b may transmit a ready / busy output signal nR / B indicating a busy state to the memory controller 210.

[0080] The control logic circuit 510 may control various operations of the nonvolatile memory 220. The control logic circuit 510 may receive the command / address CMD / ADDR acquired from the memory interface circuit 212 b. The control logic circuit 510 may generate control signals for controlling other elements of the nonvolatile memory 220 according to the received command / address CMD / ADDR. For example, the control logic circuit 510 may generate various control signals for programming data DATA in the memory cell array 520 or reading data DATA from the memory cell array 520.

[0081] The memory cell array 520 may store the data DATA acquired from the memory interface circuit 212b under the control of the control logic circuit 510. The memory cell array 520 may output the stored data DATA to the memory interface circuit 212b under the control of the control logic circuit 510.

[0082] The memory cell array 520 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells, but the present disclosure is not limited thereto. The memory cells may be resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, and magnetic random access memory (MRAM) cells. Hereinafter, various examples will be described for memory cells that are NAND flash memory cells.

[0083] The memory controller 210 may include first to eighth pins P21 to P28 and a controller interface circuit 212 a . The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the nonvolatile memory 220 .

[0084] The controller interface circuit 212a may transmit a chip enable signal nCE to the nonvolatile memory 220 through the first pin P21. The controller interface circuit 212a may transmit and receive signals to and from the nonvolatile memory 220 through the second to eighth pins P22 to P28, and the nonvolatile memory 220 is selected by the chip enable signal nCE.

[0085] The controller interface circuit 212a may send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the nonvolatile memory 220 through the second pin P22 to the fourth pin P24. The controller interface circuit 212a may send the data signal DQ to the nonvolatile memory 220 or receive the data signal DQ from the nonvolatile memory 220 through the seventh pin P27.

[0086] The controller interface circuit 212a may transmit the data signal DQ including the command CMD or the address ADDR together with the switching write enable signal nWE to the nonvolatile memory 220. The controller interface circuit 212a may transmit the data signal DQ including the command CMD to the nonvolatile memory 220 according to the transmission of the command latch enable signal CLE having the enable state, and may transmit the data signal DQ including the address ADDR to the nonvolatile memory 220 according to the transmission of the address latch enable signal ALE having the enable state.

[0087] The controller interface circuit 212a may send a read enable signal nRE to the nonvolatile memory 220 through a fifth pin P25. The controller interface circuit 212a may receive a data strobe signal DQS from the nonvolatile memory 220 or send the data strobe signal DQS to the nonvolatile memory 220 through a sixth pin P26.

[0088] In the data DATA input operation of the nonvolatile memory 220, the controller interface circuit 212a may generate a switching read enable signal nRE and may send the read enable signal nRE to the nonvolatile memory 220. For example, the controller interface circuit 212a may generate a read enable signal nRE that changes from a static state (e.g., a high level or a low level) to a switching state before outputting the data DATA. Therefore, the switching data strobe signal DQS may be generated by the nonvolatile memory 220 based on the read enable signal nRE. The controller interface circuit 212a may receive a data signal DQ including data DATA and a switching data strobe signal DQS from the nonvolatile memory 220. The controller interface circuit 212a may obtain data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0089] In the data DATA input operation of the nonvolatile memory 220, the controller interface circuit 212a may generate a switching data strobe signal DQS. For example, the controller interface circuit 212a may generate a data strobe signal DQS that changes from a static state (e.g., a high level or a low level) to a switching state before transmitting the data DATA. The controller interface circuit 212a may transmit a data signal DQ including data DATA to the nonvolatile memory 220 based on the switching timing of the data strobe signal DQS.

[0090] The controller interface circuit 212a may receive the ready / busy output signal nR / B from the nonvolatile memory 220 through the eighth pin P28. The controller interface circuit 212a may determine the state information of the nonvolatile memory 220 based on the ready / busy output signal nR / B.

[0091] Fig.11 It is shown Fig.10 An example of a block diagram of a non-volatile memory.

[0092] Reference Fig.11 , the nonvolatile memory 220 includes a control logic circuit 510, a memory cell array 520, a page buffer unit 550, a voltage generator 530, and a row decoder 540. Fig.11 Although not shown, the nonvolatile memory 220 may also include Fig.10 The memory interface circuit 212b shown in FIG. 1 may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

[0093] The control logic circuit 510 can generally control various operations within the non-volatile memory 220. The control logic circuit 510 can respond to the memory interface circuit ( Fig.10 The control logic circuit 510 may output various control signals according to the command CMD and / or address ADDR of the control logic circuit 510. For example, the control logic circuit 510 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0094] The memory cell array 520 may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), each of which may include a plurality of memory cells. The memory cell array 520 may be connected to the page buffer unit 550 through the bit lines BL, and may be connected to the row decoder 540 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0095] In some embodiments, the memory cell array 520 may include a three-dimensional memory cell array, wherein the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines stacked vertically on a substrate. In some embodiments, the memory cell array 520 may include a two-dimensional memory cell array, wherein the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0096] The page buffer unit 550 may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 3), wherein the plurality of page buffers PB1 to PBn may be connected to the memory cells through the bit lines BL, respectively. The page buffer unit 550 may select at least one of the bit lines BL in response to the column address Y-ADDR. The page buffer unit 550 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a programming operation, the page buffer unit 550 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer unit 550 may sense a current or voltage of the selected bit line to sense the data stored in the memory cell.

[0097] The voltage generator 530 may generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, the voltage generator 530 may generate a programming voltage, a reading voltage, a program verification voltage, an erasing voltage, etc. as the word line voltage VWL.

[0098] The row decoder 540 may select one of the plurality of word lines WL in response to the row address X-ADDR, and may select one of the plurality of string selection lines SSL. For example, the row decoder 540 may apply a program voltage and a program verification voltage to the selected word line during a program operation, and may apply a read voltage to the selected word line during a read operation.

[0099] Fig.12 3D V-NAND structure applicable to nonvolatile memory. When the memory module of the memory device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the memory module may be composed of Fig.12 The equivalent circuit shown in .

[0100] Fig.12 The memory block BLKi shown in 2004 represents a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0101] refer to Fig.12, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 includes a string selection transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground selection transistor GST. Although Fig.12 It is shown that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but the present disclosure is not limited thereto.

[0102] The string selection transistor SST may be connected to the corresponding string selection line SSL1, SSL2 or SSL3. A plurality of memory cells MC1, MC2, ..., MC8 may be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8, respectively. The gate lines GTL1, GTL2, ..., GTL8 may correspond to word lines, and a portion of the gate lines GTL1, GTL2, ..., GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to the corresponding ground selection line GSL1, GSL2 or GSL3. The string selection transistor SST may be connected to the corresponding bit line BL1, BL2 or BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0103] Word lines (eg, WL1) of the same height may be connected in common, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Fig.12 It is shown that the memory block BLK is connected to eight gate lines GTL1 , GTL2 , . . . , GTL8 and three bit lines BL1 , BL2 , and BL3 , but the present disclosure is not limited thereto.

[0104] Fig.13 is a flowchart illustrating an example of a write operation of a storage device. Fig.14A , Fig. 14B and Fig.15 It shows that Fig.13 A view of the operation of a flowchart.

[0105] refer to Fig.13 , a write command is received together with LPN (S100).

[0106] For example, refer to Figure 1 , the memory controller 210 may receive a write command from the host device 100 , the write command instructing to write data in the area addressed to the first LPN.

[0107] Then, refer to Fig.13, determine the virtual block and PPN corresponding to the LPN (S110), and update the L2V table (S120).

[0108] For example, refer to Figure 1 and Figure 3 , the storage controller 210 determines a virtual block that will store data addressed to the first LPN, and determines a PPN that addresses a storage location of the determined virtual block. The storage controller 210 updates the L2V table 216a so that the first LPN corresponds to the determined virtual block.

[0109] Reference Fig.13 , update the L2P cache, and write the data into the virtual block (S130).

[0110] For example, refer to Figure 1 and Fig.14A , the storage controller 210 may update the L2P cache 216b for the determined virtual block, add the LPN-PPN pair to the L2P cache 216b when the first LPN received from the host device 100 is a new LPN, invalidate the previously stored LPN-PPN pair when the first LPN received from the host device 100 is an LPN existing in the L2P cache 216b, and add the LPN-PPN pair to the L2P cache 216b. Therefore, a valid LPN-PPN pair and an invalid LPN-PPN pair may coexist and be stored in the L2P cache 216b of the virtual block that is not closed.

[0111] refer to Figure 1 , Figure 7 and Figure 8 , the storage controller 210 writes the data received from the host device 100 to the location of the determined PPN of the data region DR of the determined virtual block.

[0112] Then, refer to Fig.13 , determine whether the determined virtual block is in a full state (S140).

[0113] When the determined virtual block is not in the full state (S140-No), the corresponding virtual block is not closed. Therefore, step S100 is performed again.

[0114] When the determined virtual block is in a full state (S140-Yes), the corresponding virtual block is closed. Therefore, the LPN-PPN pair of the L2P cache for the closed virtual block is aligned (S150).

[0115] For example, refer to Figure 1 and Fig. 14B, the storage controller 210 may align the LPN-PPN pairs of the L2P cache 216 b for the virtual blocks that need to be closed so that the LPN values ​​are aligned in ascending order.

[0116] exist Fig. 14B In the example shown in , the LPN-PPN pairs may be aligned in the order of LPN3, LPN7, and LPN12. In this example, the LPN-PPN pairs are aligned as described above to facilitate LPN search.

[0117] When an LPN-PPN pair is stored in an L2P pair area of ​​a closed virtual block, in its unaligned state, all L2P pair areas of the virtual block may need to be searched to retrieve an LPN received from the host device 100. That is, the LPN search time may be O(n).

[0118] However, as in this example, when LPN-PPN pairs are aligned and stored in the L2P pair area of ​​the virtual block, the LPN search time can be shortened from O(n) to O(logn).

[0119] Then, refer to Fig.13 , the aligned LPN-PPN pairs are refreshed to the L2P pair area of ​​the virtual block that needs to be closed (S160).

[0120] For example, refer to Figure 1 and Fig.15 , the storage controller 210 may flush the aligned LPN-PPN pairs stored in the L2P cache 216 b to the L2P pair area of ​​the virtual block VB1 that needs to be closed.

[0121] In this case, in the data area of ​​the virtual block VB, data may be stored at the location of each PPN addressed to the L2P pair area through the above-described operation.

[0122] Then, refer to Fig.13 , an LPN range map for the closed virtual block is generated (S170).

[0123] For example, refer to Figure 1 and Figure 5 , the storage controller 210 may divide the LPNs stored in the L2P pair area of ​​the closed virtual block into page-sized portions and generate an LPN range map 216 c of the closed virtual block by using, for example, the last LPN of each page.

[0124] When the storage controller 210 retrieves a PPN corresponding to an LPN received from the host device 100, the LPN range map 216c may be used, and thus a page of an L2P pair area storing a received LPN value may be specified. Therefore, the PPN corresponding to the LPN received from the host device 100 may be retrieved by searching only for LPN-PPN pairs stored in a specified page. Therefore, the performance of the storage device may be improved while implementing the L2P mapping in an on-demand loading manner.

[0125] Fig.16 is a flow chart illustrating an example of a read operation of a storage device.

[0126] refer to Fig.16 , a read command is received together with the LPN (S200).

[0127] For example, refer to Figure 1 , the memory controller 210 may receive a read command having an instruction for reading data stored in the area addressed to the first LPN from the host device 100 .

[0128] Then, refer to Fig.16 , the storage device determines whether the LPN exists in the L2P cache (S210).

[0129] When the first LPN exists in the L2P cache (S210-Yes), this means that data addressed to the first LPN received from the host device 100 is stored in an unclosed virtual block. Therefore, the storage controller 210 determines a PPN corresponding to the first LPN received from the host device 100 in the L2P cache 216b (S220).

[0130] When the first LPN does not exist in the L2P cache (S210-No), this means that the data addressed to the first LPN received from the host device 100 is stored in a closed virtual block. Therefore, the storage controller 210 searches the L2V table for the VBN corresponding to the first LPN to determine a virtual block in which the data addressed to the first LPN received from the host device 100 is stored (S230).

[0131] Then, refer to Fig.16 , an LPN is searched for in an LPN range map (S240), and a PPN corresponding to the LPN is determined (S250).

[0132] For example, refer to Figure 1 and Figure 5, the storage controller 210 searches which page of the L2P pair area of ​​the virtual block stores the first LPN received from the host device 100 in the determined LPN range map of the virtual block. When the search is completed, the storage controller 210 determines a PPN corresponding to the first LPN received from the host device 100 in the search page of the L2P pair area of ​​the virtual block.

[0133] Then, refer to Fig.16 , the data is returned to the host device (S260).

[0134] For example, refer to Figure 1 , the memory controller 210 reads the data stored in the location addressed to the determined PPN from the nonvolatile memory 220 and returns the data to the host device 100 .

[0135] Next, we will refer to Fig.17 Garbage collection operations of a storage device according to some embodiments are described.

[0136] Fig.17 is a flow chart illustrating garbage collection operations of a storage device.

[0137] refer to Figure 1 and Fig.17 When the storage controller 210 determines garbage collection of the old virtual block OLD BLOCK, the storage controller 210 may migrate valid LPN-PPN pairs stored in the L2P pair area L2PR of the old virtual block OLD BLOCK to the L2P pair area L2PR of the new virtual block NEW BLOCK, and may migrate valid data stored in the data area DR of the old virtual block OLD BLOCK to the data area DR of the new virtual block NEW BLOCK. Therefore, when the stored data is migrated, since the LPN-PPN pairs corresponding to the stored data are also migrated, a separate garbage collection operation for the LPN-PPN pairs may be avoided. As a result, the performance of the storage device may be improved while implementing L2P mapping in a load-on-demand manner.

[0138] Fig.18 is a block diagram illustrating an electronic device.

[0139] Reference Fig.18 , the electronic device 601 in the network environment 600 may communicate with the electronic device 602 through a first network 698 such as a short-range wireless communication network, or may communicate with the electronic device 604 or the server 608 through a second network 699 such as a long-range wireless communication network. In some embodiments, the electronic device 601 may be, for example, a notebook computer, a laptop computer, a portable mobile terminal, etc., but the present disclosure is not limited thereto.

[0140] The electronic device 601 may perform communication with the electronic device 604 through the server 608. The electronic device 601 includes a processor 620, a memory 630, an input device 650, a sound output device 655, a display device 660, an audio module 670, a sensor module 676, an interface 677, a connection terminal 678, a haptic module 679, a camera module 680, a power management module 688, a battery 689, a communication module 690, a subscriber identification module (SIM) 696, an antenna module 697, and the like.

[0141] In some embodiments, at least one of the components such as the display device 660 or the camera module 680 may be omitted from the electronic device 601 , or one or more other components may be added to the electronic device 601 .

[0142] In some embodiments, some components may be integrated into a single integrated circuit (IC).For example, a sensor module 676 such as a fingerprint sensor, an iris sensor, and an illumination sensor may be embedded in a display device such as a display.

[0143] The processor 620 may perform various data processing or calculations by executing software (eg, program 640 ) for controlling other components of at least one electronic device 601 , such as hardware or software components connected to the processor 620 .

[0144] As at least part of data processing or computing, the processor 620 may load commands or data received from another component such as a sensor module 676 or a communication module 690 into the volatile memory 632 , process the commands or data stored in the volatile memory 632 , and store the resulting data in the non-volatile memory 634 .

[0145] The processor 620 may include a main processor 621 such as a central processing unit (CPU) or an application processor (AP), and an auxiliary processor 623 that operates independently of the main processor 621 or operates in association with the main processor 621 .

[0146] The auxiliary processor 623 may include, for example, a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP).

[0147] In some embodiments, the auxiliary processor 623 may be configured to consume less power or perform a specific function than the main processor 621. The auxiliary processor 623 may be implemented separately from the main processor 621 or as a part of the main processor 621.

[0148] The auxiliary processor 623 can control at least some functions or states related to at least one component of the electronic device 601 on behalf of the main processor 621 when the main processor 621 is in an inactive state, or control at least some functions or states related to at least one component of the electronic device 601 together with the main processor 621 when the main processor 621 is in an active state.

[0149] The memory 630 may store various data for at least one component of the electronic device 601. The data may include software such as a program 640, and input data and output data of commands associated with the software. The memory 630 may include a volatile memory 632 and / or a non-volatile memory 634. The non-volatile memory 634 may include an internal memory 636 and an external memory 638. In some embodiments, the non-volatile memory 634 may include the above-mentioned storage devices ( Figure 1 storage device 200).

[0150] The program 640 may be stored as software in the memory 630 , and may include, for example, an operating system (OS) 642 , middleware 644 , or an application 646 .

[0151] The input device 650 may receive a command or data intended for another component of the electronic device 601 from the outside of the electronic device 601. The input device 650 may include, for example, a microphone, a mouse, or a keyboard.

[0152] The sound output device 655 can output a sound signal to the outside of the electronic device 601. The sound output device 655 can include, for example, a speaker. Multimedia data can be output through the speaker.

[0153] The display device 660 may visually provide information to the outside of the electronic device 601. The display device 660 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling a corresponding one of the display, the hologram device, or the projector.

[0154] In some embodiments, the display device 660 may include a touch circuit configured to sense a touch, or a sensor circuit configured to measure the intensity of a force generated by a touch, such as a pressure sensor.

[0155] The audio module 670 can convert sound into an electrical signal, and vice versa. In some embodiments, the audio module 670 can obtain sound via the input device 650, or can output sound via the sound output device 655 or the earphone of the external electronic device 602 directly or wirelessly connected to the electronic device 601.

[0156] The sensor module 676 can sense the operating state (e.g., power or temperature) of the electronic device 601 or the external environment state (e.g., user state) of the electronic device 601, and can generate an electrical signal or data value corresponding to the sensed state. The sensor module 676 can include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0157] The interface 677 may support one or more prescribed protocols used by the electronic device 601 directly or wirelessly connected to the external electronic device 602. In some embodiments, the interface 677 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0158] The connection terminal 678 may include a connector through which the electronic device 601 may be physically connected to the external electronic device 602. In some embodiments, the connection terminal 678 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0159] The haptic module 679 may convert an electrical signal into a mechanical stimulus, such as vibration or motion, which may be recognized by a user through a tactile sense or a kinesthetic sense. In some embodiments, the haptic module 679 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0160] The camera module 680 can capture still images and moving images. In some embodiments, the camera module 680 can include one or more lenses, image sensors, image signal processors, or flashes.

[0161] The power management module 688 may manage power supplied to the electronic device 601. For example, the power management module 688 may be implemented as at least a portion of a power management integrated circuit (PMIC), for example.

[0162] The battery 689 may supply power to at least one component of the electronic device 601. According to one embodiment, the battery 689 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0163] The communication module 690 may support establishment of a direct communication channel or a wireless communication channel between the electronic device 601 and an external electronic device (eg, the electronic device 602 , the electronic device 604 , or the server 608 ), and may perform communication through the established communication channel.

[0164] The communication module 690 may include one or more communication processors that may operate independently of the processor 620 and support direct or wireless communications.

[0165] In some embodiments, the communication module 690 may include a wireless communication module 692 (such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 694 (such as a local area network (LAN) communication module or a power line communication (PLC) module).

[0166] The corresponding communication modules in these communication modules can communicate with each other via the first network 698 (for example, Bluetooth TM , Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA) standards) or a second network 699 (eg, a mobile communication network, the Internet, a telecommunication network, etc.) to perform communication with an external electronic device.

[0167] These various types of communication modules may be implemented as a single component, or may be implemented as multiple components separated from each other. The wireless communication module 692 may identify or authenticate the electronic device 601 within a communication network (such as the first network 698 or the second network 699) by using user information (e.g., an International Mobile Subscriber Identifier (IMSI)) stored in the user identification module 696.

[0168] The antenna module 697 may transmit or receive a signal or power to or from the outside of the electronic device 601. In some embodiments, the antenna module 697 may include one or more antennas, and at least one antenna suitable for a communication scheme used in a communication network (e.g., the first network 698 or the second network 699) may be selected from the antennas by the communication module 690. Then, a signal or power may be transmitted or received between the communication module and the external electronic device via the selected at least one antenna.

[0169] At least some of the above components may be interconnected to transmit signals therebetween via an inter-peripheral communication scheme such as a bus, general purpose input and output (GPIO), a serial peripheral interface (SPI), and a mobile industry processor interface (MIPI).

[0170] In some embodiments, commands or data may be sent or received between the electronic device 601 and the external electronic device 604 via a server 608 connected to the second network 699. The electronic devices 602 and 604 may be devices of the same or different types as the electronic device 601. All or some operations to be performed in the electronic device 601 may be performed in one or more external electronic devices 602 and 604. For example, all or some operations to be performed in the electronic device 601 may be performed in one or more external electronic devices 602 and 604.

[0171] For example, when the electronic device 601 needs to automatically or in response to a request from a user or another device to perform a function or service, the electronic device 601 can request one or more external electronic devices to perform at least a part of the function or service, rather than performing the function or service by itself. One or more external electronic devices that have received the request can perform at least a part of the requested function or service, or an additional function or service associated with the request, and the result of the execution can be forwarded to the electronic device 601. The electronic device 601 provides the result as at least a part of the response to the request with or without additional processing of the result. To this end, for example, cloud computing, distributed computing, or client-server computing technology can be used.

[0172] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection claimed. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0173] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it is obvious to those skilled in the art that the present disclosure can be manufactured in various forms without being limited to the above embodiments, and can be embodied in other specific forms without departing from the technical spirit and basic characteristics of the present disclosure. Therefore, the above embodiments are considered to be illustrative and not restrictive in all aspects.

Claims

1. A storage device, comprising: A non-volatile memory comprising a virtual block, the virtual block comprising: a logical page number to physical page number L2P pair area configured to store a pair LPN-PPN pair of a logical page number LPN and a physical page number PPN, and a data area configured to store data addressed to the PPN; A volatile memory comprising: a logical page number to virtual block number L2V table configured to store a virtual block number VBN corresponding to the LPN, an L2P cache configured to store the LPN-PPN pairs, and an LPN range map configured to store a portion of the LPNs stored in the L2P pair region of the virtual block; and A controller is configured to control the nonvolatile memory and the volatile memory.

2. The storage device according to claim 1, wherein the virtual block comprises a plurality of physical blocks, wherein the plurality of physical blocks include single-level cell (SLC) blocks and multi-level cell (MLC) stack blocks, the SLC blocks include SLCs, the MLC stack blocks include MLCs, and The L2P pair area is set in the SLC block.

3. The storage device according to claim 1, wherein: The dummy block includes a first portion connected to an SLC word line and a second portion connected to an MLC word line, and The L2P pair area is set in the first part.

4. The storage device according to claim 1, wherein: The L2P pair area includes a first page and a second page, and Wherein the LPN range map includes one of a first plurality of LPNs stored in the first page and one of a second plurality of LPNs stored in the second page.

5. The storage device according to claim 1, wherein: The virtual blocks include a first virtual block that is turned off and a second virtual block that is not turned off, and wherein the controller is configured to: based on receiving a write command from a host device indicating to write first data in an area addressed to a first LPN: determining a position of a first PPN addressed to the second virtual block as a position for storing the first data, updating the L2V table based on data indicative of the determined position, generating a first LPN-PPN pair configured to allow the first PPN to correspond to the first LPN of the second virtual block, updating the L2P cache based on the first LPN-PPN pair, and The first data is stored in a location addressed to a first PPN of the second virtual block.

6. The storage device of claim 5 , wherein the controller is configured to flush the LPN-PPN pairs stored in the L2P cache to the L2P pair area of ​​the second virtual block based on determining that the second virtual block is full based on the LPN-PPN pairs stored in the L2P cache and the data stored in the data area of ​​the second virtual block. 7 . The storage device of claim 6 , wherein the controller is configured to align the LPN-PPN pairs stored in the L2P cache based on the LPNs before flushing the LPN-PPN pairs stored in the L2P cache to the L2P pair area of ​​the second virtual block. 8 . The storage device of claim 7 , wherein the controller is configured to generate an LPN range map for the second virtual block based on the aligned LPN-PPN pairs.

9. The storage device according to claim 1, wherein: The controller is configured to, based on receiving a read command from a host device instructing to read data stored in a region addressed to the first LPN: determining whether the first LPN exists in the L2P cache, Based on the first LPN being present in the L2P cache, determining a PPN corresponding to a first LPN in the L2P cache, and returning data stored in a location addressed to the determined PPN to the host device, and Based on the first LPN not being present in the L2P cache, determining a VBN corresponding to a first LPN in the L2V table, determining a PPN corresponding to a first LPN in an L2P pair region of a virtual block corresponding to the determined VBN, and The data stored in the location addressed to the determined PPN is returned to the host device.

10. The storage device of claim 9, wherein the controller is configured to search for a first LPN in an LPN range map for the virtual block corresponding to the determined VBN, and access the L2P pair area of ​​the virtual block corresponding to the determined VBN based on searching for the first LPN.

11. The storage device according to claim 1, wherein: The virtual block includes a first virtual block and a second virtual block, and The controller is configured to migrate valid LPN-PPN pairs stored in an L2P pair area of ​​the first virtual block to an L2P pair area of ​​the second virtual block and migrate valid data stored in a data area of ​​the first virtual block to a data area of ​​the second virtual block in response to determining garbage collection of the first virtual block.

12. A storage device comprising: a non-volatile memory comprising a first virtual block and a second virtual block; Volatile memory; as well as a controller connected to the nonvolatile memory and the volatile memory, wherein each of the first virtual block and the second virtual block includes (i) a logical page number to physical page number L2P pair area configured to store a pair of LPN-PPN pairs of logical page numbers LPN and physical page numbers PPN and (ii) a data area storing data addressed to the PPN, and The controller is configured to migrate valid LPN-PPN pairs stored in the L2P pair area of ​​the first virtual block to the L2P pair area of ​​the second virtual block and migrate valid data stored in the data area of ​​the first virtual block to the data area of ​​the second virtual block based on determining garbage collection of the first virtual block.

13. The storage device according to claim 12, wherein: The volatile memory is configured to store the LPN-PPN pair, and The controller is configured to refresh the LPN-PPN pairs stored in the volatile memory to the L2P pair area of ​​the third virtual block in response to the storage device determining that a third virtual block in the virtual blocks of the non-volatile memory is full based on the LPN-PPN pairs and the data addressed to the PPN.

14. The memory device of claim 13, wherein the third virtual block comprises a first portion connected to an SLC word line and a second portion connected to an MLC word line, and in, The controller is configured to refresh the LPN-PPN pairs to the first portion.

15. A method for operating a storage device, the storage device comprising a volatile memory, a nonvolatile memory and a controller, the nonvolatile memory comprising a virtual block, the virtual block having an L2P pair area for storing an LPN-PPN pair and a data area configured to store data addressed to the PPN, the controller being used to control the volatile memory and the nonvolatile memory, the method comprising: receiving a write command from a host device, the write command having an instruction for writing first data in an area addressed to a first LPN; determining that a location of a first PPN addressed to a virtual block addressed to a first VBN is a location for storing the first data; Based on the determined location, i) storing a pair of the first LPN and the first VBN in an L2V table of the volatile memory, and ii) storing a pair of the first LPN and the first PPN in an L2P cache of the volatile memory; storing the first data in a location addressed to a first PPN of the virtual block; as well as determining that the virtual block is full based on LPN-PPN pairs stored in the L2P cache and data stored in a data area of ​​the virtual block; as well as Based on a determination that the virtual block is full, LPN-PPN pairs stored in the L2P cache are flushed to an L2P pair area of ​​the virtual block. 16 . The operating method of claim 15 , further comprising aligning the LPN-PPN pairs stored in the L2P cache based on the LPNs before flushing the LPN-PPN pairs stored in the L2P cache to the L2P pair area of ​​the virtual block. 17 . The operating method of claim 16 , further comprising generating an LPN range map for a virtual block in the volatile memory based on the aligned LPN-PPN pairs.

18. The operating method according to claim 17, wherein: The L2P pair area of ​​the virtual block includes a first page and a second page, and Wherein the LPN range map includes one of a first plurality of LPNs stored in the first page and one of a second plurality of LPNs stored in the second page.

19. The operating method according to claim 15, wherein the virtual block includes a plurality of physical blocks, wherein the plurality of physical blocks include SLC blocks and MLC blocks, the SLC blocks include SLCs, and the MLC blocks include MLCs, and The L2P pair area is set in the SLC block.

20. The operating method according to claim 15, wherein the dummy block includes a first portion connected to an SLC word line and a second portion connected to an MLC word line, and The L2P pair area is set in the first part.

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