Method for operating non-volatile memory

Abstract

The present specification relates to a method of operation of a non-volatile memory, comprising, after comparing attributes of a transaction with access attributes of a sector of the memory, verifying the transaction requesting modification of a configuration value of the sector of the memory.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority of French Patent Application No. FR2312668, entitled "Procédé de fonctionnement d’une mémoire non volatile", filed on November 17, 2023. Technical field

[0003] The present disclosure generally relates to methods for operating non-volatile memories and to electronic circuits implementing such methods. Background art

[0004] Many electronic circuits, such as microcontrollers, use applications loaded into the non-volatile memory of the circuit, for example, a boot program. These applications may desire to configure certain sectors of the non-volatile memory. However, malicious applications may desire to modify the configuration of memory sectors linked to other applications. Summary of the invention

[0005] There is a need to provide methods for operating non-volatile memories that prevent malicious applications from modifying the configuration of memory sectors while allowing the configuration of memory sectors throughout the life cycle of the circuit.

[0006] Embodiments overcome all or part of the drawbacks of known methods.

[0007] Embodiments provide a method for operating a non-volatile memory, including verifying a transaction that requests to modify a configuration value of a sector of the memory after comparing an attribute of the transaction with an access attribute of the sector of the memory.

[0008] According to an embodiment, the transaction is verified when the security level of all attributes of the transaction is higher than or equal to the corresponding access attribute of the sector of the memory.

[0009] According to an embodiment, a register with an associated table is configured to store the configuration value of each memory sector.

[0010] According to an embodiment, the value of a given index bit of the table corresponds to the configuration value of the sector having the same index.

[0011] According to an embodiment, the memory interface is configured to allow or reject a transaction based on the attribute of the transaction and the access attribute of the memory sector.

[0012] According to an embodiment, the memory interface is configured to implement the register using the associated table.

[0013] According to an embodiment, the verification of the transaction is performed by the memory interface.

[0014] According to an embodiment, the attributes of a transaction are the attributes of the application that implements the transaction.

[0015] According to an embodiment, the attributes of a transaction include an access restriction level, an addressing mode restriction level, and a program access prohibition level selected from a first program access prohibition level, a second program access prohibition level, and a third program access prohibition level; and the attributes of a sector include an access restriction level, an addressing mode restriction level, and a program access prohibition level selected from a fourth program access prohibition level, a fifth program access prohibition level, and a sixth program access prohibition level.

[0016] According to an embodiment, a transaction having an attribute corresponding to a first access restriction level can access a sector having a first access restriction level or a second access restriction level; a transaction having an attribute corresponding to a first addressing mode restriction level can access a sector having a second addressing mode restriction level; a transaction having an attribute corresponding to a second access restriction level cannot access a sector having a first access restriction level; and a transaction having an attribute corresponding to a second addressing mode restriction level cannot access a sector having a first addressing mode restriction level.

[0017] According to an embodiment, a transaction having an attribute corresponding to a first program access prohibition level can access a sector having a fourth program access prohibition level, a fifth program access prohibition level, or a sixth program access prohibition level as an attribute; a transaction having an attribute corresponding to a second program access prohibition level can access a sector having a fifth protection level and a sixth protection level as attributes, but cannot access a sector having a fourth program access prohibition level as an attribute; and a transaction having an attribute corresponding to a third program access prohibition level can access a sector having a sixth program access prohibition level as an attribute, but cannot access a sector having a fourth program access prohibition level or a fifth program access prohibition level as an attribute.

[0018] According to an embodiment, the attributes of a memory sector are either the attributes of a previous transaction or default attributes defined by a first access restriction level, a second addressing mode restriction level, and a fourth program access prohibition level.

[0019] According to an embodiment, the configuration value corresponds to a loop mode, a write protection mode, or a write mode.

[0020] An embodiment provides an electronic circuit configured to implement the above method, including a non-volatile memory interface and a non-volatile memory.

[0021] An embodiment provides a method for operating a non-volatile memory, wherein:

[0022] - The successive first and second transactions request to modify the configuration values of the same storage area of the non-volatile memory, and the security level of the attributes of the first transaction is higher than the security level of the attributes of the second transaction; and

[0023] - The second transaction is rejected. Description of the Drawings

[0024] The above and other features and advantages will be described in detail with reference to the accompanying drawings in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, in which:

[0025] Figure 1 An example of an integrated circuit of the type to which the embodiments are applicable is shown very schematically and in block diagram form;

[0026] Figure 2 An example of an Figure 1 operating method of the circuit is shown;

[0027] Figure 3 An Figure 1 operating method of the circuit according to an embodiment is shown;

[0028] Figure 4 An Figure 3 operating method of the circuit according to an embodiment is shown; and

[0029] Figure 5 An Figure 3 operating method of the circuit according to an embodiment is shown. Detailed Description of the Embodiments

[0030] Similar features in the various figures have been denoted by similar reference numerals. In particular, the common structural and / or functional features among the various embodiments may have the same reference numerals, and the same structure, dimensions, and material properties may be deployed.

[0031] For clarity, only those steps and elements that contribute to an understanding of the embodiments are shown and described in detail.

[0032] Unless otherwise indicated: when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0033] In the following description, when referring to absolute position determiners such as "front", "rear", "top", "bottom", "left", "right", etc., or relative position determiners such as "top", "bottom", "upper", "lower", etc., or orientation determiners such as "horizontal", "vertical", etc., unless otherwise specified, they all refer to the orientation of the drawings.

[0034] Unless otherwise specified, the expressions "about", "approximate", "substantially", and "roughly" mean plus or minus 10%, preferably plus or minus 5%.

[0035] Figure 1 An example of an integrated circuit 100 of the type to which the embodiments are applicable is shown very schematically and in the form of a block diagram. The circuit 100 is, for example, a microcontroller.

[0036] The circuit 100 includes a non-volatile memory 104 (NVM) (for example, of the FLASH or phase change memory (PCM) type), which is capable of communicating via a communication bus 114 with a non-volatile memory interface 106 (NYM interface), which is configured to write data to or read data from the non-volatile memory 104.

[0037] The circuit 100 also includes, for example, a processing unit 110 (CPU), which includes one or more processors under the control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is, for example, a volatile random access memory (RAM). The processing unit 110 and the memory 112 communicate, for example, via a system (data, address, and control) bus 140. The non-volatile memory 104 is coupled to the system bus 140 via the non-volatile memory interface 106 and via the bus 114. The device 100 also includes an input / output interface 108 (I / O interface) coupled to the system bus 140 for external communication.

[0038] The circuit 100 may integrally implement other circuits for other functions (for example, one or more volatile and / or non-volatile memories, or other processing units), symbolized by block 116 (FCT) in Figure 1 Among these other circuits, the circuit 100 includes, for example, a read-only or static memory 118 (ROM).

[0039] Figure 2 An example of Figure 1 the operation method of the circuit is shown.

[0040] More particularly, Figure 2 an example of the operation method of the memory 104 is shown.

[0041] In the illustrated example, data related to a first application, a second application, and a third application (App1, App2, and App3) is stored in different sectors of the memory 104. The applications App1, App2, and App3 are defined as having attributes including an access permission or access restriction level, a privilege level, and a program access prohibition level.

[0042] The access restriction level of an application defines, for example, the accessibility of a memory area. The privilege level of an application defines, for example, an addressing mode restriction. The program access prohibition level defines, for example, a prohibition on accessing other applications, or a prohibition on data used by other applications.

[0043] Access to different sectors is achieved by the application implementing a transaction.

[0044] In the example, an application defined as having a first access restriction level (secure, Sec) has more permissions than an application having a second access restriction level (non-secure, NS). The first access restriction level and the second access restriction level are implemented, for example, using the TrustZone protocol of the ARM® CORTEX-M architecture. In the example, an application defined as having a first privilege level (privileged, Priv) has more permissions than an application having a second privilege level (unprivileged, unPriv). The first privilege level and the second privilege level are, for example, those privilege levels implemented using the ARM architecture. An application implemented in the first privilege mode (Priv) (in other words, in the first addressing mode restriction mode) has, for example, its own space with physical addresses. An application implemented in the second privilege mode (unPriv) (i.e., in the second addressing mode restriction mode) has, for example, its own space with virtual addresses and cannot access other processes linked to the memory that will directly use physical addresses. In the example, an application defined as having a first program access prohibition level HDPL1 has more permissions than an application having a second program access prohibition level HDPL2. Similarly, an application defined as having a second program access prohibition level HDPL2 has more permissions than an application having a third program access prohibition level HDPL3. The program access prohibition levels HDPL1, HDPL2, and HDPL3 correspond to, for example, the protection levels of successively installed boot programs, such that a later installed boot program cannot access a previously installed boot program. The protection level is implemented, for example, by using a monotonic counter.

[0045] In this document, a transaction implemented by an application has the same attributes as the application implementing the transaction.

[0046] The sectors of the memory 104 are defined as having different access attributes. These access attributes are, for example, an access permission or restriction level, a privilege level, and a program access prohibition level.

[0047] Sectors can be defined, for example, as having a first access restriction level Sec or a second access restriction level NS. Thus, an application defined as having the second access restriction level NS cannot access a sector defined as having the first access restriction level Sec. An application defined as having the first access restriction level Sec can access a sector defined as having the first access restriction level Sec or the second access restriction level NS.

[0048] Sectors can also be defined as having a first privilege level Priv or a second privilege level unPriv. Thus, an application defined as having the second privilege level unPriv cannot access a sector defined as having the first privilege level Priv. An application defined as having the first privilege level Priv can access an area defined as having the first privilege level Priv or the second privilege level unPriv.

[0049] Sectors can also be defined as having a fourth program access prohibition level OB-HDP, a fifth program access prohibition level HDP-EXT, or a sixth program access prohibition level non-HDP. Thus, an application defined as having a first program access prohibition level HDPL1 (which is, for example, the first boot program stage) can access a sector defined as having the fourth program access prohibition level OB-HDP, the fifth program access prohibition level HDP-EXT, or the sixth program access prohibition level non-HDP. An application defined as having a second program access prohibition level HDPL2 (which is, for example, the second boot program stage) can access a sector defined as having the fifth protection level HDP-EXT or the sixth protection level non-HDP, but cannot access a sector defined as having the fourth program access prohibition level OB-HDP. An application defined as having a third program access prohibition level HDPL3 (which is, for example, the third boot program stage) can access a sector defined as having the sixth program access prohibition level non-HDP, but cannot access a sector defined as having the fourth program access prohibition level OB-HDP or the fifth program access prohibition level HDP-EXT.

[0050] In addition to the attributes, each sector in the memory 104 is also configured with one or more configuration values, which are stored in registers and, for example, correspond to a high cycling mode (HCD), a write protection mode, or a write mode.

[0051] In the write protection mode, sectors with this configuration do not accept write access requests. However, they can be read.

[0052] In the example shown, the memory sectors of the memory 104 (denoted by reference numerals sector #0, sector #1, sector #2) are used by the first application App1.

[0053] One disadvantage of the example shown is the fact that the sector configuration values written by an application with a given protection level may be modified by an application with fewer permissions. Thus, in the example, an application App1 with a program access prohibition level HDPL1 can write the configuration values of sectors #0, #1, and #2 to HCD. An application App2 with a program access prohibition level HDPL2 can, for example, deactivate the HCD mode of these sectors, which may result in a denial of service.

[0054] In another example, an application App1 whose attributes are defined to have a first access restriction level Sec, a first privilege level Priv, and a program access prohibition level HDPL1 has written the configuration values of sectors #0, #1, and #2 to write protection. An application App2 whose attributes are defined to have a first access restriction level Sec, a second privilege level unPriv, and a program access prohibition level HDPL2 can, for example, reduce the number of sectors configured in the write protection mode. This results in a modification of application App1.

[0055] Another disadvantage of the example shown is that the (one or more) configuration values are not available throughout the product life cycle, which is limiting.

[0056] To overcome these disadvantages, the described embodiments provide a method of operating a memory 104, including verifying a transaction that requests to modify the configuration value of a sector of the memory after comparing the attributes of the transaction with the access attributes of the sector of the memory 104.

[0057] This enables the memory sectors to be available to all applications without compromising security. In addition, different configurations of the sectors remain available to all applications at each step of the product life cycle (e.g., during customization by different subcontractors).

[0058] Figure 3 Shows an operating method of a Figure 1 circuit according to an embodiment.

[0059] At step 302 (start), the process begins.

[0060] In the next step 303 (application transaction requests a change to the memory sector configuration register), a transaction generated by an application requests a change to the configuration value related to a sector referenced, for example, using index "i". In other words, the transaction requests a write to the configuration register.

[0061] At subsequent step 304 (Do transaction attributes match sector attributes?), the memory interface 106 checks the consistency between the attributes of the transaction (in other words, the attributes of the application implementing the transaction) and the access attributes of the sector of index "i". If the application issuing the transaction has permission to access the sector with identifier "i", then the transaction is accepted (branch Y) at subsequent step 305 (Transaction verified). If the application issuing the transaction does not have permission to access the sector with identifier "i", then the transaction is rejected (branch N) at subsequent step 306 (End process), and an error is returned via bus 114, or for example no response (an operation called write ignore).

[0062] Steps 302 to 306 are performed, for example, at any point in the product life cycle.

[0063] In the example, a register with an associated table (bitmap register) is used to store the configuration values of each sector. In this case, the value of bit "i" of the register of the configuration values corresponds to the configuration value of the sector referenced using index "i". The implementation of the associated table allows for an easy implementation.

[0064] The following Tables 1, 2, and 3 summarize the cases where the security level of the transaction attributes is higher than the access attributes of sector "i". In other words, if the authorization to access bit "i" of the configuration register of sector "i" is accepted, then the security level of the transaction attributes requesting a write access to the configuration register of the sector is higher than or equal to the access attributes of sector "i". In other words, when the permissions of the application implementing the transaction are higher than or equal to the access attributes of the sector, the security level of the attributes of the transaction is higher than or equal to the access attributes of the sector.

[0065] Table 1

[0066] Attributes of a transaction requesting write access to a sector configuration register Authorization to access bit "i" of the configuration register of sector "i" HDPL1 Accepted for all bits and protection levels HDPL2 Accepted for bit "i" of the configuration register only if sector "i" has the fifth program access prohibition level HDP-EXT or the sixth program access prohibition level non-HDP as an attribute HDPL3 Accepted for bit "i" of the configuration register only if sector "i" has the sixth non-HDP program access prohibition level as an attribute

[0067] Table 2

[0068] Attributes of a transaction requesting write access to a sector configuration register Authorization to access bit "i" of the configuration register of sector "i" Sec Accepted for bit "i" of the configuration register if sector "i" has the first access restriction level Sec or the second access restriction level NS as an attribute NS Accepted for bit "i" of the configuration register only if sector "i" has the second access restriction level NS as an attribute

[0069] Table 3

[0070] Attributes of a transaction requesting write access to a sector configuration register Authorization to access bit "i" of the configuration register of sector "i" Priv Accepted for bit "i" of the configuration register if sector "i" has the first privilege level Priv or the second privilege level unPriv as an attribute unPriv Accepted for bit "i" of the configuration register only if sector "i" has the second privilege level unPriv as an attribute

[0071] If any of the three tables does not accept the authorization to access bit "i" of the configuration register of sector "i", then the transaction is ignored (command write ignore) or rejected.

[0072] In the example, by default, the memory sectors are defined by a first access restriction level (Sec), a second addressing mode restriction level (unPriv), and a fourth program access prohibition level (OB-HDP) upon reset.

[0073] Figure 4 shows an operation method of the circuit shown in accordance with an embodiment. More particularly, Figure 3 an example of Figure 4 shows a case where application App1 has a first access restriction level Sec, a first privilege level Priv, and a first program access prohibition level HDPL1 as attributes. In the example shown, application App2 has a first access restriction level Sec, a first privilege level Priv, and a second program access prohibition level HDPL2 as attributes. In this example, application App1 reserves the sector with index i = 8 by using the memory interface 106 and by defining the sector with index i = 8 as having a first access restriction level Sec, a first privilege level Priv, and a fourth program access prohibition level OB-HDP. Application 1 configures sector 8 to have one of a high cycle mode HCD, a write protection mode, or a write mode, for example, by changing the bits of index 8 in a configuration register (write mode register). Then, in the example shown, application App2 attempts to modify the value of the bits of index 8 in the register containing the configuration value write mode register. By applying Figure 3 the method of

[0074] Figure 5 shows an operation method of the circuit shown in accordance with an embodiment. Figure 3 of

[0075] More particularly, Figure 5 an example of application App1 and application App2 is similar to the example of Figure 4 In addition, a third application App3 has a second access restriction level NS, a first privilege level Priv, and a second program access prohibition level HDPL2 as attributes. In this example, application App3 has reserved the sector with index i = 14 by using the memory interface 106 and by defining the sector with index i = 14 as having a second access restriction level NS, a first privilege level Priv, and a fifth program access prohibition level HDP-EXT. Application 3 configures sector 14 to have one of a high cycle mode HCD, a write protection mode, or a write mode, for example, by changing the bits of index 14 in a configuration register (write mode register). Then, in the example shown, application App2 attempts to modify the value of the bits of index 14 in the register containing the configuration value write mode register. By applying Figure 3The method is such that App2 is authorized by the memory interface 106 to modify the value at the bit at index 14 of the configuration register (in other words, the configuration value of the sector at index 14), because the permission level of the transaction (here the first access restriction mode Sec) enables it to access the sector configured with the second access restriction level NS.

[0076] A variety of embodiments and variant embodiments have been described. Those skilled in the art will understand that certain features of these various embodiments and variant embodiments can be combined, and those skilled in the art will conceive of other variant embodiments. In particular, sector configuration values other than those corresponding to the configuration values for the high cycle mode HCD, write protection mode, or write mode can be implemented.

[0077] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variant embodiments is within the capabilities of those skilled in the art. In particular, although the disclosed examples use registers with an associated table, it can be implemented without an associated table Figure 3 of the method, however, this is not conducive to the simplicity of the implementation.

[0078] The operating method of the non-volatile memory can be summarized as including verifying a transaction and requesting to modify the configuration value (HCD, write protection, write mode) of the sector of the memory after comparing the attributes of the transaction with the access attributes of the sector of the memory.

[0079] When the security level of all attributes of the transaction is higher than or equal to the corresponding access attribute of the sector of the memory, the transaction can be verified.

[0080] Registers with an associated table can be configured to store the configuration values of each sector of the memory.

[0081] The value of the bit at a given index of the table can correspond to the configuration value of the sector with the same index.

[0082] The memory interface (106) can be configured to authorize or reject a transaction based on the attributes of the transaction and based on the attributes of the access to the sector of the memory.

[0083] The memory interface (106) can be configured to implement the register (write mode register) using an associated table.

[0084] The verification of the transaction can be performed by the memory interface (106).

[0085] The attributes of the transaction can be the attributes of the application (App1, App2, App3) implementing the transaction.

[0086] The attributes of a transaction may include an access restriction level (Sec, NS), an addressing mode restriction level (Priv, unPriv), and a program access prohibition level selected from a first program access prohibition level, a second program access prohibition level, and a third program access prohibition level (HDPL1, HDPL2, HDPL3); and the attributes of a sector may include an access restriction level (Sec, NS), an addressing mode restriction level (Priv, unPriv), and a program access prohibition level selected from a fourth program access prohibition level, a fifth program access prohibition level, and a sixth program access prohibition level (OB-HDP, HDP-EXT, non-HDP).

[0087] A transaction having an attribute corresponding to a first access restriction level (Sec) may access a sector having a first access restriction level or a second access restriction level (Sec, NS); a transaction having an attribute corresponding to a first addressing mode restriction level (Priv) may access a sector having a second addressing mode restriction level (unPriv); a transaction having an attribute corresponding to a second access restriction level (NS) may not access a sector having a first access restriction level (Sec); and a transaction having an attribute corresponding to a second addressing mode restriction level (unPriv) may not access a sector having a first addressing mode restriction level (Priv).

[0088] A transaction having an attribute corresponding to a first program access prohibition level (HDPL1) may access a sector having a fourth program access prohibition level, a fifth program access prohibition level, or a sixth program access prohibition level (OB-HDP, HDP-EXT, non-HDP) as an attribute; a transaction having an attribute corresponding to a second program access prohibition level (HDPL2) may access a sector having a fifth protection level and a sixth protection level (HDP-EXT, non-HDP) as an attribute, but may not access a sector having a fourth program access prohibition level (OB-HDP) as an attribute; and a transaction having an attribute corresponding to a third program access prohibition level (HDPL3) may access a sector having a sixth program access prohibition level (non-HDP) as an attribute, but may not access a sector having a fourth program access prohibition level or a fifth program access prohibition level (OB-HDP, HDP-EXT) as an attribute.

[0089] The attributes of a memory sector may either be the attributes of a previous transaction or default attributes defined by a first access restriction level (Sec), a second addressing mode restriction level (unPriv), and a fourth program access prohibition level (OB-HDP).

[0090] Configuration values may correspond to a loop mode (HCD, power mode, user mode), a write protection mode, or a write mode.

[0091] An electronic circuit (100) can be summarized as including a non-volatile memory interface (106) and a non-volatile memory (104), which are configured to implement the method according to any one of the appended claims.

[0092] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications cited in this specification and / or listed in the application data sheet are hereby incorporated by reference in their entirety. Aspects of the embodiments may be modified as needed to employ concepts of multiple patents, applications, and publications to provide yet further embodiments.

[0093] Based on the description of the foregoing detailed description, these and other changes may be made to the embodiments. In general, in the appended claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Thus, the claims are not limited by the disclosure.

Claims

1. A method for operating a non-volatile memory, comprising: After comparing the attributes of the transaction with the access attributes of the sector of the memory in question: verifying the transaction; as well as A request is made to modify a configuration value of the sector of the memory. 2 . The method of claim 1 , wherein the transaction is verified when the security levels of all attributes of the transaction are higher than or equal to corresponding access attributes of the sector of the memory.

3. The method of claim 1, wherein a register having an association table is configured to store a corresponding configuration value for each sector of the memory. 4 . The method according to claim 3 , wherein the value of the bit of the index of the table corresponds to the configuration value of the sector having the index. 5 . The method of claim 1 , wherein a memory interface is configured to authorize or deny the transaction based on attributes of the transaction and attributes of access to the sector of the memory. The method of claim 5 , wherein the memory interface is configured to implement registers with an association table. The method of claim 5 , wherein verifying the transaction is performed by the memory interface. The method of claim 1 , wherein the attribute of the transaction is an attribute of an application implementing the transaction.

9. The method according to claim 1, wherein: The attributes of the transaction include an access restriction level, an addressing mode restriction level, and a program access prohibition level selected from a first level group including a first program access prohibition level, a second program access prohibition level, and a third program access prohibition level; and The attributes of the sector include an access restriction level, an addressing mode restriction level, and a program access prohibition level selected from a second level group including a fourth program access prohibition level, a fifth program access prohibition level, and a sixth program access prohibition level.

10. The method according to claim 9, wherein: A transaction having an attribute corresponding to a first access restriction level can access a sector having either the first access restriction level or the second access restriction level; Transactions having attributes corresponding to a first addressing mode restriction level are able to access sectors having a second addressing mode restriction level; Transactions having attributes corresponding to the second access restriction level cannot access sectors having the first access restriction level; and Transactions having attributes corresponding to the second addressing mode restriction level cannot access sectors having the first addressing mode restriction level.

11. The method according to claim 9, wherein: A transaction having an attribute corresponding to a first program access prohibition level can access a sector having a fourth program access prohibition level, a fifth program access prohibition level, or a sixth program access prohibition level as an attribute; A transaction having an attribute corresponding to the second program access prohibition level can access sectors having the fifth protection level and the sixth protection level as attributes, but cannot access sectors having the fourth program access prohibition level as an attribute; as well as A transaction having an attribute corresponding to the third program access prohibition level can access a sector having the sixth program access prohibition level as an attribute, but cannot access a sector having the fourth program access prohibition level or the fifth program access prohibition level as an attribute.

12. The method of claim 11, wherein the attribute of the memory sector is either an attribute of a previous transaction or a default attribute defined by a first access restriction level, a second addressing mode restriction level, and a fourth program access prohibition level.

13. The method of claim 1, wherein the configuration value corresponds to a recycling mode, a write protection mode, or a write mode.

14. An electronic circuit comprising a non-volatile memory interface and a non-volatile memory, the electronic circuit being configured to implement the method according to claim 1.

Images