Chip power consumption test program generation method and device, equipment and storage medium
By grouping and filtering the instructions running on the chip, a successful test program is generated, which solves the problem of the limit power consumption of the test chip in the prior art, and achieves faster and more accurate test results.
Patent Information
- Application Number
- CN202311548776.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-17
- Publication Date
- 2025-05-20
AI Technical Summary
The prior art increases the test duration when testing chips with extreme power consumption.
By grouping all instructions that need to be run on the chip, collecting the power consumption data of each instruction, filtering out representative instructions that contribute a large amount to the limit power consumption, and generating a successful consumption test program to test the limit power consumption of the chip.
The test time required to test the chip's ultimate power consumption is shortened, while ensuring the accuracy of the test results.
Smart Images
Figure CN120020738A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power consumption testing, and in particular, to a method, device, equipment and storage medium for generating a chip power consumption testing program. Background Art
[0002] Before a chip leaves the factory, it is necessary to test its limit power consumption, that is, the maximum power consumption when the chip is under maximum load. This maximum power consumption is the limit power consumption of the chip. And the limit power consumption of the chip is related to the heat released when the chip is running. Therefore, testing the limit power consumption of the chip can help designers design a heat dissipation system that matches the limit power consumption of the chip, and this heat dissipation system is used to dissipate heat from the chip. For example, in order to test the limit power consumption of a GPGPU chip, as many instructions as possible that need to run on the GPGPU are simultaneously run on the GPGPU to make the GPGPU under maximum load, so as to test the limit power consumption of the GPGPU. Without screening all instructions, instructions that have a relatively small impact on the limit power consumption will also be used to test the limit power consumption of the GPGPU. However, running instructions with a relatively small impact on the GPGPU also requires a certain execution time, resulting in an extended test time.
[0003] In summary, the prior art increases the test duration when testing the limit power consumption of a chip.
[0004] Therefore, the prior art still needs to be improved and enhanced. Summary of the Invention
[0005] To solve the above technical problems, the present invention provides a method, device, equipment and storage medium for generating a chip power consumption testing program, which solves the problem that the prior art increases the test duration when testing the limit power consumption of a chip.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] In a first aspect, the present invention provides a method for generating a chip power consumption testing program, which includes:
[0008] Group a number of instructions that need to run on the chip to obtain each instruction group;
[0009] Collect the power consumption data generated by the chip when each of the instructions runs on the chip;
[0010] According to the power consumption data corresponding to each of the instructions in each instruction group, screen each of the instructions in each instruction group to obtain each representative instruction of each instruction group;
[0011] Generate a power consumption test program according to each of the representative instructions, where the power consumption test program is used to test the maximum power consumption of the chip.
[0012] In one implementation, the grouping of a number of instructions that all need to run on the chip to obtain each instruction group includes:
[0013] Collect the pipeline of each instruction on the chip;
[0014] Group a number of instructions according to the pipeline corresponding to each instruction to obtain each initial group;
[0015] Count the number of hardware units corresponding to all the instructions in each initial group, where the hardware unit is the hardware required for the chip to run the instruction;
[0016] When the number of hardware units corresponding to the initial group is less than the set number, use the initial group as the instruction group;
[0017] When the number of hardware units corresponding to the initial group is greater than or equal to the set number, divide the initial group according to the operand types of the instructions in the initial group to obtain each instruction group.
[0018] In one implementation, the collection of the power consumption data generated by the chip when each instruction runs on the chip includes:
[0019] Collect each sub-power consumption generated by the chip when each instruction runs on each operand of the chip, and record it as each sub-power consumption corresponding to each instruction, where the number of bits of each operand is different;
[0020] Filter each sub-power consumption corresponding to each instruction to obtain the maximum power consumption corresponding to each instruction, and use the maximum power consumption as the power consumption data generated by the chip when each instruction runs on the chip.
[0021] In one implementation, the screening of each instruction in each instruction group according to the power consumption data corresponding to each instruction in each instruction group to obtain each representative instruction in each instruction group includes:
[0022] Collect the respective running times required for the chip to run each instruction in each instruction group, and record it as the respective running times corresponding to each instruction in each instruction group;
[0023] Filter each instruction in each instruction group according to the respective power consumption data and / or respective running times corresponding to each of the instructions, so as to obtain each representative instruction of each instruction group.
[0024] In one implementation, generating a power consumption test program according to each of the representative instructions, the power consumption test program being used to test the maximum power consumption of the chip, includes:
[0025] Take each of the representative instructions as each power consumption impact representative factor of the chip, obtain other power consumption impact factors of the chip, and use the power consumption impact representative factor and the other power consumption impact factors as the respective power consumption impact factors of the chip;
[0026] Apply a random forest model to each of the power consumption impact factors to obtain an output impact factor sequence of the random forest model, and each power consumption impact factor in the impact factor sequence is sorted in descending order of importance to the chip;
[0027] Select several of the power consumption impact factors in turn from the head of the impact factor sequence until the sum of the importance of the selected power consumption impact factors is greater than a set value, to obtain respective power consumption preferred impact factors;
[0028] Generate a power consumption test program according to the respective power consumption preferred impact factors, the power consumption test program being used to test the maximum power consumption of the chip.
[0029] In one implementation, generating a power consumption test program according to the respective power consumption preferred impact factors, the power consumption test program being used to test the maximum power consumption of the chip, includes:
[0030] Set a value range for characterizing the power consumption range of each of the power consumption preferred impact factors of the chip;
[0031] For each of the power consumption preferred impact factors, randomly select parameter values within the value range to obtain respective initial parameter values of each of the power consumption preferred impact factors;
[0032] Input the respective initial parameter values into a code generator to obtain an initial power consumption test program;
[0033] Iteratively update the respective initial parameter values to iteratively update the initial power consumption test program until the number of iterative updates reaches a set number of times, to obtain the initial power consumption test program after iterative update, and use the initial power consumption test program after iterative update as the power consumption test program.
[0034] In one implementation, the iterative update method of the respective initial parameter values includes:
[0035] Collect the power consumption generated when the chip runs the initial power consumption test program as the test power consumption;
[0036] Input the test power consumption and each of the initial parameter values into the Bayesian optimization algorithm to obtain the iteratively updated initial parameter values output by the Bayesian optimization algorithm.
[0037] In a second aspect, an embodiment of the present invention further provides a chip power consumption test program generation device, where the device includes the following components:
[0038] A grouping module, configured to group a number of instructions that all need to run on the chip to obtain each instruction group;
[0039] A data acquisition module, configured to acquire the power consumption data generated by the chip when each of the instructions runs on the chip,
[0040] An instruction screening module, configured to screen each of the instructions in each instruction group according to the power consumption data corresponding to each of the instructions in each instruction group, so as to obtain each representative instruction of each instruction group;
[0041] A program generation module, configured to generate a power consumption test program according to each of the representative instructions, and the power consumption test program is used to test the limit power consumption of the chip.
[0042] In a third aspect, an embodiment of the present invention further provides a terminal device, where the terminal device includes a memory, a processor, and a chip power consumption test program generation program stored in the memory and executable on the processor. When the processor executes the chip power consumption test program generation program, the steps of the above-mentioned chip power consumption test program generation method are implemented.
[0043] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a chip power consumption test program generation program is stored. When the chip power consumption test program generation program is executed by a processor, the steps of the above-mentioned chip power consumption test program generation method are implemented.
[0044] Beneficial effects: First, the present invention groups a number of instructions that all need to run on the chip to obtain each instruction group; collects the power consumption data generated by the chip when each instruction runs on the chip, and then screens each instruction in each group based on the respective power consumption data corresponding to each instruction in each group to obtain each representative instruction of each group; finally, generates a power consumption test program based on each representative instruction, and the power consumption test program is used to test the maximum power consumption of the chip. From the above analysis, it can be seen that the present invention screens multiple instructions in each group according to the power consumption generated by the chip when they run on the chip to obtain the representative instruction of each group. That is, the present invention screens multiple instructions in each group according to the contribution of each instruction in the group to the maximum power consumption of the chip to obtain the representative instruction. Then, each representative instruction generates a power consumption test program, and as long as this power consumption test program runs on the chip, the maximum power consumption of the chip can be obtained. To sum up, the present invention only screens the instructions that contribute greatly to the maximum power consumption to generate a test program, which shortens the time required to test the maximum power consumption due to reducing the number of test instructions without affecting the finally obtained maximum power consumption. Description of the Drawings
[0045] Figure 1 is the overall flowchart of the present invention;
[0046] Figure 2 is the schematic diagram of testing the maximum power consumption in the embodiment of the present invention;
[0047] Figure 3 is the schematic diagram of screening the first group of representative instructions in the embodiment of the present invention;
[0048] Figure 4 is the schematic diagram of screening the second group of representative instructions in the embodiment of the present invention;
[0049] Figure 5 is the schematic diagram of screening the third group of representative instructions in the embodiment of the present invention;
[0050] Figure 6 is the schematic diagram of comparing the maximum power consumption of the first group in the embodiment of the present invention;
[0051] Figure 7 is the schematic diagram of comparing the maximum power consumption of the second group in the embodiment of the present invention;
[0052] Figure 8 is the schematic diagram of comparing the maximum power consumption time of the first group in the embodiment of the present invention;
[0053] Figure 9 is the schematic diagram of comparing the maximum power consumption time of the second group in the embodiment of the present invention
[0054] Figure 10Structural diagram of the chip power consumption test program generation device provided by the present invention;
[0055] Figure 11 Internal structure principle block diagram of the terminal device provided by the embodiment of the present invention. Specific implementation manner
[0056] The following combines embodiments and the accompanying drawings of the specification to clearly and completely describe the technical solutions in the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
[0057] It has been found through research that the chip needs to be tested for its limit power consumption before leaving the factory, that is, the maximum power consumption when the chip is at its maximum load, and this maximum power consumption is the limit power consumption of the chip. And the limit power consumption of the chip is related to the heat released when the chip is running. Therefore, testing the limit power consumption of the chip can help designers design a heat dissipation system that matches the limit power consumption of the chip, and this heat dissipation system is used to dissipate heat from the chip. For example, in order to test the limit power consumption of the GPGPU chip, as many instructions as possible that need to run on the GPGPU are simultaneously run on the GPGPU to make the GPGPU at its maximum load, so as to test the limit power consumption of the GPGPU. However, without screening all the instructions, instructions that have a relatively small impact on the limit power consumption will also be used to test the limit power consumption of the GPGPU, but running instructions with a relatively small impact on the GPGPU also requires a certain execution time, resulting in an extended test time.
[0058] To solve the above technical problems, the present invention provides a method, device, equipment and storage medium for generating a chip power consumption test program, which solves the problem of increasing the test duration in the prior art when testing the limit power consumption of the chip. Specifically in implementation, first, a number of instructions that need to run on the chip are grouped to obtain each instruction group; then, the power consumption data generated by the chip when each instruction runs on the chip is collected; after that, according to the respective power consumption data corresponding to each instruction in each group, each instruction in each group is screened to obtain each representative instruction of each group; finally, a power consumption test program is generated according to each representative instruction, and the power consumption test program is used to test the limit power consumption of the chip. The present invention can shorten the test duration required to test the limit power consumption of the chip.
[0059] For example, taking the GPGPU chip as an example, if the instructions that the GPGPU chip needs to run are ins 1 , ins 2 , ins 3 , ins 4 , ins 5 , ins 6 , ins7 , ins 8 , ins 9 , ins 10 , divide the instructions on the same pipeline of the GPGPU into a group. For example, the obtained grouping results are as follows:
[0060] ins 1 , ins 2 , ns 5 , ins 6 belongs to the first instruction group, ins 3 , ins 4 , ins 8 belongs to the second instruction group, ins 7 , ins 9 , ins 10 belongs to the third instruction group.
[0061] Run ins 1 , ins 2 , ins 3 , ins 4 , ins 5 , ins 6 , ins 7 , ins 8 , ins 9 , ins 10 Each instruction in runs on the GPGPU with operands of different bit widths. Since the power consumption brought to the GPGPU by the same instruction operating on operands of different bit widths is also different. For example, ins 1 Operating on operands of different bit widths brings power consumptions such as PW11, PW12, PW13, etc. to the GPGPU. Among them, PW12 is the largest. Then, take PW12 as the power consumption data P1 generated by the GPGPU when ins 1 runs on the GPGPU. Use the same method to obtain the power consumption data P2 generated by the GPGPU when ins 2 runs on the GPGPU, the power consumption data P3 generated by the GPGPU when ins 3 runs on the GPGPU, the power consumption data P4 generated by the GPGPU when ins 4 runs on the GPGPU, the power consumption data P5 generated by the GPGPU when ns 5 runs on the GPGPU, the power consumption data P6 generated by the GPGPU when ins 6 runs on the GPGPU, the power consumption data P7 generated by the GPGPU when ins 7 runs on the GPGPU, the power consumption data P8 generated by the GPGPU when ins 8 runs on the GPGPU, the power consumption data P8 generated by the GPGPU when ins 9Power consumption data P9, ins generated by the GPGPU when running on the GPGPU 10 Power consumption data P10 generated by the GPGPU when running on the GPGPU.
[0062] If ins 1 , ins 2 , ns 5 , ins 6 respectively corresponding to P1, P2, P5, P6, where P2 is the largest, and the time for the GPGPU to run ins 2 is also relatively short, then ins 2 is the representative instruction of the first group. The representative instructions of the second instruction group and the third instruction group are obtained by the same method. For example, the representative instruction of the second instruction group is ins 8 , and the representative instruction of the third instruction group is ins 9 .
[0063] After obtaining the representative instructions ins 2 , ins 8 and ins 9 of each group above, a power consumption test program is generated from ins 2 , ins 8 and ins 9 , and then the power consumption test program is run on the GPGPU to obtain the limit power consumption generated by the GPGPU when running this power consumption test program.
[0064] In this embodiment, as shown in Figure 1 , the method for generating a chip power consumption test program specifically includes the following steps:
[0065] S100, group a number of instructions that need to run on the chip to obtain each instruction group.
[0066] S200, collect the power consumption data generated by the chip when each of the instructions runs on the chip.
[0067] S300, screen each instruction in each instruction group according to the power consumption data corresponding to each instruction in each instruction group to obtain each representative instruction of each instruction group.
[0068] S400, generate a power consumption test program according to each representative instruction, and the power consumption test program is used to test the limit power consumption of the chip.
[0069] In one embodiment, step S100 includes the following specific steps S101 - S104:
[0070] S101, collect the pipeline of each of the instructions on the chip.
[0071] S102, group several of the instructions according to the pipeline corresponding to each of the instructions to obtain respective initial groups.
[0072] There are several hardware units on the chip. If the hardware units used for running several instructions are the same, then these several instructions are on the same pipeline, and then these several instructions are grouped into the same group, that is, Figure 2 the instruction grouping based on the pipeline in
[0073] S103, count the number of hardware units corresponding to all of the instructions in each of the initial groups, where the hardware units are the hardware required for the chip to run the instructions.
[0074] S104, when the number of hardware units corresponding to the initial group is less than the set number, use the initial group as the instruction group; when the number of hardware units corresponding to the initial group is greater than or equal to the set number, divide the initial group according to the operand types of the instructions in the initial group to obtain respective instruction groups.
[0075] Instructions in different groups also require different numbers of hardware units to run on the chip, that is, different pipelines cover different numbers of hardware units. If the number of hardware units corresponding to the chip in a certain initial group is large, then the initial group needs to be secondarily grouped according to the operand types. For instruction groups with the same value range, secondary grouping can ensure that the number of hardware units corresponding to each group is as equal as possible. The operand type is the data type operated on by the instruction. For example, there is an addition instruction for adding two addends, and the operand type is the type of these two addends, and the type can be integer or floating point.
[0076] In one embodiment, step S200 includes the following specific steps S201 and S202:
[0077] S201, collect each of the sub-power consumptions generated by the chip when the chip runs each of the operands of each of the instructions, and record them as each of the sub-power consumptions corresponding to each of the instructions, where the number of bits of each of the operands is different.
[0078] S202, filter each of the sub-power consumptions corresponding to each of the instructions to obtain the maximum power consumption corresponding to each of the instructions, and use the maximum power consumption as the power consumption data generated by the chip when each of the instructions runs on the chip.
[0079] Such as Figure 2As shown, each instruction is run on the chip in the form of a kernel function separately, and then a power consumption acquisition tool is used to monitor the kernel function in real time to obtain the maximum power consumption corresponding to each instruction. As Figure 2 shown, in this embodiment, not only the maximum power consumption of each instruction is monitored, but also the start time and end time of each instruction are monitored. The running duration of the instruction is obtained based on the start time and the end time. Obtaining the maximum power consumption and the running duration corresponding to each instruction in each instruction group is for facilitating subsequent screening of representative instructions according to these two factors.
[0080] In one embodiment, step S300 includes the following specific steps:
[0081] S301, collect the respective running times required for the chip to run each of the instructions in each of the instruction groups, and record them as the respective running times corresponding to each of the instructions in each of the instruction groups.
[0082] S302, screen each of the instructions in each of the instruction groups according to the respective power consumption data and / or the respective running times corresponding to each of the instructions, so as to obtain each representative instruction of each of the instruction groups.
[0083] For example, if there are three instructions in one instruction group, then step S202 is used to obtain the power consumption data and the running times of these three instructions respectively. The instruction corresponding to the maximum power consumption data and the shortest running time is used as the representative instruction of this instruction group. If the maximum power consumption data and the shortest running time cannot be satisfied simultaneously, then the instruction corresponding to the maximum power consumption data is used as the representative instruction of this instruction group. The reason for using the instruction with the maximum power consumption data as the representative instruction to participate in the subsequent power consumption test program generation is that using the instruction with the maximum power consumption data can make the power consumption of the chip approach the limit power consumption to the greatest extent, so as to improve the accuracy of the obtained limit power consumption.
[0084] In one embodiment, step S400 includes the following specific steps S401 to S407:
[0085] S401, use each of the representative instructions as each power consumption impact representative factor of the chip, obtain other power consumption impact factors of the chip, and use the power consumption impact representative factor and the other power consumption impact factors as the respective power consumption impact factors of the chip.
[0086] Not only instructions can affect the power consumption of a chip. There are many factors in the chip that can affect its power consumption, such as register dependence distance, memory access instructions, and the size of the stream, etc. These are other power consumption influencing factors. Among them, memory access instructions are used to read from or write to memory. The size of the stream is used to control the number of kernel functions in a program to improve the utilization rate of the chip. The register dependence distance affects the instruction parallelism and thus affects the power consumption of the chip.
[0087] S402. Apply the random forest model to each of the power consumption influencing factors to obtain an influencing factor sequence output by the random forest model. Each power consumption influencing factor in the influencing factor sequence is sorted in descending order of importance to the chip.
[0088] Take both the representative instructions and other power consumption influencing factors as power consumption influencing factors. Input each power consumption influencing factor into the random forest model, and the random forest model will sort the importance of the above-mentioned various power consumption influencing factors and output each power consumption influencing factor sorted according to the importance, that is, Figure 2 the sorting of the importance of the power consumption factors in. The so-called importance is the degree of influence on the power consumption of the chip.
[0089] S403. Sequentially select several of the power consumption influencing factors from the head of the influencing factor sequence until the sum of the importance of the selected power consumption influencing factors is greater than a set value, to obtain each power consumption preferred influencing factor.
[0090] For example, there are ten power consumption influencing factors, namely DE1, DE2, DE3, DE4, DE5, DE6, DE7, DE8, DE9, DE10. The obtained influencing factor sequence after sorting is DE4, DE5, DE6, DE2, DE3, DE7, DE8, DE9, DE1, DE10. Among them, the sum of DE4, DE5, DE6, DE2, and DE3 is less than the set value of 95%, while the sum of DE4, DE5, DE6, DE2, DE3, and DE7 is greater than the set value of 95%. Then the power consumption preferred influencing factors are DE4, DE5, DE6, DE2, DE3, and DE7.
[0091] S404. Set the value range for characterizing the power consumption range of each power consumption preferred influencing factor of the chip.
[0092] Set the same value range [1, 4] for each power consumption influencing factor. Each value in the value range can be used as the value of the power consumption influencing factor.
[0093] S405. For each of the power consumption preferred influencing factors, randomly select a parameter value within the value range to obtain each initial parameter value of each power consumption preferred influencing factor.
[0094] The initial parameter value of each power consumption optimization factor represents the weight of this power consumption optimization factor in the code generator. For example, for the power consumption factor of the stream size, whose value range is [4, 12], when its value is 8, it means that there are 8 kernel functions in the power consumption test program generated by the code generator.
[0095] S406. Input each of the initial parameter values into the code generator to obtain an initial power consumption test program.
[0096] S407. Iteratively update each of the initial parameter values to iteratively update the initial power consumption test program until the number of iterations reaches a set number, obtaining the iteratively updated initial power consumption test program, and use the iteratively updated initial power consumption test program as the power consumption test program.
[0097] Place the initial power consumption test program on the GPGPU chip. When the chip runs the initial power consumption test program, a test power consumption will be generated. Then, input the test power consumption and the initial parameter values of each power consumption optimization factor into the Bayesian optimization algorithm Optuna. Optuna will output the initial parameter values of each power consumption optimization factor after optimization, that is, the iteratively updated parameter values. Then, use the iteratively updated parameter values of each power consumption optimization factor to generate a power consumption test program. After that, repeatedly run the iteratively updated power consumption test program on the chip to update the power consumption of the chip, and continuously repeat the above operations until the number of iterations reaches the set number of 300. At this time, the obtained power consumption test program is the final power consumption test program, and the ultimate power consumption of the chip can be tested using this power consumption test program.
[0098] Taking two types of GPGPU chips, Tesla T4 and Tesla A10, as examples, introduce the representative instructions selected by the present invention, grouping, the hardware units required to run the instructions, the sorting of power consumption factors, and verify the accuracy of the ultimate power consumption obtained by the present invention. The following will be described one by one:
[0099] Figure 3 、 Figure 4 、 Figure 5 The abscissas of all are instruction names, and the ordinates are power consumption and running time.
[0100] From Figure 3 、 Figure 4 、 Figure 5 it can be seen that different arithmetic instructions have different power consumptions, and the power consumptions of the same arithmetic instruction with different operand bit widths are also different; for the same arithmetic instruction, the single-precision floating-point instruction has a higher power consumption and a shorter execution time than the double-precision floating-point instruction. Figures 3 to 5 The instructions between the two dashed lines on are on the same pipeline
[0101] Through power consumption and running time fromFigure 3 , Figure 4 , Figure 5 Among a number of instructions in Figure 3 , Float, Int, and Sub-Byte are warp-level matrix multiply-accumulate instructions, and Tanh-F16x2, Ex2-F16x2, Add-F16x2, Sub-F16x2, Mul-F16x2, Fma-F16x2, and Abs-F16x2 are vector instructions.
[0102] In Table 1, Group represents the grouping, Representative Instruction represents the representative instruction within the group, and Unit is the hardware unit where the grouping is located.
[0103] Table 1
[0104]
[0105] Table 2 shows the results of ranking the power consumption impact factors using the random forest algorithm. It can be learned from Table 2 that the two instructions, blockDim and gridDim, always rank in the top two. They jointly determine the parallelism of the program; the number of streams significantly affects the parallelism and efficiency of the CUDA program (the CUDA program is the power consumption test program); the basic block size determines the number of instructions in the basic block, and the larger the basic block, the more computational instructions and fewer branches in the program.
[0106] Table 2
[0107]
[0108] Figure 6 and Figure 7 both have the power consumption test programs on the abscissa, and the ordinate is the measured maximum power consumption. Among them, the last power consumption test program Guser on the abscissa is the power consumption test program of the present invention, and the others are existing power consumption test programs, that is, benchmark test programs. From Figure 6 and Figure 7 , it can be seen that the maximum chip power consumption obtained using the power consumption test program of the present invention is much greater than that obtained using the existing benchmark test programs.
[0109] Figure 8 and Figure 9 are both comparison charts of the maximum power consumption tested by the power consumption test method Guser of the present invention and the existing state-of-the-art power consumption test method MAMPO on different chips. From Figure 8It can be learned that the limit power consumption obtained by the present invention is 109.3W, while the limit power consumption obtained by the existing method is 73.5W. Therefore, the limit power consumption obtained by the present invention is 48.7% higher than that obtained by the existing method, and the test duration of the present invention is shortened by 3.5 times compared with the existing test duration. From Figure 9 It can be learned that the limit power consumption obtained by the present invention is 238.7W, while the limit power consumption obtained by the existing method is 138W. Therefore, the limit power consumption obtained by the present invention is 73% higher than that obtained by the existing method, and the test duration of the present invention is shortened by 6 times compared with the existing test duration.
[0110] In summary, the present invention systematically analyzes the power consumption and running time of each arithmetic instruction under operands of different bit numbers. The arithmetic instructions are grouped using a pipeline, thereby reducing the dimension of the parameters. The power consumption influencing factors are analyzed, and then the importance of the power consumption influencing factors is ranked using the random forest algorithm, and the important power consumption influencing factors are selected as the parameters of the code generator. The state-of-the-art optimization algorithm Optuna is used to find the optimal parameters, thereby obtaining the limit power consumption of the GPGPU and reducing the optimization time.
[0111] This embodiment also provides a device for generating a chip power consumption test program. As shown in FIG. 10, the device includes the following components:
[0112] A grouping module, configured to group a plurality of instructions that all need to run on the chip to obtain each instruction group;
[0113] A data acquisition module, configured to acquire power consumption data generated by the chip when each of the instructions runs on the chip,
[0114] An instruction screening module, configured to screen each instruction in each instruction group according to the power consumption data corresponding to each instruction in each instruction group, so as to obtain each representative instruction of each instruction group;
[0115] A program generation module, configured to generate a power consumption test program according to each representative instruction, and the power consumption test program is used to test the limit power consumption of the chip.
[0116] Based on the above embodiments, the present invention also provides a terminal device, and its principle block diagram can be as Figure 11As shown in the figure. The terminal device includes a processor, a memory, a network interface, and a display screen connected by a system bus. Among them, the processor of the terminal device is used to provide computing and control capabilities. The memory of the terminal device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the terminal device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it realizes a method for generating a chip power consumption test program. The display screen of the terminal device can be a liquid crystal display screen or an electronic ink display screen.
[0117] Those skilled in the art can understand that Figure 11 the block diagram of the principle shown in the figure is only the block diagram of the part of the structure related to the solution of the present invention, and does not constitute a limitation on the terminal device to which the solution of the present invention is applied. The specific terminal device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.
[0118] In one embodiment, a terminal device is provided. The terminal device includes a memory, a processor, and a chip power consumption test program generation program stored in the memory and executable on the processor. When the processor executes the chip power consumption test program generation program, the following operation instructions are realized:
[0119] Group a number of instructions that all need to run on the chip to obtain each instruction group;
[0120] Collect the power consumption data generated by the chip when each of the instructions runs on the chip;
[0121] According to the power consumption data corresponding to each of the instructions in each instruction group, screen each of the instructions in each instruction group to obtain each representative instruction of each instruction group;
[0122] Generate a power consumption test program according to each representative instruction, and the power consumption test program is used to test the limit power consumption of the chip.
[0123] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.
[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for generating a chip power consumption test program, characterized in that: include: Grouping all instructions that need to be run on the chip to obtain instruction groups; Collecting power consumption data generated by the chip when each instruction is executed on the chip; Screening each of the instructions in each of the instruction groups according to the power consumption data corresponding to each of the instructions in each of the instruction groups to obtain each representative instruction of each of the instruction groups; A power consumption test program is generated according to each representative instruction, and the power consumption test program is used to test the extreme power consumption of the chip.
2. The chip power consumption test program generation method according to claim 1, characterized in that: The step of grouping all instructions that need to be run on the chip to obtain instruction groups includes: Acquire the pipeline of each of the instructions on the chip; According to the pipeline corresponding to each of the instructions, a plurality of the instructions are grouped to obtain initial groups; Counting the number of hardware units corresponding to all the instructions in each of the initial groups, the hardware unit being the hardware required for the chip to run the instructions; When the number of the hardware units corresponding to the initial group is less than the set number, the initial group is used as the instruction group; When the number of the hardware units corresponding to the initial group is greater than or equal to a set number, the initial group is divided according to the operand type of the instructions in the initial group to obtain individual instruction groups.
3. The chip power consumption test program generation method according to claim 1, characterized in that: The collecting of power consumption data generated by the chip when each instruction is executed on the chip includes: Collecting each sub-power consumption generated by the chip when each instruction runs each operand on the chip, and recording the sub-power consumption corresponding to each instruction, wherein the number of bits of each operand is different; The sub-power consumptions corresponding to each of the instructions are screened to obtain the maximum power consumption corresponding to each of the instructions, and the maximum power consumption is used as the power consumption data generated by the chip when each of the instructions runs on the chip.
4. The chip power consumption test program generation method according to claim 1, characterized in that: The filtering of each instruction in each instruction group according to the power consumption data corresponding to each instruction in each instruction group to obtain each representative instruction of each instruction group includes: Collecting the respective running times required by the chip to run the respective instructions in each of the instruction groups, and recording the respective running times corresponding to the respective instructions in each of the instruction groups; The instructions in each instruction group are screened according to the power consumption data and / or the running time corresponding to each instruction to obtain each representative instruction of each instruction group.
5. The chip power consumption test program generation method according to claim 1, characterized in that: The step of generating a power consumption test program according to each representative instruction, wherein the power consumption test program is used to test the extreme power consumption of the chip, including: Using each of the representative instructions as each power consumption impact representative factor of the chip, acquiring other power consumption impact factors of the chip, and using the power consumption impact representative factors and the other power consumption impact factors as individual power consumption impact factors of the chip; Applying a random forest model to each of the power consumption influencing factors to obtain an influencing factor sequence output by the random forest model, wherein each of the power consumption influencing factors in the influencing factor sequence is sorted from greatest to least important according to importance to the chip; Selecting a number of the power consumption influencing factors from the head of the influencing factor sequence in sequence until the sum of the importance of each of the selected power consumption influencing factors is greater than a set value, thereby obtaining each power consumption preferred influencing factor; A power consumption test program is generated according to each of the preferred power consumption influencing factors, and the power consumption test program is used to test the extreme power consumption of the chip.
6. The chip power consumption test program generation method according to claim 5, characterized in that: The step of generating a power consumption test program according to each of the power consumption preferred influencing factors, wherein the power consumption test program is used to test the extreme power consumption of the chip, includes: Setting a value range for characterizing the power consumption range of each power consumption preferred influencing factor of the chip; For each of the preferred power consumption influencing factors, randomly select a parameter value within the value range to obtain each initial parameter value of each of the preferred power consumption influencing factors; Inputting each of the initial parameter values into a code generator to obtain an initial power consumption test program; Iteratively update each of the initial parameter values to iteratively update the initial power consumption test program until the number of iterative updates reaches a set number, to obtain the initial power consumption test program after iterative update, and use the initial power consumption test program after iterative update as the power consumption test program.
7. The chip power consumption test program generation method according to claim 6, characterized in that: The iterative updating method of each of the initial parameter values includes: collecting power consumption generated when the chip runs the initial power consumption test program as test power consumption; The test power consumption and each of the initial parameter values are input into a Bayesian optimization algorithm to obtain the initial parameter values after iterative update output by the Bayesian optimization algorithm.
8. A chip power consumption test program generation device, characterized in that: The device comprises the following components: A grouping module, used for grouping all instructions that need to be run on the chip to obtain individual instruction groups; A data collection module is used to collect power consumption data generated by the chip when each instruction is executed on the chip. An instruction screening module, used for screening each instruction in each instruction group according to the power consumption data corresponding to each instruction in each instruction group, so as to obtain each representative instruction of each instruction group; The program generation module is used to generate a power consumption test program according to each representative instruction, and the power consumption test program is used to test the extreme power consumption of the chip.
9. A terminal device, characterized in that: The terminal device includes a memory, a processor, and a chip power consumption test program generation program stored in the memory and executable on the processor. When the processor executes the chip power consumption test program generation program, the steps of the chip power consumption test program generation method as described in any one of claims 1 to 7 are implemented.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a chip power consumption test program generation program. When the chip power consumption test program generation program is executed by a processor, the steps of the chip power consumption test program generation method according to any one of claims 1 to 7 are implemented.