Semiconductor device

Abstract

The present disclosure relates to a semiconductor device including: a data pad; at least one merge node; a first data path coupled between the data pad and the at least one merge node, and outputting a first data signal to the at least one merge node in a first mode based on the data signal, a reference signal, and a mode selection signal; a second data path coupled between the data pad and the at least one merge node, and outputting a second data signal to the at least one merge node in a second mode based on the data signal, the reference signal, and the mode selection signal; and a synchronization path coupled to the at least one merge node and outputting a respective one of the first data signal and the second data signal as a data signal synchronized with the at least one data strobe signal in one of the first mode and the second mode.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0160312, filed on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Various embodiments of the present disclosure relate to a semiconductor design technology, and more particularly, to a semiconductor device including an interface circuit. Background art

[0004] A semiconductor device may receive or output various signals through a predetermined operation. For example, a memory device receives data signals and data strobe signals from a memory control device or outputs them to the memory control device.

[0005] A semiconductor device includes an interface circuit for inputting and outputting various signals. The interface circuit is developed in various ways according to a mode. Summary of the invention

[0006] Various embodiments of the present disclosure relate to a semiconductor device that supports various interface modes.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a data pad; at least one merging node; a first data path coupled between the data pad and the at least one merging node and adapted to output a first data signal to the at least one merging node in a first mode based on a data signal, a reference signal, and a mode selection signal; a second data path coupled between the data pad and the at least one merging node and adapted to output a second data signal to the at least one merging node in a second mode based on the data signal, the reference signal, and the mode selection signal; and a synchronization path coupled to the at least one merging node and adapted to output a corresponding signal of the first data signal and the second data signal as a data signal synchronized with at least one data strobe signal in one of the first mode and the second mode.

[0008] According to an embodiment of the present disclosure, a semiconductor device may include: a data pad; at least one common node; a common path coupled between the data pad and the at least one common node and adapted to output a common data signal to the at least one common node based on a data signal and a reference signal; at least one merging node; a first data path coupled between the at least one common node and the at least one merging node and adapted to output a first data signal to the at least one merging node in a first mode based on the common data signal and a mode selection signal; a second data path coupled between the at least one common node and the at least one merging node and adapted to output a second data signal to the at least one merging node in a second mode based on the common data signal and the mode selection signal; and a synchronization path coupled to the at least one merging node and adapted to output a corresponding signal of the first data signal and the second data signal as a data signal synchronized with a data strobe signal in one of the first mode and the second mode.

[0009] According to an embodiment of the present disclosure, a semiconductor device may include: a first data path adapted to generate a first data signal in a first mode based on a data signal and a reference signal; a second data path adapted to generate a second data signal in a second mode based on the data signal and the reference signal; and a synchronization path adapted to output a selected data signal among the first data signal and the second data signal as a data signal synchronized with at least one data strobe signal in each of the first mode and the second mode based on a mode selection signal, at least one data strobe signal, and the first data signal and the second data signal.

[0010] Other features, aspects, and advantages of the present invention will become apparent from the following detailed description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a semiconductor device according to a first embodiment of the present disclosure.

[0012] Figure 2 is a block diagram showing Figure 1 the first data path, the second data path, and the synchronization path shown.

[0013] Figure 3 is a circuit diagram showing a repeater at an end of a second replica circuit included in the first data path shown in Figure 2 is a circuit diagram showing an input circuit included in the second data path shown in

[0014] Figure 4 is a block diagram showing Figure 2 the input circuit included in the second data path shown.

[0015] Figure 5 is a block diagram showing Figure 1 another embodiment of the first data path, second data path, and synchronization path shown.

[0016] Figure 6 is a block diagram showing a semiconductor device according to a second embodiment of the present disclosure.

[0017] Figure 7 is a block diagram showing Figure 6 the first data path, second data path, and synchronization path shown.

[0018] Figure 8 is a block diagram showing a semiconductor device according to a third embodiment of the present disclosure.

[0019] Figure 9 is a block diagram showing Figure 8 an example of the first data path, second data path, and synchronization path shown.

[0020] Figure 10 is a block diagram showing Figure 9 a circuit diagram of the first selection circuit included in the synchronization path shown.

[0021] Figure 11 is a block diagram showing Figure 8 another embodiment of the first data path, second data path, and synchronization path shown.

[0022] Figure 12 is a block diagram showing Figure 8 yet another embodiment of the first data path, second data path, and synchronization path shown.

[0023] Figure 13 is a block diagram showing Figure 12 a circuit diagram of the first integrated circuit shown. DETAILED DESCRIPTION

[0024] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings in order to describe the embodiments of the present disclosure in detail, so that those of ordinary skill in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0025] It should be understood that when referring to an element "connected to" or "coupled to" another element, the element can be directly connected to or coupled to the other element, or the element can be electrically connected to or coupled to the other element while one or more elements are interposed therebetween. Additionally, it should also be understood that unless otherwise stated, the terms "comprising", "comprises", "including", and "includes" used in this specification do not exclude the presence of one or more other elements, but can further include or have one or more other elements. Throughout the description of the specification, some components are described in the singular form, but the present disclosure is not limited thereto, and it should be understood that the components can be formed in the plural form. In the present disclosure, a pair of positive and negative signals can refer to signals that are complementary to each other, such as differential complementary signals. The positive signal does not necessarily always have a positive value and can have a negative value as required. The negative signal does not necessarily always have a negative value and can have a positive value as required.

[0026] Figure 1 is a block diagram showing a semiconductor device 100 according to a first embodiment of the present disclosure.

[0027] Referring to Figure 1 , the semiconductor device 100 can include a data pad PD, a first data path 110, a second data path 120, and a synchronization path 130.

[0028] The data pad PD can be coupled to an external device. The data pad PD can receive a data signal DQ output from the external device. The data pad PD can be coupled to a power supply terminal of a high voltage VTT through a termination resistor RZ.

[0029] The first data path 110 can be coupled between the data pad PD and a pair of merge nodes TN and BN. The first data path 110 can be enabled in a first mode based on a mode selection signal EN. For example, the first mode can be a low-speed mode that applies a predetermined amount of internal delay time. The first data path 110 can output first differential data signals DQ1 and / DQ1 as differential data signals DDQ and / DDQ to a pair of merge nodes TN and BN respectively in the first mode based on the data signal DQ, a reference signal VREF, and the mode selection signal EN.

[0030] The second data path 120 can be coupled between the data pad PD and a pair of merge nodes TN and BN. The second data path 120 can be enabled in a second mode based on the mode selection signal EN. For example, the second mode can be a high-speed mode that does not apply an amount of internal delay time. According to an example, the second data path 120 can output second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to a pair of merge nodes TN and BN respectively in the second mode based on the data signal DQ, the reference signal VREF, and the mode selection signal EN (referring to Figure 2). According to another example, the second data path 120 can, in the second mode, based on the data signal DQ, the reference signal VREF, and the mode selection signal EN, output the second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to a pair of merging nodes TN and BN respectively, and can output the third differential data signals DQ2' and / DQ2' as differential data signals DDQ' and / DDQ' to a pair of merging nodes TN' and BN' respectively.

[0031] The synchronization path 130 can be coupled to a pair of merging nodes TN and BN. The synchronization path 130 can output the differential data signals DDQ and / DDQ as first to fourth data signals DQi, DQq, Dqib, and DQqb synchronized with the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb in the first mode or the second mode. The first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb can have different phases. For example, the first data strobe signal DQSi and the second data strobe signal DQSq can have a 90-degree phase difference, the second data strobe signal DQSq and the third data strobe signal DQSib can have a 90-degree phase difference, and the third data strobe signal DQSib and the fourth data strobe signal DQSqb can have a 90-degree phase difference.

[0032] Figure 2 is a diagram showing Figure 1 the first data path 110, the second data path 120, and the synchronization path 130 shown.

[0033] Referring to Figure 2 , the first data path 110 can include a first input circuit AMP1, a first replication circuit RP1, a second replication circuit RP2, and a third replication circuit RP3.

[0034] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0035] The first replication circuit RP1 can delay the input data signal by a first delay time amount and can output the delayed input data signal to a branch node VN. For example, the first replication circuit RP1 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0036] The second replication circuit RP2 can delay the delayed input data signal by a second delay time amount and can output the first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1 to the first merging node TN among a pair of merging nodes TN and BN. For example, the second replication circuit RP2 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series. The second repeater RT1 among the one or more repeaters located at the end of the second replication circuit RP2 (i.e., closest to the first merging node TN) can be enabled in response to the mode selection signal EN (refer to Figure 3 ) and enabled.

[0037] The third replication circuit RP3 can delay the delayed input data signal by a second delay time amount and can output the first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1 to the second merging node BN among a pair of merging nodes TN and BN. For example, the third replication circuit RP3 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series. The third repeater RT2 among the one or more repeaters located at the end of the third replication circuit RP3 (i.e., closest to the second merging node BN) can be designed in the same manner as the second repeater RT1 and can be enabled in response to the mode selection signal EN (refer to Figure 3 ) and enabled.

[0038] The first delay time amount and the second delay time amount can be determined according to the internal delay time amount caused by the paths for transmitting the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. For example, the sum of the first delay time amount and the second delay time amount can be equal to the internal delay time amount. Although not shown in the figure, the internal delay time amount can include the time point when the data strobe signal generated by an external device is input to the corresponding pad included in the semiconductor device 100 to the time point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 130.

[0039] The second data path 120 can include a second input circuit AMP2.

[0040] The second input circuit AMP2 can output the second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to the first merging node TN and the second merging node BN respectively based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0041] The synchronization path 130 may include first to fourth comparison circuits C1 to C4 and first to fourth latch circuits LC1 to LC4.

[0042] The first comparison circuit C1 may be synchronized with the first data strobe signal DQSi and may perform a comparison operation within a first time period. The first time period may be related to the phase of the first data strobe signal DQSi. For example, the first time period may correspond to one period of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 may compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the first mode, and may generate and latch a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 may compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the second mode, and may generate and latch a first comparison data signal corresponding to the comparison result.

[0043] The second comparison circuit C2 may be synchronized with the second data strobe signal DQSq and may perform a comparison operation within a second time period. The second time period may be related to the phase of the second data strobe signal DQSq. For example, the second time period may correspond to one period of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 may compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the first mode, and may generate and latch a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 may compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the second mode, and may generate and latch a second comparison data signal corresponding to the comparison result.

[0044] The third comparison circuit C3 can be synchronized with the third data strobe signal DQSib and can perform a comparison operation within a third time period. The third time period can be related to the phase of the third data strobe signal DQSib. For example, the third time period can correspond to one cycle of the third data strobe signal DQSib based on the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the positive data signal DDQ output through the first merging node TN with the negative data signal / DDQ output through the second merging node BN in the first mode, and can generate and latch a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the positive data signal DDQ output through the first merging node TN with the negative data signal / DDQ output through the second merging node BN in the second mode, and can generate and latch a third comparison data signal corresponding to the comparison result.

[0045] The fourth comparison circuit C4 can be synchronized with the fourth data strobe signal DQSqb and can perform a comparison operation within a fourth time period. The fourth time period can be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth time period can correspond to one cycle of the fourth data strobe signal DQSqb based on the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the positive data signal DDQ output through the first merging node TN with the negative data signal / DDQ output through the second merging node BN in the first mode, and can generate and latch a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the positive data signal DDQ output through the first merging node TN with the negative data signal / DDQ output through the second merging node BN in the second mode, and can generate and latch a fourth comparison data signal corresponding to the comparison result.

[0046] Each of the first to fourth comparison circuits C1 to C4 can receive the comparison data signal output from the adjacent comparison circuit C1 to C4. The first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This operation is called a decision feedback equalization (DFE) operation.

[0047] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0048] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0049] The third latching circuit LC3 can latch the third comparison data signal as the third internal data signal DQib. For example, the third latching circuit LC3 can include an SR latch.

[0050] The fourth latching circuit LC4 can latch the fourth comparison data signal as the fourth internal data signal DQqb. For example, the fourth latching circuit LC4 can include an SR latch.

[0051] Figure 3 is a circuit diagram showing Figure 2 the second repeater RT1 located at the end of one or more repeaters included in the second replication circuit RP2 shown.

[0052] Referring to Figure 3 , the second repeater RT1 can include a first pull-up driver DD1, a first selection driver SD1, a second selection driver SD2, a first pull-down driver DD2, and a power gating element ED.

[0053] The first pull-up driver DD1 can be connected between the power terminal of the first voltage and the first power node. The first pull-up driver DD1 can pull up and drive the first power node using the first voltage based on the first drive data signal IN corresponding to the delayed input data signal.

[0054] The first selection driver SD1 can be connected between the first power node and the first output node. The first selection driver SD1 can selectively connect the first power node to the first output node based on the mode selection signal EN. An output signal corresponding to the first positive data signal DQ1 can be generated through the first output node.

[0055] The second selection driver SD2 can be connected between the first output node and the second power node. The second selection driver SD2 can selectively connect the first output node to the second power node based on the inverted signal / EN of the mode selection signal EN.

[0056] The first pull-down driver DD2 can be connected between the second power node and the power terminal of the second voltage. The first pull-down driver DD2 can pull down and drive the second power node using the second voltage based on the first drive data signal IN.

[0057] The power gating element ED can enable the second repeater RT1 based on the enable signal PG_EN. For example, the enable signal PG_EN can be a write enable signal.

[0058] Since Figure 2 the third repeater RT2 located at the end of one or more repeaters included in the third replication circuit RP3 shown can be in accordance with Figure 3The third repeater RT2 is designed in the same way as the second repeater RT1 shown, so the description of the third repeater RT2 is omitted.

[0059] Figure 4 is a diagram showing Figure 2 the circuit diagram of the second input circuit AMP2 included in the second data path 120 shown.

[0060] Referring to Figure 4 , the second input circuit AMP2 may include a source driver SD1, a first input driver ID1, a third selection driver SD3, a second input driver ID2, a fourth selection driver SD4, a first sink driver KD1, a second sink driver KD2, and a logic circuit LOG.

[0061] The source driver SD1 may be connected between the power supply terminal of the first voltage and the common node CN. The source driver SD1 may receive a bias voltage VBIAS. The source driver SD1 may supply the first voltage to the common node CN based on the bias voltage VBIAS.

[0062] The first input driver ID1 may be connected between the common node CN and the first node. The first input driver ID1 may receive a data signal DQ.

[0063] The third selection driver SD3 may be connected between the first node and the second merging node BN. The third selection driver SD3 may receive the inverted signal / EN of the mode selection signal EN.

[0064] The second input driver ID2 may be connected between the common node CN and the second node. The second input driver ID2 may receive a reference signal VREF.

[0065] The fourth selection driver SD4 may be connected between the second node and the first merging node TN. The fourth selection driver SD4 may receive the inverted signal / EN of the mode selection signal EN.

[0066] The first sink driver KD1 may be connected between the second merging node BN and the power supply terminal of the second voltage. The first sink driver KD1 may receive a control signal.

[0067] The second sink driver KD2 may be connected between the first merging node TN and the power supply terminal of the second voltage. The second sink driver KD2 may receive a control signal.

[0068] The logic circuit LOG can generate a control signal based on a mode selection signal EN and an enable signal PG_EN. For example, the logic circuit LOG can include a NAND gate and an inverter. The NAND gate can perform a NOR operation on the mode selection signal EN and the enable signal PG_EN. The inverter can invert the output signal of the NAND gate and can generate the control signal.

[0069] Figure 5 is a block diagram showing Figure 1 another embodiment of the first data path 110, the second data path 120, and the synchronization path 130 shown.

[0070] Referring to Figure 5 , the first data path 110 may include a first input circuit AMP1, a first replication circuit RP1, a second replication circuit RP2, and a third replication circuit RP3.

[0071] The first input circuit AMP1 can generate an input data signal based on a data signal DQ and a reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0072] The first replication circuit RP1 can delay the input data signal by a first delay time amount and can output the delayed input data signal to a branch node VN. For example, the first replication circuit RP1 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0073] The second replication circuit RP2 can delay the delayed input data signal by a second delay time amount and output the first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1 to the third merging node TN among a pair of merging nodes TN and BN and the fifth merging node TN' among a pair of merging nodes TN' and BN'. For example, the second replication circuit RP2 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series. The second repeater RT1 among the one or more repeaters located at the end of the second replication circuit RP2 (i.e., closest to the third merging node TN) can be enabled in response to the mode selection signal EN (refer to Figure 3 ).

[0074] The third replication circuit RP3 can delay the delayed input data signal by a second delay time amount, and output the first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1 to the fourth merging node BN among a pair of merging nodes TN and BN and the sixth merging node BN' among a pair of merging nodes TN' and BN'. For example, the third replication circuit RP3 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series. The third repeater RT2 among the one or more repeaters located at the end of the third replication circuit RP3 (i.e., closest to the fourth merging node BN) can be enabled in response to the mode selection signal EN (refer to Figure 3 ) and enabled.

[0075] The first delay time amount and the second delay time amount can be determined according to the internal delay time amount caused by the paths for transmitting the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. For example, the sum of the first delay time amount and the second delay time amount can be equal to the internal delay time amount. Although not shown in the figure, the internal delay time amount can include the time point when the data strobe signal generated by an external device is input to the corresponding pad included in the semiconductor device 100 to the time point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 130.

[0076] The second data path 120 can include second to fourth input circuits AMP2, AMP3, and AMP4.

[0077] The second input circuit AMP2 can output a differential data signal to a pair of branch nodes TNN and BNN based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0078] The third input circuit AMP3 can output the second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to a pair of merging nodes TN and BN based on the differential data signal output from the second input circuit AMP2. For example, the third input circuit AMP3 can include an amplifier.

[0079] The fourth input circuit AMP4 can output the third differential data signals DQ2' and / DQ2' as differential data signals DDQ' and / DDQ' to a pair of merging nodes TN' and BN' based on the differential data signal output from the second input circuit AMP2. For example, the fourth input circuit AMP4 can include an amplifier.

[0080] Each of the second to fourth input circuits AMP2, AMP3, and AMP4 can be in accordance withFigure 4 designed in the same or different ways as the second input circuit AMP2 shown.

[0081] The synchronization path 130 may include first to fourth comparison circuits C1 to C4 and first to fourth latch circuits LC1 to LC4.

[0082] The first comparison circuit C1 may be synchronized with the first data strobe signal DQSi and may perform a comparison operation within a first time period. The first time period may be related to the phase of the first data strobe signal DQSi. For example, the first time period may correspond to one cycle of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 may compare the third positive data signal DDQ output through the first merge node TN with the third negative data signal / DDQ output through the second merge node BN in the first mode, and may generate and latch a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 may compare the third positive data signal DDQ output through the first merge node TN with the third negative data signal / DDQ output through the second merge node BN in the second mode, and may generate and latch a first comparison data signal corresponding to the comparison result.

[0083] The second comparison circuit C2 may be synchronized with the second data strobe signal DQSq and may perform a comparison operation within a second time period. The second time period may be related to the phase of the second data strobe signal DQSq. For example, the second time period may correspond to one cycle of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 may compare the third positive data signal DDQ output through the first merge node TN with the third negative data signal / DDQ output through the second merge node BN in the first mode, and may generate and latch a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 may compare the third positive data signal DDQ output through the first merge node TN with the third negative data signal / DDQ output through the second merge node BN in the second mode, and may generate and latch a second comparison data signal corresponding to the comparison result.

[0084] The third comparison circuit C3 can be synchronized with the third data strobe signal DQSib and can perform a comparison operation within a third time period. The third time period can be related to the phase of the third data strobe signal DQSib. For example, the third time period can correspond to one period of the third data strobe signal DQSib based on the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the fourth positive data signal DDQ' output through the third merging node TN' with the fourth negative data signal / DDQ' output through the fourth merging node BN' in the first mode, and can generate and latch a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the fourth positive data signal DDQ' output through the third merging node TN' with the fourth negative data signal / DDQ' output through the fourth merging node BN' in the second mode, and can generate and latch a third comparison data signal corresponding to the comparison result.

[0085] The fourth comparison circuit C4 can be synchronized with the fourth data strobe signal DQSqb and can perform a comparison operation within a fourth time period. The fourth time period can be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth time period can correspond to one period of the fourth data strobe signal DQSqb based on the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the fourth positive data signal DDQ' output through the third merging node TN' with the fourth negative data signal / DDQ' output through the fourth merging node BN' in the first mode, and can generate and latch a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the fourth positive data signal DDQ' output through the third merging node TN' with the fourth negative data signal / DDQ' output through the fourth merging node BN' in the second mode, and can generate and latch a fourth comparison data signal corresponding to the comparison result.

[0086] Each of the first to fourth comparison circuits C1 to C4 can receive a comparison data signal output from an adjacent comparison circuit C1 to C4. The first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This operation is called a decision feedback equalization (DFE) operation.

[0087] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0088] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0089] The third latch circuit LC3 can latch the third comparison data signal into a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0090] The fourth latch circuit LC4 can latch the fourth comparison data signal into a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0091] Figure 6 is a block diagram showing a semiconductor device 200 according to a second embodiment of the present disclosure.

[0092] Referring to Figure 6 , the semiconductor device 200 may include a data pad PD, a common path 210, a first data path 220, a second data path 230, and a synchronization path 240.

[0093] The data pad PD may be coupled to an external device. The data pad PD may receive a data signal DQ output from the external device. The data pad PD may be coupled to a power terminal of a high voltage VTT through a termination resistor RZ.

[0094] The common path 210 may be coupled between the data pad PD and a pair of common nodes CTN and CBN. The common path 210 may output differential common data signals CDQ and / CDQ to the pair of common nodes CTN and CBN based on the data signal DQ and the reference signal VREF, respectively.

[0095] The first data path 220 may be coupled between the pair of common nodes CTN and CBN and a pair of merged nodes TN and BN. The first data path 220 may be enabled in a first mode based on a mode selection signal EN. For example, the first mode may be a low speed mode in which a predetermined amount of internal delay time is applied. The first data path 220 may output first differential data signals DQ1 and / DQ1 as differential data signals DDQ and / DDQ to the pair of merged nodes TN and BN, respectively, in the first mode based on the differential common data signals CDQ and / CDQ and the mode selection signal EN.

[0096] The second data path 230 may be coupled between the pair of common nodes CTN and CBN and a pair of merged nodes TN and BN. The second data path 230 may be enabled in a second mode based on a mode selection signal EN. For example, the second mode may be a high speed mode in which no internal delay time is applied. The second data path 230 may output second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to the pair of merged nodes TN and BN, respectively, in the second mode based on the differential common data signals CDQ and / CDQ and the mode selection signal EN.

[0097] The synchronization path 240 can be connected to a pair of merging nodes TN and BN. The synchronization path 240 can output differential data signals DDQ and / DDQ in a first mode or a second mode as first to fourth data signals DQi, DQq, Dqib, and DQqb synchronized with first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. The first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb can have different phases. For example, the first data strobe signal DQSi and the second data strobe signal DQSq can have a phase difference of 90 degrees, the second data strobe signal DQSq and the third data strobe signal DQSib can have a phase difference of 90 degrees, and the third data strobe signal DQSib and the fourth data strobe signal DQSqb can have a phase difference of 90 degrees.

[0098] Figure 7 is a block diagram showing Figure 6 the common path 210, the first data path 220, the second data path 230, and the synchronization path 240 shown.

[0099] Referring to Figure 7 , the common path 210 can include a first input circuit AMP1.

[0100] The first input circuit AMP1 can output differential common data signals CDQ and / CDQ to a pair of common nodes CTN and CBN based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0101] The first data path 220 can include a second input circuit AMP2, a first replication circuit RP1, a second replication circuit RP2, and a third replication circuit RP3.

[0102] The second input circuit AMP2 can generate an input data signal based on the differential common data signals CDQ and / CDQ. For example, the second input circuit AMP2 can include an amplifier.

[0103] The first replication circuit RP1 can delay the input data signal by a first delay time amount and can output the delayed input data signal to a branch node VN. For example, the first replication circuit RP1 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0104] The second replication circuit RP2 can delay the delayed input data signal by a second delay time amount and can output the first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1 to the first merging node TN among a pair of merging nodes TN and BN. For example, the second replication circuit RP2 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series. The second repeater RT1 among the one or more repeaters located at the end of the second replication circuit RP2 (i.e., closest to the first merging node TN) can be enabled in response to the mode selection signal EN (refer to Figure 3 ).

[0105] The third replication circuit RP3 can delay the delayed input data signal by a second delay time amount and can output the first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1 to the second merging node BN among a pair of merging nodes TN and BN. For example, the third replication circuit RP3 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series. The third repeater RT2 among the one or more repeaters located at the end of the third replication circuit RP3 (i.e., closest to the second merging node BN) can be enabled in response to the mode selection signal EN (refer to Figure 3 ).

[0106] The first delay time amount and the second delay time amount can be determined according to the internal delay time amount caused by the paths for transmitting the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. For example, the sum of the first delay time amount and the second delay time amount can be equal to the internal delay time amount. Although not shown in the figure, the internal delay time amount can include the time point when the data strobe signal generated by an external device is input to the corresponding pad included in the semiconductor device 200 to the time point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 240.

[0107] The second data path 230 can include a third input circuit AMP3.

[0108] The third input circuit AMP3 can output the second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to a pair of merging nodes TN and BN respectively based on the differential common data signals CDQ and / CDQ. For example, the third input circuit AMP3 can include an amplifier.

[0109] The synchronization path 240 can include first to fourth comparison circuits C1 to C4 and first to fourth latch circuits LC1 to LC4.

[0110] The first comparison circuit C1 can be synchronized with the first data strobe signal DQSi and can perform a comparison operation within a first time period. The first time period can be related to the phase of the first data strobe signal DQSi. For example, the first time period can correspond to one period of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the first mode, and can generate and latch a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the second mode, and can generate and latch a first comparison data signal corresponding to the comparison result.

[0111] The second comparison circuit C2 can be synchronized with the second data strobe signal DQSq and can perform a comparison operation within a second time period. The second time period can be related to the phase of the second data strobe signal DQSq. For example, the second time period can correspond to one period of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the first mode, and can generate and latch a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the second mode, and can generate and latch a second comparison data signal corresponding to the comparison result.

[0112] The third comparison circuit C3 can be synchronized with the third data strobe signal DQSib and can perform a comparison operation within a third time period. The third time period can be related to the phase of the third data strobe signal DQSib. For example, the third time period can correspond to one period of the third data strobe signal DQSib based on the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the first mode, and can generate and latch a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the second mode, and can generate and latch a third comparison data signal corresponding to the comparison result.

[0113] The fourth comparison circuit C4 can be synchronized with the fourth data strobe signal DQSqb and can perform a comparison operation within a fourth time period. The fourth time period can be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth time period can correspond to one period of the fourth data strobe signal DQSqb based on the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the first mode, and can generate and latch a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the positive data signal DDQ output through the first merge node TN with the negative data signal / DDQ output through the second merge node BN in the second mode, and can generate and latch a fourth comparison data signal corresponding to the comparison result.

[0114] Each of the first to fourth comparison circuits C1 to C4 can receive a comparison data signal output from an adjacent comparison circuit C1 to C4. The first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This operation is called a decision feedback equalization (DFE) operation.

[0115] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0116] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0117] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0118] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0119] In an embodiment, it is described that the second data path 230 includes a third input circuit AMP3, but the embodiment is not necessarily limited thereto, and the second data path 230 can be designed in the same manner as Figure 5 the second data path 120 shown. Therefore, the connection structure between the second data path 230 and the synchronization path 240 can be designed in the same manner as Figure 5 the connection structure between the second data path 120 and the synchronization path 130 shown.

[0120] Figure 8 is a block diagram showing a semiconductor device 300 according to a third embodiment of the present disclosure.

[0121] Referring Figure 8 , the semiconductor device 300 may include a data pad PD, a first data path 310, a second data path 320, and a synchronization path 330.

[0122] The data pad PD may be coupled to an external device. The data pad PD may receive a data signal DQ output from the external device. The data pad PD may be coupled to a power terminal of a high voltage VTT through a termination resistor RZ.

[0123] The first data path 310 may be coupled between the data pad PD and the synchronization path 330. The first data path 310 may generate first differential data signals DQ1 and / DQ1 in a first mode based on the data signal DQ and a reference signal VREF. For example, the first mode may be a low-speed mode in which a predetermined amount of internal delay time is applied.

[0124] The second data path 320 may be coupled between the data pad PD and the synchronization path 330. The second data path 320 may generate second differential data signals DQ2 and / DQ2 in a second mode based on the data signal DQ and the reference signal VREF. For example, the second mode may be a high-speed mode in which no internal delay time is applied.

[0125] Although not shown in the figure, in the first mode, the first data path 310 may be enabled and the second data path 320 may be disabled, and in the second mode, the first data path 310 may be disabled and the second data path 320 may be enabled.

[0126] Based on the mode selection signal EN, the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb, the first differential data signals DQ1 and / DQ1, and the second differential data signals DQ2 and / DQ2, in the first mode and the second mode, the synchronization path 330 can output differential data signals selected from the first differential data signals DQ1 and / DQ1 and the second differential data signals DQ2 and / DQ2 as the first to fourth data signals DQi, DQq, DQib, and DQqb synchronized with the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. The first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb can have different phases. For example, the first data strobe signal DQSi and the second data strobe signal DQSq can have a phase difference of 90 degrees, the second data strobe signal DQSq and the third data strobe signal DQSib can have a phase difference of 90 degrees, and the third data strobe signal DQSib and the fourth data strobe signal DQSqb can have a phase difference of 90 degrees.

[0127] Figure 9 is a diagram showing Figure 8 the first data path 310, the second data path 320, and the synchronization path 330 shown in the figure.

[0128] Referring to Figure 9 , the first data path 310 may include a first input circuit AMP1, a first replication circuit RP1, a second replication circuit RP2, and a third replication circuit RP3.

[0129] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 may include an amplifier.

[0130] The first replication circuit RP1 can delay the input data signal by a first delay time amount and output the delayed input data signal to the branch node VN. For example, the first replication circuit RP1 may include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters may be connected in series.

[0131] The second replication circuit RP2 can delay the delayed input data signal by a second delay time amount and generate the first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1. For example, the second replication circuit RP2 may include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters may be connected in series.

[0132] The third replication circuit RP3 can delay the delayed input data signal by a second delay time amount and can generate a first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1. For example, the third replication circuit RP3 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0133] The first delay time amount and the second delay time amount can be determined according to the internal delay time amount caused by the paths for transmitting the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. For example, the sum of the first delay time amount and the second delay time amount can be equal to the internal delay time amount. Although not shown in the figure, the internal delay time amount can include the time point when the data strobe signal generated by an external device is input to the corresponding pad included in the semiconductor device 300 to the time point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 330.

[0134] The second data path 320 can include a second input circuit AMP2.

[0135] The second input circuit AMP2 can generate the second differential data signals DQ2 and / DQ2 based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier. Since the second input circuit AMP2 can be designed in the same manner as the Figure 4 second input circuit AMP2 shown, a detailed description of the second input circuit AMP2 is omitted.

[0136] The synchronization path 330 can include first and second selection circuits M1 and M2, first to fourth comparison circuits C1 to C4, and first to fourth latch circuits LC1 to LC4.

[0137] The first selection circuit M1 can generate the first differential data signals DQ1 and / DQ1 or the second differential data signals DQ2 and / DQ2 as the first differential selection data signal based on the mode selection signal EN.

[0138] The second selection circuit M2 can generate the first differential data signals DQ1 and / DQ1 or the second differential data signals DQ2 and / DQ2 as the second differential selection data signal based on the mode selection signal EN.

[0139] The first comparison circuit C1 can be synchronized with the first data strobe signal DQSi and can perform a comparison operation within a first time period. The first time period can be related to the phase of the first data strobe signal DQSi. For example, the first time period can correspond to one cycle of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 can compare the first differential selected data signals with each other in a first mode, and can generate and latch a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 can compare the first differential selected data signals with each other in a second mode, and can generate and latch a first comparison data signal corresponding to the comparison result.

[0140] The second comparison circuit C2 can be synchronized with the second data strobe signal DQSq and can perform a comparison operation within a second time period. The second time period can be related to the phase of the second data strobe signal DQSq. For example, the second time period can correspond to one cycle of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 can compare the first differential selected data signals with each other in a first mode, and can generate and latch a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 can compare the first differential selected data signals with each other in a second mode, and can generate and latch a second comparison data signal corresponding to the comparison result.

[0141] The third comparison circuit C3 can be synchronized with the third data strobe signal DQSib and can perform a comparison operation within a third time period. The third time period can be related to the phase of the third data strobe signal DQSib. For example, the third time period can correspond to one cycle of the third data strobe signal DQSib based on the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the second differential selected data signals with each other in a first mode, and can generate and latch a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the second differential selected data signals with each other in a second mode, and can generate and latch a third comparison data signal corresponding to the comparison result.

[0142] The fourth comparison circuit C4 can be synchronized with the fourth data strobe signal DQSqb and can perform a comparison operation within a fourth time period. The fourth time period can be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth time period can correspond to one period of the fourth data strobe signal DQSqb based on the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the second differential selected data signals with each other in a first mode and can generate and latch a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the second differential selected data signals with each other in a second mode and can generate and latch a fourth comparison data signal corresponding to the comparison result.

[0143] Each of the first to fourth comparison circuits C1 to C4 can receive a comparison data signal output from an adjacent comparison circuit C1 to C4. The first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This operation is called a decision feedback equalization (DFE) operation.

[0144] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0145] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0146] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0147] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0148] Figure 10 is a circuit diagram showing Figure 9 the first selection circuit M1 included in the synchronization path 330 shown.

[0149] Referring to Figure 10 , the first selection circuit M1 can include a source unit MC1, a sink unit MC2, a first selection unit MC3, and a second selection unit MC4.

[0150] The source unit MC1 can be connected between the power supply terminal of the first voltage and a pair of output terminals (+, -). For example, the source unit MC1 can include a first resistor and a second resistor. The first resistor can be connected between the power supply terminal of the first voltage and the first output terminal (+). The second resistor can be connected between the power supply terminal of the first voltage and the second output terminal (-).

[0151] The bus unit MC2 can be connected between the connection node NN and the power supply terminal of the second voltage. For example, the bus unit MC2 can include a first transistor and a second transistor connected in series. The first transistor can be connected between the connection node NN and the sink node and can receive the bias voltage VBIAS at its gate terminal. The second transistor can be connected between the sink node and the power supply terminal of the second voltage, and can receive the enable signal PG_EN at its gate terminal.

[0152] Based on the inverted signal / EN of the mode selection signal EN, the first selection unit MC3 can be enabled in the first mode and disabled in the second mode.

[0153] Based on the mode selection signal EN, the second selection unit MC4 can be enabled in the second mode and disabled in the first mode.

[0154] Since Figure 9 the second selection circuit M2 included in the synchronization path 330 shown can be designed in the same way as Figure 10 the first selection circuit M1 shown, the detailed description of the second selection circuit M2 is omitted.

[0155] Figure 11 is a block diagram showing Figure 8 another embodiment of the first data path 310, the second data path 320, and the synchronization path 330 shown.

[0156] Referring to Figure 11 , the first data path 310 can include a first input circuit AMP1, a first replication circuit RP1, a second replication circuit RP2, and a third replication circuit RP3.

[0157] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0158] The first replication circuit RP1 can delay the input data signal by a first delay time amount and output the delayed input data signal to the branch node VN. For example, the first replication circuit RP1 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0159] The second replication circuit RP2 can delay the delayed input data signal by a second delay time amount and generate a first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1. For example, the second replication circuit RP2 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0160] The third replication circuit RP3 can delay the delayed input data signal by a second delay time amount and generate a first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1. For example, the third replication circuit RP3 can include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters can be connected in series.

[0161] The first delay time amount and the second delay time amount can be determined according to the internal delay time amount caused by the paths for transmitting the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. For example, the sum of the first delay time amount and the second delay time amount can be equal to the internal delay time amount. Although not shown in the figure, the internal delay time amount can include the time point when the data strobe signal generated by an external device is input to the corresponding pad included in the semiconductor device 300 to the time point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 330.

[0162] The second data path 320 can include second to fourth input circuits AMP2, AMP3, and AMP4.

[0163] The second input circuit AMP2 can output a differential input data signal to a pair of branch nodes DTN and DBN based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0164] The third input circuit AMP3 can generate second differential data signals DQ2 and / DQ2 based on the differential input data signal. For example, the third input circuit AMP3 can include an amplifier.

[0165] The fourth input circuit AMP4 can generate third differential data signals DQ2’ and / DQ2’ based on differential input data signals. For example, the fourth input circuit AMP4 can include an amplifier.

[0166] The second to fourth input circuits AMP2, AMP3, and AMP4 can be designed in the same or different ways as Figure 4 the shown second input circuit AMP2.

[0167] The synchronization path 330 can include first and second selection circuits M1 and M2, first to fourth comparison circuits C1 to C4, and first to fourth latch circuits LC1 to LC4.

[0168] The first selection circuit M1 can generate first differential data signals DQ1 and / DQ1 or second differential data signals DQ2 and / DQ2 as first differential selection data signals based on a mode selection signal EN.

[0169] The second selection circuit M2 can generate first differential data signals DQ1 and / DQ1 or third differential data signals DQ2’ and / DQ2’ as second differential selection data signals based on a mode selection signal EN.

[0170] The first comparison circuit C1 can be synchronized with a first data strobe signal DQSi and can perform a comparison operation within a first time period. The first time period can be related to the phase of the first data strobe signal DQSi. For example, the first time period can correspond to one period of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 can compare the first differential selection data signals with each other in a first mode and can generate and latch a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 can compare the first differential selection data signals with each other in a second mode and can generate and latch a first comparison data signal corresponding to the comparison result.

[0171] The second comparison circuit C2 can be synchronized with a second data strobe signal DQSq and can perform a comparison operation within a second time period. The second time period can be related to the phase of the second data strobe signal DQSq. For example, the second time period can correspond to one period of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 can compare the first differential selection data signals with each other in a first mode and can generate and latch a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 can compare the first differential selection data signals with each other in a second mode and can generate and latch a second comparison data signal corresponding to the comparison result.

[0172] The third comparison circuit C3 can be synchronized with the third data strobe signal DQSib and can perform a comparison operation within a third time period. The third time period can be related to the phase of the third data strobe signal DQSib. For example, the third time period can correspond to one period of the third data strobe signal DQSib based on the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the second differential selected data signals with each other in a first mode and can generate and latch a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the second differential selected data signals with each other in a second mode and can generate and latch a third comparison data signal corresponding to the comparison result.

[0173] The fourth comparison circuit C4 can be synchronized with the fourth data strobe signal DQSqb and can perform a comparison operation within a fourth time period. The fourth time period can be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth time period can correspond to one period of the fourth data strobe signal DQSqb based on the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the second differential selected data signals with each other in a first mode and can generate and latch a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the second differential selected data signals with each other in a second mode and can generate and latch a fourth comparison data signal corresponding to the comparison result.

[0174] Each of the first to fourth comparison circuits C1 to C4 can receive a comparison data signal output from an adjacent comparison circuit C1 to C4. The first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This operation is called a decision feedback equalization (DFE) operation.

[0175] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0176] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0177] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0178] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0179] Figure 12 is a block diagram showing Figure 8 another embodiment of the first data path 310, the second data path 320, and the synchronization path 330 shown.

[0180] Referring to Figure 12 , the first data path 310 may include a first input circuit AMP1, a first replication circuit RP1, a second replication circuit RP2, and a third replication circuit RP3.

[0181] The first input circuit AMP1 may generate an input data signal based on a data signal DQ and a reference signal VREF. For example, the first input circuit AMP1 may include an amplifier.

[0182] The first replication circuit RP1 may delay the input data signal by a first delay time amount and may output the delayed input data signal to a branch node VN. For example, the first replication circuit RP1 may include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters may be connected in series.

[0183] The second replication circuit RP2 may delay the delayed input data signal by a second delay time amount and may generate a first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1. For example, the second replication circuit RP2 may include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters may be connected in series.

[0184] The third replication circuit RP3 may delay the delayed input data signal by a second delay time amount and may generate a first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1. For example, the third replication circuit RP3 may include one or more delay lines (e.g., RC lines) and one or more repeaters. The one or more delay lines and the one or more repeaters may be connected in series.

[0185] The first delay time amount and the second delay time amount may be determined according to an internal delay time amount caused by a path for transmitting the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb. For example, the sum of the first delay time amount and the second delay time amount may be equal to the internal delay time amount. Although not shown in the figure, the internal delay time amount may include a time point when a data strobe signal generated by an external device is input to a corresponding pad included in the semiconductor device 300 to a time point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 330.

[0186] The second data path 320 may include a second input circuit AMP2.

[0187] The second input circuit AMP2 may generate a second differential data signal DQ2 and / DQ2 based on a data signal DQ and a reference signal VREF. For example, the second input circuit AMP2 may include an amplifier.

[0188] The synchronization path 330 may include first to fourth integrated circuits X1 to X4, and first to fourth latch circuits LC1 to LC4.

[0189] Based on a mode selection signal EN and a first data strobe signal DQSi, the first integrated circuit X1 may select the first differential data signal DQ1 and / DQ1 or the second differential data signal DQ2 and / DQ2 within a first time period, and may simultaneously compare the positive data signal included in the selected differential data signal with the negative data signal included in the selected differential data signal, thereby generating a first comparison data signal. The first time period may be related to the phase of the first data strobe signal DQSi.

[0190] Based on a mode selection signal EN and a second data strobe signal DQSq, the second integrated circuit X2 may select the first differential data signal DQ1 and / DQ1 or the second differential data signal DQ2 and / DQ2 within a second time period, and may simultaneously compare the positive data signal included in the selected differential data signal with the negative data signal included in the selected differential data signal, thereby generating a second comparison data signal. The second time period may be related to the phase of the second data strobe signal DQSq.

[0191] Based on a mode selection signal EN and a third data strobe signal DQSib, the third integrated circuit X3 may select the first differential data signal DQ1 and / DQ1 or the second differential data signal DQ2 and / DQ2 within a third time period, and may simultaneously compare the positive data signal included in the selected differential data signal with the negative data signal included in the selected differential data signal, thereby generating a third comparison data signal. The third time period may be related to the phase of the third data strobe signal DQSib.

[0192] Based on a mode selection signal EN and a fourth data strobe signal DQSqb, the fourth integrated circuit X4 may select the first differential data signal DQ1 and / DQ1 or the second differential data signal DQ2 and / DQ2 within a fourth time period, and may simultaneously compare the positive data signal included in the selected differential data signal with the negative data signal included in the selected differential data signal, thereby generating a fourth comparison data signal. The fourth time period may be related to the phase of the fourth data strobe signal DQSqb.

[0193] The first latch circuit LC1 can latch the first comparison data signal into a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0194] The second latch circuit LC2 can latch the second comparison data signal into a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0195] The third latch circuit LC3 can latch the third comparison data signal into a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0196] The fourth latch circuit LC4 can latch the fourth comparison data signal into a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0197] In an embodiment, it is described that the second data path 320 includes a second input circuit AMP2, but the embodiment is not necessarily limited thereto, and the second data path 320 can be designed in the same manner as Figure 9 the second data path 320 shown. Therefore, the connection structure between the second data path 320 and the synchronization path 330 can be designed to be similar to Figure 9 the connection structure between the second data path 320 and the synchronization path 330 shown in

[0198] Figure 13 is a circuit diagram showing Figure 12 the first integrated circuit X1 shown in

[0199] Referring to Figure 13 , the first integrated circuit X1 can include a common source circuit SOC, a first bus circuit SK1, and a second bus circuit SK2.

[0200] The common source circuit SOC can be connected between the power supply terminal of the first voltage and a pair of output terminals OT1 and OT2. When the first data strobe signal DQSi is at a low logic level, the common source circuit SOC can reset or precharge the pair of output terminals OT1 and OT2 to the first voltage, such as VDD.

[0201] The first bus circuit SK1 can be connected between a pair of output terminals OT1 and OT2 and the power supply terminal of the second voltage. Based on the first mode signal MD_M, the first bus circuit SK1 can be enabled in the first mode, i.e., the low-speed mode, and disabled in the second mode, i.e., the high-speed mode. The first bus circuit SK1 can output differential data signals COUT and TOUT corresponding to the first differential data signals DQ1 and / DQ1 through a pair of output terminals OT1 and OT2 based on the first data strobe signal DQSi. The differential data signals COUT and TOUT can correspond to the result of comparing the positive data signal DQ1 included in the first differential data signals DQ1 and / DQ1 with the negative data signal / DQ1.

[0202] The second bus circuit SK2 can be connected between a pair of output terminals OT1 and OT2 and the power supply terminal of the second voltage. Based on the second mode signal MD_U, the second bus circuit SK2 can be enabled in the second mode and disabled in the first mode. The second bus circuit SK2 can output differential data signals COUT and TOUT corresponding to the second differential data signals DQ2 and / DQ2 through a pair of output terminals OT1 and OT2 based on the first data strobe signal DQSi. The differential data signals COUT and TOUT can correspond to the result of comparing the positive data signal DQ2 included in the second differential data signals DQ2 and / DQ2 with the negative data signal / DQ2. When generating the differential data signals COUT and TOUT, the second bus circuit SK2 can be based on the equalization control signal KDFE <m:0>Perform a decision feedback equalization (DFE) operation with the previous differential data signals LAT_PRE and / LAT_PRE.

[0203] The generation circuit GNR can generate differential comparison data signals LAT and / LAT based on the differential data signals COUT and TOUT. One of the positive comparison data signal LAT and the negative comparison data signal / LAT included in the differential comparison data signals LAT and / LAT can be the first comparison data signal.

[0204] In an embodiment, the common source circuit SOC, the first bus circuit SK1, the second bus circuit SK2, and the generation circuit GNR can be a configuration integrating a double-tail latch-based comparison circuit and a DFE circuit. However, this embodiment is not necessarily limited thereto, and can have a configuration integrating various types of comparison circuits (e.g., a strong-arm-based comparison circuit) and a DFE circuit.

[0205] The control circuit CTR can generate a first mode signal MD_M and a second mode signal MD_U based on a mode selection signal EN and an operation enable signal EN_DIN. For example, the control circuit CTR can activate the first mode signal MD_M and deactivate the second mode signal MD_U in the first mode, can deactivate the first mode signal MD_M and activate the second mode signal MD_U in the second mode, and can deactivate both the first mode signal MD_M and the second mode signal MD_U in a specific mode. The operation enable signal EN_DIN can be a write enable signal corresponding to a write mode, and the specific mode can be at least one mode other than the write mode.

[0206] In an embodiment, it is described that the control circuit CTR is included in each of the first to fourth integrated circuits X1 to X4, but the embodiment is not necessarily limited thereto, and the first to fourth integrated circuits X1 to X4 can be designed to share a control circuit CTR.

[0207] According to an embodiment of the present disclosure, various interface modes can be supported.

[0208] According to an embodiment of the present disclosure, various interface modes can be supported, thereby improving compatibility.

[0209] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are for illustrative purposes only and are not intended to be limiting. Further, it should be noted that the embodiments of the present disclosure can be implemented in various ways by substitutions, changes, and modifications that fall within the scope of the appended claims, as will be recognized by those skilled in the art based on the present disclosure. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should include equivalents thereof.

[0210] In the above embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, these operations are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the drawings are only examples for facilitating the understanding of the present disclosure, and the present disclosure is not limited to these embodiments. That is to say, it will be obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure.

[0211] The embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to describe the embodiments of the present disclosure. Accordingly, the present disclosure is not limited to the above-described embodiments, and many variations are possible within the scope of the present disclosure. It will be obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein. Further, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: Data pad; At least one merge node; a first data path coupled between the data pad and the at least one merging node and outputting a first data signal to the at least one merging node in a first mode based on a data signal, a reference signal, and a mode selection signal; a second data path coupled between the data pad and the at least one merging node and outputting a second data signal to the at least one merging node in a second mode based on the data signal, the reference signal, and the mode selection signal; as well as A synchronization path is coupled to the at least one merging node and outputs a corresponding signal of the first data signal and the second data signal as a data signal synchronized with at least one data strobe signal in one of the first mode and the second mode.

2. The semiconductor device according to claim 1, wherein The at least one merge node includes a first merge node and a second merge node, and The first data path comprises: a first input circuit, generating an input data signal based on the data signal and the reference signal; a first replica circuit that delays the input data signal by a first delay time amount and outputs the delayed input data signal to the branch node; a second replica circuit that delays the delayed input data signal by a second delay time amount and outputs a first positive data signal corresponding to the first data signal to the first merging node; and A third replica circuit delays the delayed input data signal by the second delay time amount and outputs a first negative data signal corresponding to the first data signal to the second merging node.

3. The semiconductor device according to claim 2, wherein: The second replica circuit comprises: a first pull-up driver coupled between a power supply terminal of a first voltage and a first power supply node and receiving a first driving data signal corresponding to the delayed input data signal; a first selection driver coupled between the first power supply node and the first output node and receiving the mode selection signal; a second selection driver connected between the first output node and a second power supply node and receiving an inverted signal of the mode selection signal; and The first pull-down driver is coupled between the second power supply node and a power supply terminal of a second voltage, and receives the first driving data signal.

4. The semiconductor device according to claim 2, wherein: The third replica circuit comprises: a second pull-up driver coupled between the power supply terminal of the first voltage and a third power supply node and receiving a second driving data signal corresponding to the delayed input data signal; a third selection driver coupled between the third power supply node and the second output node and receiving the mode selection signal; a fourth selection driver connected between the second output node and a fourth power supply node and receiving an inverted signal of the mode selection signal; and The second pull-down driver is coupled between the fourth power supply node and a power supply terminal of a second voltage and receives the second driving data signal.

5. The semiconductor device according to claim 2, wherein: The first delay time amount and the second delay time amount are determined according to an internal delay time amount caused by a path transmitting the data strobe signal.

6. The semiconductor device according to claim 2, wherein: The second data path includes a second input circuit that outputs a second positive data signal and a second negative data signal corresponding to the second data signal to respective first and second merging nodes based on the data signal and the reference signal.

7. The semiconductor device according to claim 6, wherein: The second input circuit comprises: A source driver connected between a power supply terminal of a first voltage and a common node and receiving a bias voltage; a first input driver coupled between the common node and the first node and receiving the data signal; a fifth selection driver, connected between the first node and the second merging node, and receiving an inverted signal of the mode selection signal; a second input driver coupled between the common node and a second node and receiving the reference signal; a sixth selection driver, connected between the second node and the first merging node, and receiving an inverted signal of the mode selection signal; A first bus driver, connected between the second merging node and a power supply terminal of a second voltage, and receiving a control signal; a second bus driver coupled between the first merging node and a power supply terminal of the second voltage and receiving the control signal; and A logic circuit generates the control signal based on the mode selection signal and the enable signal.

8. The semiconductor device according to claim 6, wherein: The synchronization path includes: at least one comparison circuit that generates at least one comparison data signal by comparing a first target signal and a second target signal with each other based on the at least one data strobe signal, the first target signal being one of a first positive data signal and a second positive data signal output through the first merging node, and the second target signal being one of a first negative data signal and a second negative data signal output through the second merging node; and At least one latch circuit latches the at least one comparison data signal into a data signal synchronized with the at least one data strobe signal.

9. The semiconductor device according to claim 8, wherein: The at least one comparison circuit performs the comparison by a decision feedback equalization operation, ie, a DFE operation.

10. The semiconductor device according to claim 1, wherein The at least one merging node includes a first merging node, a second merging node, a third merging node, and a fourth merging node, and The first data path includes: a first input circuit, generating an input data signal based on the data signal and the reference signal; a first replica circuit that delays the input data signal by a first delay time amount and outputs the delayed input data signal to the branch node; a second replica circuit that delays the delayed input data signal by a second delay time amount and outputs a first positive data signal corresponding to the first data signal to the first merging node and the third merging node; and A third replica circuit delays the delayed input data signal by the second delay time amount and outputs a first negative data signal corresponding to the first data signal to the second merging node and the fourth merging node.

11. The semiconductor device according to claim 10, wherein The second data path includes: a second input circuit that outputs a positive input data signal and a negative input data signal to the corresponding first node and second node based on the data signal and the reference signal; a first amplifying circuit, outputting a second positive data signal and a second negative data signal corresponding to the second data signal to corresponding first merging nodes and second merging nodes based on the positive input data signal and the negative input data signal; and The second amplifying circuit outputs a third positive data signal and a third negative data signal corresponding to the second data signal to the corresponding third merging node and fourth merging node based on the positive input data signal and the negative input data signal.

12. The semiconductor device according to claim 11, wherein The synchronization path includes: at least one first comparison circuit that generates at least one first comparison data signal by comparing a first target signal and a second target signal with each other based on the at least one data strobe signal, the first target signal being one of a first positive data signal and a second positive data signal output through the first merging node, and the second target signal being one of a first negative data signal and a second negative data signal output through the second merging node; at least one second comparison circuit that generates at least one second comparison data signal by comparing a third target signal and a fourth target signal with each other based on the at least one data strobe signal, the third target signal being one of a first positive data signal and a second positive data signal output through the third merging node, and the fourth target signal being one of a first negative data signal and a second negative data signal output through the fourth merging node; and A plurality of latch circuits latch the at least one first comparison data signal and the at least one second comparison data signal as data signals synchronized with the at least one data strobe signal.

13. The semiconductor device according to claim 12, wherein: Each of the at least one first comparison circuit and the at least one second comparison circuit performs the comparison through a decision feedback equalization operation, ie, a DFE operation.

14. A semiconductor device comprising: Data pad; At least one public node; a common path coupled between the data pad and the at least one common node and outputting a common data signal to the at least one common node based on a data signal and a reference signal; At least one merge node; a first data path coupled between the at least one common node and the at least one merging node and outputting a first data signal to the at least one merging node in a first mode based on the common data signal and a mode selection signal; a second data path coupled between the at least one common node and the at least one merging node and outputting a second data signal to the at least one merging node in a second mode based on the common data signal and the mode selection signal; as well as A synchronization path is coupled to the at least one merging node and outputs a corresponding signal of the first data signal and the second data signal as a data signal synchronized with a data strobe signal in one of the first mode and the second mode.

15. The semiconductor device according to claim 14, wherein: The at least one merge node includes a first merge node and a second merge node, and The first data path comprises: a first input circuit that generates an input data signal based on the common data signal and the mode selection signal; a first replica circuit that delays the input data signal by a first delay time amount and outputs the delayed input data signal to the branch node; a second replica circuit that delays the delayed input data signal by a second delay time amount and outputs a first positive data signal corresponding to the first data signal to the first merging node; and A third replica circuit delays the delayed input data signal by the second delay time amount and outputs a first negative data signal corresponding to the first data signal to the second merging node.

16. The semiconductor device according to claim 15, wherein: The second replica circuit comprises: a first pull-up driver coupled between a power supply terminal of a first voltage and a first power supply node and receiving a first driving data signal corresponding to the delayed input data signal; a first selection driver coupled between the first power supply node and the first output node and receiving the mode selection signal; a second selection driver connected between the first output node and a second power supply node and receiving an inverted signal of the mode selection signal; and The first pull-down driver is coupled between the second power supply node and a power supply terminal of a second voltage, and receives the first driving data signal.

17. The semiconductor device according to claim 15, wherein: The third replica circuit comprises: a second pull-up driver coupled between the power supply terminal of the first voltage and a third power supply node and receiving a second driving data signal corresponding to the delayed input data signal; a third selection driver coupled between the third power supply node and the second output node and receiving the mode selection signal; a fourth selection driver connected between the second output node and a fourth power supply node and receiving an inverted signal of the mode selection signal; and The second pull-down driver is coupled between the fourth power supply node and a power supply terminal of a second voltage and receives the second driving data signal.

18. The semiconductor device according to claim 15, wherein The first delay time amount and the second delay time amount are determined according to an internal delay time amount caused by a path transmitting the data strobe signal.

19. The semiconductor device according to claim 15, wherein: The second data path includes a second input circuit that outputs a second positive data signal and a second negative data signal corresponding to the second data signal to the respective first and second merging nodes based on the common data signal and the mode selection signal.

20. The semiconductor device according to claim 19, wherein The second input circuit comprises: A source driver connected between a power supply terminal of a first voltage and a common node and receiving a bias voltage; a first input driver coupled between the common node and the first node and receiving a positive data signal among differential data signals corresponding to the common data signal; a fifth selection driver, connected between the first node and the second merging node, and receiving an inverted signal of the mode selection signal; a second input driver connected between the common node and the second node and receiving a negative data signal among the differential data signals; a sixth selection driver, connected between the second node and the first merging node, and receiving an inverted signal of the mode selection signal; A first bus driver, connected between the second merging node and a power supply terminal of a second voltage, and receiving a control signal; a second bus driver coupled between the first merging node and a power supply terminal of the second voltage and receiving the control signal; and A logic circuit generates the control signal based on the mode selection signal and the enable signal.

21. The semiconductor device according to claim 19, wherein The synchronization path includes: at least one comparison circuit that generates at least one comparison data signal by comparing a first target signal and a second target signal with each other based on the at least one data strobe signal, the first target signal being one of a first positive data signal and a second positive data signal output through the first merging node, and the second target signal being one of a first negative data signal and a second negative data signal output through the second merging node; and At least one latch circuit latches the at least one comparison data signal into a data signal synchronized with the data strobe signal.

22. The semiconductor device according to claim 21, wherein The at least one comparison circuit performs the comparison by a decision feedback equalization operation, ie, a DFE operation.

23. A semiconductor device comprising: A first data path generates a first data signal in a first mode based on the data signal and the reference signal; a second data path, generating a second data signal in a second mode based on the data signal and the reference signal; as well as a synchronization path that outputs a selected data signal among the first data signal and the second data signal in each of the first mode and the second mode as a data signal synchronized with the at least one data strobe signal based on a mode selection signal, at least one data strobe signal, and the first data signal and the second data signal.

24. The semiconductor device according to claim 23, wherein: The first data path comprises: a first input circuit, generating an input data signal based on the data signal and the reference signal; a first replica circuit that delays the input data signal by a first delay time amount and outputs the delayed input data signal to the branch node; a second replica circuit that delays the delayed input data signal by a second delay time amount and generates a first positive data signal corresponding to the first data signal; and The third replica circuit delays the delayed input data signal by the second delay time amount and generates a first negative data signal corresponding to the first data signal.

25. The semiconductor device according to claim 24, wherein: The first delay time amount and the second delay time amount are determined according to an internal delay time amount caused by a path transmitting the at least one data strobe signal.

26. The semiconductor device according to claim 23, wherein: The second data path includes: a second input circuit, generating an input data signal based on the data signal and the reference signal; a first amplifying circuit, generating a third data signal corresponding to the second data signal based on the input data signal; The second amplifier circuit generates a fourth data signal corresponding to the second data signal based on the input data signal.

27. The semiconductor device according to claim 26, wherein: The synchronization path includes: a first selection circuit, outputting one of the first data signal and the third data signal as a first selection data signal based on the mode selection signal; at least one first comparison circuit, generating at least one first comparison data signal by comparing a positive signal and a negative signal included in the first selection data signal based on the at least one data strobe signal; a second selection circuit, outputting one of the first data signal and the fourth data signal as a second selection data signal based on the mode selection signal; at least one second comparison circuit that generates at least one second comparison data signal by comparing a positive signal and a negative signal included in the second selection data signal based on the at least one data strobe signal; and A plurality of latch circuits latch the at least one first comparison data signal and the at least one second comparison data signal as data signals synchronized with the at least one data strobe signal.

28. The semiconductor device according to claim 27, wherein: Each of the at least one first comparison circuit and the at least one second comparison circuit performs the comparison through a decision feedback equalization operation, ie, a DFE operation.

29. The semiconductor device according to claim 23, wherein: The synchronization path includes: at least one integrated circuit that selects one of the first data signal and the second data signal based on the mode selection signal and the at least one data strobe signal, and generates at least one comparison data signal by comparing a positive signal and a negative signal included in the selected data signal; and At least one latch circuit latches the at least one comparison data signal into a data signal synchronized with the at least one data strobe signal.

30. The semiconductor device according to claim 29, wherein The at least one integrated circuit comprises: A common source circuit connected between a power supply terminal of a first voltage and a pair of output nodes; a first bus circuit coupled between the pair of output nodes and a power supply terminal of a second voltage and outputting a differential data signal corresponding to the first data signal through the pair of output nodes in a first mode based on the at least one data strobe signal; a second bus circuit coupled between the pair of output nodes and a power supply terminal of the second voltage and outputting a differential data signal corresponding to the second data signal through the pair of output nodes in a second mode based on the at least one data strobe signal; and A generating circuit generates the at least one comparison data signal based on a differential data signal corresponding to a selected data signal of the first data signal and the second data signal.

31. The semiconductor device according to claim 30, wherein: The second bus circuit further generates a differential data signal corresponding to the second data signal by performing a decision feedback equalization operation (DFE) based on at least one equalization control signal and a previous differential data signal.

32. The semiconductor device according to claim 30, wherein: The at least one integrated circuit further includes a control circuit that activates each of the first mode and the second mode based on the mode selection signal and an operation enable signal.

Images