Memory device and operation method of data movement between memory blocks and external interface

Abstract

The invention discloses a memory device which comprises a memory array and a data transfer circuit. The memory array is divided into a plurality of memory blocks, and each memory block comprises a memory unit. The data transfer circuit is located between two memory blocks, and data can be moved from all or a selected group of bit lines in one memory block to an adjacent memory block, or moved between data interfaces outside the bit lines in the memory block through the data transfer circuit. Data signals of all or a selected group of bit lines in the memory block are sensed, latched, buffered and repeated by the data transfer circuit for data transmission or logical operation execution. The data movement and logic operations in the memory device can be performed in parallel. In addition, a method of controlling and operating such a memory device is also provided.

Description

Technical Field

[0001] The present invention relates to memory management, and more particularly to an operating method for moving data between memory devices and memory blocks and through external interfaces. Background Technology

[0002] The data access scheme of traditional memory devices usually faces the problem of the inability to balance the area of ​​the array peripheral circuit, power consumption and bandwidth. This problem becomes more serious when traditional memory devices are used as AI / ML computing storage units. Therefore, a novel architecture and data access method are urgently needed to solve these limitations. SUMMARY OF THE INVENTION

[0003] Therefore, one of the purposes of the present invention is to provide a memory device and an operation method for moving data between memory blocks and through an external interface to solve the above-mentioned problems.

[0004] An embodiment of the present invention provides a memory device, comprising: a memory array, divided into a plurality of memory blocks, each memory block including a plurality of memory cells; and a plurality of data transfer circuits, each data transfer circuit being arranged between two memory blocks; wherein a data movement occurring from all or selected groups of bit lines or bit line pairs between any two adjacent memory blocks of the memory array is performed, during which a data transfer circuit arranged between two adjacent memory blocks senses, latches, buffers and repeats data signals of all or selected groups of bit lines or bit line pairs between two adjacent memory blocks, and the data movement is performed sequentially between the two memory blocks to transmit the data signal to any memory block in the memory array without requiring global or multi-block length data lines.

[0005] An embodiment of the present invention also provides an operating method for data movement between memory blocks of a memory device and through an external interface of the memory device, wherein the memory device includes a memory array divided into a plurality of memory blocks, each memory block including a plurality of memory cells, and the operating method includes: performing a data movement occurring from all or selected groups of bit lines or bit line pairs between any two adjacent memory blocks of the memory array; during the data movement, a data transfer circuit disposed between the two memory blocks senses, latches, buffers and repeats data signals of all or selected groups of bit lines or bit line pairs of one of the two adjacent memory blocks to transmit to an adjacent memory block or an external interface of the memory device; and sequentially performing the data movement between the two memory blocks to transmit the data signal to the adjacent memory block and then to any memory block of the memory array without requiring global or multi-block length data lines. Brief Description of the Figures

[0006] Figure 1Schematic diagram of a memory device according to an embodiment of the present invention.

[0007] Figure 2 is Figure 1 Schematic diagram of an embodiment of a DRAM memory cell including a transistor and a capacitor in a memory array.

[0008] Figure 3 is Figure 1 Schematic diagram of an embodiment of a DRAM memory cell with six transistors in a memory array.

[0009] Figure 4 Schematic diagram of a first type of data transfer circuit according to an embodiment of the present invention.

[0010] Figure 5 Schematic diagram of a second type of data transfer circuit according to an embodiment of the present invention.

[0011] Figure 6 Schematic diagram of a third type of data transfer circuit according to an embodiment of the present invention.

[0012] Figure 7 Schematic diagram of a fourth type of data transfer circuit according to an embodiment of the present invention.

[0013] Figure 8 Schematic diagram of a fifth type of data transfer circuit according to an embodiment of the present invention.

[0014] Figure 9 Schematic diagram of a variant embodiment of the third type of data transfer circuit according to an embodiment of the present invention

[0015] Figure 10 Schematic diagram of a variant embodiment of the fourth type of data transfer circuit according to an embodiment of the present invention.

[0016] Figure 11 Schematic diagram of a variant embodiment of the fifth type of data transfer circuit according to an embodiment of the present invention.

[0017] Figure 12 Schematic diagram of another variant embodiment of the third type of data transfer circuit according to an embodiment of the present invention.

[0018] Figure 13 Schematic diagram of a first type of interface transfer circuit according to an embodiment of the present invention.

[0019] Figure 14 Schematic diagram of a second type of interface transfer circuit according to an embodiment of the present invention.

[0020] Figure 15 Schematic diagram of a third type of interface transfer circuit according to an embodiment of the present invention.

[0021] Figure 16Schematic diagram of a fourth - type interface transfer circuit according to an embodiment of the present invention.

[0022] Figure 17 Schematic diagram of a fifth - type interface transfer circuit according to an embodiment of the present invention.

[0023] Figure 18 Schematic diagram of a variant embodiment of a third - type interface transfer circuit according to an embodiment of the present invention

[0024] Figure 19 Schematic diagram of a variant embodiment of a fourth - type interface transfer circuit according to an embodiment of the present invention

[0025] Figure 20 Schematic diagram of a variant embodiment of a fifth - type interface transfer circuit according to an embodiment of the present invention

[0026] Figure 21 Schematic diagram of another variant embodiment of a fourth - type data transfer circuit according to an embodiment of the present invention.

[0027] Figure 22 And Figure 23 Schematic diagram of a variant embodiment of a third - type interface transfer circuit according to an embodiment of the present invention.

[0028] Figures 24 to 26 Schematic diagram of a variant embodiment of a fourth - type interface transfer circuit according to an embodiment of the present invention.

[0029] Figure 27 According to an embodiment of the present invention Figure 18 Schematic diagram of the circuit architecture of a third - type interface transfer circuit.

[0030] Figure 28 According to an embodiment of the present invention Figure 27 Schematic diagram of a variant embodiment of a third - type interface transfer circuit.

[0031] Figure 29 And Figure 30 According to an embodiment of the present invention Figure 18 Schematic diagram of a variant embodiment of a third - type interface transfer circuit.

[0032] Among them, the reference numerals are explained as follows:

[0033] 10: Memory device

[0034] 100: Memory array

[0035] 102: Memory block

[0036] 200: Data transfer circuit

[0037] 202: First - type data transfer circuit

[0038] 2022, 2022_1, 2022_2: First - type sensing buffer circuit

[0039] 2024, 2024_1, 2024_2: Second - type sensing buffer circuit

[0040] 2026: Third - type sensing buffer circuit

[0041] 2028, 2028_1, 2028_2, 2028_3, 2028_4: Fourth - type sensing buffer circuit

[0042] 204: Second - type data transfer circuit

[0043] 206: Third - type data transfer circuit

[0044] 208: Fourth - type data transfer circuit

[0045] 210: Fifth - type data transfer circuit

[0046] 300: Interface transfer circuit

[0047] 302: First - type interface transfer circuit

[0048] 304: Second - type interface transfer circuit

[0049] 306: Third - type interface transfer circuit

[0050] 308: Fourth - type interface transfer circuit

[0051] 310: Fifth - type interface transfer circuit

[0052] 400: Arithmetic logic circuit

[0053] 402: Multiplier - adder tree circuit

[0054] 404: Accumulator or activation operation circuit

[0055] BL, BLB, DLa - DLd: Bit line

[0056] BLSA, BLSA1, BLSA2, BLSA3, BLSA4: Bit - line sense amplifier

[0057] Cap: Capacitor

[0058] DI, DI1, DI2, DI3, DI4: Data interface

[0059] MUX1, MUX1_1, MUX1_2: First multiplexer

[0060] MUX2: Second multiplexer

[0061] Q1 - Q6: Transistors

[0062] WL: Word Line

[0063] X0 - X3: Select Signals Detailed Implementation Manner

[0064] Figure 1 FIG. is a schematic diagram of a memory device 10 according to an embodiment of the present invention. The memory device 10 can be applied to various memory cores, such as static - random - access memory (SRAM), dynamic random access memory (DRAM), resistive random access memory (RRAM), magneto - resistive random - access - memory (MRAM), ferroelectric random - access memory (FeRAM), or any other memory core. As Figure 1 shown, the memory device 10 includes a memory array 100, a data transfer circuit 200, an interface transfer circuit 300, and an arithmetic logic circuit 400. The memory array 100 can be used to store data. The memory array 100 can be divided into a plurality of memory blocks 102. Each memory block 102 includes a plurality of memory cells divided into multiple pages, and each page of memory cells is coupled to a corresponding word line. For example, the memory block 102 can be used to store parameters of an AI / ML model and intermediate data generated during deep operations. A plurality of bit lines and a plurality of word lines are respectively coupled to a plurality of memory cells of the memory array 100. These bit lines and word lines can be configured to perform access control of the memory array 100.

[0065] The memory array 100 can be designed using a differential bit - line mechanism or a single - bit - line mechanism. For example, for a memory array with a single - bit - line mechanism, please refer to Figure 2 , Figure 2 is Figure 1 a schematic diagram of an embodiment of a transistor and a capacitor (1T1C) dynamic random access memory (DRAM) memory cell of the memory array 100 in. The memory cell can be an embodiment of any memory cell (e.g., each memory cell) among the plurality of memory cells of the memory array 100. As Figure 2As shown, the memory cell may include switching transistors (e.g., implemented as transistors such as metal oxide semiconductor field effect transistors (MOSFETs)), which are coupled to a selected one of a plurality of word lines (e.g., word line WL) and a selected one of a plurality of bit lines (e.g., bit line BL), and the memory cell may include a capacitor Cap. The capacitor Cap can store memory charge, and different states of the charge can represent one bit of information (e.g., 0 or 1), but the present invention is not limited thereto. In some embodiments, two-transistor and two-capacitor (2T2C) memory cells may also be utilized to increase reliability. Those skilled in the art know the general structure and function of 2T2C memory cells. For a memory array with a differential bit line mechanism, please refer to Figure 3 , Figure 3 is Figure 1 a schematic diagram of an embodiment of a six-transistor (6T) dynamic random access memory (DRAM) memory cell of the memory array 100 in Figure 3 . As shown, the memory cell may include transistors Q1-Q6. Transistors Q1 and Q2 are coupled to a selected one of a plurality of word lines (e.g., word line WL) and a selected pair of bit lines (e.g., Figure 3 the bit lines BL and BLB in

[0066] to access or store data in the memory cell. Figure 1, the memory device 10 includes a plurality of data transfer circuits 200. Each data transfer circuit 200 is disposed between two memory blocks 102. Each data transfer circuit 200 is coupled to two bit lines or a pair of bit lines located in different memory blocks 102. The data transfer circuit 200 can serve as a data path for inter-section data movement. The data transfer circuit 200 can be coupled between two memory blocks 102 to perform data movement occurring on all or a selected group of bit lines or a pair of bit lines between any two adjacent memory blocks. The data transfer circuit 200 disposed between two adjacent memory blocks 102 can sense, latch, buffer, and reproduce data signals on all or a selected group of bit lines or a pair of bit lines of the two adjacent memory blocks 102. In this way, data movement can be sequentially performed between two memory blocks 102 of the memory array 100 to transmit data signals to any memory block 102 in the memory array 100 without using global or trans-multiple-section data lines. Therefore, the data signals can be sequentially passed between subsequent memory blocks through the data transfer circuits 200 between subsequent memory blocks 102, so that the data signals can be sequentially passed from one memory block to subsequent adjacent memory blocks until the target position is reached to achieve inter-block data movement. In addition, during block-by-block (one memory block followed by the next memory block) data transfer, the target memory block or the character lines of the signal passing through the block can be activated to retrieve the data on its bit lines or a pair of bit lines and store the obtained data in the memory cells coupled to the activated character lines. The data transfer circuit 200 can also serve as a circuit for transferring data from the memory block 102 to a signal interface different from the bit lines or a pair of bit lines (i.e., a signal interface other than the bit lines or a pair of bit lines). The data transfer circuit 200 can also serve as a circuit for transferring data from a signal interface different from the bit lines or a pair of bit lines to the memory block 102. The data sequence can be written into the data transfer circuit 200 block by block in a serial manner (standard manner), or parallelized to a plurality of data transfer circuits 200 in a parallel manner (transpose manner). A serial data originally stored in a memory cell coupled to a character line can be obtained, and then, with or without further processing, the serial data is subsequently sequentially stored in the memory cells coupled to a plurality of character lines in the memory block to rotate the serial data in the memory device in a transpose manner. A page of data can be pre-copied and moved from a memory block to a memory block adjacent to or near the arithmetic logic circuit to quickly or copy access and operate the page data.

[0067] The memory device 10 includes a plurality of interface transfer circuits 300. As Figure 1As shown, the memory block 102 coupled to the interface transfer circuit 300 can be regarded as an edge memory block. Each interface transfer circuit 300 is coupled to an edge memory block 102. The interface transfer circuit 300 can be used to directly transfer or multiplex data from the edge memory block 102 to a circuit connected to a signal interface different from a bit line or a pair of bit lines. Wherein the edge memory block 102 can be used as a cache block to pre-move and store data for subsequent rapid access. The interface transfer circuit 300 can also write data from the circuit connected to the signal interface different from the bit line or the pair of bit lines to the edge memory block 102 to achieve off-bit-line data transition. The circuit connected to the signal interface different from the bit line or the pair of bit lines can be any internal circuit in the memory device 10. For example, the circuit connected to the signal interface different from the bit line or the pair of bit lines can be a core logic circuit or an arithmetic logic circuit for subsequent arithmetic operations, but is not limited thereto. The circuit connected to the signal interface different from the bit line or the pair of bit lines can be an external device. For example, the circuit connected to the signal interface different from the bit line or the pair of bit lines can be a large-capacity storage device, but is not limited thereto.

[0068] Please continue to refer to Figure 1, any two memory blocks can be the same as or similar to each other. Any two data transfer circuits 200 can be the same as or similar to each other. Each data transfer circuit 200 is disposed between two memory blocks 102. For each data transfer circuit 200, the data transfer circuit 200 can be coupled to two bit lines or a pair of bit lines in two different memory blocks 102 located on opposite sides of the data transfer circuit 200 (e.g., two memory blocks adjacent to a certain data transfer circuit). The data transfer circuit 200 can be regarded as a data path for inter-block data movement between two adjacent memory blocks 102. A data signal on a bit line or a pair of bit lines in a memory block 102 can be transmitted to a bit line or a pair of bit lines in an adjacent memory block adjacent to the memory block 102. For example, the data signal can be input or output by the topmost (frontmost) data transfer circuit 200 coupled to the arithmetic logic circuit 400 and transmitted to the first-stage data transfer circuit 200. The data signal can also be input or output by a data interface of the data transfer circuit 200 between any two memory blocks other than the bit line or the pair of bit lines. Through signal sensing and buffering performed by the data transfer circuit 200, the data signal on the bit line or the pair of bit lines in the memory block can be transmitted to a bit line or a pair of bit lines in an adjacent memory block. In this way, the data signal can be sequentially transmitted across multiple subsequent memory blocks through multiple data transfer circuits 200 between multiple subsequent memory blocks. The interface transfer circuit 300 coupled to the bottommost memory block 102 can access the data signal and transmit the data signal to the arithmetic logic circuit 400 or an external device for further operations.

[0069] The data transfer circuit 200 coupled to two different memory blocks via different bit lines or a pair of bit lines can be used to perform a data movement operation to transfer a data signal from one memory block to an adjacent memory block to achieve inter-block data movement. All or a part of different types of data transfer circuits coupled to the bit lines or the pair of bit lines in the memory block can operate serially or in parallel. Embodiments of the present invention can be performed for moving one page of data at a time, where one page can be defined as data stored in all memory cells activated by the same single character line. The data transfer circuit 200 can include a plurality of first-type data transfer circuits 202 for inter-block data movement.

[0070] Please refer to Figure 4 , Figure 4 is a schematic diagram of a first-type data transfer circuit 202 according to an embodiment of the present invention. The first-type data transfer circuit 202 can be used to perform a data movement operation to transfer a data signal from one memory block (e.g., memory block A) to an adjacent memory block (e.g., memory block B) to achieve inter-block data movement, as Figure 4As shown, the first type of data transfer circuit 202 includes a first type of sense buffer circuit 2022. The first type of sense buffer circuit 2022 includes a bit-line sense amplifier (BLSA) BLSA. The bit-line sense amplifier BLSA of the first type of sense buffer circuit 2022 is coupled to a bit line or a pair of bit lines of a memory block A and a bit line or a pair of bit lines of a memory block B adjacent to the memory block A. For example, when applied to a memory array using a single bit-line mechanism, the first type of sense buffer circuit 2022 can be coupled to a bit line in the memory block A and a bit line in the adjacent memory block B. When applied to a memory array using a differential bit-line mechanism, the first type of sense buffer circuit 2022 can be coupled to a pair of bit lines in the memory block A and a pair of bit lines in the adjacent memory block B. The bit-line sense amplifier BLSA of the first type of sense buffer circuit 2022 is configured to sense the data signal driven on the bit line or the pair of bit lines of the memory block A, and is configured to latch and buffer the sensed / amplified data signal. Then, the bit-line sense amplifier BLSA of the first type of sense buffer circuit 2022 drives and transmits the latched data signal to the bit line or the pair of bit lines in the adjacent memory block B. In this way, the data signal on the bit line or the pair of bit lines of the memory block A can be transferred to the bit line or the pair of bit lines of the memory block B via the first type of sense buffer circuit 202. The first type of data transfer circuit 202 of the data transfer circuit 200 can serve as a data path for inter-block data movement between the memory block A and the memory block B. In addition, a word line of the memory block B can be activated to capture the data signal on its bit line or pair of bit lines and store the obtained data signal into the memory cell coupled to the activated word line.

[0071] Through the data sensing and buffering performed by the first type of data transfer circuit 202 of the data transfer circuit 200, the data signal on the bit line or the pair of bit lines of a memory block can be transferred to the bit line or the pair of bit lines of an adjacent memory block. In this way, via the use of other data transfer circuits between the memory block B and a memory block C, the data signal that has been transferred to the adjacent memory block B can be further transferred to the memory block C adjacent to the memory block B. Therefore, the data signal can be sequentially transferred between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks. The data signal can be sequentially transferred from one memory block to subsequent adjacent memory blocks until it reaches the target location.

[0072] In a variant embodiment, the data transfer circuit 200 may include a plurality of second type of data transfer circuits 204 for inter-block data movement. Please refer to Figure 5 , Figure 5Schematic diagram of a second type of data transfer circuit 204 according to an embodiment of the present invention. The second type of data transfer circuit 204 can be used to perform data movement operations, transferring data signals from a memory block (such as memory block A) to an adjacent memory block (such as memory block B) to achieve data movement between blocks, as Figure 5 shown, the second type of data transfer circuit 204 includes a first type of sense buffer circuit 2022, a first multiplexer (MUX) MUX1, and a second multiplexer MUX2. The first type of sense buffer circuit 2022 includes a bit line sense amplifier BLSA. The bit line sense amplifier BLSA of the first type of sense buffer circuit 2022 is coupled to the first multiplexer MUX1 and the second multiplexer MUX2. The first multiplexer MUX1 is coupled to a first number of bit lines or bit line pairs of a memory block A and the bit line sense amplifier BLSA of the first type of sense buffer circuit 2022.

[0073] The first multiplexer MUX1 is configured to select a selected group of bit lines or bit line pairs of the memory block A from the first number of bit lines or bit line pairs of the memory block A, and connect the selected group of bit lines or bit line pairs in the memory block A to the bit line sense amplifier BLSA of the first type of sense buffer circuit 2022. The second multiplexer MUX2 is coupled to a second number of bit lines or bit line pairs of a memory block B adjacent to the memory block A and the bit line sense amplifier BLSA of the first type of sense buffer circuit 2022. The second multiplexer MUX2 is configured to select a selected group of bit lines or bit line pairs of the memory block B from the second number of bit lines or bit line pairs of the memory block B, and connect the selected group of bit lines or bit line pairs in the memory block B to the bit line sense amplifier BLSA of the first type of sense buffer circuit 2022. In this way, the selected group of bit lines or bit line pairs in the memory block A can be connected to the selected group of bit lines or bit line pairs in the memory block B through the first type of sense buffer circuit 2022.

[0074] During data movement between blocks, through the connection operation of the first multiplexer MUX, the bit line sense amplifier BLSA of the first type sense buffer circuit 2022 can be configured to sense data signals on the bit lines or bit line pairs of a selected group of memory block A, and be configured to latch and buffer the sensed / amplified data signals. Then, through the connection operation of the second multiplexer MUX2, the bit line sense amplifier BLSA of the first type sense buffer circuit 2022 drives and transmits the latched data signals to the bit lines or bit line pairs of a selected group in memory block B. In this way, the data signals on the bit lines or bit line pairs of the selected group of memory block A can be transferred to the bit lines or bit line pairs of the selected group of memory block B via the second type data transfer circuit 204. The second type data transfer circuit 204 of the data transfer circuit 200 can serve as the data path for data movement between memory block A and memory block B. In addition, a word line of memory block B can be activated to obtain the data signals on its bit lines or bit line pairs and store the obtained data signals into the memory cells coupled to the activated word line.

[0075] Through the data sensing and buffering performed by the second type data transfer circuit 204 of the data transfer circuit 200, the data signals on the bit lines or bit line pairs of a memory block can be transmitted to the bit lines or bit line pairs of an adjacent memory block. In this way, via the use of other data transfer circuits between memory block B and a memory block C, the data signals that have been transferred to the adjacent memory block B can be further transferred to the memory block C adjacent to memory block B. Therefore, the data signals can be sequentially transferred between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks. The data signals can be sequentially transferred from one memory block to subsequent adjacent memory blocks until the target location is reached.

[0076] In a variant embodiment, the data transfer circuit 200 may include a plurality of third type data transfer circuits 206 for inter-block data movement. Please refer to Figure 6 , Figure 6 which is a schematic diagram of a third type data transfer circuit 206 according to an embodiment of the present invention. As Figure 6As shown, the third type of data transfer circuit 206 can be used to perform a data movement operation to transfer a data signal from a memory block (such as memory block A) to an adjacent memory block (such as memory block B) to achieve data movement between blocks. The third type of data transfer circuit 206 includes first type sense buffer circuits 2022_1 and 2022_2, a first multiplexer MUX1, and a second multiplexer MUX2. The first type sense buffer circuit 2022_1 includes a plurality of bit line sense amplifiers BLSA, and each bit line sense amplifier BLSA of the first type sense buffer circuit 2022_1 is coupled to a bit line or a pair of bit lines of a memory block A. The first type sense buffer circuit 2022_2 includes a plurality of bit line sense amplifiers BLSA, and each bit line sense amplifier BLSA of the first type sense buffer circuit 2022_2 is coupled to a bit line or a pair of bit lines of a memory block B adjacent to the memory block A. The first multiplexer MUX1 is coupled to the plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1 and the second multiplexer MUX2. The first multiplexer MUX1 is configured to select a selected group of bit line sense amplifiers BLSA from the plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1 and connect the selected group of bit line sense amplifiers BLSA to the second multiplexer MUX2.

[0077] The second multiplexer MUX2 is coupled to the plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_2 and the first multiplexer MUX1. The second multiplexer MUX2 is configured to select a selected group of bit line sense amplifiers BLSA from the plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_2 and connect the selected group of bit line sense amplifiers BLSA to the first multiplexer MUX1. In this way, through the selection and connection operations of the first multiplexer MUX1 and the second multiplexer MUX, the selected group of bit line sense amplifiers BLSA in the first type sense buffer circuit 2022_1 (coupled to the bit line or the pair of bit lines of the memory block A) can be connected to the selected group of bit line sense amplifiers BLSA in the first type sense buffer circuit 2022_2 (coupled to the bit line or the pair of bit lines of the memory block B).

[0078] During data movement between blocks, the bit-line sense amplifiers BLSA of a selected group of the first type of sense buffer circuit 2022_1 can sense, latch, and buffer data signals on the bit lines or bit line pairs coupled to the selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 in memory block A. Through the connection operation of the first multiplexer MUX1 and the second multiplexer MUX2, the selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 can drive and transfer the latched data signals to the selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_2. The selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_2 can transfer the data signals to the bit lines or bit line pairs coupled to the selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_2 in memory block B. For example, each of the bit-line sense amplifiers BLSA of the selected group of the first type of sense buffer circuit 2022_1 can be configured to sense data signals on the bit lines or bit line pairs in the coupled memory block A, and be configured to latch and buffer the sensed / amplified data signals. Then, each of the bit-line sense amplifiers BLSA of the selected group of the first type of sense buffer circuit 2022_1 can be configured to drive and transfer the latched data signals to the selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_2, so that the selected group of bit-line sense amplifiers BLSA of the first type of sense buffer circuit 2022_2 can transfer the data signals to the bit lines or bit line pairs of the memory block B to which it is coupled. In this way, the data signals on the bit lines or bit line pairs of memory block A can be transferred to the bit lines or bit line pairs of memory block B via the third type of data transfer circuit 206. The third type of data transfer circuit 206 of the data transfer circuit 200 can serve as the data path for data movement between memory block A and memory block B. In this manner, data signals can be sequentially transferred between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks until reaching the target location.

[0079] In a variant embodiment, the data transfer circuit 200 may include a plurality of fourth type data transfer circuits 208 for inter-block data movement. Refer to Figure 7 . Figure 7 is a schematic diagram of a fourth type data transfer circuit 208 according to an embodiment of the present invention. It should be noted that since Figure 7 the fourth type data transfer circuit 208 and Figure 4 the first type data transfer circuit 202 of Figure 7As shown, it will not be elaborated here. As Figure 7 shown. The fourth type of data transfer circuit 208 can be used to perform a data movement operation to transfer a data signal from a memory block (e.g., memory block A) to an adjacent memory block (e.g., memory block B) to achieve inter-block data movement. The fourth type of data transfer circuit 208 includes a second type of sense buffer circuit 2024. The second type of sense buffer circuit 2024 includes a bitline sense amplifier BLSA and an external data interface DI. The bitline sense amplifier BLSA of the second type of sense buffer circuit 2024 is coupled to a bitline or a pair of bitlines of a memory block A and a bitline or a pair of bitlines of a memory block B adjacent to the memory block A. The bitline sense amplifier BLSA is also coupled to the external data interface DI. The external data interface DI of the second type of sense buffer circuit 2024 can serve as a direct or selective / multiplexed interface for communicating with a circuit connected to a signal interface different from the bitline or the pair of bitlines. The circuit connected to the signal interface different from the bitline or the pair of bitlines can be any internal circuit in the memory device 10. The circuit can be a core logic circuit or an arithmetic logic circuit for subsequent arithmetic operations, but is not limited thereto. The external data interface DI of the second type of sense buffer circuit 2024 is configured to directly or selectively transfer data between the bitline sense amplifier BLSA of the second type of sense buffer circuit 2024 and the circuit connected to the signal interface different from the bitline or the pair of bitlines.

[0080] Similar to Figure 4 the operation of the bitline sense amplifier BLSA of the first type of sense buffer circuit 2022 in Figure 7The bit line sense amplifier BLSA of the second type sense buffer circuit 2024 in [description] is configured to sense data signals on the bit lines or bit line pairs of memory block A, and is configured to latch and buffer the sensed / amplified data signals. Then, the bit line sense amplifier BLSA of the second type sense buffer circuit 2024 drives and transfers the latched data signal to the bit lines or bit line pairs in the adjacent memory block B. In this way, the data signals on the bit lines or bit line pairs of memory block A can be transferred to the bit lines or bit line pairs of memory block B via the fourth type data transfer circuit 208. The fourth type data transfer circuit 208 of the data transfer circuit 200 can serve as a data path for inter-block data movement between memory block A and memory block B. In a variant embodiment, the bit line sense amplifier BLSA of the second type sense buffer circuit 2024 can sense data signals on the bit lines or bit line pairs of memory block A, and latch, buffer and transfer the sensed / amplified data signal to the external data interface DI, so that the external data interface DI can directly or selectively output the data signal to a circuit connected to a signal interface different from the bit lines or bit line pairs for subsequent operations. In addition, the external data interface DI of the second type sense buffer circuit 2024 can receive data from a circuit connected to a signal interface different from the bit lines or bit line pairs and can directly or selectively transfer the received data to the bit line sense amplifier BLSA of the second type sense buffer circuit 2024. The bit line sense amplifier BLSA of the second type sense buffer circuit 2024 can transfer the received data to the bit lines or bit line pairs in the coupled memory block A and / or memory block B. In this way, the fourth type data transfer circuit 208 of the data transfer circuit 200 can be used to multiplex data from the memory block to a circuit connected to a signal interface different from the bit lines or bit line pairs, and write the data from the circuit connected to the signal interface different from the bit lines or bit line pairs to the memory block for off-bit line data transfer. Therefore, the fourth type data transfer circuit 208 can be used not only for inter-block data movement, but also for external interface data transfer away from the bit lines.

[0081] In a variant embodiment, the data transfer circuit 200 may include a plurality of fifth type data transfer circuits 210 for inter-block data movement. Please refer to Figure 8 , Figure 8 which is a schematic diagram of a fifth type data transfer circuit 210 according to an embodiment of the present invention. It should be noted that since Figure 8 the fifth type data transfer circuit 210 and Figure 5 the second type data transfer circuit 204 in Figure 7 have components with the same name and similar operating modes and functions, for the sake of brevity of the specification, the detailed description is omitted here. The connection relationships of these components are as shown in Figure 8As shown, the fifth type of data transfer circuit 210 performs a data movement operation to transfer a data signal from a memory block (e.g., memory block A) to an adjacent memory block (e.g., memory block B) to achieve inter-block data movement. The fifth type of data transfer circuit 210 includes a second type of sense buffer circuit 2024, a first multiplexer MUX1, and a second multiplexer MUX2. The second type of sense buffer circuit 2024 includes a bit line sense amplifier BLSA and an external data interface DI. The bit line sense amplifier BLSA of the second type of sense buffer circuit 2024 is coupled to the first multiplexer MUX1 and the second multiplexer MUX2. The first multiplexer MUX1 is coupled to a first number of bit lines or bit line pairs of a memory block A and the bit line sense amplifier BLSA of the second type of sense buffer circuit 2024. The second multiplexer MUX2 is coupled to a second number of bit lines or bit line pairs of a memory block B adjacent to the memory block A and the bit line sense amplifier BLSA of the second type of sense buffer circuit 2024.

[0082] Similar to Figure 5 the operation of the bit line sense amplifier BLSA, the first multiplexer MUX1, and the second multiplexer MUX2 of the first type of sense buffer circuit 2022 in Figure 8 the bit line sense amplifier BLSA of the second type of sense buffer circuit 2024 in is configured to sense the data signal on the bit lines or bit line pairs of the memory block A and is configured to latch and buffer the sensed / amplified data signal. Then, via the connection operation of the second multiplexer MUX2, the bit line sense amplifier BLSA of the second type of sense buffer circuit 2024 drives and transfers the latched data signal to a selected group of bit lines or bit line pairs in the memory block B. In this way, the data signal of the selected group of bit lines or bit line pairs of the memory block A can be transferred to the selected group of bit lines or bit line pairs of the memory block B via the fifth type of data transfer circuit 210. The fifth type of data transfer circuit 210 of the data transfer circuit 200 can serve as a multiplexed data path for inter-block data movement between the memory block A and the memory block B.

[0083] Moreover, the bit line sense amplifier BLSA is also coupled to the external data interface DI of the second type sense buffer circuit 2024. The external data interface DI of the second type sense buffer circuit 2024 can serve as an interface for directly or selectively communicating with a circuit connected to a signal interface different from the bit line or bit line pair. The external data interface DI of the second type sense buffer circuit 2024 is configured to directly or selectively transfer data from the bit line sense amplifier BLSA of the second type sense buffer circuit 2024 to a circuit connected to a signal interface different from the bit line or bit line pair, or directly or selectively transfer data from a circuit connected to a signal interface different from the bit line or bit line pair to the bit line sense amplifier BLSA of the second type sense buffer circuit 2024. In addition, the external data interface DI can directly or selectively receive data from the coupled circuit connected to a signal interface different from the bit line or bit line pair, and can directly or selectively transfer the received data to the bit line sense amplifier BLSA. The bit line sense amplifier BLSA then transfers the received data to the bit line or bit line pair in the coupled memory block A and / or memory block B. In this way, the fifth type data transfer circuit 210 of the data transfer circuit 200 can be used to multiplex data from the memory block to a circuit connected to a signal interface different from the bit line or bit line pair, and write the data from the circuit connected to a signal interface different from the bit line or bit line pair to the memory block for off-bit line data transfer. Therefore, the fifth type data transfer circuit 210 can be used not only for inter-block data movement, but also for external interface data transfer away from the bit line.

[0084] In a variant embodiment, please refer to Figure 9 , Figure 9 which is a schematic diagram of a variant embodiment of the third type data transfer circuit 206 of the embodiment of the present invention. It should be noted that since Figure 9 the third type data transfer circuit 206 of Figure 6 and the third type data transfer circuit 206 of Figure 7 have components with the same name and similar operating modes and functions, for the sake of brevity of the specification content, the detailed description is omitted here. The connection relationships of these components are as Figure 6 shown and will not be elaborated here. Compared with the third type data transfer circuit 206 of Figure 9 , the third type data transfer circuit 206 in Figure 9As shown, the first multiplexer MUX1 is coupled to a plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1, the second multiplexer MUX2, and an external data interface DI. The first multiplexer MUX1 is configured to select a selected group of bit line sense amplifiers BLSA from the plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1, and connect the selected group of bit line sense amplifiers BLSA to the second multiplexer MUX2 and / or the external data interface DI.

[0085] As Figure 9 shown, the third type data transfer circuit 206 performs a data movement operation to transfer a data signal from a memory block (e.g., memory block A) to an adjacent memory block (e.g., memory block B) to achieve inter-block data movement. Similar to Figure 6 the operations of the bit line sense amplifiers BLSA, the first multiplexer MUX1, and the second multiplexer MUX2 in the first type sense buffer circuits 2022_1 and 2022_2, the first multiplexer MUX1 is configured to select a selected group of bit line sense amplifiers BLSA from the plurality of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1, and connect the selected group of bit line sense amplifiers BLSA to the second multiplexer MUX2. The selected group of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1 can sense, latch, and buffer the data signal on the bit lines or bit line pairs coupled to the selected group of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_1 in the memory block A, and drive and transfer the latched data signal to the selected group of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_2 through the connection operation of the first multiplexer MUX1 and the second multiplexer MUX2. The selected group of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_2 can drive and transfer the data signal to the bit lines or bit line pairs coupled to the selected group of bit line sense amplifiers BLSA of the first type sense buffer circuit 2022_2 in the memory block B. Therefore, the third type data transfer circuit 206 of the data transfer circuit 200 can serve as a data path for inter-block data movement between the memory block A and the memory block B.

[0086] In a variant embodiment, as Figure 9As shown, the first multiplexer MUX1 is configured to select a selected group of bit line sense amplifiers BLSA from a plurality of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1, and connect the selected group of bit line sense amplifiers BLSA to the external data interface DI. The selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 can sense, latch, and buffer the data signals on the bit lines or bit line pairs coupled to the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 in the memory block A, and drive and transfer the latched data signals to the external data interface DI through the connection operation of the first multiplexer MUX1. The external data interface DI can directly or selectively output the data signals to a circuit connected to a signal interface different from the bit lines or bit line pairs for subsequent operations. In addition, the external data interface DI can directly or selectively receive data from the circuit coupled to the signal interface different from the bit lines or bit line pairs, and transfer the received data to the bit line sense amplifiers BLSA of the first type of sense buffer circuits 2022_1 and 2022_2 through the operations of the first multiplexer MUX1 and the second multiplexer MUX2, so that the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuits 2022_1 and 2022_2 can transfer the received data to the bit lines or bit line pairs in the coupled memory block A and / or memory block C. In this way, the third type of data transfer circuit 206 of the data transfer circuit 200 can be used to multiplex data from the memory block to a circuit connected to a signal interface different from the bit lines or bit line pairs, and write the data from the circuit connected to the signal interface different from the bit lines or bit line pairs to the memory block for off-bit line data transfer. Therefore, the fifth type of data transfer circuit 210 can be used not only for inter-block data movement but also for external interface data transfer away from the bit lines.

[0087] In a variant embodiment, please refer to Figure 10 , Figure 10 which is a schematic diagram of a variant embodiment of a fourth type of data transfer circuit 208 according to an embodiment of the present invention. It should be noted that since Figure 10 the fourth type of data transfer circuit 208 and Figure 7 the fourth type of data transfer circuit 208 have components with the same name and similar operating modes and functions, for the sake of brevity of the specification content, the detailed description is omitted here. The connection relationships of these components are as Figure 7 shown and will not be elaborated here. Compared with Figure 7 the fourth type of data transfer circuit 208, Figure 10The fourth type of data transfer circuit 208 further includes an arithmetic logic circuit 400. For example, the arithmetic logic circuit 400 may include a NOR gate, a systolic array, a multiplication and adder tree (MUL / Adder tree) circuit, an accumulator (ACC), and / or an activation arithmetic circuit, but is not limited thereto. The arithmetic logic circuit 400 may be integrated into the data transfer circuit 200. The fourth type of data transfer circuit 208 can be used as a data path for inter-block data movement between memory block A and memory block B. The bit line sense amplifier BLSA of the second type of sense buffer circuit 2024 can sense the data signals on the bit lines or bit line pairs of memory block A, and latch, buffer, and transmit the sensed / amplified data signals to the external data interface DI. The external data interface DI can directly or selectively drive and transmit data signals to the arithmetic logic circuit 400 for subsequent arithmetic operations. The external data interface DI of the second type of sense buffer circuit 2024 can also receive data from the arithmetic logic circuit 400 and can transmit the received data to the bit line sense amplifier BLSA of the second type of sense buffer circuit 2024. The bit line sense amplifier BLSA then transmits the received data to the bit lines or bit line pairs in the coupled memory block A. In this way, the fourth type of data transfer circuit 208 of the data transfer circuit 200 can be used not only for inter-block data movement but also for data transfer of related arithmetic logic circuits.

[0088] In a variant embodiment, please refer to Figure 11 and Figure 12 , Figure 11 is a schematic diagram of a variant embodiment of the fifth type of data transfer circuit 210 according to an embodiment of the present invention. Figure 12 is a schematic diagram of another variant embodiment of the third type of data transfer circuit 206 according to an embodiment of the present invention. It should be noted that since Figure 11 the fifth type of data transfer circuit 210 and Figure 8 the fifth type of data transfer circuit 210 have components with the same name and have similar operating modes and functions, Figure 12 the third type of data transfer circuit 206 and Figure 9 the third type of data transfer circuit 206 have components with the same name and have similar operating modes and functions. Therefore, for the sake of brevity of the specification content, the detailed description is omitted here. The connection relationships of these components Figure 11 and Figure 12, which will not be elaborated here. As Figure 11 shown, the fifth type of data transfer circuit 210 further includes an arithmetic logic circuit 400. As Figure 12 shown, the third type of data transfer circuit 206 further includes an arithmetic logic circuit 400. Figure 11 The fifth type of data transfer circuit 210 and Figure 12 the third type of data transfer circuit 206 can both be used as the data path for inter-block data movement between memory block A and memory block B. The data signal on the bit line or bit line pair of memory block A can be sensed and transmitted to the arithmetic logic circuit 400 via the external data interface DI, and the operation result of the arithmetic logic circuit 400 is transmitted to the memory block via the external data interface DI. Therefore, Figure 11 the fifth type of data transfer circuit 210 and Figure 12 the third type of data transfer circuit 206 can not only be used for inter-block data movement, but also for the data transfer of external interface data leaving the bit line to the relevant arithmetic logic circuit.

[0089] The memory device 10 includes a plurality of interface transfer circuits 300, and each interface transfer circuit 300 is coupled to a memory block 102. All or part of the different types of interface transfer circuits 300 in the memory arrays of the multiple memory blocks can operate serially or in parallel. The interface transfer circuit 300 can include a plurality of first type interface transfer circuits 302. Please refer to Figure 13 , Figure 13 which is a schematic diagram of a first type interface transfer circuit 302 according to an embodiment of the present invention. As Figure 13 shown, the first type interface transfer circuit 302 can be used for data sensing and buffering. The first type interface transfer circuit 302 includes a third type sense buffer circuit 2026. The third type sense buffer circuit 2026 includes a bit line sense amplifier BLSA. The bit line sense amplifier BLSA of the third type sense buffer circuit 2026 is coupled to a bit line or bit line pair of a memory block A. The bit line sense amplifier BLSA of the third type sense buffer circuit 2026 is configured to sense the data signal on the bit line or bit line pair of memory block A, and is configured to latch and buffer the sensed / amplified data signal.

[0090] In a variant embodiment, the interface transfer circuit 300 can include a plurality of second type interface transfer circuits 304. Please refer to Figure 14 , Figure 14 which is a schematic diagram of a second type interface transfer circuit 304 according to an embodiment of the present invention. As Figure 14As shown, the second type of interface transfer circuit 304 can be used for data sensing and buffering. The second type of interface transfer circuit 304 includes a third type of sensing buffer circuit 2026 and a first multiplexer MUX1. The third type of sensing buffer circuit 2026 includes a bit line sense amplifier BLSA. The first multiplexer MUX1 is coupled to a first number of bit lines or bit line pairs of a memory block A to the bit line sense amplifier BLSA of the third type of sensing buffer circuit 2026. The first multiplexer MUX1 is configured to select a selected group of bit lines or bit line pairs of the memory block A from the first number of bit lines or bit line pairs of the memory block A, and connect the selected group of bit lines or bit line pairs in the memory block A to the bit line sense amplifier BLSA of the third type of sensing buffer circuit 2026. Through the connection operation of the first multiplexer MUX, the third type of sensing buffer circuit 2026 can sense, latch, and buffer the data signals on the selected group of bit lines or bit line pairs of the memory block A to achieve data sensing and buffering.

[0091] In a variant embodiment, the interface transfer circuit 300 may include a plurality of third type interface transfer circuits 306. Please refer to Figure 15 , Figure 15 which is a schematic diagram of the third type interface transfer circuit 306 according to an embodiment of the present invention. As Figure 15 shown, the third type interface transfer circuit 306 can be used for external interface data transfer of the outgoing bit lines of the edge memory block. The third type interface transfer circuit 306 includes a fourth type sensing buffer circuit 2028. The fourth type sensing buffer circuit 2028 includes a bit line sense amplifier BLSA and an external data interface DI. The bit line sense amplifier BLSA of the fourth type sensing buffer circuit 2028 is coupled to a bit line or a bit line pair of an edge memory block (such as the memory block A) and an external data interface DI different from the bit line or the bit line pair. The external data interface DI of the fourth type sensing buffer circuit 2028 is used to facilitate data transmission between the bit line sense amplifier BLSA and other connected circuits.

[0092] As Figure 15As shown, the bit line sense amplifier BLSA of the fourth type sense buffer circuit 2028 is configured to sense data signals on the bit lines or bit line pairs in the edge memory block A, and latch and buffer the sensed / amplified data signals. The bit line sense amplifier BLSA of the fourth type sense buffer circuit 2028 drives and transmits the latched data signals to the external data interface DI, enabling the external data interface DI to output the data signals to circuits connected outside the bit line sense amplifier BLSA for subsequent operations. Variably, the external data interface DI of the fourth type sense buffer circuit 2028 can receive data from the coupled circuits and can transmit the received data to the bit line sense amplifier BLSA of the fourth type sense buffer circuit 2028. The bit line sense amplifier BLSA of the fourth type sense buffer circuit 2028 can transmit the received data to the bit lines or bit line pairs in the coupled memory block A. Therefore, the third type interface transfer circuit 306 of the interface transfer circuit 300 can implement data transmission between the edge memory block and a connected circuit.

[0093] In a variant embodiment, the interface transfer circuit 300 may include a plurality of fourth type interface transfer circuits 308. Refer to Figure 16 , Figure 16 , which is a schematic diagram of a fourth type interface transfer circuit 308 according to an embodiment of the present invention. As Figure 16As shown, the fourth type of interface transfer circuit 308 can be used for external interface data transfer of the outgoing bit lines of the edge memory block. The fourth type of interface transfer circuit 308 includes a fourth type of sense buffer circuit 2028 and a first multiplexer MUX1. The fourth type of sense buffer circuit 2028 includes a bit line sense amplifier BLSA and an external data interface DI. The bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028 is coupled to the first multiplexer MUX1 and the external data interface DI. The first multiplexer MUX1 is coupled to the bit lines or bit line pairs of an edge memory block (such as memory block A). Therefore, the external data interface DI of the fourth type of sense buffer circuit 2028 can be used to facilitate data transmission between the edge memory block and a connection circuit. The first multiplexer MUX1 is configured to select a selected group of bit lines or bit line pairs of memory block A from the first number of bit lines or bit line pairs of memory block A, and connect the selected group of bit lines or bit line pairs in memory block A to the bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028. The bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028 can sense, latch, buffer, and transmit the data signals on the selected group of bit lines or bit line pairs of memory block A to the external data interface DI, so that the external data interface DI can output the data signals to the circuit other than the bit line sense amplifier BLSA to which it is coupled for subsequent operations. The external data interface DI of the fourth type of sense buffer circuit 2028 can receive data from the circuit other than the bit line sense amplifier BLSA to which it is coupled, and can transmit the received data to the bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028. The bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028 can transmit the received data to the bit lines or bit line pairs in the coupled memory block A. Therefore, the fourth type of interface transfer circuit 308 of the interface transfer circuit 300 can multiplex the data between the edge memory block and the circuit connected thereto and selectively write the data from the connected circuit to the bit lines or bit line pairs of the edge memory block.

[0094] In a variant embodiment, the interface transfer circuit 300 may include a plurality of fifth type interface transfer circuits 310. Please refer to Figure 17 , Figure 17 which is a schematic diagram of a fifth type interface transfer circuit 310 according to an embodiment of the present invention. As Figure 17As shown, the fifth type of interface transfer circuit 310 is used for external interface data transfer of the leaving bit lines of the edge memory block. The fifth type of interface transfer circuit 310 includes a first type of sense buffer circuit 2022_1, a first multiplexer MUX1, and an external data interface DI. The first type of sense buffer circuit 2022_1 includes a plurality of bit line sense amplifiers BLSA. Each bit line sense amplifier BLSA of the first type of sense buffer circuit 2022_1 is coupled to a bit line or a pair of bit lines of an edge memory block (such as memory block A). The first multiplexer MUX1 is coupled to the plurality of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1. The first multiplexer MUX1 is configured to select a selected group of bit line sense amplifiers BLSA from the plurality of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 and connect the selected group of bit line sense amplifiers BLSA to the external data interface DI. The external data interface DI can serve as an interface for communicating with circuits other than the bit line sense amplifiers BLSA. Through the connection operation of the first multiplexer MUX1, the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 can sense, latch, buffer, and transmit the data signals on the bit lines or pairs of bit lines coupled to the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 in the memory block A to the external data interface DI. The external data interface DI can output the data signals to a circuit different from the bit line sense amplifiers BLSA for subsequent operations. The external data interface DI of the fourth type of sense buffer circuit 2028 can receive data from the circuit coupled thereto that is different from the bit line sense amplifiers BLSA, and through the connection operation of the first multiplexer MUX1, can transmit the received data to the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1. The selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 can transmit the received data to the bit lines or pairs of bit lines in the coupled memory block A. Therefore, the fifth type of interface transfer circuit 310 of the interface transfer circuit 300 can multiplex and process the data from the edge memory block to the circuit different from the bit line sense amplifiers BLSA, and write the data from the circuit different from the bit line sense amplifiers BLSA to the edge memory block to achieve the external interface data transfer of the leaving bit lines of the edge memory block.

[0095] In a variant embodiment, please refer to Figure 18 , Figure 18 which is a schematic diagram of a variant embodiment of the third type of interface transfer circuit 306 according to an embodiment of the present invention. It should be noted that since Figure 18 the third type of interface transfer circuit 306 of Figure 15Components with the same name in the third type of interface transfer circuit 306 have similar operating modes and functions. Therefore, for the sake of simplicity of the specification content, the detailed description is omitted here. The connection relationships of these components are as shown in Figure 18 and will not be elaborated here. Figure 18 The third type of interface transfer circuit 306 of Figure 1 further includes an arithmetic logic circuit 400. Please continue to refer to Figure 18 . For example, the arithmetic logic circuit 400 can be integrated into the interface transfer circuit 300. For example, the arithmetic logic circuit 400 may include a NOR gate, a systolic array, a multiplication adder tree circuit (MUL / Adder tree), an accumulator (ACC), and / or an activation arithmetic circuit, but is not limited thereto. The arithmetic logic circuit 400 is coupled to the external data interface DI. The bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028 can sense, latch, and buffer the data signals on the bit lines or bit line pairs in a peripheral memory block (such as memory block A). The bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028 can drive and transmit the latched data signals to the external data interface DI. The external data interface DI can drive and transmit the data signals to the arithmetic logic circuit 400 for subsequent arithmetic operations. Therefore, the data signals on the bit lines or bit line pairs in the peripheral memory block A can be multiplexed through the third type of interface transfer circuit 306 of the interface transfer circuit 300 to the arithmetic logic circuit 400 for subsequent arithmetic operations. For example, as shown in Figure 1 , the arithmetic logic circuit 400 includes a multiplication adder tree circuit 402 and an accumulator (ACC) or activation arithmetic circuit 404. The data signals on the bit lines or bit line pairs in the peripheral memory block 102 can be multiplexed from the peripheral memory block 102 to the multiplication adder tree circuit 402 for subsequent arithmetic operations.

[0096] In a variant embodiment, as shown in Figure 18 , the external data interface DI of the fourth type of sense buffer circuit 2028 can receive data from the arithmetic logic circuit 400 and transmit the received data to the bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028. The bit line sense amplifier BLSA of the fourth type of sense buffer circuit 2028 then transmits the received data to the bit lines or bit line pairs in the coupled memory block A. For example, as shown in Figure 1As shown, the operation result data of the accumulator or activation operation circuit 404 can be written into the edge memory block via the coupled interface transfer circuit 300. Therefore, the third type of interface transfer circuit 306 of the interface transfer circuit 300 can multiplex and process the data between the edge memory block and the operation logic circuit 400, and write the operation result data from the operation logic circuit 400 into the edge memory block, so as to realize the external interface data transfer of the edge memory block to the relevant operation logic circuit for the outgoing bit line.

[0097] In a variant embodiment, please refer to Figure 19 , Figure 19 which is a schematic diagram of a variant embodiment of the fourth type of interface transfer circuit 308 of the embodiment of the present invention. It should be noted that since Figure 19 the fourth type of interface transfer circuit 308 of Figure 16 and the fourth type of interface transfer circuit 308 of Figure 19 have components with the same name and similar operating modes and functions, for the sake of simplicity of the specification content, the detailed description is omitted here. The connection relationships of these components are as Figure 16 shown and will not be elaborated here. Compared with Figure 19 the fourth type of interface transfer circuit 308 of

[0098] In a variant embodiment, please refer to Figure 20 , Figure 20 which is a schematic diagram of a variant embodiment of the fifth type of interface transfer circuit 310 of the embodiment of the present invention. It should be noted that since Figure 20 the fifth type of interface transfer circuit 310 ofFigure 17 Components with the same name in the fifth type of interface transfer circuit 310 have similar operating methods and functions. Therefore, for the sake of simplicity of the specification content, the detailed description is omitted here. The connection relationship of these components is as Figure 20 shown and will not be elaborated here. Compared with Figure 17 the fifth type of interface transfer circuit 310 of Figure 20 the fifth type of interface transfer circuit 310 of also includes an arithmetic logic circuit 400. The arithmetic logic circuit 400 is coupled to the external data interface DI. Through the connection operation of the first multiplexer MUX1, the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 can sense, latch, buffer, and transfer the data signals on the bit lines or bit line pairs in the memory block A to the external data interface DI. The external data interface DI can drive and transfer the data signals to the arithmetic logic circuit 400 for subsequent arithmetic operations. In addition, the external data interface DI can receive the data from the arithmetic logic circuit 400 and transfer the received data to the selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 through the connection operation of the first multiplexer MUX1. The selected group of bit line sense amplifiers BLSA of the first type of sense buffer circuit 2022_1 then transfers the received data to the bit lines or bit line pairs in the coupled memory block A. Therefore, the fifth type of interface transfer circuit 310 of the interface transfer circuit 300 can multiplex and process the data between the edge memory block and the arithmetic logic circuit 400, and write the operation result data from the arithmetic logic circuit 400 to the edge memory block to achieve the external interface data transfer of the bit lines leaving the edge memory block to the relevant arithmetic logic circuit.

[0099] In a variant embodiment, please refer to Figure 21 Figure 21 which is another variant embodiment schematic diagram of the fourth type of data transfer circuit of the embodiment of the present invention. Figure 21 Another variant design of the fourth type of data transfer circuit of the embodiment of the present invention is provided. Figure 21 The fourth type of data transfer circuit in Figure 7 is a modified design based on the second type of sense buffer circuit 2024 in Figure 21 shows an embodiment of the circuit architecture of the fourth type of data transfer circuit 208. Figure 21 The fourth type of data transfer circuit 208 shown in Figure 7 includes a combination of two Figure 21 second type of sense buffer circuits 2024. As Figure 21 shown, the fourth type of data transfer circuit 208 may include the second type of sense buffer circuits 2024_1 and 2024_2. Figure 21The second type of sense buffer circuits 2024_1 and 2024_2 and Figure 7 components with the same name in the second type of sense buffer circuit 2024 have similar operating manners and functions. The connection relationships of these components are as Figure 21 shown. The bit line sense amplifier BLSA1 of the second type of sense buffer circuit 2024_1 and the bit line sense amplifier BLSA1 of the second type of sense buffer circuit 2024_2 are both coupled to the same bit line or bit line pair of a memory block (such as memory block A), and are also both coupled to the same bit line or bit line pair of an adjacent memory block (such as memory block B). The external data interface DI1 of the second type of sense buffer circuit 2024_1 is coupled to or connected to the external data interface DI2 of the second type of sense buffer circuit 2024_2. Therefore, the fourth type of data transfer circuit 208 of the interface transfer circuit 300 can be used to simultaneously perform data movement between memory blocks and external interface data transfer from the bit line.

[0100] In a variant embodiment, please refer to Figure 22 , Figure 22 which is a schematic diagram of a variant embodiment of the third type of interface transfer circuit 306 according to an embodiment of the present invention. Figure 22 Another variant design of the third type of interface transfer circuit 306 according to an embodiment of the present invention is provided. Figure 22 A circuit architecture embodiment of the third type of interface transfer circuit 306 is shown. Figure 22 The third type of interface transfer circuit 306 in Figure 15 is a modified design based on the fourth type of sense buffer circuit 2028 in Figure 22 The third type of interface transfer circuit 306 shown in Figure 15 comprises a combination of two Figure 22 of the fourth type of sense buffer circuits. As Figure 22 shown, the third type of interface transfer circuit 306 may include the fourth type of sense buffer circuits 2028_1 and 2028_2. Figure 15 Components with the same name in the fourth type of sense buffer circuits 2028_1 and 2028_2 and Figure 22As shown. The bit-line sense amplifier BLSA1 of the fourth type of sense buffer circuit 2028_1 and the bit-line sense amplifier BLSA2 of the fourth type of sense buffer circuit 2028_2 are both coupled to the same bit line or bit-line pair of a memory block (such as memory block A). The external data interface DI1 of the fourth type of sense buffer circuit 2028_1 is coupled to or connected to the external data interface DI2 of the fourth type of sense buffer circuit 2028_2. Therefore, the third type of interface transfer circuit 306 of the interface transfer circuit 300 can be used to simultaneously perform data sensing of the edge memory block and external interface data transfer of the bit line leaving.

[0101] In a variant embodiment, please refer to Figure 23 , Figure 23 which is a schematic diagram of a variant embodiment of the third type of interface transfer circuit 306 of the embodiment of the present invention. Different from Figure 22 the third type of interface transfer circuit 306, Figure 23 the external data interface DI1 of the fourth type of sense buffer circuit 2028_1 in

[0102] In a variant embodiment, please refer to Figure 24 , Figure 24 which is a schematic diagram of a variant embodiment of the fourth type of interface transfer circuit 308 of the embodiment of the present invention. Figure 24 Another variant design of the fourth type of interface transfer circuit 308 of the embodiment of the present invention is provided. Figure 24 shows a circuit architecture embodiment of the fourth type of interface transfer circuit 308. Figure 24 The fourth type of interface transfer circuit 308 in Figure 16 is a modified design based on the fourth type of sense buffer circuit 2028 and the fourth type of interface transfer circuit 308 in Figure 24 The fourth type of interface transfer circuit 308 shown in Figure 16 includes a combination of two Figure 24 the fourth type of sense buffer circuit 308 of Figure 24 The fourth type of sense buffer circuits 2028_1 and 2028_2 of Figure 16 have similar operating modes and functions to the components with the same names in the fourth type of sense buffer circuit 2028 in Figure 24 as shown. Figure 24 The first multiplexers MUX1_1 and MUX1_2 of Figure 16Components with the same name in the first multiplexer MUX1 have similar operating manners and functions, and the linking relationships of these components are as Figure 24 shown. The first multiplexers MUX1_1 and MUX1_2 are both coupled to the same bit line or bit line pair of a memory block (such as memory block A). Therefore, the fourth type of interface transfer circuit 308 of the interface transfer circuit 300 can be used to simultaneously sense data of the edge memory block and transfer external interface data leaving the bit line.

[0103] In a variant embodiment, please refer to Figure 25 , Figure 25 which is a schematic diagram of a variant embodiment of the fourth type of interface transfer circuit 308 according to an embodiment of the present invention. Figure 25 Another variant design of the fourth type of interface transfer circuit 308 according to an embodiment of the present invention is provided. Figure 25 Another circuit architecture embodiment of the fourth type of interface transfer circuit 308 is shown. Figure 25 The fourth type of interface transfer circuit 308 in Figure 16 is a modified design based on the fourth type of sense buffer circuit 2028 in Figure 22 and the fourth type of sense buffer circuits 2028_1 and 2028_2 in Figure 25 As shown, the fourth type of interface transfer circuit 308 may include fourth type of sense buffer circuits 2028_1 - 2028_4, and the first multiplexers MUX1_1 and MUX1_2. Figure 25 The first multiplexers MUX1_1 and MUX1_2 in Figure 16 have similar operating manners and functions to the components with the same name in the first multiplexer MUX1 in Figure 24 shown. Figure 25 The fourth type of sense buffer circuits 2028_1 - 2028_4 in Figure 22 have similar operating manners and functions to the components with the same name in the fourth type of sense buffer circuits 2028_1 and 2028_2 in Figure 24As shown. The first multiplexers MUX1_1 and MUX1_2 are both coupled to the same bit line or bit line pair of a memory block (e.g., memory block A). The bit line sense amplifier BLSA1 of the fourth type sensing buffer circuit 2028_1 and the bit line sense amplifier BLSA2 of the fourth type sensing buffer circuit 2028_2 are both coupled to the first multiplexer MUX1_1. The external data interface DI1 of the fourth type sensing buffer circuit 2028_1 is coupled to or connected to the external data interface DI2 of the fourth type sensing buffer circuit 2028_2. The bit line sense amplifier BLSA3 of the fourth type sensing buffer circuit 2028_3 and the bit line sense amplifier BLSA4 of the fourth type sensing buffer circuit 2028_4 are both coupled to the first multiplexer MUX1_2. The external data interface DI3 of the fourth type sensing buffer circuit 2028_3 is coupled to or connected to the external data interface DI4 of the fourth type sensing buffer circuit 2028_4.

[0104] In a variant embodiment, please refer to Figure 26 , Figure 26 is a schematic diagram of a variation of the fourth type interface transfer circuit 308 of the embodiment of the present invention. Different from Figure 25 The fourth type interface transfer circuit 308 of , Figure 26 The external data interface DI1 of the fourth type sensing buffer circuit 2028_1 is not coupled to the external data interface DI2 of the fourth type sensing buffer circuit 2028_2. Figure 26 The external data interface DI3 of the fourth type sensing buffer circuit 2028_3 is not coupled to the external data interface DI4 of the fourth type sensing buffer circuit 2028_4.

[0105] Please refer to Figure 27 , is an embodiment of the present invention Figure 18 A circuit structure diagram of the third type interface transfer circuit 306. The operation logic circuit 400 can be used to perform bit-wise multiplication operation. The fourth type sensing buffer circuit 2028 can sense, latch and buffer the data signal on the memory block bit line or bit line pair, and drive and transmit the latched data signal to the operation logic circuit 400 via the external data interface DI. The operation logic circuit 400 is configured to perform bit-wise multiplication operation on the received data signal according to the selection signal X0-X3 respectively, and output the operation result to the coupled bit line DLa-DLd.

[0106] In a variant embodiment, Figure 28 is the of the embodiment of the present invention Figure 27 ​​​​Schematic diagram of a variation embodiment of the third type of interface transfer circuit 306. A plurality of third type interface transfer circuits 306 are used to perform shifted-multiplicand bit-wise multiplication.

[0107] Please refer to Figure 29 and Figure 30 , Figure 29 and Figure 30 for embodiments of the present invention Figure 18Schematic diagram of a variant embodiment of the third type of interface transfer circuit 306. The third type of interface transfer circuit 306 of the interface transfer circuit 300 can be used to perform a seamless bit multiplication operation. The third type of interface transfer circuit 306 includes fourth type sense buffer circuits 2028_1 and 2028_2. The fourth type sense buffer circuits 2028_1 and 2028_2 can be arranged in a ping-pong circuit architecture. The bit line sense amplifier BLSA1 of the fourth type sense buffer circuit 2028_1 and the bit line sense amplifier BLSA2 of the fourth type sense buffer circuit 2028_2 are coupled to the same bit line or bit line pair of the memory block and are also coupled to the external data interface DI. The arithmetic logic circuit 400 can be used to perform a bit multiplication operation. During a first operation period, the fourth type sense buffer circuit 2028_1 can sense, latch, and buffer the data signals of the memory block from the memory block, and the fourth type sense buffer circuit 2028_2 can provide the latched data signals to the arithmetic logic circuit 400 via the external data interface DI for further arithmetic operations, so that the arithmetic logic circuit 400 can perform a bit multiplication operation on the received data signals respectively according to the selection signals X0-X3 and output the operation results to the coupled bit lines DLa-DLd. During a second operation period, the fourth type sense buffer circuit 2028_1 can provide the latched data signals to the arithmetic logic circuit 400 via the external data interface DI for further arithmetic operations, so that the arithmetic logic circuit 400 can be divided so that the arithmetic logic circuit 400 can perform a bit multiplication operation on the received data signals respectively according to the selection signals X0-X3 and output the operation results to the coupled bit lines DLa-DLd. During the second operation period, the fourth type sense buffer circuit 2028_2 can sense, latch, and buffer the data signals of the memory block from the memory block. And so on. During a third operation period, the fourth type sense buffer circuit 2028_2 can provide the latched data signals to the arithmetic logic circuit 400 via the external data interface DI for further arithmetic operations, and the fourth type sense buffer circuit 2028_1 can sense, latch, and buffer the data signals of the memory block from the memory block, and so that the arithmetic logic circuit 400 can perform a bit multiplication operation on the received data signals respectively according to the selection signals X0-X3 and output the operation results to the coupled bit lines DLa-DLd. During a fourth operation period, the fourth type sense buffer circuit 2028_1 can provide the latched data signals to the arithmetic logic circuit 400 via the external data interface DI for further arithmetic operations, and the fourth type sense buffer circuit 2028_2 can sense, latch, and buffer the data signals of the memory block from the memory block, and so that the arithmetic logic circuit 400 can perform a bit multiplication operation on the received data signals respectively according to the selection signals X0-X3 and output the operation results to the coupled bit lines DLa-DLd.Therefore, the third type of interface transfer circuit 306 with a ping-pong circuit architecture can perform seamless bit multiplication operations. Similarly, please refer to... Figure 30 , Figure 30 for an exemplary embodiment of the present invention Figure 29 is a schematic diagram of a variant exemplary embodiment of the third type of interface transfer circuit 306. A plurality of third type of interface transfer circuits 30 with a ping-pong circuit architecture are applied to perform seamless bit multiplication operations.

[0108] In summary, the exemplary embodiments of the present invention can provide a memory device and an operating method for data movement between memory blocks and with an external interface of the memory device to achieve data movement between blocks and external interface data transfer away from bit lines without global or multi-block-length data lines, thereby effectively reducing circuit area, manufacturing cost, and power consumption.

[0109] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A memory device, characterized in that: include: a memory array, divided into a plurality of memory blocks, each memory block including a plurality of memory cells; as well as A plurality of data transfer circuits, each of which is disposed between two memory blocks; A data movement is performed on all or selected groups of bit lines or bit line pairs between any two adjacent memory blocks of the memory array. During the data movement, a data transfer circuit arranged between the two adjacent memory blocks senses, latches, buffers and repeats the data signals of all or selected groups of bit lines or bit line pairs between the two adjacent memory blocks. The data movement is performed sequentially between the two memory blocks to transmit the data signal to any memory block in the memory array without the need for global or multi-block length data lines.

2. The memory device according to claim 1, wherein: Each data transfer circuit includes a plurality of first-type data transfer circuits, and each first-type data transfer circuit includes: A first type sensing buffer circuit includes a bit line sensing amplifier and is coupled to a bit line or a bit line pair of a memory block and a bit line or a bit line pair of an adjacent memory block; The first type sensing buffer circuit senses, latches and buffers the data signal on the bit line or bit line pair of the memory block, the first type sensing buffer circuit drives and transmits the latched data signal to the bit line or bit line pair in the adjacent memory block, and the data signal is sequentially transmitted between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

3. The memory device according to claim 1, wherein: Each data transfer circuit includes a plurality of second-type data transfer circuits, and each second-type data transfer circuit includes: a first type sensing buffer circuit including a bit line sensing amplifier; a first multiplexer coupled to a first number of bit lines or bit line pairs in a memory block and the first type of sensing buffer circuit, configured to select a selected group of bit lines or bit line pairs in the memory block from the first number of bit lines or bit lines in the memory block, and connect the selected group of bit lines or bit line pairs in the memory block to the first type of sensing buffer circuit; and a second multiplexer coupled to a second number of bit lines or bit line pairs of an adjacent memory block and the first type of sensing buffer circuit, configured to select a selected group of bit lines or bit line pairs of the adjacent memory block from the second number of bit lines or bit lines of the adjacent memory block, and to connect the selected group of bit lines or bit line pairs of the adjacent memory block to the first type of sensing buffer circuit; Wherein, through the connection operation of the first multiplexer, the first type of sensing buffer circuit senses, latches and buffers the data signal on the bit line or bit line pair of the selected group of the memory block, through the connection operation of the second multiplexer, the first type of sensing buffer circuit drives and transmits the latched data signal to the bit line or bit line pair of the selected group in the adjacent memory block, and the data signal is transmitted sequentially between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

4. The memory device according to claim 1, wherein: Each data transfer circuit includes a plurality of third-type data transfer circuits, and each third-type data transfer circuit includes: A first first-type sensing buffer circuit includes a plurality of first bit line sensing amplifiers, and each first bit line sensing amplifier is coupled to a bit line or a bit line pair of a memory block; a first multiplexer coupled to the plurality of first bit line sense amplifiers and configured to select a selected group of first bit line sense amplifiers from the plurality of first bit line sense amplifiers; and a second multiplexer coupled to the first multiplexer; and a second first-type sensing buffer circuit, comprising a plurality of second bit line sensing amplifiers, each of which is coupled to the second multiplexer and a bit line or a bit line pair of an adjacent memory block; wherein the first multiplexer is configured to connect the selected first bit line sense amplifier of the selected group to the second multiplexer, and the second multiplexer is configured to select a selected group of second bit line sense amplifiers from the plurality of second bit line sense amplifiers and connect the selected second bit line sense amplifier of the selected group to the first multiplexer; The first bit line sense amplifier of the selected group senses, latches and buffers the data signal on the bit line or bit line pair coupled to the first bit line sense amplifier of the selected group in the memory block, and operates through the connection of the first multiplexer and the second multiplexer. The first bit line sense amplifier of the selected group drives and transmits the latched data signal to the second bit line sense amplifier of the selected group. The second bit line sense amplifier of the selected group transmits the data signal to the bit line or bit line pair coupled to the second bit line sense amplifier of the selected group in the adjacent memory block, and the data signal is sequentially transmitted between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

5. The memory device according to claim 4, wherein: Each third type data transfer circuit further includes: a data interface coupled to the first multiplexer; wherein the first multiplexer is configured to connect the first bit line sense amplifier of the selected group to the second multiplexer or the data interface; The first bit line sense amplifier of the selected group senses, latches and buffers the data signal on the bit line or bit line pair coupled to the first bit line sense amplifier of the selected group in the memory block, and the first bit line sense amplifier of the selected group drives and transmits the latched data signal to the second bit line sense amplifier of the selected group through the connection operation of the first multiplexer and the second multiplexer, and the second bit line sense amplifier of the selected group transmits the data signal to the bit line or bit line pair coupled to the second bit line sense amplifier of the selected group in the adjacent memory block, or the first bit line sense amplifier of the selected group drives and transmits the latched data signal to the data interface through the connection operation of the first multiplexer and the data interface.

6. The memory device according to claim 5, wherein: Each third type data transfer circuit further includes: An operational logic circuit is directly, selectively or multiplexed coupled to the data interface; wherein the first bit line sense amplifier of the selected group transmits the data signal on the bit line or bit line pair coupled to the first bit line sense amplifier of the selected group to the data interface, and the data interface transmits the data signal to the operational logic circuit directly, selectively or multiplexed.

7. The memory device according to claim 1, wherein: Each data transfer circuit includes a plurality of fourth-type data transfer circuits, and each fourth-type data transfer circuit includes: A second type sensing buffer circuit comprises: a bit line sense amplifier coupled to a bit line or bit line pair of a memory block and a bit line or bit line pair of an adjacent memory block; and a data interface coupled to the bit line sense amplifier, the data interface being different from the bit line or bit line pair; The bit line sense amplifier senses, latches and buffers the data signal on the bit line or bit line pair of the memory block, the bit line sense amplifier drives and transmits the latched data signal to the bit line or bit line pair in the adjacent memory block or to the data interface different from the bit line or bit line pair in the memory block, and the data signal is sequentially transmitted between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

8. The memory device according to claim 7, wherein: Each fourth type data transfer circuit further includes: An operation logic circuit is directly, selectively or multiplexed coupled to the data interface, wherein the data interface transmits the data signal to the operation logic circuit directly, selectively or multiplexed.

9. The memory device according to claim 1, wherein: Each data transfer circuit includes a plurality of fifth-type data transfer circuits, and each fifth-type data transfer circuit includes: A second type sensing buffer circuit comprises: a bit line sense amplifier coupled to a bit line or a bit line pair of a memory block; and a data interface coupled to the bit line sense amplifier, the data interface being different from the bit line or bit line pair in the memory block; a first multiplexer coupled to a first number of bit lines or bit line pairs in a memory block and the second type of sense buffer circuit, configured to select a selected group of bit lines or bit line pairs in the memory block from the first number of bit lines or bit lines in the memory block, and to connect the selected group of bit lines or bit line pairs in the memory block to the bit line sense amplifier; and a second multiplexer coupled to a second number of bit lines or bit line pairs of an adjacent memory block and the second type of sense buffer circuit, configured to select a selected group of bit lines or bit line pairs of the adjacent memory block from the second number of bit lines or bit lines of the adjacent memory block, and to connect the selected group of bit lines or bit line pairs in the adjacent memory block to the bit line sense amplifier; Wherein, through the connection operation of the first multiplexer, the bit line sense amplifier senses, latches and buffers the data signal on the bit line or bit line pair of the selected group in the memory block, the bit line sense amplifier drives and transmits the latched data signal to the bit line or bit line pair of the selected group in the adjacent memory block or the data interface, and the data signal is sequentially transmitted between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

10. The memory device according to claim 9, wherein: Each fifth type data transfer circuit further includes: An operation logic circuit is directly, selectively or multiplexed coupled to the data interface, wherein the data interface drives and transmits the data signal to the operation logic circuit directly, selectively or multiplexed.

11. The memory device according to claim 1, wherein: Also included is an interface transfer circuit, wherein the interface transfer circuit includes a plurality of first-type interface transfer circuits, and each first-type interface transfer circuit includes: a third type sensing buffer circuit including a bit line sensing amplifier and coupled to a bit line or a bit line pair of a memory block; The bit line sense amplifier senses, latches and buffers the data signal on the bit line or bit line pair of the memory block.

12. The memory device according to claim 1, wherein: Also included is an interface transfer circuit, wherein the interface transfer circuit includes a plurality of second-type interface transfer circuits, and each second-type interface transfer circuit includes: a third type sensing buffer circuit, comprising a bit line sensing amplifier; and a multiplexer coupled to a first number of bit lines or bit line pairs in a memory block and the bit line sense amplifier, configured to select a selected group of bit lines or bit line pairs in the memory block from the first number of bit lines or bit lines in the memory block, and to connect the selected group of bit lines or bit line pairs in the memory block to the bit line sense amplifier; Wherein, through the connection operation of the multiplexer, the third type sensing buffer circuit senses, latches and buffers the data signal on the bit line or bit line pair of the selected group in the memory block.

13. The memory device according to claim 1, wherein: Also included is an interface transfer circuit, wherein the interface transfer circuit includes a plurality of third-type interface transfer circuits, and each third-type interface transfer circuit includes: A fourth type sensing buffer circuit comprises: a bit line sense amplifier coupled to a bit line or a bit line pair of a memory block; and a data interface coupled to the bit line sense amplifier; The bit line sense amplifier senses, latches and buffers the data signal on the bit line or bit line pair of the memory block, and the bit line sense amplifier drives and transmits the latched data signal to the data interface.

14. The memory device according to claim 13, wherein: Each third type interface transfer circuit further includes: An operation logic circuit is directly, selectively or multiplexed coupled to the data interface, wherein the data interface transmits the data signal to the operation logic circuit directly, selectively or multiplexed.

15. The memory device according to claim 1, wherein: Also included is an interface transfer circuit, wherein the interface transfer circuit includes a plurality of fourth-type interface transfer circuits, and each fourth-type interface transfer circuit includes: A fourth type sensing buffer circuit comprises: a bit line sense amplifier; and a data interface coupled to the bit line sense amplifier; and a multiplexer coupled to a first number of bit lines or bit line pairs of the memory block and the bit line sense amplifier, configured to select a selected group of bit lines or bit line pairs of the memory block from the first number of bit lines or bit lines of the memory block, and to connect the selected group of bit lines or bit line pairs in the memory block to the bit line sense amplifier; Wherein, through the connection operation of the multiplexer, the bit line sense amplifier senses, latches and buffers the data signal on the bit line or bit line pair of the selected group in the memory block, and the bit line sense amplifier drives and transmits the latched data signal to the bit line or bit line pair of the selected group in the adjacent memory block or the data interface.

16. The memory device according to claim 15, wherein: Each fourth type interface transfer circuit further includes: An operation logic circuit is directly, selectively or multiplexed coupled to the data interface, wherein the data interface transmits the data signal to the operation logic circuit directly, selectively or multiplexed.

17. The memory device according to claim 1, wherein: Also included is an interface transfer circuit, wherein the interface transfer circuit includes a plurality of fifth-type interface transfer circuits, and each fifth-type interface transfer circuit includes: A plurality of first type sensing buffer circuits, including a plurality of bit line sensing amplifiers, wherein each bit line sensing amplifier is coupled to a bit line or a bit line pair of a memory block; a multiplexer coupled to the plurality of bit line sense amplifiers and configured to select a selected group of bit line sense amplifiers from the plurality of bit line sense amplifiers; and a data interface coupled to the multiplexer; The multiplexer is configured to connect the selected bit line sense amplifier of the selected group to the data interface, and the bit line sense amplifier of the selected group senses, latches and buffers the data signal on the bit line or bit line pair coupled to the bit line sense amplifier of the selected group in the memory block, and operates through the connection of the multiplexer. The bit line sense amplifiers of the selected group drive and transmit the latched data signals to the data interface.

18. The memory device of claim 17, wherein: Each fifth type interface transfer circuit further includes: An operation logic circuit is directly, selectively or multiplexed coupled to the data interface, wherein the data interface transmits the data signal to the operation logic circuit directly, selectively or multiplexed.

19. A method for operating data movement between memory blocks of a memory device and through an external interface of the memory device, wherein the memory device comprises a memory array divided into a plurality of memory blocks, each memory block comprising a plurality of memory cells, characterized in that: The operation method comprises: A data movement is performed on all or selected groups of bit lines or bit line pairs between any two adjacent memory blocks of the memory array; During the data movement, a data transfer circuit disposed between the two memory blocks senses, latches, buffers and repeats data signals of all or a selected group of bit lines or bit line pairs of one of the two adjacent memory blocks to transmit to the adjacent memory block; and The data movement is performed between two memory blocks in sequence to transmit the data signal to an adjacent memory block and then to any memory block of the memory array without requiring a global data line or a data line spanning multiple blocks.

20. The operating method according to claim 19, characterized in that: Also includes: Connecting a bit line or bit line pair of a memory block to a bit line or bit line pair of an adjacent memory block by a data transfer circuit; The data transfer circuit senses, latches and buffers the data signal on the bit line or bit line pair of the memory block; Transmitting the data signal to the bit line or bit line pair in the adjacent memory block or transmitting the data signal to a data interface through the data transfer circuit; as well as The data signal is sequentially transferred between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

21. The operating method according to claim 19, characterized in that: Also includes: A word line from a target memory block or any memory block through which a signal is passed, wherein during cross-block data movement, the word line is activated to retrieve data on the bit line or bit line pair of the memory block and store the data in the memory cells of the memory block coupled to the activated word line.

22. The operating method according to claim 19, characterized in that: Also includes: selecting a selected group of bit lines or bit line pairs in a memory block from a first number of bit lines or bit lines in the memory block, and connecting the selected group of bit lines or bit line pairs in the memory block to the data transfer circuit; sensing, latching and buffering data signals on the bit lines or bit line pairs of the selected group of the memory block; as well as The data signal is transmitted to the bit line or bit line pair of the selected group of the adjacent memory block through the data transfer circuit or the data signal is transmitted to a data interface different from the bit line or bit line pair, or the data signal is directly or multiplexedly transmitted from an external device or other data output port of the memory device to the data transfer circuit through the data interface different from the bit line or bit line pair.

23. The operating method according to claim 19, characterized in that: Also includes: Selecting a selected group of first bitline sense amplifiers from a plurality of first bitline sense amplifiers of a first first type sense buffer circuit of the data transfer circuit coupled to the bitline or bitline pair of a memory block by a first multiplexer and connecting the selected group of first bitline sense amplifiers to a second multiplexer, wherein a first first type sense buffer circuit of the data transfer circuit coupled to the bitline or bitline pair of a memory block includes the plurality of first bitline sense amplifiers; selecting a selected group of second bit line sense amplifiers from a plurality of second bit line sense amplifiers of a second first type sense buffer circuit of the data transfer circuit coupled to a bit line or a bit line pair of an adjacent memory block by the second multiplexer and connecting the selected group of second bit line sense amplifiers to the first multiplexer, wherein a second first type sense buffer circuit of the data transfer circuit coupled to a bit line or a bit line pair of an adjacent memory block includes the plurality of second bit line sense amplifiers; sensing, latching and buffering, by the selected group of first bit line sense amplifiers, a data signal on a bit line or a bit line pair in the memory block coupled to the selected group of first bit line sense amplifiers; The first bit line sense amplifier of the selected group transmits the data signal to the second bit line sense amplifier of the selected group or a data interface through the connection operation of the first multiplexer and the second multiplexer; transmitting the data signal to a bit line or a bit line pair in the adjacent memory block coupled to a second bit line sense amplifier of the selected group; as well as The data signal is sequentially transferred between subsequent memory blocks through other data transfer circuits coupled to two adjacent memory blocks.

24. The operating method according to claim 19, characterized in that: Also includes: An interface transfer circuit connects a bit line or a bit line pair of a memory block to a data interface or an arithmetic logic circuit; The interface transfer circuit senses, latches and buffers the data signal on the bit line or bit line pair of the memory block; as well as The data signal is transmitted directly or multiplexed from an external device or other data output port of the memory device to the interface transfer circuit via the data interface; or the data signal on the bit line or bit line pair of the memory block is transmitted by the interface transfer circuit to the data interface or the operation logic circuit.

25. The operating method according to claim 19, characterized in that: Also includes: selecting, by a multiplexer of an interface transfer circuit, a selected group of bit lines or bit line pairs of the memory block from a first number of bit lines or bit lines of the memory block; Connecting the selected group of bit lines or bit line pairs in the memory block to a data interface or an arithmetic logic circuit by the multiplexer; sensing, latching and buffering, by the interface transfer circuit, data signals on the bit lines or bit line pairs of the selected group in the memory block; as well as Directly or multiplexedly transmitting data signals from an external device or other data output ports of the memory device to the interface transfer circuit and to the bit lines or bit line pairs of the selected group via the data interface; or The data signal on the bit line or the bit line pair of the memory block is transmitted to the data interface or the operation logic circuit via the interface transfer circuit.

26. The operating method according to claim 19, characterized in that: Also includes: Selecting a selected group of bit line sense amplifiers from a plurality of bit line sense amplifiers of a first type sense buffer circuit of an interface transfer circuit coupled to a bit line or a bit line pair of a memory block; A multiplexer of the interface transfer circuit connects the bit lines or bit line pairs of the selected group to a data interface or an arithmetic logic circuit; sensing, latching and buffering, by the selected group of bit line sense amplifiers of the first type sense buffer circuit, a data signal on the bit line or bit line pair coupled to the selected group of bit line sense amplifiers; as well as Directly or multiplexedly transmitting data signals from an external device or other data output ports of the memory device to the interface transfer circuit and to the bit lines or bit line pairs of the selected group via the data interface; or The bit line sense amplifiers of the selected group are connected through the first multiplexer to transmit the data signal to the data interface or the operation logic circuit.

27. The operating method according to claim 19, characterized in that: Also includes: During a first operation, connecting a bit line or a bit line pair of a memory block to a first sensing buffer circuit of an interface transfer circuit; During the first operation, the first sensing buffer circuit senses, latches and buffers a data signal on a bit line or a bit line pair of the memory block; In a second operation period after the first operation period, the first sensing buffer circuit transmits the latched data signal to an operation logic circuit; During the second operation period, a second sensing buffer circuit of the interface transfer circuit connects the bit line or bit line pair of the memory block to the arithmetic logic circuit; During the second operation, the second sensing buffer circuit senses, latches and buffers a data signal on a bit line or a bit line pair of the memory block; as well as During a third operation period, the second sensing buffer circuit transmits the latched data signal to the arithmetic logic circuit, and senses the data signal of the bit line or the bit line pair of the memory block simultaneously with the first sensing buffer circuit.

28. The operating method according to claim 19, characterized in that: Also includes: A serial data originally stored in a memory cell coupled to a word line is obtained, wherein the string data is then sequentially stored in memory cells coupled to the word lines in a plurality of memory blocks with or without further processing, thereby rotating the serial data in the memory device in a transposed manner.

29. The operating method according to claim 19, further comprising: A page of data is copied in advance from the memory block and moved to a memory block adjacent to or near the arithmetic logic circuit to quickly or repeatedly access and operate the page of data.

30. The operating method according to claim 19, characterized in that: All or part of the different types of data transfer circuits coupled to the bit lines or bit line pairs in the memory block, the interface transfer circuits, and the data interfaces in the multi-block memory array are configured to operate in series or in parallel.

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