A dual-mode offset calibration circuit for comparators used in high-speed time-domain interleaved ADCs

Abstract

This invention discloses a dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC, comprising: calibration logic, n channels, and a configurable resistor string; wherein, the calibration logic includes detection logic and compensation logic; each channel is connected to the calibration logic and the configurable resistor string respectively; any one of the n channels includes: a switch array, a latch array, and a comparator. The detection logic proposed in this invention reduces the noise impact during the comparator offset detection process; multiple channels reuse a single calibration logic and configurable resistor string, greatly reducing the circuit's power consumption and area; the configurable resistor string selects either a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL. The coarse calibration mode has a larger calibration range and faster convergence speed compared to the fine calibration mode, while the fine calibration mode has higher calibration accuracy compared to the coarse calibration mode.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design, specifically relating to a dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC. Background Technology

[0002] Time-domain interleaved ADCs (TIADCs) employ multiple sub-channel ADCs to sample and quantize the same input signal in parallel. Each sub-channel ADC performs the conversion from analog to digital signal separately and outputs the results alternately. This allows the overall ADC to maintain the conversion accuracy of a single channel while significantly increasing the ADC's conversion rate. However, in practical production applications, due to factors such as chip manufacturing processes, environmental conditions like temperature and voltage during chip operation, and the imperfect symmetry and matching of sub-channels in the layout design, the sub-channel ADCs cannot be completely identical and cannot achieve identical operating states. This results in mismatch in time-domain interleaved ADCs. While the comparators in a single-channel ADC have some offset, the offset magnitudes of the comparators in a time-domain interleaved ADC are not identical, leading to the mismatch phenomenon.

[0003] Inter-channel mismatch affects the accuracy of the data obtained from sampling and quantization in a time-domain interleaved ADC. It distorts the resulting time-domain waveform and introduces harmonics and spurious signals into the ADC's output spectrum, severely degrading the system's signal-to-noise ratio and dynamic performance metrics such as spurious-free dynamic range. In practical ADC design, neglecting comparator mismatch calibration significantly impacts ADC performance. Therefore, calibrating the comparator mismatch in each channel of the time-domain interleaved ADC to minimize mismatch is crucial.

[0004] In traditional time-domain interleaved ADC comparator offset calibration circuits, each channel's comparator often requires a separate calibration circuit. The more channels there are, the larger the power consumption and area of ​​the calibration circuit become. Furthermore, the calibration circuit is susceptible to noise when detecting comparator offset, leading to calibration errors. In addition, traditional calibration circuits have limited application scenarios and often lack good portability. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A dual-mode offset calibration circuit for a comparator used in a high-speed time-domain interleaved ADC includes:

[0007] Calibration logic, n channels, and a configurable resistor string; among which,

[0008] The calibration logic includes detection logic and compensation logic;

[0009] Each channel is connected in series with the calibration logic and the configurable resistor, respectively.

[0010] Any one of the n channels includes: a switch array, a latch array, and a comparator;

[0011] The detection logic determines the offset polarity of the comparator based on the output of the comparator, generates offset polarity selection signals APSEL and ANSEL, and simultaneously generates control signals OPS and ONS.

[0012] The compensation logic generates 64-bit digital codes S0~S63 based on the control signals OPS and ONS;

[0013] The latch array latches according to the 64-bit digital code S0~S63, and generates corresponding signals S0L~S63L;

[0014] The switch array controls the switching between itself and the configurable resistor string according to the signals S0L~S63L to generate node voltage VCAL;

[0015] The configurable resistor string selects either coarse calibration mode or fine calibration mode according to the obtained external signal MODESEL.

[0016] The switch array outputs calibration terminal voltages VIPC and VINC based on the offset polarity selection signals APSEL and ANSEL and the node voltage VCAL, thereby achieving offset calibration of the comparator.

[0017] In one embodiment of the present invention, the circuit structure of the detection logic includes:

[0018] Pulse counter 1, pulse counter 2, D flip-flop 1, D flip-flop 2, and latch unit; wherein,

[0019] The CLK1 terminal of the pulse counter 1 is connected to the VOP output terminal of the comparator, the Reset1 terminal of the pulse counter 1 is connected to the reset signal RD of the calibration logic, and the OUT1 terminal of the pulse counter 1 is connected to the CLK2 terminal of the D flip-flop 1, and outputs the control signal OPS.

[0020] The D1 input of the D flip-flop 1 is connected to VDD, the Reset2 input of the D flip-flop 1 is connected to the reset signal RD of the calibration logic, and the QB1 output of the D flip-flop 1 is connected to the AP input of the latch unit.

[0021] The CLK3 terminal of the pulse counter 2 is connected to the VON output terminal of the comparator, the Reset3 terminal of the pulse counter 2 is connected to the reset signal RD of the calibration logic, and the OUT2 terminal of the pulse counter 2 is connected to the CLK4 terminal of the D flip-flop 2, and outputs the control signal ONS.

[0022] The D2 input terminal of the D flip-flop 2 is connected to the VDD, the Reset4 terminal of the D flip-flop 2 is connected to the reset signal RD of the calibration logic, and the QB2 output terminal of the D flip-flop 2 is connected to the AN input terminal of the latch unit.

[0023] The RD1 terminal of the latch unit is connected to the reset signal RD of the calibration logic. The APL output terminal of the latch unit outputs the offset polarity selection signal APSEL, and the ANL output terminal of the latch unit outputs the offset polarity selection signal ANSEL.

[0024] In one embodiment of the present invention, pulse counter 1 and pulse counter 2 have the same structure, and the circuit structure of either one includes:

[0025] D flip-flop 3, D flip-flop 4, first AND gate, second AND gate, first OR gate, and third AND gate; among which...

[0026] The CLK5 terminal of the D flip-flop 3 is connected to the first input terminal of the third AND gate, serving as the CLK terminal of the pulse flip-flop. The D3 input terminal of the D flip-flop 3 is connected to the first input terminal of the first AND gate. The Reset5 terminal of the D flip-flop 3 is connected to the Reset6 terminal of the D flip-flop 4, serving as the Reset terminal of the pulse flip-flop, and is used to connect the reset signal RD of the calibration logic. The Q3 output terminal of the D flip-flop 3 is connected to the second input terminal of the second AND gate. The QB3 output terminal of the D flip-flop 3 is connected to the D3 input terminal of the D flip-flop 3.

[0027] The CLK6 terminal of the D flip-flop 4 is connected to the first input terminal of the third AND gate, the D4 input terminal of the D flip-flop 4 is connected to the output terminal of the first OR gate, the Q4 output terminal of the D flip-flop 4 is connected to the second input terminal of the first AND gate, and the QB4 output terminal of the D flip-flop 4 is connected to the first input terminal of the second AND gate.

[0028] The output of the first AND gate is connected to the first input of the first OR gate, and the output of the second AND gate is connected to the second input of the first OR gate.

[0029] The second input of the third AND gate is connected to the Q4 output of the D flip-flop 4, the third input of the third AND gate is connected to the second input of the second AND gate, and the output of the third AND gate serves as the OUT terminal of the pulse counter.

[0030] In one embodiment of the present invention, the circuit structure of the latch unit includes:

[0031] MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8; a first NOT gate and a second NOT gate; among which,

[0032] The source of the MOS transistor M1 is grounded, the gate of the MOS transistor M1 is connected to the output of the first NOT gate, and the drain of the MOS transistor M1 is connected to the drain of the MOS transistor M5, serving as the APL output of the latch unit.

[0033] The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the drain of the MOS transistor M6, serving as the ANL output terminal of the latch unit, and the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M5, serving as the APL output terminal of the latch unit.

[0034] The source of the MOS transistor M3 is grounded, the gate of the MOS transistor M3 is connected to the drain of the MOS transistor M5, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M6.

[0035] The source of the MOS transistor M4 is grounded, the gate of the MOS transistor M4 is connected to the output terminal of the second NOT gate, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M6.

[0036] The source of the MOS transistor M5 is connected to the drain of the MOS transistor M7, and the gate of the MOS transistor M5 serves as the AP input terminal of the latch unit.

[0037] The source of the MOS transistor M6 is connected to the drain of the MOS transistor M8, and the gate of the MOS transistor M6 serves as the AN input terminal of the latch unit.

[0038] The source of the MOS transistor M7 is connected to VDD, and the gate of the MOS transistor M7 is connected to the gate of the MOS transistor M2.

[0039] The source of the MOS transistor M8 is connected to VDD, and the gate of the MOS transistor M8 is connected to the drain of the MOS transistor M2.

[0040] The input terminals of the first NOT gate and the second NOT gate are connected to the RD1 terminal of the latch unit and the reset signal RD of the calibration logic.

[0041] In one embodiment of the present invention, the circuit structure of the compensation logic includes:

[0042] The system includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a D flip-flop 5, a D flip-flop 6, a second OR gate, a 6-bit counter, and a 6-to-64 decoder; among which,

[0043] The first terminal of the first switch S1 is connected to the control signal ONS, and the second terminal of the first switch S1 is connected to the CLK7 terminal of the D flip-flop 5.

[0044] The first terminal of the second switch S2 is connected to the control signal OPS, and the second terminal of the second switch S2 is connected to the CLK7 terminal of the D flip-flop 5.

[0045] The D5 input of the D flip-flop 5 is connected to VDD, the Reset7 input of the D flip-flop 5 is connected to the reset signal RD of the calibration logic, and the Q5 output of the D flip-flop 5 is connected to the first input of the second OR gate.

[0046] The D6 input of the D flip-flop 6 is connected to VDD, the CLK8 input of the D flip-flop 6 is connected to the Z output of the 6-bit counter, the Reset8 input of the D flip-flop 6 is connected to the reset signal RD of the calibration logic, and the Q6 output of the D flip-flop 6 is connected to the second input of the second OR gate.

[0047] The first terminal of the third switch S3 is connected to the control signal OPS, and the second terminal of the third switch S3 is connected to the CLK9 terminal of the 6-bit counter.

[0048] The first terminal of the fourth switch S4 is connected to the control signal ONS, and the second terminal of the fourth switch S4 is connected to the CLK9 terminal of the 6-bit counter.

[0049] The H input terminal of the 6-bit counter is connected to the output terminal of the second OR gate, the Reset9 terminal of the 6-bit counter is connected to the reset signal RD of the calibration logic, and the Q0~Q5 output terminals of the 6-bit counter are respectively connected to the H0~H5 input terminals of the 6-64 decoder.

[0050] The S0~S63 output terminals of the 6-64 decoder are connected to the input terminals of the latch array.

[0051] In one embodiment of the present invention, the circuit structure of a 6-bit counter includes:

[0052] 3-bit counter 1, 3-bit counter 2, a third NOT gate, and a fourth AND gate; among which,

[0053] The H1 terminal of the 3-bit counter 1 serves as the H terminal of the 6-bit counter; the Reset10 terminal of the 3-bit counter 1 and the Reset11 terminal of the 3-bit counter 2 serve as the Reset9 terminal of the 6-bit counter; the CLK10 terminal of the 3-bit counter 1 and the CLK11 terminal of the 3-bit counter 2 serve as the CLK9 terminal of the 6-bit counter; the Qa output terminal of the 3-bit counter 1 is connected to the first input terminal of the fourth AND gate and serves as the Q0 output terminal of the 6-bit counter; the Qb output terminal of the 3-bit counter 1 is connected to the second input terminal of the fourth AND gate and serves as the Q1 output terminal of the 6-bit counter; the Qc output terminal of the 3-bit counter 1 is connected to the third input terminal of the fourth AND gate and serves as the Q2 output terminal of the 6-bit counter; and the Z1 output terminal of the 3-bit counter 1 is connected to the input terminal of the third NOT gate.

[0054] The output of the third NOT gate is connected to the H2 terminal of the 3-bit counter 2;

[0055] The Qd output of the 3-bit counter 2 serves as the Q3 output of the 6-bit counter, the Qe output of the 3-bit counter 2 serves as the Q4 output of the 6-bit counter, the Qf output of the 3-bit counter 1 serves as the Q5 output of the 6-bit counter, the Z2 output of the 3-bit counter 2 is connected to the fourth input of the fourth AND gate, and the output of the fourth AND gate serves as the Z output of the 6-bit counter.

[0056] In one embodiment of the present invention, the circuit structure of the latch array includes:

[0057] 64 identical latch modules; the input terminal of each latch module is connected to the corresponding output terminals S0~S63 of the 6-64 decoder, and the output terminal of each latch module corresponds to the output signals S0L~S63L, wherein,

[0058] Any one of the 64 identical latch modules includes:

[0059] Switch 1, switch 2, inverter 1 and inverter 2;

[0060] The first end of the switch 1 is connected to one of the outputs S0 to S63 of the 6-64 decoder, and the second end of the switch 1 is connected to the input of the inverter 1.

[0061] The first end of the switch 2 is connected to the second end of the switch 1, and the second end of the switch 2 is connected to the output end of the inverter 2;

[0062] The output terminal of inverter 1 is connected to the input terminal of inverter 2;

[0063] The output terminal of the inverter 2 outputs one of the output signals S0L to S63L.

[0064] In one embodiment of the present invention, the circuit structure of the configurable resistor string includes:

[0065] MOSFETs M9 and M10, first resistor, second resistor, third resistor, fourth resistor, switch 3, switch 4, fourth NOT gate, and resistor string; among them,

[0066] The source of the MOS transistor M9 is grounded, the gate of the MOS transistor M9 is connected to the enable signal SEL, and the drain of the MOS transistor M9 is connected to the first terminal of the first resistor.

[0067] The second end of the first resistor is connected to the first end of the resistor string;

[0068] The first end of the second resistor is connected to the drain of the MOSFET M9, and the second end of the second resistor is connected to the first end of the switch 3;

[0069] The second terminal of the switch 3 is connected to the second terminal of the first resistor;

[0070] The resistor string consists of 64 resistors connected in series, with voltages V1 to V63 sequentially drawn between adjacent resistors. A voltage VL is drawn from the first end of the resistor string, and a voltage VH is drawn from the second end of the resistor string.

[0071] The first end of the third resistor is connected to the drain of the MOS transistor M10, and the second end of the third resistor is connected to the second end of the resistor string.

[0072] The first end of the fourth resistor is connected to the first end of the third resistor;

[0073] The first end of the switch 4 is connected to the second end of the resistor string, and the second end of the switch 4 is connected to the second end of the fourth resistor;

[0074] The source of the MOS transistor M10 is connected to VDD, and the gate of the MOS transistor M10 is connected to the output of the fourth NOT gate.

[0075] The input terminal of the fourth NOT gate is connected to the enable signal SEL.

[0076] In one embodiment of the present invention, the circuit structure of the switch array includes:

[0077] 64 switches, switch 5, switch 6, switch 7 and switch 8; among them,

[0078] The first terminals of the 64 switches are respectively connected to voltages VL~V63, and the second terminals of the 64 switches are connected to the first node.

[0079] The first terminal of the switch 5 is connected to the voltage VCAL of the first node, and the second terminal of the switch 5 is connected to the second terminal of the switch 6 at the second node.

[0080] The first terminal of the switch 6 is connected to the voltage VL drawn from the first terminal of the resistor string;

[0081] The first terminal of the switch 7 is connected to the voltage VCAL of the first node, and the second terminal of the switch 7 is connected to the second terminal of the switch 8 at the third node;

[0082] The first terminal of the switch 8 is connected to the voltage VL drawn from the first terminal of the resistor string;

[0083] The voltage of the second node is used as the calibration terminal voltage VIPC;

[0084] The voltage of the third node is used as the calibration terminal voltage VINC.

[0085] The beneficial effects of this invention are:

[0086] The solution provided in this invention reduces noise interference during comparator offset detection by employing a proposed detection logic. Multiple channels reuse a single calibration logic and a configurable resistor string, significantly reducing circuit power consumption and area. The configurable resistor string selects either a coarse or fine calibration mode based on the obtained external signal MODESEL. The coarse calibration mode offers a wider calibration range and faster convergence speed compared to the fine calibration mode, while the fine calibration mode provides higher calibration accuracy. This invention offers two operating modes, better adapting to comparators with different structures and performance characteristics, and enabling a wider range of applications. Attached Figure Description

[0087] Figure 1 This is a schematic diagram of the structure of a dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0088] Figure 2 This is a schematic diagram of the structure of a single-channel offset calibration circuit in a dual-mode offset calibration circuit for a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0089] Figure 3 This is a schematic diagram of the detection logic in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0090] Figure 4 This is a schematic diagram of the pulse counter in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0091] Figure 5 This is a schematic diagram of the latch unit in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0092] Figure 6 This is a schematic diagram of the compensation logic in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0093] Figure 7 This is a schematic diagram of the structure of a 6-bit counter in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, provided in an embodiment of the present invention.

[0094] Figure 8 This is a schematic diagram of the latch array structure in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, as provided in an embodiment of the present invention.

[0095] Figure 9 This is a schematic diagram of the structure of a configurable resistor string in a dual-mode offset calibration circuit of a comparator applied to a high-speed time-domain interleaved ADC, as provided in an embodiment of the present invention.

[0096] Figure 10 This is a schematic diagram of the switch array structure in a dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC, as provided in an embodiment of the present invention. Detailed Implementation

[0097] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0098] This invention proposes a dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC. See [link to relevant documentation]. Figure 1 ,include:

[0099] Calibration logic, n channels, and a configurable resistor string; among which,

[0100] Calibration logic includes detection logic and compensation logic;

[0101] Each channel is connected in series with calibration logic and a configurable resistor;

[0102] Any one of the n channels includes: a switch array, a latch array, and a comparator;

[0103] The detection logic determines the offset polarity of the comparator based on the output of the comparator, generates offset polarity selection signals APSEL and ANSEL, and generates control signals OPS and ONS at the same time.

[0104] The compensation logic generates 64-bit digital codes S0~S63 based on the control signals OPS and ONS;

[0105] The latch array latches according to the 64-bit digital code S0~S63, and generates corresponding signals S0L~S63L;

[0106] The switch array controls the on / off state between itself and the configurable resistor string according to signals S0L~S63L, generating node voltage VCAL;

[0107] The configurable resistor string selects either coarse or fine calibration mode based on the obtained external signal MODESEL.

[0108] The switch array selects the offset polarity selection signals APSEL, ANSEL and the node voltage VCAL to output the calibration terminal voltages VIPC and VINC, thereby achieving offset calibration of the comparator.

[0109] This invention primarily designs a comparator offset calibration circuit for a time-domain interleaved ADC. The circuit mainly consists of calibration logic, a switch array, a latch array, and a configurable resistor string. In a multi-channel time-domain interleaved ADC, multiple channels can reuse a single calibration logic and configurable resistor string. Specifically, the calibration logic comprises detection logic and compensation logic; the detection logic consists of D flip-flops, a pulse counter, and a latch unit; the compensation logic consists of D flip-flops, a 6-bit counter with hold and asynchronous clear functions, a 6-64 decoder, switches, and logic gates.

[0110] The appropriate calibration circuit operating mode is selected based on the offset voltage range of the comparator in the time-domain interleaved ADC and the required accuracy of the ADC. When the mode selection signal MODESEL is high, the offset calibration circuit can perform coarse calibration of the comparator offset voltage; when the mode selection signal MODESEL is low, the offset calibration circuit can perform fine calibration of the comparator offset voltage. The coarse calibration mode has a larger calibration range and faster convergence speed than the fine calibration mode, while the fine calibration mode has higher calibration accuracy than the coarse calibration mode.

[0111] The comparator offset calibration process is consistent across all channels of the time-domain interleaved ADC; see [link / reference]. Figure 2 The comparator offset calibration process is illustrated using a single-channel calibration process as an example:

[0112] 1) Before calibration begins, connect the comparator inputs VIN and VIP to the common-mode level Vcm (Vcm is half of the power supply voltage). Then the comparator will start comparing and output the comparison results VOP and VON.

[0113] 2) The detection logic determines the offset polarity of the comparator based on the comparison result of the comparator, generates offset polarity selection signals APSEL and ANSEL, and generates control signals OPS and ONS for the compensation logic.

[0114] 3) The compensation logic generates 64-bit digital codes S0-S63 under the control of the detection logic.

[0115] 4) The 64-bit digital codes S0-S63 are latched by the latch array to generate signals S0L-S63L. S0L-S63L generates calibration terminal voltages VIC and VINC by controlling the connection relationship between the switch array and the configurable resistor string.

[0116] In practical applications, the appropriate calibration circuit operating mode can be selected based on the offset voltage range of the comparator in the time-domain interleaved ADC and the required accuracy of the ADC: one operating mode can perform coarse calibration of the comparator offset voltage, and another operating mode can perform fine calibration of the comparator offset voltage. A calibration circuit with two operating modes can better adapt to comparators with different structures and performance characteristics. In multi-channel time-domain interleaved ADCs, multiple channels can reuse a single calibration logic and configurable resistor string, significantly reducing the power consumption and area of ​​the offset calibration circuit compared to traditional structures.

[0117] For ease of understanding, the various modules in the later embodiments of the present invention will be described below.

[0118] Calibration Logic

[0119] The calibration logic includes detection logic and compensation logic.

[0120] The circuit structure of the detection logic is as follows: Figure 3 As shown, it includes:

[0121] Pulse counter 1, pulse counter 2, D flip-flop 1, D flip-flop 2, and latch unit; wherein,

[0122] The CLK1 terminal of pulse counter 1 is connected to the VOP output terminal of the comparator, the Reset1 terminal of pulse counter 1 is connected to the reset signal RD of the calibration logic, and the OUT1 terminal of pulse counter 1 is connected to the CLK2 terminal of D flip-flop 1 and outputs the control signal OPS.

[0123] The D1 input of D flip-flop 1 is connected to VDD, the Reset2 input of D flip-flop 1 is connected to the reset signal RD of the calibration logic, and the QB1 output of D flip-flop 1 is connected to the AP input of the latch unit.

[0124] The CLK3 terminal of pulse counter 2 is connected to the VON output terminal of the comparator, the Reset3 terminal of pulse counter 2 is connected to the reset signal RD of the calibration logic, and the OUT2 terminal of pulse counter 2 is connected to the CLK4 terminal of D flip-flop 2 and outputs the control signal ONS.

[0125] The D2 input of D flip-flop 2 is connected to VDD, the Reset4 input of D flip-flop 2 is connected to the reset signal RD of the calibration logic, and the QB2 output of D flip-flop 2 is connected to the AN input of the latch unit.

[0126] The RD1 terminal of the latch unit is connected to the reset signal RD of the calibration logic. The APL output terminal of the latch unit outputs the offset polarity selection signal APSEL, and the ANL output terminal of the latch unit outputs the offset polarity selection signal ANSEL.

[0127] The detection logic determines the offset polarity of the comparator based on the output of the comparator, generates offset polarity selection signals APSEL and ANSEL, and simultaneously generates control signals OPS and ONS.

[0128] Specifically, pulse counter 1 and pulse counter 2 have the same structure, and the circuit structure of either one is as follows: Figure 4 As shown, it includes:

[0129] D flip-flop 3, D flip-flop 4, first AND gate, second AND gate, first OR gate, and third AND gate; among which...

[0130] The CLK5 terminal of D flip-flop 3 is connected to the first input terminal of the third AND gate, serving as the CLK terminal of the pulse flip-flop. The D3 input terminal of D flip-flop 3 is connected to the first input terminal of the first AND gate. The Reset5 terminal of D flip-flop 3 is connected to the Reset6 terminal of D flip-flop 4, serving as the Reset terminal of the pulse flip-flop, used to connect the reset signal RD of the calibration logic. The Q3 output terminal of D flip-flop 3 is connected to the second input terminal of the second AND gate. The QB3 output terminal of D flip-flop 3 is connected to the D3 input terminal of D flip-flop 3.

[0131] The CLK6 terminal of D flip-flop 4 is connected to the first input terminal of the third AND gate, the D4 input terminal of D flip-flop 4 is connected to the output terminal of the first OR gate, the Q4 output terminal of D flip-flop 4 is connected to the second input terminal of the first AND gate, and the QB4 output terminal of D flip-flop 4 is connected to the first input terminal of the second AND gate.

[0132] The output of the first AND gate is connected to the first input of the first OR gate, and the output of the second AND gate is connected to the second input of the first OR gate.

[0133] The second input of the third AND gate is connected to the Q4 output of the D flip-flop 4, the third input of the third AND gate is connected to the second input of the second AND gate, and the output of the third AND gate serves as the OUT terminal of the pulse counter.

[0134] RD is the reset signal for the calibration logic. When RD is low, a reset is performed; when RD is high, the circuit operates normally.

[0135] Pulse counter 1 and pulse counter 2 detect the number of pulses at the two output terminals VOP and VON of the comparator, respectively. For every four pulses generated at the comparator's output, the pulse counter outputs one pulse. If the pulse counter at the VOP terminal outputs the first pulse, it is determined that the comparator's P terminal needs compensation, i.e., the voltage at the calibration terminal VINC needs to be increased; otherwise, it is determined that the comparator's N terminal needs compensation, i.e., the voltage at the calibration terminal VINC needs to be increased. Pulse counter 1 and pulse counter 2 output control signals OPS and ONS.

[0136] Specifically, the circuit structure of the latch unit is as follows: Figure 5 As shown, it includes:

[0137] MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8; a first NOT gate and a second NOT gate; among which,

[0138] The source of MOSFET M1 is grounded, the gate of MOSFET M1 is connected to the output of the first NOT gate, and the drain of MOSFET M1 is connected to the drain of MOSFET M5, serving as the APL output of the latch unit.

[0139] The source of MOSFET M2 is grounded, the gate of MOSFET M2 is connected to the drain of MOSFET M6, serving as the ANL output terminal of the latch unit, and the drain of MOSFET M2 is connected to the drain of MOSFET M5, serving as the APL output terminal of the latch unit.

[0140] The source of MOSFET M3 is grounded, the gate of MOSFET M3 is connected to the drain of MOSFET M5, and the drain of MOSFET M3 is connected to the drain of MOSFET M6.

[0141] The source of MOSFET M4 is grounded, the gate of MOSFET M4 is connected to the output of the second NOT gate, and the drain of MOSFET M4 is connected to the drain of MOSFET M6.

[0142] The source of MOSFET M5 is connected to the drain of MOSFET M7, and the gate of MOSFET M5 serves as the AP input terminal of the latch unit.

[0143] The source of MOSFET M6 is connected to the drain of MOSFET M8, and the gate of MOSFET M6 serves as the AN input terminal of the latch unit.

[0144] The source of MOSFET M7 is connected to VDD, and the gate of MOSFET M7 is connected to the gate of MOSFET M2.

[0145] The source of MOSFET M8 is connected to VDD, and the gate of MOSFET M8 is connected to the drain of MOSFET M2.

[0146] The inputs of the first NOT gate and the second NOT gate are connected to the RD1 terminal of the latch unit and the reset signal RD of the calibration logic.

[0147] The outputs OPS and ONS of the two pulse counters are processed by D flip-flops and latch units to generate offset polarity selection signals APSEL and ANSEL. When the offset polarity selection signal APSEL is high and ANSEL is low, the calibration terminal VIPC is defined as the rise terminal and the calibration terminal VINC is defined as the hold terminal; when the offset polarity selection signal APSEL is low and ANSEL is high, the calibration terminal VIPC is defined as the hold terminal and the calibration terminal VINC is defined as the rise terminal.

[0148] The specific working process of the detection logic is as follows: The comparator outputs VOP and VON are respectively processed by pulse counter 1 and pulse counter 2 to generate control signals OPS and ONS. OPS and ONS serve as clock signals for the two D flip-flops. The input signals of the two D flip-flops are both connected to a high level VDD. The inverting outputs QB of the two D flip-flops are connected to the latch inputs AP and AN, respectively. Initially, AP and AN are high, and APL and ANL are low. Subsequently, if OPS goes high first, AP goes low before AN, and the latch unit outputs APL latch high and ANL latch low; if ONS goes high first, AN goes low before AP, and the latch unit outputs APL latch low and ANL latch high. The latch unit outputs APL and ANL serve as the offset polarity selection signals APSEL and ANSEL for the calibration circuit, respectively. When the offset polarity selection signal APSEL is high and ANSEL is low, the calibration terminal VIPC is defined as the rise terminal and the calibration terminal VINC is defined as the hold terminal; when the offset polarity selection signal APSEL is low and ANSEL is high, the calibration terminal VIPC is defined as the hold terminal and the calibration terminal VINC is defined as the rise terminal.

[0149] The circuit structure of the compensation logic is as follows: Figure 6As shown, it includes:

[0150] The system includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a D flip-flop 5, a D flip-flop 6, a second OR gate, a 6-bit counter, and a 6-to-64 decoder; among which,

[0151] The first terminal of the first switch S1 is connected to the control signal ONS, and the second terminal of the first switch S1 is connected to the CLK7 terminal of the D flip-flop 5.

[0152] The first terminal of the second switch S2 is connected to the control signal OPS, and the second terminal of the second switch S2 is connected to the CLK7 terminal of the D flip-flop 5.

[0153] The D5 input of D flip-flop 5 is connected to VDD, the Reset7 input of D flip-flop 5 is connected to the reset signal RD of the calibration logic, and the Q5 output of D flip-flop 5 is connected to the first input of the second OR gate.

[0154] The D6 input of D flip-flop 6 is connected to VDD, the CLK8 input of D flip-flop 6 is connected to the Z output of the 6-bit counter, the Reset8 input of D flip-flop 6 is connected to the reset signal RD of the calibration logic, and the Q6 output of D flip-flop 6 is connected to the second input of the second OR gate.

[0155] The first terminal of the third switch S3 is connected to the control signal OPS, and the second terminal of the third switch S3 is connected to the CLK9 terminal of the 6-bit counter.

[0156] The first terminal of the fourth switch S4 is connected to the control signal ONS, and the second terminal of the fourth switch S4 is connected to the CLK9 terminal of the 6-bit counter.

[0157] The H input of the 6-bit counter is connected to the output of the second OR gate, the Reset9 input of the 6-bit counter is connected to the reset signal RD of the calibration logic, and the Q0~Q5 outputs of the 6-bit counter are connected to the H0~H5 inputs of the 6-64 decoder respectively.

[0158] The S0~S63 outputs of the 6-64 decoder are connected to the inputs of the latch array.

[0159] The compensation logic generates 64-bit digital codes S0~S63 based on the control signals OPS and ONS.

[0160] Specifically, the circuit structure of a 6-bit counter is as follows: Figure 7 As shown, it includes:

[0161] 3-bit counter 1, 3-bit counter 2, a third NOT gate, and a fourth AND gate; among which,

[0162] The H1 terminal of the 3-bit counter 1 is used as the H terminal of the 6-bit counter; the Reset10 terminal of the 3-bit counter 1 and the Reset11 terminal of the 3-bit counter 2 are used as the Reset9 terminal of the 6-bit counter; the CLK10 terminal of the 3-bit counter 1 and the CLK11 terminal of the 3-bit counter 2 are used as the CLK9 terminal of the 6-bit counter; the Qa output terminal of the 3-bit counter 1 is connected to the first input terminal of the fourth AND gate and is used as the Q0 output terminal of the 6-bit counter; the Qb output terminal of the 3-bit counter 1 is connected to the second input terminal of the fourth AND gate and is used as the Q1 output terminal of the 6-bit counter; the Qc output terminal of the 3-bit counter 1 is connected to the third input terminal of the fourth AND gate and is used as the Q2 output terminal of the 6-bit counter; and the Z1 output terminal of the 3-bit counter 1 is connected to the input terminal of the third NOT gate.

[0163] The output of the third NOT gate is connected to the H2 terminal of the 3-bit counter 2;

[0164] The Qd output of the 3-bit counter 2 is used as the Q3 output of the 6-bit counter, the Qe output of the 3-bit counter 2 is used as the Q4 output of the 6-bit counter, the Qf output of the 3-bit counter 1 is used as the Q5 output of the 6-bit counter, the Z2 output of the 3-bit counter 2 is connected to the fourth input of the fourth AND gate, and the output of the fourth AND gate is used as the Z output of the 6-bit counter.

[0165] When the reset signal RD of the calibration logic is low, the 6-bit counter is reset; when the reset signal RD of the calibration logic is high, the 6-bit counter works normally.

[0166] The offset polarity selection signals APSEL and ANSEL select one of the outputs of the two pulse counters, OPS and ONS, as the pulse input signal for the 6-bit counter. The 6-bit counter counts the number of pulses of either OPS or ONS starting from zero, and the counter output is a 6-bit binary number. The carry signal Z. When one of the two pulse counter outputs, OPS and ONS, serves as the pulse input signal for the 6-bit counter, the other signal serves as the stop signal HCLK for the compensation logic. The carry signal Z of the counter serves as the other stop signal ZCLK for the compensation logic.

[0167] The specific working process of the compensation logic is as follows: When the offset polarity selection signal APSEL is high and ANSEL is low, the calibration terminal VIPC is defined as the rise terminal and the calibration terminal VINC is defined as the hold terminal, with OPS serving as the pulse input signal for the 6-bit counter; when the offset polarity selection signal APSEL is low and ANSEL is high, the calibration terminal VIPC is defined as the hold terminal and the calibration terminal VINC is defined as the rise terminal, with ONS serving as the pulse input signal for the 6-bit counter. The 6-bit counter counts the number of pulses from OPS or ONS starting from zero, and the counter output is a 6-bit binary number and a carry signal Z. When OPS serves as the pulse input signal for the 6-bit counter, ONS serves as the stop signal HCLK for the compensation logic. When ONS serves as the pulse input signal for the 6-bit counter, OPS serves as the stop signal HCLK for the compensation logic. The carry signal Z of the counter serves as another stop signal ZCLK for the compensation logic. HCLK and ZCLK generate the hold signal H of the counter via a D flip-flop and a two-input OR gate. When HCLK or ZCLK changes from low to high, the hold signal H also changes from low to high, at which point the counter stops counting and maintains the 6-bit binary number output by the counter. The 6-bit binary number is then converted into 64-bit digital codes S0-S63 by a 6-64 decoder.

[0168] latch array

[0169] Specifically, the circuit structure of the latch array is as follows: Figure 8 As shown, it includes:

[0170] 64 identical latch modules; the input of each latch module is connected to the corresponding outputs S0~S63 of the 6-64 decoder, and the output of each latch module corresponds to the output signals S0L~S63L.

[0171] Any one of the 64 identical latch modules includes:

[0172] Switch 1, switch 2, inverter 1 and inverter 2;

[0173] The first terminal of switch 1 is connected to one of the output terminals S0 to S63 of the 6-64 decoder, and the second terminal of switch 1 is connected to the input terminal of inverter 1.

[0174] The first terminal of switch 2 is connected to the second terminal of switch 1, and the second terminal of switch 2 is connected to the output terminal of inverter 2.

[0175] The output terminal of inverter 1 is connected to the input terminal of inverter 2;

[0176] The output terminal of inverter 2 corresponds to one of the output signals S0L to S63L.

[0177] The latch array consists of 64 identical latch modules. For ease of understanding, any one of the 64 identical latch modules will be described. Switch 1 is the switch connected to the S0~S63 output terminals of the 6-64 decoder, switch 2 is the switch connected to the output terminals S0L~S63L of the latch array, inverter 1 is the inverter near the S0~S63 output terminals of the 6-64 decoder, and inverter 2 is the inverter near the output terminals S0L~S63L of the latch array.

[0178] The latch array latches data based on 64-bit digital codes S0~S63, generating corresponding signals S0L~S63L. The latch array consists of inverters and switches. When signal EN is high, the latch writes data. When signal EN is low, the latch latches data.

[0179] Configurable resistor string

[0180] Specifically, the circuit structure of a configurable resistor string is as follows: Figure 9 As shown, it includes:

[0181] MOSFETs M9 and M10, first resistor, second resistor, third resistor, fourth resistor, switch 3, switch 4, fourth NOT gate, and resistor string; among them,

[0182] The source of MOSFET M9 is grounded, the gate of MOSFET M9 is connected to the enable signal SEL, and the drain of MOSFET M9 is connected to the first terminal of the first resistor.

[0183] The second end of the first resistor is connected to the first end of the resistor string;

[0184] The first end of the second resistor is connected to the drain of the MOSFET M9, and the second end of the second resistor is connected to the first end of the switch 3.

[0185] The second terminal of switch 3 is connected to the second terminal of the first resistor;

[0186] The resistor string consists of 64 resistors connected in series. Voltages V1 to V63 are sequentially drawn between adjacent resistors. Voltage VL is drawn from the first end of the resistor string, and voltage VH is drawn from the second end of the resistor string.

[0187] The first end of the third resistor is connected to the drain of the MOSFET M10, and the second end of the third resistor is connected to the second end of the resistor string.

[0188] The first terminal of the fourth resistor is connected to the first terminal of the third resistor;

[0189] The first terminal of switch 4 is connected to the second terminal of the resistor string, and the second terminal of switch 4 is connected to the second terminal of the fourth resistor.

[0190] The source of MOSFET M10 is connected to VDD, and the gate of MOSFET M10 is connected to the output of the fourth NOT gate.

[0191] The input of the fourth NOT gate is connected to the enable signal SEL.

[0192] The configurable resistor string can select either coarse or fine calibration mode based on the obtained external signal MODESEL.

[0193] The configurable resistor string consists of 64 resistors connected in series to generate a voltage divider. SEL is the enable signal for the resistor string. When SEL is high, the circuit operates normally; when SEL is low, the resistor string is disconnected from the power supply, resulting in no quiescent current and saving power. The MODESEL signal is the mode selection signal for the resistor string. When the MODESEL signal is high, the offset calibration circuit can perform coarse calibration of the comparator offset voltage. When the MODESEL signal is low, the offset calibration circuit can perform fine calibration of the comparator offset voltage.

[0194] Switch array

[0195] Specifically, the circuit structure of the switch array is as follows: Figure 10 As shown, it includes:

[0196] 64 switches, switch 5, switch 6, switch 7 and switch 8; among them,

[0197] The first terminals of the 64 switches are respectively connected to voltages VL~V63, and the second terminals of the 64 switches are connected to the first node.

[0198] The first terminal of switch 5 is connected to the voltage VCAL of the first node, and the second terminal of switch 5 and the second terminal of switch 6 are connected to the second node.

[0199] The first terminal of switch 6 is connected to the voltage VL drawn from the first terminal of the resistor string;

[0200] The first terminal of switch 7 is connected to the voltage VCAL of the first node, and the second terminal of switch 7 and the second terminal of switch 8 are connected to the third node.

[0201] The first terminal of switch 8 is connected to the voltage VL drawn from the first terminal of the resistor string;

[0202] The voltage at the second node is used as the calibration terminal voltage VIPC;

[0203] The voltage at the third node is used as the calibration terminal voltage VINC.

[0204] All switches in the switch array are turned on when high and off when low. The 64 switches on the left are controlled by signals S0L-S63L, with inputs being the 64 voltage dividers VL-V63 of the resistor string, and outputs being node VCAL. Switches 5, 6, 7, and 8 on the right are controlled by selection signals APSEL and ANSEL, making VCAL the voltage at the rise terminal in the calibration circuit and VL the voltage at the hold terminal in the calibration circuit.

[0205] The S0L-S63L series generates the voltage VCAL by controlling the connection between the switch array and the configurable resistor string. After selection by the offset polarity selection signals APSEL and ANSEL, VCAL serves as the voltage at the rise end of the calibration circuit, and VL serves as the voltage at the hold end. The switch array controls the on / off connection between itself and the configurable resistor string according to the signals S0L~S63L, generating the node voltage VCAL; and outputs the calibration terminal voltages VIC and VINC based on the offset polarity selection signals APSEL, ANSEL, and the node voltage VCAL, thus achieving offset calibration of the comparator.

[0206] The solution provided in this invention reduces noise interference during comparator offset detection by employing a proposed detection logic. Multiple channels reuse a single calibration logic and a configurable resistor string, significantly reducing circuit power consumption and area. The configurable resistor string selects either a coarse or fine calibration mode based on the obtained external signal MODESEL. The coarse calibration mode offers a wider calibration range and faster convergence speed compared to the fine calibration mode, while the fine calibration mode provides higher calibration accuracy. This invention offers two operating modes, better adapting to comparators with different structures and performance characteristics, and enabling a wider range of applications.

[0207] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC, characterized in that, include: Calibration logic, n channels, and a configurable resistor string; among which, The calibration logic includes detection logic and compensation logic; Each channel is connected in series with the calibration logic and the configurable resistor, respectively. Any one of the n channels includes: a switch array, a latch array, and a comparator; The detection logic determines the offset polarity of the comparator based on the output of the comparator, generates offset polarity selection signals APSEL and ANSEL, and simultaneously generates control signals OPS and ONS. The compensation logic generates 64-bit digital codes S0~S63 based on the control signals OPS and ONS; The latch array latches according to the 64-bit digital code S0~S63, and generates corresponding signals S0L~S63L; The switch array controls the switching between itself and the configurable resistor string according to the signals S0L~S63L to generate node voltage VCAL; The configurable resistor string selects either coarse calibration mode or fine calibration mode according to the obtained external signal MODESEL. The switch array outputs calibration terminal voltages VIPC and VINC based on the offset polarity selection signals APSEL and ANSEL and the node voltage VCAL, thereby achieving offset calibration of the comparator.

2. The dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 1, characterized in that, The circuit structure of the detection logic includes: Pulse counter 1, pulse counter 2, D flip-flop 1, D flip-flop 2, and latch unit; wherein, The CLK1 terminal of the pulse counter 1 is connected to the VOP output terminal of the comparator, the Reset1 terminal of the pulse counter 1 is connected to the reset signal RD of the calibration logic, and the OUT1 terminal of the pulse counter 1 is connected to the CLK2 terminal of the D flip-flop 1, and outputs the control signal OPS. The D1 input of the D flip-flop 1 is connected to VDD, the Reset2 input of the D flip-flop 1 is connected to the reset signal RD of the calibration logic, and the QB1 output of the D flip-flop 1 is connected to the AP input of the latch unit. The CLK3 terminal of the pulse counter 2 is connected to the VON output terminal of the comparator, the Reset3 terminal of the pulse counter 2 is connected to the reset signal RD of the calibration logic, and the OUT2 terminal of the pulse counter 2 is connected to the CLK4 terminal of the D flip-flop 2, and outputs the control signal ONS. The D2 input terminal of the D flip-flop 2 is connected to the VDD, the Reset4 terminal of the D flip-flop 2 is connected to the reset signal RD of the calibration logic, and the QB2 output terminal of the D flip-flop 2 is connected to the AN input terminal of the latch unit. The RD1 terminal of the latch unit is connected to the reset signal RD of the calibration logic. The APL output terminal of the latch unit outputs the offset polarity selection signal APSEL, and the ANL output terminal of the latch unit outputs the offset polarity selection signal ANSEL.

3. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 2, characterized in that, The pulse counter 1 and pulse counter 2 have the same structure, and the circuit structure of either one includes: D flip-flop 3, D flip-flop 4, first AND gate, second AND gate, first OR gate, and third AND gate; among which... The CLK5 terminal of the D flip-flop 3 is connected to the first input terminal of the third AND gate, serving as the CLK terminal of the pulse flip-flop. The D3 input terminal of the D flip-flop 3 is connected to the first input terminal of the first AND gate. The Reset5 terminal of the D flip-flop 3 is connected to the Reset6 terminal of the D flip-flop 4, serving as the Reset terminal of the pulse flip-flop, and is used to connect the reset signal RD of the calibration logic. The Q3 output terminal of the D flip-flop 3 is connected to the second input terminal of the second AND gate. The QB3 output terminal of the D flip-flop 3 is connected to the D3 input terminal of the D flip-flop 3. The CLK6 terminal of the D flip-flop 4 is connected to the first input terminal of the third AND gate, the D4 input terminal of the D flip-flop 4 is connected to the output terminal of the first OR gate, the Q4 output terminal of the D flip-flop 4 is connected to the second input terminal of the first AND gate, and the QB4 output terminal of the D flip-flop 4 is connected to the first input terminal of the second AND gate. The output of the first AND gate is connected to the first input of the first OR gate, and the output of the second AND gate is connected to the second input of the first OR gate. The second input of the third AND gate is connected to the Q4 output of the D flip-flop 4, the third input of the third AND gate is connected to the second input of the second AND gate, and the output of the third AND gate serves as the OUT terminal of the pulse counter.

4. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 3, characterized in that, The circuit structure of the latch unit includes: MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8; a first NOT gate and a second NOT gate; among which, The source of the MOS transistor M1 is grounded, the gate of the MOS transistor M1 is connected to the output of the first NOT gate, and the drain of the MOS transistor M1 is connected to the drain of the MOS transistor M5, serving as the APL output of the latch unit. The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the drain of the MOS transistor M6, serving as the ANL output terminal of the latch unit, and the drain of the MOS transistor M2 is connected to the drain of the MOS transistor M5, serving as the APL output terminal of the latch unit. The source of the MOS transistor M3 is grounded, the gate of the MOS transistor M3 is connected to the drain of the MOS transistor M5, and the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M6. The source of the MOS transistor M4 is grounded, the gate of the MOS transistor M4 is connected to the output terminal of the second NOT gate, and the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M6. The source of the MOS transistor M5 is connected to the drain of the MOS transistor M7, and the gate of the MOS transistor M5 serves as the AP input terminal of the latch unit. The source of the MOS transistor M6 is connected to the drain of the MOS transistor M8, and the gate of the MOS transistor M6 serves as the AN input terminal of the latch unit. The source of the MOS transistor M7 is connected to VDD, and the gate of the MOS transistor M7 is connected to the gate of the MOS transistor M2. The source of the MOS transistor M8 is connected to VDD, and the gate of the MOS transistor M8 is connected to the drain of the MOS transistor M2. The input terminals of the first NOT gate and the second NOT gate are connected to the RD1 terminal of the latch unit and the reset signal RD of the calibration logic.

5. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 4, characterized in that, The circuit structure of the compensation logic includes: The system includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a D flip-flop 5, a D flip-flop 6, a second OR gate, a 6-bit counter, and a 6-to-64 decoder; among which, The first terminal of the first switch S1 is connected to the control signal ONS, and the second terminal of the first switch S1 is connected to the CLK7 terminal of the D flip-flop 5. The first terminal of the second switch S2 is connected to the control signal OPS, and the second terminal of the second switch S2 is connected to the CLK7 terminal of the D flip-flop 5. The D5 input of the D flip-flop 5 is connected to VDD, the Reset7 input of the D flip-flop 5 is connected to the reset signal RD of the calibration logic, and the Q5 output of the D flip-flop 5 is connected to the first input of the second OR gate. The D6 input of the D flip-flop 6 is connected to VDD, the CLK8 input of the D flip-flop 6 is connected to the Z output of the 6-bit counter, the Reset8 input of the D flip-flop 6 is connected to the reset signal RD of the calibration logic, and the Q6 output of the D flip-flop 6 is connected to the second input of the second OR gate. The first terminal of the third switch S3 is connected to the control signal OPS, and the second terminal of the third switch S3 is connected to the CLK9 terminal of the 6-bit counter. The first terminal of the fourth switch S4 is connected to the control signal ONS, and the second terminal of the fourth switch S4 is connected to the CLK9 terminal of the 6-bit counter. The H input terminal of the 6-bit counter is connected to the output terminal of the second OR gate, the Reset9 terminal of the 6-bit counter is connected to the reset signal RD of the calibration logic, and the Q0~Q5 output terminals of the 6-bit counter are respectively connected to the H0~H5 input terminals of the 6-64 decoder. The S0~S63 output terminals of the 6-64 decoder are connected to the input terminals of the latch array.

6. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 5, characterized in that, The circuit structure of the 6-bit counter includes: 3-bit counter 1, 3-bit counter 2, a third NOT gate, and a fourth AND gate; among which, The H1 terminal of the 3-bit counter 1 serves as the H terminal of the 6-bit counter; the Reset10 terminal of the 3-bit counter 1 and the Reset11 terminal of the 3-bit counter 2 serve as the Reset9 terminal of the 6-bit counter; the CLK10 terminal of the 3-bit counter 1 and the CLK11 terminal of the 3-bit counter 2 serve as the CLK9 terminal of the 6-bit counter; the Qa output terminal of the 3-bit counter 1 is connected to the first input terminal of the fourth AND gate and serves as the Q0 output terminal of the 6-bit counter; the Qb output terminal of the 3-bit counter 1 is connected to the second input terminal of the fourth AND gate and serves as the Q1 output terminal of the 6-bit counter; the Qc output terminal of the 3-bit counter 1 is connected to the third input terminal of the fourth AND gate and serves as the Q2 output terminal of the 6-bit counter; and the Z1 output terminal of the 3-bit counter 1 is connected to the input terminal of the third NOT gate. The output of the third NOT gate is connected to the H2 terminal of the 3-bit counter 2; The Qd output of the 3-bit counter 2 serves as the Q3 output of the 6-bit counter, the Qe output of the 3-bit counter 2 serves as the Q4 output of the 6-bit counter, the Qf output of the 3-bit counter 1 serves as the Q5 output of the 6-bit counter, the Z2 output of the 3-bit counter 2 is connected to the fourth input of the fourth AND gate, and the output of the fourth AND gate serves as the Z output of the 6-bit counter.

7. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 5, characterized in that, The circuit structure of the latch array includes: 64 identical latch modules; the input of each latch module is connected to the corresponding outputs S0~S63 of the 6-64 decoder, and the output of each latch module corresponds to the output signals S0L~S63L, wherein, Any one of the 64 identical latch modules includes: Switch 1, switch 2, inverter 1 and inverter 2; The first end of the switch 1 is connected to one of the outputs S0 to S63 of the 6-64 decoder, and the second end of the switch 1 is connected to the input of the inverter 1. The first end of the switch 2 is connected to the second end of the switch 1, and the second end of the switch 2 is connected to the output end of the inverter 2; The output terminal of inverter 1 is connected to the input terminal of inverter 2; The output terminal of the inverter 2 outputs one of the output signals S0L to S63L.

8. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 7, characterized in that, The circuit structure of the configurable resistor string includes: MOSFETs M9 and M10, first resistor, second resistor, third resistor, fourth resistor, switch 3, switch 4, fourth NOT gate, and resistor string; among them, The source of the MOS transistor M9 is grounded, the gate of the MOS transistor M9 is connected to the enable signal SEL, and the drain of the MOS transistor M9 is connected to the first terminal of the first resistor. The second end of the first resistor is connected to the first end of the resistor string; The first end of the second resistor is connected to the drain of the MOSFET M9, and the second end of the second resistor is connected to the first end of the switch 3; The second terminal of the switch 3 is connected to the second terminal of the first resistor; The resistor string consists of 64 resistors connected in series, with voltages V1 to V63 sequentially drawn between adjacent resistors. A voltage VL is drawn from the first end of the resistor string, and a voltage VH is drawn from the second end of the resistor string. The first end of the third resistor is connected to the drain of the MOS transistor M10, and the second end of the third resistor is connected to the second end of the resistor string. The first end of the fourth resistor is connected to the first end of the third resistor; The first end of the switch 4 is connected to the second end of the resistor string, and the second end of the switch 4 is connected to the second end of the fourth resistor; The source of the MOS transistor M10 is connected to VDD, and the gate of the MOS transistor M10 is connected to the output of the fourth NOT gate. The input terminal of the fourth NOT gate is connected to the enable signal SEL.

9. A dual-mode offset calibration circuit for a comparator applied to a high-speed time-domain interleaved ADC according to claim 8, characterized in that, The circuit structure of the switch array includes: 64 switches, switch 5, switch 6, switch 7 and switch 8; among them, The first terminals of the 64 switches are respectively connected to voltages VL~V63, and the second terminals of the 64 switches are connected to the first node. The first terminal of the switch 5 is connected to the voltage VCAL of the first node, and the second terminal of the switch 5 is connected to the second terminal of the switch 6 at the second node. The first terminal of the switch 6 is connected to the voltage VL drawn from the first terminal of the resistor string; The first terminal of the switch 7 is connected to the voltage VCAL of the first node, and the second terminal of the switch 7 is connected to the second terminal of the switch 8 to the third node; The first terminal of the switch 8 is connected to the voltage VL drawn from the first terminal of the resistor string; The voltage of the second node is used as the calibration terminal voltage VIPC; The voltage of the third node is used as the calibration terminal voltage VINC.

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