Chip, preparation method thereof and electronic equipment

Abstract

The invention provides a chip, a preparation method thereof and electronic equipment. The chip comprises a base material layer, a piezoelectric layer, an electrode layer and a release barrier layer. The substrate layer and the piezoelectric layer are laminated and bonded, and an integrated circuit processing factory performs pre-embedded groove processing, release barrier layer and electrode layer manufacturing, and concave cavity manufacturing of the substrate layer. The release barrier layer is made of a polymer, the liquid polymer can be easily filled in the pre-buried groove of the chip, the process is simple, and the filling effect is good. The hardness of the cured polymer is small, the stress strain of the substrate layer is small when the filling side is flattened, and the damage is very small. A cavity is formed in the base material layer through the reaction of the released fluid and the base material layer, so that the resonance region arranged on the piezoelectric layer and the bottom surface of the cavity are arranged at an interval. The lateral dimension of the cavity is defined by the release barrier such that the lateral dimension of the cavity can be made small. The substrate layer, the piezoelectric layer, the electrode layer and the release barrier layer in the chip are combined to serve as an air gap type acoustic resonator, and the chip is low in preparation difficulty, low in cost and high in yield.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a chip, a preparation method thereof, and an electronic device. Background Art

[0002] In related technology, the acoustic wave resonators in chips include bulk acoustic wave (BAW) devices and plate wave devices. Structurally, both types of devices can be divided into three categories: back-etched type, air-gap type, and solid-state assembly type. These three structures can confine acoustic waves in the piezoelectric layer as much as possible to improve the quality factor (Q) of the device. The air-gap type structure is superior to the back-etched type structure in mechanical strength and superior to the solid-state assembly type structure in acoustic wave confinement ability. Therefore, the air-gap type structure is widely used in the industry. The air-gap type acoustic wave resonator has a concave cavity, the resonant region of the piezoelectric layer is arranged corresponding to the concave cavity, and an electrode layer is arranged on the resonant region.

[0003] When manufacturing a chip with an air-gap type acoustic wave resonator, a release barrier layer or a release sacrificial layer can be pre-embedded in the substrate or the dielectric layer to define the lateral dimension of the concave cavity. However, in related technology, the preparation of chips with air-gap type acoustic wave resonators is difficult and costly. Summary of the Invention

[0004] The embodiments of the present application provide a chip, a preparation method thereof, and an electronic device, which solve the problems of high preparation difficulty and high cost of chips with air-gap type acoustic wave resonators in related technology.

[0005] The embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, the embodiments of the present application provide a chip, including: a substrate layer, a piezoelectric layer, an electrode layer, and a release barrier layer. The piezoelectric layer and the substrate layer are laminated and bonded, and the piezoelectric layer has a resonant region. The chip has a pre-embedded groove that communicates with the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer. The pre-embedded groove is arranged around the resonant region, and the pre-embedded groove forms an opening on the piezoelectric layer. The electrode layer is arranged on the resonant region. The substrate layer has a concave cavity arranged opposite to the resonant region. The resonant region and the bottom surface of the concave cavity are spaced apart in the thickness direction of the substrate layer, and the pre-embedded groove is connected to the concave cavity. The material of the release barrier layer is a polymer, and the release barrier layer is arranged in the pre-embedded groove for defining the lateral dimension of the concave cavity.

[0007] In the chip provided in the embodiment of the present application, the wafer factory stacks and bonds the substrate layer and the piezoelectric layer. After the integrated circuit processing factory gets the wafer with the piezoelectric layer and the substrate layer bonded, it performs embedded groove processing, releases the barrier layer and the electrode layer, and makes the cavity of the substrate layer. There is no need to move the wafer back and forth between the integrated circuit processing factory and the wafer factory as in the related art to reduce wafer damage. If the size or position of the electrode layer is to be changed, the position of the embedded groove of the release barrier layer can be changed directly on the wafer, without the need to spend more than 6 weeks to re-customize the piezoelectric layer in the wafer factory as in the related art. The material of the release barrier layer is a polymer, and the liquid polymer is easy to fill in the embedded groove of the chip, with a simple process and a good filling effect. After the polymer is cured, the hardness is small, the stress and strain of the substrate layer is small when the filling side is flattened, and the damage to the substrate layer is small. There is no need to pre-customize a large thickness substrate as in the related art and grind and thin the bottom side of the substrate after filling the embedded groove. During the front-to-back processing, the polymer can release the mechanical stress of the electrode layer above the cavity, reducing the difficulty of processing. By releasing the fluid and reacting with the substrate layer, a cavity is formed in the substrate layer, so that the resonance area of ​​the piezoelectric layer provided on the substrate layer and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer. The release barrier layer and the release fluid hardly react, and the lateral size of the cavity is limited by the release barrier layer, so that the lateral size of the cavity can be made smaller, and more acoustic resonators can be arranged on the wafer, thereby improving the mechanical strength and power tolerance of the device. The substrate layer, piezoelectric layer, electrode layer and release barrier layer in the chip can be combined as an air gap type acoustic resonator. The preparation difficulty of the chip is low, the cost is low, and the yield is high.

[0008] In an optional implementation, the substrate layer, piezoelectric layer, electrode layer and release barrier layer can be combined to act as an air gap type acoustic wave resonator. There can be one or more acoustic wave resonators on a chip.

[0009] In an optional implementation, the chip has multiple acoustic wave resonators, and the multiple acoustic wave resonators can be cascaded together in a series-parallel manner to form a filter.

[0010] In an optional implementation, multiple acoustic wave resonators can share a substrate layer and a piezoelectric layer, and each acoustic wave resonator has an independent electrode layer and a release barrier layer. A partition wall is formed between the concave cavities of two adjacent acoustic wave resonators, that is, a part of the substrate layer.

[0011] In an optional implementation, the piezoelectric layer has a resonant region and a non-resonant region. An electrode layer is provided on the resonant region, and a high-frequency electrical signal is applied to the electrode layer to excite a high-frequency acoustic wave signal on the resonant region. The non-resonant region is the region on the piezoelectric layer other than the resonant region. The non-resonant region and the region on the substrate layer other than the concave cavity are provided correspondingly.

[0012] In an alternative implementation, the electrode layer adopts a structure with a predetermined shape, and the piezoelectric layer and the electrode layer adopt a predetermined bonding method, which can form different types of acoustic wave resonators, such as thin film bulk acoustic wave resonators, Lamb wave resonators / horizontally excited bulk acoustic wave resonators.

[0013] In an alternative implementation, the bonded piezoelectric layer can be a single crystal structure, which has a better orientation and better performance.

[0014] In an alternative implementation, a plurality of release holes are provided on the resonant region, and the plurality of release holes communicate with the cavity. After the release holes are made, the release fluid is allowed to pass through the release holes and react with the substrate layer, thereby forming a depression in the substrate layer. The release holes can be arranged along the edge of the resonant region.

[0015] In an alternative implementation, the resonant region is generally rectangular, and the plurality of release holes are generally arranged in a rectangular shape. By introducing a release fluid that can react with the substrate layer into all the release holes, a cavity that generally looks like a rounded rectangle in a top view can be formed on the substrate layer.

[0016] In an alternative implementation, a conductive portion is provided on the piezoelectric layer, and the conductive portion is connected and conducted with the electrode layer, so that the electrode layers of a plurality of acoustic wave resonators are cascaded together in a series-parallel manner to form a filter circuit.

[0017] In an alternative implementation, a horizontally excited bulk acoustic wave resonator is adopted. The electrode layer includes interdigital transducers, and the interdigital transducers are provided on the side of the resonant region facing away from the substrate layer. The interdigital transducers are provided on one side of the piezoelectric layer, and the resonant region of the piezoelectric layer is located above the cavity, which can form an air-gap type horizontally excited bulk acoustic wave resonator. By applying a high-frequency electrical signal between the first bus bar and the second bus bar, Lamb waves can be excited on the resonant region of the piezoelectric layer.

[0018] In an alternative implementation, the interdigital transducers can include a first bus bar, a second bus bar, a plurality of first electrode fingers, and a plurality of second electrode fingers. The first bus bar and the second bus bar are arranged in parallel at intervals. The plurality of first electrode fingers are arranged in parallel at intervals and connected to the same side of the first bus bar. The plurality of second electrode fingers are arranged in parallel at intervals and connected to the same side of the second bus bar. The plurality of first electrode fingers and the plurality of second electrode fingers are located between the first bus bar and the second bus bar, and the plurality of first electrode fingers and the plurality of second electrode fingers are arranged alternately at intervals. The first bus bar and the second bus bar can be conductively connected to different conductive portions on the chip to achieve the transmission of electrical signals.

[0019] In an alternative implementation, the resonant region of the piezoelectric layer can be generally rectangular, the first bus bar and the second bus bar can extend along the length direction of the resonant region, and the plurality of first electrode fingers and the plurality of second electrode fingers can extend along the width direction of the resonant region, so that a large number of first electrode fingers and second electrode fingers can be arranged alternately at intervals on the resonant region.

[0020] In an alternative implementation, a lateral excitation bulk acoustic wave resonator is adopted. The electrode layer includes an interdigital transducer which is disposed on one side of the resonance region facing the substrate layer. The interdigital transducer is disposed on one side of the piezoelectric layer, and the resonance region of the piezoelectric layer is located above the cavity, so that an air-gap type lateral excitation bulk acoustic wave resonator can be formed. By applying a high-frequency electrical signal between the first bus bar and the second bus bar, Lamb waves can be excited on the resonance region of the piezoelectric layer.

[0021] In an alternative implementation, a thin film bulk acoustic wave resonator is adopted. The electrode layer includes a first electrode plate and a second electrode plate. The first electrode plate is disposed on one side of the resonance region facing away from the substrate layer, and the second electrode plate is disposed on one side of the resonance region facing the substrate layer. By applying a high-frequency electrical signal between the first electrode plate and the second electrode plate, bulk acoustic waves oscillating and propagating between the first electrode plate and the second electrode plate can be excited on the resonance region of the piezoelectric layer.

[0022] In an alternative implementation, the material of the piezoelectric layer includes one or more of lithium niobate, lithium tantalate, aluminum nitride, zinc oxide, and quartz in each tangential direction.

[0023] In an alternative implementation, the materials of the electrode layer and the conductive part include one or more of aluminum, copper, platinum, molybdenum, tungsten, tantalum, gold, and silver. The electrode layer and the conductive part can be fabricated by physical vapor deposition processes such as vacuum evaporation and sputtering processes.

[0024] In an alternative implementation, the substrate layer includes a stacked substrate and a dielectric layer. The dielectric layer is located between the substrate and the piezoelectric layer. The piezoelectric layer and the dielectric layer are laminated and bonded. The pre-buried groove communicates with the piezoelectric layer, the dielectric layer, and the substrate along the thickness direction of the substrate layer, and the cavity is formed on the substrate. By providing the dielectric layer on the substrate, the connection effect is good when the piezoelectric layer and the dielectric layer are laminated and bonded. The pre-buried groove communicates with the piezoelectric layer, the dielectric layer, and the substrate, and a release barrier layer is provided in the pre-buried groove.

[0025] In an alternative implementation, the substrate layer includes a stacked substrate and a dielectric layer. The dielectric layer is located between the substrate and the piezoelectric layer. The piezoelectric layer and the dielectric layer are laminated and bonded. The pre-buried groove communicates with the piezoelectric layer and the dielectric layer along the thickness direction of the substrate layer, and the cavity is formed on the dielectric layer. By providing the dielectric layer on the substrate, the connection effect is good when the piezoelectric layer and the dielectric layer are laminated and bonded. The pre-buried groove communicates with the piezoelectric layer and the dielectric layer, and a release barrier layer is provided in the pre-buried groove.

[0026] In an alternative implementation, the substrate layer includes a substrate, the piezoelectric layer and the substrate are laminated and bonded, the pre-buried groove communicates with the substrate along the thickness direction of the substrate layer, and the cavity is formed on the substrate. The pre-buried groove is formed on the substrate, and a release barrier layer is provided in the pre-buried groove.

[0027] In an alternative implementation, the material of the substrate includes one or more of silicon, silicon carbide, diamond, sapphire, aluminum nitride, ceramic, lithium tantalate, and lithium niobate.

[0028] In an alternative implementation, the material of the dielectric layer includes one or more of silicon dioxide, silicon nitride, silicon oxynitride, or aluminum oxide. By providing a dielectric layer on the substrate, a good connection effect is achieved when the piezoelectric layer and the dielectric layer are stacked and bonded.

[0029] In an alternative implementation, the cross-sectional shapes of the pre-embedded groove and the release barrier layer in a top view are the same, and the cross-sections of the pre-embedded groove and the release barrier layer can be arranged in a circular, elliptical, or polygonal shape. The polygon can be a triangle, a quadrilateral, or a shape with more sides.

[0030] In an alternative implementation, the electrode layer is arranged substantially in a rectangle, the release barrier layer is arranged substantially in a rectangular ring, and the cross-section of the cavity defined by the release barrier layer in a top view is substantially rectangular.

[0031] In an alternative implementation, the pre-embedded groove includes a plurality of sub-grooves distributed around the resonance region and connected end to end in sequence; the release barrier layer includes a plurality of lateral blocking portions, and the plurality of lateral blocking portions are respectively filled in the plurality of sub-grooves one by one. Lateral blocking portions are respectively formed in each sub-groove, and the plurality of lateral blocking portions are connected to form an annular release barrier layer.

[0032] In an alternative implementation, the pre-embedded groove includes a plurality of sub-grooves distributed around the resonance region and arranged at intervals in sequence; the release barrier layer includes a plurality of lateral blocking portions, and the plurality of lateral blocking portions are respectively filled in the plurality of sub-grooves one by one. Lateral blocking portions are respectively formed in each sub-groove, and the plurality of lateral blocking portions are distributed at intervals, unconnected, and substantially in an annular shape.

[0033] In an alternative implementation, the plurality of lateral blocking portions in the release barrier layer can be arranged in a circular, elliptical, or polygonal shape. The polygon can be a triangle, a quadrilateral, or a shape with more sides.

[0034] In an alternative implementation, the electrode layer is arranged substantially in a rectangle, the plurality of lateral blocking portions in the release barrier layer are arranged substantially in a rectangular ring, and the cross-section of the cavity defined by the release barrier layer in a top view is substantially rectangular.

[0035] In an alternative implementation, the longitudinal depth range of the pre-embedded groove or the release barrier layer is 1 micrometer (μm) to 50 micrometers. The liquid polymer is made to flow into the pre-embedded groove.

[0036] In an alternative implementation, the width of the release barrier layer in a top view is greater than or equal to 10 micrometers. The liquid polymer can easily flow into and fully fill the pre-embedded groove.

[0037] In an alternative implementation, a plurality of lateral blocking portions in the release barrier layer are arranged substantially in a rectangular ring shape.

[0038] In an alternative implementation, the polymer may include one or more of polyimide, polydimethylsiloxane, polyvinylidene fluoride, benzocyclobutene, polyethylene terephthalate, and photoresist. The photoresist may be polymethyl methacrylate or the like.

[0039] In an alternative implementation, the release barrier layer can be formed by spin-coating a polymer to fill the pre-embedded groove, curing the polymer, and planarizing the filled side of the polymer. The filled side of the polymer refers to the side of the wafer where the polymer is filled during the manufacturing process.

[0040] In an alternative implementation, the Young's modulus of the polymer after curing is less than 10 gigapascals (GPa). The Young's modulus of the polymer after curing is relatively small, and the hardness is relatively low. When planarizing the side filled with the polymer, the processing force is transmitted to the substrate layer, causing relatively small stress in the substrate layer, and little damage to the substrate layer. The polymer can release the mechanical stress of the electrode layer above the cavity, reducing the processing difficulty.

[0041] In an alternative implementation, the Young's modulus of the polymer after curing is less than 5 gigapascals. The smaller the Young's modulus of the polymer after curing, the lower the hardness, and the less damage to the substrate layer when planarizing the side filled with the polymer.

[0042] In an alternative implementation, the chip has one or more micro-grooves that communicate the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more micro-grooves communicate with the pre-embedded groove. The micro-grooves can form openings on the piezoelectric layer.

[0043] The liquid polymer can enter the pre-embedded groove but is difficult to enter the micro-grooves. When heating and curing the polymer, there will be bubbles in the liquid polymer at the pre-embedded groove, and the bubbles can overflow from the unfilled micro-grooves beside, making the polymer fill the pre-embedded groove more fully and tightly. The micro-grooves can provide a certain deformation space for the thermally expanded release barrier layer.

[0044] In an alternative implementation, the pre-embedded groove may include a plurality of sub-grooves, and the number of micro-grooves corresponding to each sub-groove can be one or more.

[0045] In an alternative implementation, the plurality of micro-grooves are arranged at intervals along the edge of the resonant region.

[0046] In an alternative implementation, the pre-embedded groove includes a plurality of sub-grooves distributed around the resonant region and connected end to end in sequence, and each sub-groove can communicate with the micro-grooves.

[0047] In an alternative implementation, the embedded slot includes a plurality of sub-slots distributed around the resonant region and arranged at intervals in sequence, and each sub-slot can also communicate with the micro-slot.

[0048] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view can be circular, elliptical, polygonal or X-shaped. The polygon can be triangular, quadrilateral or a shape with more sides. One side or a part of the polygonal cross-section of the micro-slot is connected to the embedded slot, making it difficult for the liquid polymer to enter through the opening of the micro-slot and also difficult to enter the micro-slot from the embedded slot.

[0049] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is circular, and a part of the circular cross-section of the micro-slot is connected to the long side of the sub-slot in the embedded slot.

[0050] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is triangular, and one side of the triangular cross-section of the micro-slot is connected to the long side of the sub-slot in the embedded slot. In addition, one end of the triangular cross-section of the micro-slot can also be connected to the long side of the sub-slot.

[0051] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is rectangular, and one short side of the rectangular cross-section of the micro-slot is connected to the long side of the sub-slot in the embedded slot.

[0052] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is X-shaped, and one end of the X-shaped cross-section of the micro-slot is connected to the long side of the sub-slot in the embedded slot.

[0053] In an alternative implementation, the length of the micro-slot in a top view is less than or equal to 10 micrometers (um). Or, the cross-sectional area of the micro-slot in a top view is less than or equal to 100 square micrometers (um 2 ). This makes it difficult for the liquid polymer to enter the micro-slot through the opening.

[0054] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is circular, and the length of the micro-slot in a top view is the diameter of the circular cross-section.

[0055] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is triangular, and the length of the micro-slot in a top view is the maximum side length of the triangle.

[0056] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is rectangular, and the length of the micro-slot in a top view is the length of the long side of the rectangular cross-section.

[0057] In an alternative implementation, the cross-sectional shape of the micro-slot in a top view is X-shaped, and the length of the micro-slot in a top view is the arm length of the X-shaped cross-section.

[0058] In an alternative implementation, a communication port is formed between the microgroove and the pre-embedded groove, and the length of the communication port is less than or equal to 10 micrometers (um); or, a communication port is formed between the microgroove and the pre-embedded groove, and the cross-sectional area of the communication port is less than or equal to 100 square micrometers (um 2 ). The communication port has a rectangular cross-section, and the length of the communication port is the long-side dimension of the communication port on the rectangular cross-section of the communication port. This makes it difficult for the liquid polymer to enter the microgroove from the pre-embedded groove through the communication port.

[0059] In an alternative implementation, the substrate layer, the piezoelectric layer, the electrode layer, and the release barrier layer can be combined as an air-gap type acoustic wave resonator, and multiple acoustic wave resonators are cascaded to form a filter.

[0060] In an alternative implementation, the filter can be a separate component, or the filter can be integrated with components such as a power amplifier into a module. The filter is coupled to the power amplifier for signal processing and transmission.

[0061] In an alternative implementation, the filter includes multiple cascaded resonators. The multiple resonators can have different resonant frequencies and are cascaded together in a series-parallel manner. The filter has a signal input terminal Vi, a signal output terminal Vo, and a ground terminal GND.

[0062] In a second aspect, an embodiment of the present application provides an electronic device, including a printed circuit board and the above-mentioned chip, and the chip is disposed on the printed circuit board.

[0063] In an alternative implementation, the electronic device is a mobile phone. The electronic device includes a cover plate, a display screen, a middle frame, and a rear shell. The rear shell and the display screen are respectively located on opposite sides of the middle frame. The middle frame and the display screen can be disposed inside the rear shell, the cover plate is disposed on the side of the display screen away from the middle frame, and the display side of the display screen faces the cover plate.

[0064] In an alternative implementation, the display screen can be a liquid crystal display screen. The liquid crystal display screen includes a liquid crystal display panel and a backlight module. The liquid crystal display panel is disposed between the cover plate and the backlight module, and the backlight module is used to provide light source for the liquid crystal display panel.

[0065] In an alternative implementation, the display screen can be an organic light-emitting diode display screen. The self-emitting display screen does not need to be provided with a backlight module.

[0066] In an alternative implementation, the middle frame can include a carrier plate and a frame disposed around the carrier plate.

[0067] In an alternative implementation, the electronic device may further include a system-on-chip, a radio frequency chip, etc. disposed on a printed circuit board. The printed circuit board is used to carry the system-on-chip, the radio frequency chip, etc. and is electrically connected to the system-on-chip, the radio frequency chip, etc. The radio frequency chip may include parts such as a filter and a processor. The processor is used to process various signals.

[0068] In a third aspect, an embodiment of the present application provides a method for manufacturing a chip, including:

[0069] Using a wafer with a piezoelectric layer and a substrate layer laminated and bonded;

[0070] Etching a pre-embedded groove on the wafer. The pre-embedded groove communicates with the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer. The pre-embedded groove is arranged around the resonant region of the piezoelectric layer, and an opening is formed on the piezoelectric layer. When etching the pre-embedded groove on the wafer, a photoresist or other material can be used as a mask for etching the pattern of the pre-embedded groove;

[0071] Spin-coating a polymer on the piezoelectric layer to fill the pre-embedded groove; during the spin-coating process, the liquid polymer will enter the pre-embedded groove through the opening of the pre-embedded groove to form a good filling;

[0072] Curing the polymer and planarizing the filling side of the polymer to form a release barrier layer in the pre-embedded groove; the filling side of the polymer refers to the side of the wafer filled with the polymer during the manufacturing process;

[0073] Fabricating an electrode layer on the resonant region;

[0074] Fabricating a release hole penetrating the piezoelectric layer; when fabricating the release hole, a photoresist or other material can be used as a mask for fabricating the pattern of the release hole;

[0075] Allowing a release fluid to pass through the release hole and react with the substrate layer by etching to form a cavity on the substrate layer, so that the resonant region and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer, and the lateral dimension of the cavity is defined by the release barrier layer.

[0076] The preparation method of the chip provided in the embodiment of the present application is that the wafer factory stacks and bonds the substrate layer and the piezoelectric layer, and after the integrated circuit processing factory gets the wafer with the piezoelectric layer and the substrate layer bonded, the pre-buried groove is processed on the wafer, the production of the release barrier layer and the electrode layer, and the concave cavity of the substrate layer is produced. When forming the release barrier layer, it is not restricted by the bonding of the piezoelectric layer and the substrate layer. There is no need to move the wafer back and forth between the integrated circuit processing factory and the wafer factory as in the related art to reduce wafer damage. If the size or position of the electrode layer is to be changed, the position of the pre-buried groove of the release barrier layer can be changed directly on the wafer, and there is no need to spend more than 6 weeks to re-customize the piezoelectric layer in the wafer factory as in the related art. The material of the release barrier layer is a polymer, and the liquid polymer is easy to fill in the pre-buried groove of the chip, the process is simple, and the filling effect is good. The hardness of the polymer is small after curing, the stress and strain of the substrate layer is small when the filling side is flattened, and the damage to the substrate layer is very small. There is no need to pre-customize a large thickness substrate as in the related art and grind and thin the bottom side of the substrate after filling the pre-buried groove. During the front-end and back-end processing, the polymer can release the mechanical stress of the electrode layer above the cavity, reducing the difficulty of processing. By releasing the fluid and reacting with the substrate layer, a cavity is formed in the substrate layer, so that the resonance area of ​​the piezoelectric layer provided on the substrate layer and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer. The release barrier layer and the release fluid hardly react, and the lateral size of the cavity is limited by the release barrier layer, so that the lateral size of the cavity can be made smaller, and more acoustic resonators can be arranged on the wafer, thereby improving the mechanical strength and power tolerance of the device. The preparation process of the chip with a release barrier layer is optimized, the processing process is more reasonable, the process feasibility is improved, the chip preparation difficulty is small, the cost is low, and the yield is high.

[0077] In an optional implementation, etching a pre-buried groove on a wafer specifically includes: applying photoresist on the surface of the piezoelectric layer; matching the pattern of the photoresist plate with the shape of the pre-buried groove, placing the wafer on a photolithography machine and aligning the wafer and the photoresist plate before exposure; after development, removing part of the photoresist corresponding to the pre-buried groove area, transferring the pattern of the photoresist plate to the photoresist; using the photoresist as a mask for etching the pre-buried groove pattern, and after etching, transferring the pattern of the photoresist to the wafer, forming the pre-buried groove on the wafer. Etching can be plasma reactive etching.

[0078] In an optional implementation, etching a pre-buried groove on a wafer specifically includes: etching a pre-buried groove and one or more micro grooves on the wafer, wherein the one or more micro grooves connect the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more micro grooves are connected to the pre-buried groove. The micro groove may form an opening on the piezoelectric layer. Photoresist or other materials may be used as a mask for etching the pre-buried groove pattern and the micro groove pattern, and the interconnected pre-buried groove and micro groove are etched on the wafer.

[0079] In an alternative implementation, when fabricating the microgrooves, a pre-embedded groove and microgrooves are etched and formed on the wafer, which specifically includes: coating photoresist on the surface of the piezoelectric layer; the pattern of the photomask is adapted to the shape of the pre-embedded groove and the shape of the microgrooves. The wafer is placed on the lithography machine and aligned with the photomask, and then exposed; after development, part of the photoresist corresponding to the areas of the pre-embedded groove and the microgrooves is removed, so that the pattern of the photomask is transferred to the photoresist; the photoresist is used as a mask for etching the patterns of the pre-embedded groove and the microgrooves. After etching, the pattern of the photoresist is transferred to the wafer, and a pre-embedded groove and microgrooves are formed on the wafer. The etching can be plasma reactive etching.

[0080] In an alternative implementation, one or more microgrooves are provided on one side of the pre-embedded groove facing the resonant region. Alternatively, one or more microgrooves are provided on one side of the pre-embedded groove facing away from the resonant region. Alternatively, one or more microgrooves are provided on one side of the pre-embedded groove facing the resonant region, and one or more microgrooves are provided on one side of the pre-embedded groove facing away from the resonant region. The microgrooves can be provided on one or both sides of the pre-embedded groove. When filling with the liquid polymer, it is easy to enter the pre-embedded groove, but difficult to enter the microgrooves, and the inside of the microgrooves may be empty.

[0081] In an alternative implementation, curing the polymer and planarizing the filling side of the polymer specifically includes: pre-baking the wafer filled with the polymer; lithography and development to remove the polymer outside the extended space of the pre-embedded groove; dry stripping to remove the polymer outside the pre-embedded groove; planarizing the filling side of the polymer; completely baking the wafer to cure the polymer.

[0082] In an alternative implementation, curing the polymer and planarizing the filling side of the polymer specifically includes: completely baking the wafer filled with the polymer to cure the polymer; planarizing the filling side of the polymer.

[0083] In an alternative implementation, planarizing the filling side of the polymer specifically includes one or more of lithography and development, dry etching, and chemical mechanical polishing. Through the above methods, the filling side of the polymer can be planarized to form a flat surface on the piezoelectric layer, preparing for the subsequent formation of the electrode layer on the piezoelectric layer.

[0084] In an alternative implementation, an electrode layer is fabricated on the resonant region of the piezoelectric layer, and a conductive part is fabricated on the non-resonant region of the piezoelectric layer. The conductive part is connected and conducted with the electrode layer, so that the electrode layers of multiple acoustic wave resonators are cascaded together in series-parallel to form a filter circuit. Description of the Drawings

[0085] Figure 1 In (a) and (b) are schematic structural diagrams of chips in the related art;

[0086] Figure 2 In (a) to (h) are schematic diagrams of the preparation process of chips in the related art;

[0087] Figure 3 Among (a) to (h) are schematic diagrams of the manufacturing process of a chip of another related art;

[0088] Figure 4 Among (a) to (h) are schematic diagrams of the manufacturing process of a chip of another related art;

[0089] Figure 5 is the front view of the chip provided by an embodiment of the present application;

[0090] Figure 6 is Figure 5 a partial cross-sectional view of the chip along line A-A;

[0091] Figure 7 Among (a) to (h) are Figure 6 schematic diagrams of the manufacturing process of the chip;

[0092] Figure 8 is the structural schematic diagram of the chip provided by another embodiment of the present application;

[0093] Figure 9 is the structural schematic diagram of the chip provided by another embodiment of the present application;

[0094] Figure 10 is the structural schematic diagram of the chip provided by another embodiment of the present application;

[0095] Figure 11 is the structural schematic diagram of the chip provided by another embodiment of the present application;

[0096] Figure 12 is the front view of the chip provided by another embodiment of the present application;

[0097] Figure 13 is the front view of the chip provided by another embodiment of the present application;

[0098] Figure 14 is Figure 13 a partial cross-sectional view of the chip along line B-B;

[0099] Figure 15 Among (a) to (h) are Figure 14 schematic diagrams of the manufacturing process of the chip;

[0100] Figure 16 Among (a) to (d) are respectively the structural schematic diagrams of the embedded groove and the micro-groove provided by different embodiments of the present application;

[0101] Figure 17 is the circuit schematic diagram of the filter provided by an embodiment of the present application;

[0102] Figure 18Schematic structural diagram of the electronic device provided by the embodiment of the present application;

[0103] Figure 19 Flowchart of the preparation method of the chip provided by the embodiment of the present application;

[0104] Figure 20 Schematic diagram of the preparation process of the chip provided by the embodiment of the present application for curing the polymer and planarizing the filling side;

[0105] Figure 21 Flowchart of the partial preparation method of the chip provided by the embodiment of the present application;

[0106] Figure 22 Schematic diagram of the preparation process of the chip provided by another embodiment of the present application for curing the polymer and planarizing the filling side;

[0107] Figure 23 Flowchart of the partial preparation method of the chip provided by the embodiment of the present application.

[0108] Description of reference numerals:

[0109] 1 - Chip; 1a - Resonator; 2 - Substrate; 3 - Dielectric layer; 4 - Piezoelectric layer; 5 - Electrode layer; 6 - Cavity; 7 - Release barrier layer; 8 - Release sacrificial layer; 9 - Embedded groove; 10 - Release hole; 11 - Photoresist;

[0110] 100 - Chip; 100a - Resonator;

[0111] 110 - Substrate layer; 111 - Cavity; 112 - Substrate; 113 - Dielectric layer;

[0112] 120 - Piezoelectric layer; 121 - Resonant region; 122 - Non - resonant region;

[0113] 130 - Electrode layer; 130a - Conductive part; 131 - Interdigital transducer; 1311 - First bus bar; 1312 - Second bus bar; 1313 - First electrode finger; 1314 - Second electrode finger; 132 - First electrode plate; 133 - Second electrode plate;

[0114] 140 - Release barrier layer; 141 - Lateral barrier part; 140a - Polymer; 150 - Embedded groove; 151 - Opening; 152 - Sub - groove; 153 - Extension space; 160 - Release hole; 170 - Micro - groove; 171 - Opening; 172 - Communication port; 180 - Photoresist;

[0115] 200 - Printed circuit board; 300 - Cover plate; 400 - Display screen; 500 - Middle frame; 510 - Carrier plate; 520 - Frame; 600 - Rear shell; 1000 - Electronic device. Detailed implementation manners

[0116] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. Although the description of the present application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to this implementation. On the contrary, the purpose of introducing the embodiments is to cover other alternatives or modifications that may be extended based on the claims of the present application. In order to provide a deep understanding of the present application, many specific details will be included in the following description. The present application can also be implemented without these details. In addition, in order to avoid confusion or obscuring the focus of the present application, some specific details will be omitted in the description. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0117] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0118] It should be understood that in the description of the embodiments of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0119] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0120] In the embodiments of the present application, "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, in this text, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0121] Reference to "one embodiment" or "some embodiments" etc. described in this specification means that in one or more embodiments of the present application, specific features, structures or characteristics described in connection with that embodiment are included. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprise", "include", "have" and their variants all mean "include but not limited to", unless otherwise specifically emphasized in other ways.

[0122] Refer to Figure 1 In (a) and (b) of Figure 2 as shown, the chip 1 with the air-gap type acoustic resonator 1a in the related art mainly includes a substrate 2, a dielectric layer 3, a piezoelectric layer 4 and an electrode layer 5. The substrate 2 has a cavity 6. The piezoelectric layer 4 and the bottom surface of the cavity 6 are spaced apart. The electrode layer 5 is disposed on the piezoelectric layer 4. A release barrier layer 7 (such as Figure 3 as shown) or a release sacrificial layer 8 (such as Figure 1 as shown) can be pre-embedded in the substrate 2 or the dielectric layer 3 to realize the limitation of the lateral dimension of the cavity 6. The lateral dimension of the cavity 6 refers to any dimension in the plane perpendicular to the thickness direction of the substrate 2 (such as the dimension in the left-right direction in

[0123] Refer to Figure 1 In (a) and (b) of

[0124] When manufacturing the air-gap type acoustic resonator 1a, the piezoelectric layer 4 can be epitaxially grown on the substrate 2, and the piezoelectric layer 4 can also be connected to the substrate 2 by a bonding method. Compared with the polycrystalline piezoelectric layer 4 grown epitaxially, the bonded piezoelectric layer 4 is a single-crystal structure, has better orientation and better performance. However, when pre-embedding the release barrier layer 7 or the release sacrificial layer 8 for the bonded piezoelectric layer 4 and the substrate 2, the preparation difficulty is greater and the cost is higher.For the air-gap type acoustic wave resonator 1a with a bonded piezoelectric layer 4, there are multiple manufacturing processes. For example, a release barrier layer 7 or a release sacrificial layer 8 can be pre-embedded first and then the piezoelectric layer 4 can be bonded, or the piezoelectric layer 4 can be bonded first and then the release barrier layer 7 can be pre-embedded. These manufacturing processes will be introduced separately below.

[0125] Refer to Figure 2 , the manufacturing process of pre-embedding the release barrier layer 7 first and then bonding the piezoelectric layer 4: First, as shown in (a) and (b) of Figure 2 , the wafer substrate 2 is etched by an integrated circuit fabrication (fab) to etch a pre-embedded groove 9 corresponding to the release barrier layer 7 on the substrate 2; then, as shown in (c) of Figure 2 , a material that does not react with the release gas (such as silicon dioxide) is used as the material of the release barrier layer 7, and the release barrier layer 7 material is filled into the pre-embedded groove 9, and the filling side is planarized; then, as shown in (d) of Figure 2 , the substrate 2 pre-embedded with the release barrier layer 7 is sent to a wafer factory, and the single-crystal piezoelectric layer 4 and the substrate 2 are bonded by the wafer factory; finally, the wafer after bonding is sent back to the integrated circuit fabrication for device processing; as shown in (e) of Figure 2 , an electrode layer 5 is provided on the piezoelectric layer 4; as shown in (f) of Figure 2 , a photoresist 11 is used as a mask for the non-release hole area; as shown in (g) of Figure 2 , a release hole 10 is etched on the piezoelectric layer 4; as shown in (h) of Figure 2 , the release gas is passed through the release hole 10 to react with the substrate 2, the release of the substrate 2 is completed, and a cavity 6 is formed on the substrate 2, and the lateral dimension of the cavity 6 is defined by the release barrier layer 7.

[0126] Refer to Figure 3 , the manufacturing process of pre-embedding the release sacrificial layer 8 first and then bonding the piezoelectric layer 4: First, as shown in (a) and (b) of Figure 3 , the wafer substrate 2 is etched by an integrated circuit fabrication to etch a pre-embedded groove 9 corresponding to the release sacrificial layer 8 on the substrate 2; then, as shown in (c) of Figure 3 , a material that is easy to react with the release gas is selected as the material of the release sacrificial layer 8, and the release sacrificial layer 8 material is filled into the pre-embedded groove 9, and the filling side is planarized; then, as shown in (d) of Figure 3 , the substrate 2 pre-embedded with the release sacrificial layer 8 is sent to a wafer factory, and the single-crystal piezoelectric layer 4 and the substrate 2 are bonded by the wafer factory; finally, the wafer after bonding is sent back to the integrated circuit fabrication for device processing; as shown in (e) of Figure 3 , an electrode layer 5 is provided on the piezoelectric layer 4; as shown in (f) of Figure 3 , a photoresist 11 is used as a mask for the non-release hole area; as shown in (f) ofFigure 3 As shown in (g) in [reference], release holes 10 are etched in the piezoelectric layer 4; as Figure 3 shown in (h) in [reference], the release gas passes through the release holes 10 to react with the release sacrificial layer 8, completing the release of the release sacrificial layer 8, and a cavity 6 is formed on the substrate 2, and the lateral dimension of the cavity 6 is defined by the release sacrificial layer 8.

[0127] Refer to Figure 4 , the preparation process of first bonding the piezoelectric layer 4 and then embedding the release barrier layer 7: First, as Figure 4 shown in (a) in [reference], the integrated circuit processing factory obtains a wafer from the foundry, and the substrate 2, the dielectric layer 3 and the piezoelectric layer 4 are stacked in sequence, and the piezoelectric layer 4 and the dielectric layer 3 are already bonded; as Figure 4 shown in (b) in [reference], a photoresist 11 or other material is used as an etching mask; as Figure 4 shown in (c) in [reference], embedding grooves 9 and release holes 10 are etched in the piezoelectric layer 4 and the substrate 2; as Figure 4 shown in (d) in [reference], the release holes 10 are covered with the photoresist 11 again; then, as Figure 4 shown in (e) in [reference], a metal or dielectric material is selected as the material of the release barrier layer 7, and the release barrier layer 7 material is filled in the embedding groove 9; as Figure 4 shown in (f) in [reference], the filling side is planarized; then, as Figure 4 shown in (g) in [reference], using an etching or release process, the release gas passes through the release holes 10 to remove a predetermined area of the dielectric layer 3, and a cavity 6 is formed on the dielectric layer 3, and the lateral dimension of the cavity 6 is defined by the release barrier layer 7; finally, as Figure 4 shown in (h) in [reference], an electrode layer 5 is provided on the piezoelectric layer 4.

[0128] Refer to Figure 2 , Figure 3 , for the first two preparation processes, the release barrier layer 7 or the release sacrificial layer 8 is embedded first and then the piezoelectric layer 4 is bonded, and the wafer needs to travel back and forth between the integrated circuit processing factory and the foundry multiple times, which may damage the wafer. The embedding positions of the release barrier layer 7 or the release sacrificial layer 8 are set in one-to-one correspondence with the position of the electrode layer 5. If the size or position of the electrode layer 5 needs to be changed, the embedding position of the release barrier layer 7 or the release sacrificial layer 8 on the wafer needs to be changed. It is necessary to re-customize the piezoelectric layer 4 from the foundry. The piezoelectric layer 4 is a high-precision device, involving multiple process steps such as the bonding of the piezoelectric layer 4 and the substrate 2, plasma thinning of the piezoelectric layer 4, and polishing, which takes more than 6 weeks.

[0129] Refer to Figure 4 , the third preparation process is to bond the piezoelectric layer 4 first and then embed the release barrier layer 7. As Figure 4As shown in (d) thereof, the depth of the pre-embedded groove 9 corresponding to the release barrier layer 7 is the sum of the thicknesses of the photoresist 11, the piezoelectric layer 4, and the dielectric layer 3. The pre-embedded groove 9 has a large depth and a small width, that is, the depth-width ratio of the pre-embedded groove 9 is large. When filling the pre-embedded groove 9 with a metal or dielectric material using traditional deposition techniques such as sputtering and evaporation, the filling is difficult, the filling property is poor, and the filling process is complex. As Figure 4 As shown in (e) thereof, after filling, some materials cover the surface of the photoresist 11, and the filling side needs to be planarized and ground. The hardness of the metal or dielectric material is relatively large, and the processing force is transmitted to the substrate 2, causing relatively large stress on the substrate 2 and easily damaging the substrate 2. During the front and back processings, the metal or dielectric material is not easy to release the stress of the electrode layer 5 above the cavity 6. A substrate 2 with a large thickness can be pre-customized, planarized after filling the pre-embedded groove 9 with a metal or dielectric material, and the bottom side of the substrate 2 with relatively large stress is ground and thinned to overcome the problem of large stress caused by planarization.

[0130] As Figure 4 As shown in (g) and (h) thereof, first, the cavity 6 is processed on the dielectric layer 3, and then the piezoelectric layer 4 is fabricated on the piezoelectric layer 4. The preparation process has a high risk and a low yield. When fabricating the electrode layer 5 on the area of the piezoelectric layer 4 without support at the bottom, it is easy to cause deformation and damage of the piezoelectric layer 4. As Figure 4 As shown in (c) and (d) thereof, after the pre-embedded groove 9 and the release hole 10 are fabricated, liquids such as the photoresist 11 and the developer in the process will enter the pre-embedded groove 9 and the release hole 10. The small openings of the pre-embedded groove 9 and the release hole 10 make it difficult for the liquid to flow out. The photoresist 11 adheres to the wall surface of the release hole 10 and solidifies into a film, which is not conducive to the release of gas and the reaction with the dielectric layer 3, and will affect the formation of the cavity 6.

[0131] It can be seen that the preparation of the chip 1 with the air-gap type acoustic resonator 1a in the related art is difficult and costly. When bonding the piezoelectric layer 4 and the substrate 2 in the related art during the pre-embedded release barrier layer 7, it is difficult to achieve good filling of the release barrier layer 7 material, and the planarization of the filling side after filling is likely to cause damage to the substrate 2.

[0132] To facilitate the description of the direction and position of the chip 100, two directions on the top surface of the chip 100 are defined as the X direction and the Y direction below, the direction perpendicular to the top surface of the chip 100 or the top-down direction is defined as the Z direction, and the thickness direction of the chip 100 and the thickness direction of the base material layer 110 in the chip 100 are both the Z direction. The X direction, the Y direction, and the Z direction are perpendicular to each other in pairs.

[0133] Refer to Figure 5 and Figure 6, an embodiment of the present application provides a chip 100, including: a substrate layer 110, a piezoelectric layer 120, an electrode layer 130, and a release barrier layer 140. The piezoelectric layer 120 and the substrate layer 110 are laminated and bonded, and the piezoelectric layer 120 has a resonant region 121. The chip 100 has a pre-embedded groove 150 that communicates with the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110. The pre-embedded groove 150 is arranged around the resonant region 121, and an opening 151 is formed on the piezoelectric layer 120. The electrode layer 130 is disposed on the resonant region 121. The substrate layer 110 has a cavity 111 disposed opposite to the resonant region 121. The bottom surfaces of the resonant region 121 and the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110, and the pre-embedded groove 150 communicates with the cavity 111. The material of the release barrier layer 140 is a polymer, and the release barrier layer 140 is disposed in the pre-embedded groove 150 for defining the lateral dimension of the cavity 111.

[0134] Among them, the substrate layer 110, the piezoelectric layer 120, the electrode layer 130, and the release barrier layer 140 can be combined as an air-gap type acoustic resonator 100a. One or more acoustic resonators 100a can be provided on the chip 100. In the case where the chip 100 has multiple acoustic resonators 100a, the multiple acoustic resonators 100a can be cascaded together in a series-parallel manner to form a filter. The filter can allow a signal of a predetermined frequency to pass through and block a signal of another predetermined frequency. The chip 100 can be a filter chip, a radio frequency chip, or other chips.

[0135] In an acoustic filter, multiple acoustic resonators 100a can share the substrate layer 110 and the piezoelectric layer 120, and each acoustic resonator 100a has an independent electrode layer 130 and a release barrier layer 140. A partition wall is formed between the cavities 111 of two adjacent acoustic resonators 100a, that is, a part of the substrate layer 110.

[0136] The substrate layer 110 serves as the bottom layer of the chip 100 and is a carrier for structures such as the piezoelectric layer 120 and the electrode layer 130. The pre-embedded groove 150 and the cavity 111 communicate only when there is no release barrier layer 140 provided in the pre-embedded groove 150.

[0137] The piezoelectric layer 120 is made of a piezoelectric material, and the piezoelectric material has a piezoelectric effect and an inverse piezoelectric effect. The piezoelectric effect means that when a pressure is applied to the piezoelectric material, the piezoelectric material will generate a potential difference. The inverse piezoelectric effect means that when a voltage is applied to the piezoelectric material, a mechanical stress is generated on the piezoelectric material. When a high-frequency changing pressure (mechanical vibration) is applied to the piezoelectric material, the piezoelectric material will generate a high-frequency current. When a high-frequency electrical signal is applied to the piezoelectric material, the piezoelectric material will generate a high-frequency acoustic signal (mechanical vibration), that is, an ultrasonic signal.

[0138] The piezoelectric layer 120 has a resonant region 121 and a non-resonant region 122. An electrode layer 130 is disposed on the resonant region 121. By applying a high-frequency electrical signal to the electrode layer 130, a high-frequency acoustic wave signal can be excited on the resonant region 121. In the air-gap type acoustic wave resonator 100a, the resonant region 121 and the cavity 111 of the substrate layer 110 are correspondingly disposed, and the bottom surfaces of the resonant region 121 and the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110. The non-resonant region 122 is the region of the piezoelectric layer 120 other than the resonant region 121. The non-resonant region 122 and the region of the substrate layer 110 other than the cavity 111 are correspondingly disposed.

[0139] The electrode layer 130 is used to convert an electrical signal into an acoustic wave signal and can also convert an acoustic wave signal into an electrical signal. The electrode layer 130 adopts a structure with a predetermined shape, and the piezoelectric layer 120 and the electrode layer 130 adopt a predetermined bonding method, so as to form different types of acoustic wave resonators, such as film bulk acoustic resonators (FBAR), Lamb wave resonators / laterally excited bulk wave resonators (XBAR), etc. Specific embodiments will be described in detail later.

[0140] The bonded piezoelectric layer 120 can be a single crystal structure, which has better orientation and better performance. An embedded groove 150 is formed on the bonded piezoelectric layer 120 and the substrate layer 110 by means of etching or the like. The embedded groove 150 communicates with the piezoelectric layer 120 and the substrate layer 110 in the thickness direction (Z direction) of the substrate layer 110, that is, the embedded groove 150 penetrates through the piezoelectric layer 120 and extends into the substrate layer 110, so that an opening 151 is formed on the piezoelectric layer 120 for the embedded groove 150.

[0141] The material of the release barrier layer 140 is a polymer. The liquid polymer is easily filled in the embedded groove 150 of the chip 100, and the polymer is cured and the filling side is planarized to form a release barrier layer 140 in the embedded groove 150. The polymer can be cured in a wide temperature range, has low residual stress and good adhesion, will not generate cracks after reliability tests, and has stable physical and chemical properties. During the process of forming the cavity 111, the release fluid reacts with the substrate layer 110, and the release of the release fluid to the periphery of the cavity 111 (i.e., the non-resonant region 122) is restricted through the release barrier layer 140, thereby defining the lateral dimension of the cavity 111. The lateral dimension of the cavity 111 refers to any dimension in a plane perpendicular to the thickness direction of the substrate layer 110 (such as the dimensions in the X direction and the Y direction).

[0142] In the chip 100 provided by the embodiment of the present application, as Figure 7As shown in (a) of FIG. 1 , the wafer factory stacks and bonds the substrate layer 110 and the piezoelectric layer 120, as shown in Figure 7 As shown in (b) and (c) of , after the integrated circuit processing factory receives the wafer with the piezoelectric layer 120 and the substrate layer 110 bonded, it processes the embedded groove 150, as shown in Figure 7 As shown in (d) and (e) of , the production of the release barrier layer 140 and the electrode layer 130 is as shown in Figure 7 As shown in (f) to (h) in , the concave cavity 111 of the substrate layer 110 is manufactured. It is not necessary to move the wafer back and forth between the integrated circuit processing plant and the wafer factory as in the related art to reduce wafer damage. If the size or position of the electrode layer 130 is to be changed, the position of the embedded groove 150 of the release barrier layer 140 can be directly changed on the wafer, without having to spend more than 6 weeks to re-customize the piezoelectric layer 120 in the wafer factory as in the related art. As Figure 7 As shown in (c) and (d) in , the material of the release barrier layer 140 is a polymer. The liquid polymer is easy to fill in the embedded groove 150 of the chip 100, the process is simple, and the filling effect is good. The hardness of the polymer is small after curing. When the filling side is flattened, the stress strain of the substrate layer 110 is small, and the damage to the substrate layer 110 is very small. There is no need to pre-customize a thick substrate and grind and thin the bottom side of the substrate after filling the embedded groove as in the related art. During the front-end processing, the polymer can release the mechanical stress of the electrode layer 130 above the cavity 111, reducing the difficulty of processing. As shown in Figure 7 As shown in (f) and (g) in , a cavity 111 is formed in the substrate layer 110 by reacting the release fluid with the substrate layer 110, so that the resonance region 121 of the piezoelectric layer 120 disposed on the substrate layer 110 and the bottom surface of the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110. The release barrier layer 140 and the release fluid hardly react, and the lateral dimension of the cavity 111 is limited by the release barrier layer 140, so that the lateral dimension of the cavity 111 can be made smaller, and more acoustic wave resonators 100a can be arranged on the wafer, thereby improving the mechanical strength and power tolerance of the device. The substrate layer 110, the piezoelectric layer 120, the electrode layer 130 and the release barrier layer 140 in the chip 100 can be combined to form an air gap type acoustic wave resonator 100a. The chip 100 has low difficulty in preparation, low cost and high yield.

[0143] The release fluid may be a release gas stream or solution that can react with the substrate layer 110 and substantially does not react with the polymer, such as xenon difluoride (XeF 2 ) gas, hydrofluoric acid (HF) solution and its buffer solution, etc.

[0144] In order to make the release fluid react with the predetermined area of ​​the substrate layer 110 to form a cavity 111 on the substrate layer 110, in some embodiments, refer to Figure 5 、 Figure 6 ​​, a plurality of release holes 160 are provided on the resonance region 121, and the plurality of release holes 160 communicate with the concave cavity 111. After the release holes 160 are fabricated, a release fluid is allowed to pass through the release holes 160 and react with the substrate layer 110, thereby forming a depression in the substrate layer 110. The release holes 160 may be provided along the edge of the resonance region 121.

[0145] In some embodiments, referring to Figure 5 , the resonance region 121 is generally rectangular, and the plurality of release holes 160 are generally arranged in a rectangular shape. By introducing a release fluid that can react with the substrate layer 110 into all the release holes 160, a concave cavity 111 that is generally rounded-rectangular in a top-down view can be formed on the substrate layer 110. Referring to Figure 6 , the release fluid reacts with the substrate layer 110 isotropically through the release holes 160, and cavities with spherical-like walls centered on each release hole 160 are formed in the substrate layer 110. All the cavities form the concave cavity 111. There may be a non-reacted raised area in the middle of the bottom surface of the concave cavity 111, which can satisfy the requirement that the resonance region 121 of the piezoelectric layer 120 and the bottom surface of the concave cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110.

[0146] In order to connect the electrode layers 130 of the plurality of acoustic wave resonators 100a in the filter in series and parallel, in some embodiments, referring to Figure 5 、 Figure 6 , a conductive portion 130a is provided on the piezoelectric layer 120, and the conductive portion 130a is connected and conducted with the electrode layer 130, so that the electrode layers 130 of the plurality of acoustic wave resonators 100a are cascaded together in a series-parallel manner to form a filter circuit.

[0147] When arranging the piezoelectric layer 120 and the electrode layer 130, there are various optional arrangement methods. Here, three arrangement methods are exemplarily given.

[0148] The first arrangement method of the piezoelectric layer 120 and the electrode layer 130 is a laterally excited bulk acoustic wave resonator 100a: Referring to Figure 5 、 Figure 6 , the electrode layer 130 includes an interdigital transducer (IDT) 131, and the interdigital transducer 131 is provided on the side of the resonance region 121 facing away from the substrate layer 110. The interdigital transducer 131 is provided on one side of the piezoelectric layer 120, and the resonance region 121 of the piezoelectric layer 120 is located above the concave cavity 111, and an air-gap type laterally excited bulk acoustic wave resonator 100a can be formed.

[0149] Figure 5 、 Figure 6The structure of the interdigital transducer 131 is shown. The actual number of electrode fingers can be large and the width can be small. The interdigital transducer 131 may include a first bus bar 1311, a second bus bar 1312, a plurality of first electrode fingers 1313 and a plurality of second electrode fingers 1314. The first bus bar 1311 and the second bus bar 1312 are arranged in parallel at intervals. The plurality of first electrode fingers 1313 are arranged in parallel at intervals and connected to the same side of the first bus bar 1311. The plurality of second electrode fingers 1314 are arranged in parallel at intervals and connected to the same side of the second bus bar 1312. The plurality of first electrode fingers 1313 and the plurality of second electrode fingers 1314 are located between the first bus bar 1311 and the second bus bar 1312, and the plurality of first electrode fingers 1313 and the plurality of second electrode fingers 1314 are alternately arranged at intervals in sequence. The first bus bar 1311 and the second bus bar 1312 may be conductively connected to different conductive portions 130a on the chip 100 to achieve the transmission of electrical signals.

[0150] During operation, a high-frequency electrical signal is applied between the first bus bar 1311 and the second bus bar 1312, and Lamb waves can be excited on the resonant region 121 of the piezoelectric layer 120. In the case where the piezoelectric layer 120 and the substrate layer 110 are already bonded, it is easy to form the interdigital transducer 131 on the side of the piezoelectric layer 120 away from the substrate layer 110.

[0151] Exemplarily, the resonant region 121 of the piezoelectric layer 120 may be generally rectangular. The first bus bar 1311 and the second bus bar 1312 may extend along the length direction (Y direction) of the resonant region 121, and the plurality of first electrode fingers 1313 and the plurality of second electrode fingers 1314 may extend along the width direction (X direction) of the resonant region 121, so that a large number of first electrode fingers 1313 and second electrode fingers 1314 can be alternately arranged at intervals on the resonant region 121.

[0152] The second arrangement of the piezoelectric layer 120 and the electrode layer 130 is the lateral excitation bulk acoustic wave resonator 100a: Refer to Figure 8 , the electrode layer 130 includes an interdigital transducer 131, and the interdigital transducer 131 is disposed on the side of the resonant region 121 facing the substrate layer 110. The interdigital transducer 131 is disposed on one side of the piezoelectric layer 120, and the resonant region 121 of the piezoelectric layer 120 is located above the cavity 111, and an air-gap type lateral excitation bulk acoustic wave resonator 100a can be formed.

[0153] The specific structure and connection manner of the interdigital transducer 131 may refer to the first arrangement of the piezoelectric layer 120 and the electrode layer 130, and will not be elaborated here. During operation, a high-frequency electrical signal is applied between the first bus bar 1311 and the second bus bar 1312, and Lamb waves can be excited on the resonant region 121 of the piezoelectric layer 120.

[0154] The third arrangement of the piezoelectric layer 120 and the electrode layer 130 is the thin-film bulk acoustic wave resonator 100a: Refer to Figure 9 , the electrode layer 130 includes a first electrode plate 132 and a second electrode plate 133. The first electrode plate 132 is disposed on the side of the resonance region 121 facing away from the substrate layer 110, and the second electrode plate 133 is disposed on the side of the resonance region 121 facing the substrate layer 110.

[0155] The resonance region 121 of the piezoelectric layer 120 is located above the cavity 111. A first electrode plate 132 is disposed on one side in the thickness direction (Z direction) of the resonance region 121, and a second electrode plate 133 is disposed on the other side. The first electrode plate 132 faces outward, and the second electrode plate 133 faces the cavity 111, so that an air-gap type thin-film bulk acoustic wave resonator 100a can be formed. During operation, a high-frequency electrical signal is applied between the first electrode plate 132 and the second electrode plate 133, and a bulk acoustic wave that oscillates and propagates between the first electrode plate 132 and the second electrode plate 133 can be excited on the resonance region 121 of the piezoelectric layer 120. The outside of the first electrode plate 132 and the outside of the second electrode plate 133 are both air, and the acoustic impedance of air is much lower than the acoustic impedance of the piezoelectric layer 120, so that most of the acoustic waves are reflected.

[0156] When setting the piezoelectric layer 120, refer to Figure 6 , Figure 8 , Figure 9 , the material of the piezoelectric layer 120 includes lithium niobate (LiNbO 3 ), lithium tantalate (LiTaO 3 ), aluminum nitride (AlN), zinc oxide (ZnO), quartz, or one or more of them. As the tangential direction of the single crystal structure of the piezoelectric layer 120 is related to the specific acoustic mode, the tangential direction of the material can be set as needed, such as X tangential, Y tangential, Z tangential, rotated Y tangential, or rotated Z tangential.

[0157] When setting the electrode layer 130 and the conductive portion 130a, refer to Figure 6 , Figure 8 , Figure 9 , the materials of the electrode layer 130 and the conductive portion 130a include one or more of aluminum (Al), copper (Cu), platinum (Pt), molybdenum (Mo), tungsten (W), tantalum (Ta), gold (Au), and silver (Ag). The electrode layer 130 and the conductive portion 130a can be fabricated by physical vapor deposition (PVD) processes, such as vacuum evaporation and sputtering processes.

[0158] When setting the substrate layer 110, there are multiple optional implementation methods. Three implementation methods are exemplarily given below.

[0159] The first implementation method of the substrate layer 110: Refer toFigure 6 , the substrate layer 110 includes a stacked substrate 112 and a dielectric layer 113. The dielectric layer 113 is located between the substrate 112 and the piezoelectric layer 120. The piezoelectric layer 120 and the dielectric layer 113 are laminated and bonded. The embedded groove 150 communicates with the piezoelectric layer 120, the dielectric layer 113, and the substrate 112 along the thickness direction (Z direction) of the substrate layer 110, and the cavity 111 is formed on the substrate 112.

[0160] When the dielectric layer 113 is disposed on the substrate 112, the bonding effect is good when the piezoelectric layer 120 and the dielectric layer 113 are laminated and bonded. The embedded groove 150 communicates with the piezoelectric layer 120, the dielectric layer 113, and the substrate 112, and the release barrier layer 140 is disposed in the embedded groove 150. The release fluid reacts with the substrate 112 to form the cavity 111 on the substrate 112, and the lateral dimension of the cavity 111 is defined by the release barrier layer 140 that basically does not react with the release fluid, so that the resonant region 121 of the piezoelectric layer 120 and the bottom surface of the cavity 111 are spaced apart in the thickness direction of the substrate layer 110.

[0161] The second implementation manner of the substrate layer 110: Refer to Figure 10 , the substrate layer 110 includes a stacked substrate 112 and a dielectric layer 113. The dielectric layer 113 is located between the substrate 112 and the piezoelectric layer 120. The piezoelectric layer 120 and the dielectric layer 113 are laminated and bonded. The embedded groove 150 communicates with the piezoelectric layer 120 and the dielectric layer 113 along the thickness direction (Z direction) of the substrate layer 110, and the cavity 111 is formed on the dielectric layer 113.

[0162] When the dielectric layer 113 is disposed on the substrate 112, the bonding effect is good when the piezoelectric layer 120 and the dielectric layer 113 are laminated and bonded. The embedded groove 150 communicates with the piezoelectric layer 120 and the dielectric layer 113, and the release barrier layer 140 is disposed in the embedded groove 150. The release fluid reacts with the dielectric layer 113 to form the cavity 111 on the dielectric layer 113, and the lateral dimension of the cavity 111 is defined by the release barrier layer 140 that basically does not react with the release fluid, so that the resonant region 121 of the piezoelectric layer 120 and the bottom surface of the cavity 111 are spaced apart in the thickness direction of the substrate layer 110.

[0163] The third implementation manner of the substrate layer 110: Refer to Figure 11 , the substrate layer 110 includes the substrate 112. The piezoelectric layer 120 and the substrate 112 are laminated and bonded. The embedded groove 150 communicates with the substrate 112 along the thickness direction (Z direction) of the substrate layer 110, and the cavity 111 is formed on the substrate 112.

[0164] The embedded groove 150 is formed on the substrate 112, and the release barrier layer 140 is disposed in the embedded groove 150. A release fluid reacts with the substrate 112 to form a cavity 111 on the substrate 112, and the lateral dimension of the cavity 111 is defined by the release barrier layer 140 that substantially does not react with the release fluid, so that the resonance region 121 of the piezoelectric layer 120 and the bottom surface of the cavity 111 are spaced apart in the thickness direction of the base material layer 110.

[0165] When setting the substrate 112, refer to Figure 6 , Figures 8 to 11 , the material of the substrate 112 includes one or more of silicon (Si), silicon carbide (SiC), diamond, sapphire, aluminum nitride (AlN), ceramics, lithium tantalate (LiTaO 3 ), lithium niobate (LiNbO 3 ). The specific material of the substrate 112 is selected as required.

[0166] When setting the dielectric layer 113, refer to Figure 6 , Figures 8 to 11 , the material of the dielectric layer 113 includes one or more of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or aluminum oxide (Al 2 O 3 ). By setting the dielectric layer 113 on the substrate 112, the connection effect is good when the piezoelectric layer 120 and the dielectric layer 113 are laminated and bonded.

[0167] When setting the shapes of the embedded groove 150 and the release barrier layer 140, refer to Figure 5 , the cross-sectional shapes of both the embedded groove 150 and the release barrier layer 140 in the top view are the same, and the cross-sections of both the embedded groove 150 and the release barrier layer 140 can be arranged in a circular, elliptical or polygonal shape. The polygon can be a triangular, quadrilateral or more-sided shape. The shape of the release barrier layer 140 can be determined according to the arrangement shape of the electrode layer 130, and the shape of the cavity 111 is defined by the release barrier layer 140.

[0168] Exemplarily, refer to Figure 5 , the electrode layer 130 is arranged substantially in a rectangular shape, the release barrier layer 140 is arranged substantially in a rectangular ring shape, and the cross-section of the cavity 111 defined by the release barrier layer 140 in the top view is substantially rectangular.

[0169] When setting the forms of the embedded groove 150 and the release barrier layer 140, there are various optional implementation manners, and two implementation manners are exemplarily given below.

[0170] The first implementation method of the embedded groove 150 and the release barrier layer 140: Refer to Figure 5 , Figure 6 , the embedded groove 150 includes a plurality of sub-grooves 152 that are distributed around the resonant region 121 and are connected end to end in sequence; the release barrier layer 140 includes a plurality of transverse barrier portions 141, and the plurality of transverse barrier portions 141 are filled in the plurality of sub-grooves 152 one by one.

[0171] The embedded groove 150 is set in a ring-shaped connected form, that is, a plurality of sub-grooves 152 are connected end to end in sequence. As shown in (d) of Figure 7 , a liquid polymer is filled in the plurality of sub-grooves 152. For example, the liquid polymer is filled on one side of the embedded groove 150 of the substrate layer 110 by spin coating, and then the polymer is cured and the filled side is flattened, so as to respectively form transverse barrier portions 141 in each sub-groove 152, and the plurality of transverse barrier portions 141 are connected to form a ring-shaped release barrier layer 140. As shown in (g) and (h) of Figure 7 , when the release fluid reacts with the substrate layer 110, the release fluid does not react with the transverse barrier portions 141, effectively restricting the lateral dimension of the cavity 111 in the substrate layer 110.

[0172] The second implementation method of the embedded groove 150 and the release barrier layer 140: Refer to Figure 12 , the embedded groove 150 includes a plurality of sub-grooves 152 that are distributed around the resonant region 121 and are arranged at intervals in sequence; the release barrier layer 140 includes a plurality of transverse barrier portions 141, and the plurality of transverse barrier portions 141 are filled in the plurality of sub-grooves 152 one by one.

[0173] The embedded groove 150 is set in a ring-shaped non-connected form, that is, a plurality of sub-grooves 152 are arranged at intervals in sequence. A liquid polymer is filled in the plurality of sub-grooves 152. For example, the liquid polymer is on one side of the embedded groove 150 of the substrate layer 110 by spin coating, and then the polymer is cured and the filled side is flattened, so as to respectively form transverse barrier portions 141 in each sub-groove 152, and the plurality of transverse barrier portions 141 are distributed at intervals, without connection and substantially in a ring shape. When the release fluid reacts with the substrate layer 110, each release fluid does not react with the transverse barrier portions 141, and can restrict the lateral dimension of the cavity 111 in the substrate layer 110. By setting the appropriate width and spacing of the sub-grooves 152, the lateral dimension of the cavity 111 can be defined, so that the wall surface of the cavity 111 substantially surrounds the resonant region 121 of the piezoelectric layer 120.

[0174] The plurality of transverse barrier portions 141 in the release barrier layer 140 can be arranged in a circular, elliptical or polygonal shape. The polygon can be a triangle, a quadrilateral or a shape with more sides.

[0175] Exemplarily, refer toFigure 12 The electrode layer 130 is arranged substantially in a rectangular shape, and a plurality of lateral blocking portions 141 in the release blocking layer 140 are arranged substantially in a rectangular ring shape. The cross-section of the cavity 111 defined by the release blocking layer 140 in a top view is substantially rectangular.

[0176] When setting the longitudinal depth of the embedded groove 150 or the release blocking layer 140, refer to Figure 6 The longitudinal depth range of the embedded groove 150 or the release blocking layer 140 is 1 micrometer (μm) to 50 micrometers. The longitudinal depth of the embedded groove 150 or the release blocking layer 140 is the dimension in the thickness direction (Z direction) of the substrate layer 110. By using the embedded groove 150 within the above range, after the liquid polymer flows into the embedded groove 150 and solidifies, the release fluid and the substrate layer 110 react to form the cavity 111 in the substrate layer 110, which can space the resonant region 121 of the piezoelectric layer 120 from the bottom surface of the cavity 111.

[0177] In order to facilitate the easy flow of the liquid polymer into the embedded groove 150, in some embodiments, refer to Figure 5 、 Figure 6 The width L1 of the release blocking layer 140 in a top view is greater than or equal to 10 micrometers. The top view is the view looking down at the chip 100 and its cross-section along the top-down direction (Z direction). The width L1 of the release blocking layer 140 in a top view is the width of the embedded groove 150 in a top view, that is, the short side dimension of a single lateral blocking portion 141 in the release blocking layer 140 in the cross-section in the top-down direction, and is also the short side dimension of a single sub-groove 152 in the embedded groove 150 in the cross-section in the top-down direction.

[0178] By defining the minimum value of the short side dimension of a single lateral blocking portion 141 (or a single sub-groove 152 in the embedded groove 150) in the cross-section in the top-down direction, the liquid polymer can easily flow into and fully fill the embedded groove 150. The liquid polymer can form the release blocking layer 140 after curing.

[0179] Exemplarily, refer to Figure 5 A plurality of lateral blocking portions 141 in the release blocking layer 140 are arranged substantially in a rectangular ring shape, and the width L1 of the release blocking layer 140 in a top view is the short side dimension of a single lateral blocking portion 141 in the cross-section in the top-down direction.

[0180] When selecting the polymer for the release barrier layer 140, the polymer may include one or more of polyimide (PI), polydimethylsiloxane (PDMS), polyvinylidene fluoride (PVDF), benzocyclobutene (BCB), polyethylene glycol terephthalate (PET), and photoresist (Pr). The photoresist may be polymethyl methacrylate (PMMA), etc. There are many materials for the photoresist, and its main component is photosensitive rubber, which belongs to a high molecular polymer. The polymer used is a material that basically does not react with the release fluid, and the liquid polymer is easily filled into the pre-embedded groove 150.

[0181] When fabricating the release barrier layer 140, referring to Figure 7 (d) in, the release barrier layer 140 can be formed by spin-coating the polymer to fill the pre-embedded groove 150, curing the polymer, and planarizing the filled side of the polymer. The filled side of the polymer refers to the side of the wafer where the polymer is filled during the fabrication process.

[0182] After the pre-embedded groove 150 is fabricated, a liquid polymer is applied to the middle of the side of the wafer having the pre-embedded groove 150. By rotating the wafer, the liquid polymer is evenly coated on the wafer, so that the pre-embedded groove 150 at each acoustic resonator 100a is filled with the liquid polymer. The polymer is cured by heating the wafer, so that the polymer adheres effectively to one side of the piezoelectric layer 120. The filled side of the polymer is planarized, and the excess polymer covering the piezoelectric layer 120 is removed. The release barrier layer 140 is reliably attached to the pre-embedded groove 150, preparing for the reaction between the release fluid and the substrate layer 110.

[0183] When setting the polymer, the Young's modulus of the polymer after curing is less than 10 gigapascals (GPa). Compared with the related art that fills the pre-embedded groove with a metal or dielectric material having a Young's modulus greater than 70 GPa, in this embodiment, the liquid polymer is cured to form the release barrier layer 140. The Young's modulus of the polymer after curing is smaller and the hardness is lower. When planarizing the filled side of the polymer, the processing force is transmitted to the substrate layer 110, causing less stress on the substrate layer 110 and little damage to the substrate layer 110. There is no need to pre-customize a thick substrate and grind and thin the bottom side of the substrate after filling the pre-embedded groove as in the related art. During the front and back processings, the polymer can release the mechanical stress of the electrode layer 130 above the cavity 111, reducing the processing difficulty. The preparation of the chip 100 is less difficult, has a low cost, and a high yield.

[0184] Exemplarily, the Young's modulus of the polymer after curing is less than 5 GPa. The smaller the Young's modulus of the polymer after curing, the lower the hardness, and the less damage to the substrate layer 110 when planarizing the side filled with the polymer.

[0185] In order to tightly fill the liquid polymer in the embedded groove 150 and enable the polymer to be deformed by heat after curing, in some embodiments, referring to Figure 13 、 Figure 14 , the chip 100 has one or more micro-grooves 170 that communicate the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110, and the one or more micro-grooves 170 communicate with the embedded groove 150. An opening 171 can be formed on the piezoelectric layer 120 for the micro-groove 170. Figure 13 、 Figure 14 The shape of the micro-groove 170 is shown in

[0186] . Actually, the size of the micro-groove 170 is relatively small. Figure 15 When manufacturing the chip 100, as shown in (a) to (c) of Figure 15 , first, the embedded groove 150 and the micro-groove 170 are fabricated on the substrate layer 110. As shown in (d) of Figure 15 , then the liquid polymer is filled and cured and planarized. As shown in (g) and (h) of Figure 13 、 Figure 14 , the size of the opening 171 of the micro-groove 170 is much smaller than the size of the opening 151 of the embedded groove 150, and the size of the communication port 172 between the micro-groove 170 and the embedded groove 150 is also very small. As shown in (d) of Figure 15 , when filling the liquid polymer into the embedded groove 150 and the micro-groove 170, the liquid polymer has a certain viscosity and surface tension. The liquid polymer can enter the embedded groove 150, but it is difficult to enter the micro-groove 170, and the inside of the micro-groove 170 may be empty. When heating and curing the polymer, there will be bubbles in the liquid polymer at the embedded groove 150, and the bubbles can overflow from the unfilled micro-groove 170 beside, making the polymer more fully and tightly fill the embedded groove 150. As shown in (g) and (h) of Figure 15 , it is beneficial to cure the polymer to form a firm release barrier layer 140, and the release fluid is effectively blocked by the release barrier layer 140, so as to form a cavity 111 with a predetermined lateral dimension in the substrate layer 110. After the polymer is cured to form the release barrier layer 140, the micro-groove 170 can provide a certain deformation space for the thermally expanded release barrier layer 140, reduce the situation that the release barrier layer 140 is squeezed and broken by heat, and enhance the reliability of the device.

[0187] The embedded groove 150 may include a plurality of sub-grooves 152. The number of micro-grooves 170 corresponding to each sub-groove 152 and communicating therewith may be one or more, and the specific number is related to the size of the sub-groove 152. The longer the length of the sub-groove 152 in the top view, the more micro-grooves 170 communicate with the sub-groove 152.

[0188] In some embodiments, referring to Figure 13 , Figure 14 , a plurality of micro-grooves 170 are arranged at intervals along the edge of the resonance region 121. A plurality of micro-grooves 170 are provided to communicate with the embedded groove 150, so that the liquid polymer fills the embedded groove 150 but does not fill in the plurality of micro-grooves 170, which is conducive to exhausting gas through the micro-grooves 170 when the polymer is heated and cured, and is conducive to the polymer curing to form a reliable release barrier layer 140. The micro-grooves 170 provide a deformation space for the release barrier layer 140 that expands due to heat.

[0189] In Figure 13 shown in the embodiment, the embedded groove 150 includes a plurality of sub-grooves 152 distributed around the resonance region 121 and connected end to end in sequence, and each sub-groove 152 can communicate with the micro-groove 170. In Figure 12 shown in the embodiment, the embedded groove 150 includes a plurality of sub-grooves 152 distributed around the resonance region 121 and arranged at intervals in sequence, and each sub-groove 152 can also communicate with the micro-groove 170.

[0190] When setting the shape of the micro-groove 170, referring to Figure 16 , the cross-sectional shape of the micro-groove 170 in the top view can be circular, elliptical, polygonal or X-shaped. The polygon can be triangular, quadrilateral or a shape with more sides. When using a micro-groove 170 with a polygonal cross-section, one side or a part of the polygonal cross-section of the micro-groove 170 is connected to the embedded groove 150, making it difficult for the liquid polymer to enter from the opening 171 of the micro-groove 170 and also difficult to enter the micro-groove 170 from the embedded groove 150. Figure 16 shows the shape of the micro-groove 170, and the actual size of the micro-groove 170 is relatively small.

[0191] Exemplarily, as Figure 16 shown in (a) of, the cross-sectional shape of the micro-groove 170 in the top view is circular, and a part of the circular cross-section of the micro-groove 170 is connected to the long side of the sub-groove 152 in the embedded groove 150. A plurality of micro-grooves 170 are arranged at intervals along the long side direction of the sub-groove 152 in the embedded groove 150. It is difficult for the liquid polymer to enter the micro-groove 170. The internal bubbles in the liquid polymer in the embedded groove 150 are released from the nearby micro-grooves 170 when heated and cured, making the liquid polymer fill tightly in the embedded groove 150. The micro-grooves 170 also provide a deformation space for the release barrier layer 140 that expands due to heat.

[0192] Exemplarily, as Figure 16As shown in (b) thereof, the cross-sectional shape of the micro-groove 170 in the top view is triangular, and one side of the triangular cross-section of the micro-groove 170 communicates with the long side of the sub-groove 152 in the embedded groove 150. A plurality of micro-grooves 170 are arranged at intervals along the long side direction of the sub-groove 152 in the embedded groove 150. In addition, one end of the triangular cross-section of the micro-groove 170 may also communicate with the long side of the sub-groove 152.

[0193] Exemplarily, as Figure 16 As shown in (c) thereof, the cross-sectional shape of the micro-groove 170 in the top view is rectangular, and one short side of the rectangular cross-section of the micro-groove 170 communicates with the long side of the sub-groove 152 in the embedded groove 150. A plurality of micro-grooves 170 are arranged at intervals along the long side direction of the sub-groove 152 in the embedded groove 150.

[0194] Exemplarily, as Figure 16 As shown in (d) thereof, the cross-sectional shape of the micro-groove 170 in the top view is X-shaped, and one end of the X-shaped cross-section of the micro-groove 170 communicates with the long side of the sub-groove 152 in the embedded groove 150. A plurality of micro-grooves 170 are arranged at intervals along the long side direction of the sub-groove 152 in the embedded groove 150.

[0195] In order to make it difficult for the liquid polymer to flow into the embedded groove 150 through the opening 171, in some embodiments, refer to Figure 16 , Figure 16 The view shown is the top view of the embedded groove 150 and the micro-groove 170. The length L2 of the micro-groove 170 in the top view is less than or equal to 10 micrometers (μm). Or, the cross-sectional area of the micro-groove 170 in the top view is less than or equal to 100 square micrometers (μm 2 ). The top view is the view looking down at the chip 100 and its cross-section along the top view direction (Z direction). The length L2 of the micro-groove 170 in the top view is the long side dimension of the micro-groove 170 in the cross-section in the top view direction.

[0196] By limiting the maximum value of the long side dimension of the micro-groove 170 in the cross-section in the top view direction, or by limiting the maximum value of the cross-sectional area of the micro-groove 170 in the cross-section in the top view direction, it is made difficult for the liquid polymer to enter the micro-groove 170 through the opening 171.

[0197] Exemplarily, as Figure 16 As shown in (a) thereof, the cross-sectional shape of the micro-groove 170 in the top view is circular, and the length L2 of the micro-groove 170 in the top view is the diameter of the circular cross-section.

[0198] Exemplarily, as Figure 16 As shown in (b) thereof, the cross-sectional shape of the micro-groove 170 in the top view is triangular, and the length L2 of the micro-groove 170 in the top view is the maximum side length of the triangle.

[0199] Exemplarily, asFigure 16 As shown in (c) therein, the cross-sectional shape of the micro-groove 170 in the top view is rectangular, and the length L2 of the micro-groove 170 in the top view is the length of the long side of the rectangular cross-section.

[0200] Exemplarily, as Figure 16 shown in (d) therein, the cross-sectional shape of the micro-groove 170 in the top view is X-shaped, and the length L2 of the micro-groove 170 in the top view is the arm length of the X-shaped cross-section.

[0201] In order to make it difficult for the liquid polymer to enter the micro-groove 170 from the pre-embedded groove 150, in some embodiments, referring to Figure 14 , a communication port 172 is formed between the micro-groove 170 and the pre-embedded groove 150, and the length L3 of the communication port 172 is less than or equal to 10 micrometers (μm); or, a communication port 172 is formed between the micro-groove 170 and the pre-embedded groove 150, and the cross-sectional area of the communication port 172 is less than or equal to 100 square micrometers (μm 2 ). The communication port 172 has a rectangular cross-section, and the length L3 of the communication port 172 is the long side dimension of the communication port 172 on the rectangular cross-section of the communication port 172.

[0202] By limiting the maximum value of the long side dimension on the plane where the communication port 172 is located, or by limiting the maximum value of the cross-sectional area of the communication port 172, it is difficult for the liquid polymer to enter the micro-groove 170 from the pre-embedded groove 150 through the communication port 172.

[0203] In some embodiments, referring to Figure 6 , Figures 8 to 11 , Figure 14 , the substrate layer 110, the piezoelectric layer 120, the electrode layer 130, and the release barrier layer 140 can be combined as the air-gap type acoustic resonator 100a, and multiple acoustic resonators 100a are cascaded to form a filter. The filter can be a low-pass filter, a high-pass filter, a band-pass filter, a band-stop filter, or an active filter, etc. The filter can be used as a single component, or the filter can be integrated with components such as a power amplifier into a module (such as a radio frequency device, a radio frequency module, a filter module, etc.), and the filter is coupled to the power amplifier for signal processing and transmission.

[0204] Referring to Figure 17 , the ladder acoustic filter is a commonly used topological structure for current acoustic filters. The filter includes multiple cascaded resonators 100a, and multiple resonators 100a can have different resonance frequencies and are cascaded together in a series-parallel manner. The filter has a signal input terminal Vi, a signal output terminal Vo, and a ground terminal GND. The acoustic filter formed by cascading series-parallel resonators 100a with different resonance frequencies has the advantages of small passband insertion loss, high out-of-band steepness, and strong power tolerance.

[0205] The above filter can be an acoustic filter for the 5th generation mobile communication technology (5G) band, or can also be an acoustic filter for other bands.

[0206] When verifying the chip 100 of the embodiment of the present application, refer to Figure 6 , Figures 8 to 11 , Figure 14 , the chip 100 can be dissected, sliced, and observed for its stacked structure and the thickness of each layer using a focused ion beam (FIB) microscope or a transmission electron microscope (TEM); elemental analysis can be performed on the stack of the chip 100 to identify the materials of each layer of the chip 100 and determine whether the material of the release barrier layer 140 is a polymer; in the case where the chip 100 has a microgroove 170, observe whether there is a microgroove 170 at the edge position of the release barrier layer 140 in the top-down direction.

[0207] Refer to Figure 18 , the embodiment of the present application provides an electronic device 1000, including a printed circuit board 200 and the above chip 100, and the chip 100 is disposed on the printed circuit board 200.

[0208] The electronic device 1000 can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. Among them, the consumer electronic product can be a mobile phone, a tablet, a laptop computer, an e-reader, a personal computer (PC), a personal digital assistant (PDA), a desktop monitor, a smart wearable product (such as a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a TV, a remote control, a refrigerator, a small household appliance for charging (such as a soybean milk machine, a floor sweeping robot), etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted high-density digital video disc (DVD), etc. The financial terminal product can be an automated teller machine (ATM), a terminal for self-service business handling, etc. The communication electronic product can be a communication device such as a server, a memory, a radar, a base station, etc.

[0209] Taking the electronic device 1000 as a mobile phone as an example for illustration, the electronic device 1000 includes a cover plate 300, a display screen 400, a middle frame 500, and a rear case 600. The rear case 600 and the display screen 400 are respectively located on opposite sides of the middle frame 500. The middle frame 500 and the display screen 400 can be arranged inside the rear case 600. The cover plate 300 is arranged on the side of the display screen 400 away from the middle frame 500, and the display side of the display screen 400 faces the cover plate 300.

[0210] When setting the display screen 400, there are various optional implementation methods. For example, the display screen 400 can be a liquid crystal display (LCD). The liquid crystal display includes a liquid crystal display panel and a backlight module. The liquid crystal display panel is arranged between the cover plate 300 and the backlight module, and the backlight module is used to provide light source for the liquid crystal display panel. Alternatively, the display screen 400 can be an organic light emitting diode (OLED) display screen. The OLED display screen is a self-luminous display screen and does not require a backlight module to be set.

[0211] When setting the middle frame 500, the middle frame 500 can include a carrier plate 510 and a frame 520 arranged around the carrier plate 510. The electronic device 1000 can also include electronic components such as a printed circuit board (PCB) 200, a battery, a camera, etc. The printed circuit board 200, the battery, the camera, etc. can be arranged on the carrier plate 510.

[0212] The electronic device 1000 can also include a system on chip (SOC), a radio frequency chip, etc. arranged on the printed circuit board 200. The printed circuit board 200 is used to carry the system on chip, the radio frequency chip, etc. and is electrically connected to the system on chip, the radio frequency chip, etc. Among them, the radio frequency chip can include parts such as a filter and a processor. The processor is used to process various signals. The filter is an important part of radio frequency signal processing and is used to allow signals of a predetermined frequency to pass through and block signals of another predetermined frequency.

[0213] Refer to Figure 7 、 Figure 19 An embodiment of the present application provides a method for preparing a chip 100, including:

[0214] Step 710: As shown in (a) of Figure 7 , a wafer with a piezoelectric layer 120 and a substrate layer 110 laminated and bonded is used;

[0215] Step 720: As shown in Figure 7As shown in (b) and (c), an embedded groove 150 is etched on the wafer. The embedded groove 150 communicates with the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110. The embedded groove 150 is arranged around the resonance region 121 of the piezoelectric layer 120, and an opening 151 is formed on the piezoelectric layer 120. When etching the embedded groove 150 on the wafer, photoresist 180 or other materials can be used as a mask for etching the pattern of the embedded groove 150.

[0216] Step 730: As Figure 7 As shown in (d), a polymer is spin-coated on the piezoelectric layer 120 so that the polymer fills the embedded groove 150. During the spin-coating process, the liquid polymer will enter the embedded groove 150 through the opening 151 of the embedded groove 150 to form a good filling.

[0217] Step 740: Cure the polymer and planarize the filling side of the polymer so that the polymer in the embedded groove 150 forms a release barrier layer 140. The filling side of the polymer refers to the side of the wafer filled with the polymer during the manufacturing process.

[0218] Step 750: As Figure 7 As shown in (e), an electrode layer 130 is fabricated on the resonance region 121.

[0219] Step 760: As Figure 7 As shown in (f) and (g), release holes 160 penetrating the piezoelectric layer 120 are fabricated. When fabricating the release holes 160, photoresist 180 or other materials can be used as a mask for fabricating the pattern of the release holes 160.

[0220] Step 770: As Figure 7 As shown in (h), a release fluid is passed through the release holes 160 and etched and reacted with the substrate layer 110 to form a cavity 111 on the substrate layer 110, so that the resonance region 121 and the bottom surface of the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110, and the lateral dimension of the cavity 111 is defined by the release barrier layer 140.

[0221] In the method for preparing the chip 100 provided in the embodiment of the present application, the wafer factory stacks and bonds the substrate layer 110 and the piezoelectric layer 120. After the integrated circuit processing factory obtains the wafer with the piezoelectric layer 120 and the substrate layer 110 bonded, the embedded groove 150 is processed on the wafer, the release barrier layer 140 and the electrode layer 130 are produced, and the cavity 111 of the substrate layer 110 is produced. When the release barrier layer 140 is formed, it is not restricted by the bonding of the piezoelectric layer 120 and the substrate layer 110. There is no need to move the wafer back and forth between the integrated circuit processing plant and the wafer factory as in the related art to reduce wafer damage. If the size or position of the electrode layer 130 is to be changed, the position of the embedded groove 150 of the release barrier layer 140 can be directly changed on the wafer, without having to spend more than 6 weeks to re-customize the piezoelectric layer 120 in the wafer factory as in the related art. The material of the release barrier layer 140 is a polymer, and the liquid polymer is easy to fill in the embedded groove 150 of the chip 100, with a simple process and a good filling effect. After the polymer is cured, the hardness is small, the stress and strain of the substrate layer 110 is small when the filling side is flattened, and the damage to the substrate layer 110 is very small. There is no need to pre-customize a large thickness substrate as in the related art and grind and thin the bottom side of the substrate after filling the embedded groove. During the front-end processing, the polymer can release the mechanical stress of the electrode layer 130 above the cavity 111, reducing the difficulty of processing. By releasing the fluid and reacting with the substrate layer 110, a cavity 111 is formed in the substrate layer 110, so that the resonance zone 121 of the piezoelectric layer 120 provided on the substrate layer 110 and the bottom surface of the cavity 111 are spaced apart in the thickness direction of the substrate layer 110. The release barrier layer 140 and the release fluid hardly react. The release barrier layer 140 limits the lateral size of the cavity 111, so that the lateral size of the cavity 111 can be made smaller, and more acoustic wave resonators 100a are arranged on the wafer, thereby improving the mechanical strength and power tolerance of the device. The preparation process of the chip 100 with the release barrier layer 140 is optimized, the processing process is more reasonable, and the process feasibility is improved. The preparation difficulty of the chip 100 is small, the cost is low, and the yield is high.

[0222] In some embodiments, such as Figure 7 As shown in (b) and (c) of , etching the embedded groove 150 on the wafer specifically includes: coating the surface of the piezoelectric layer 120 with photoresist 180; matching the pattern of the photoresist board with the shape of the embedded groove 150, placing the wafer on a photolithography machine and aligning the wafer and the photoresist board before exposure; removing part of the photoresist 180 corresponding to the embedded groove 150 area after development, so that the pattern of the photoresist board is transferred to the photoresist 180; using the photoresist 180 as a mask for etching the pattern of the embedded groove 150, and transferring the pattern of the photoresist 180 to the wafer after etching, so as to form the embedded groove 150 on the wafer. Etching can be plasma reactive etching.

[0223] In order to tightly fill the liquid polymer in the embedded groove 150 and allow the polymer to deform upon heating after curing, in some embodiments, refer to Figure 15 , an embedded groove 150 is etched on the wafer, specifically including: as shown in (b) and (c) of Figure 15 , an embedded groove 150 and one or more micro-grooves 170 are etched on the wafer. One or more micro-grooves 170 communicate with the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110, and one or more micro-grooves 170 are connected to the embedded groove 150. An opening 171 can be formed on the piezoelectric layer 120 in the micro-groove 170. A photoresist 180 or other material can be used as a mask for etching the patterns of the embedded groove 150 and the micro-groove 170, and the connected embedded groove 150 and micro-groove 170 are etched on the wafer.

[0224] The size of the opening 171 of the micro-groove 170 is much smaller than the size of the opening 151 of the embedded groove 150, and the size of the communication port 172 between the micro-groove 170 and the embedded groove 150 is also very small. When filling the liquid polymer into the embedded groove 150 and the micro-groove 170, the liquid polymer has a certain viscosity and surface tension. The liquid polymer can enter the embedded groove 150, but it is difficult to enter the micro-groove 170, and the inside of the micro-groove 170 may be empty. When heating and curing the polymer, there will be bubbles in the liquid polymer at the embedded groove 150, and the bubbles can overflow from the unfilled micro-groove 170 beside, making the polymer fill the embedded groove 150 more fully and tightly. After the polymer cures to form the release barrier layer 140, the micro-groove 170 can provide a certain deformation space for the thermally expanded release barrier layer 140, reduce the situation that the release barrier layer 140 is squeezed and broken by heat, and enhance the reliability of the device.

[0225] In the case of fabricating the micro-groove 170, as shown in (b) and (c) of Figure 15 , an embedded groove 150 and a micro-groove 170 are etched on the wafer, specifically including: coating a photoresist 180 on the surface of the piezoelectric layer 120; the pattern of the photomask is adapted to the shape of the embedded groove 150 and the shape of the micro-groove 170. After placing the wafer on the lithography machine and aligning the wafer with the photomask, exposure is performed; after development, a part of the photoresist 180 corresponding to the regions of the embedded groove 150 and the micro-groove 170 is removed, so that the pattern of the photomask is transferred to the photoresist 180; taking the photoresist 180 as a mask for etching the patterns of the embedded groove 150 and the micro-groove 170, after etching, the pattern of the photoresist 180 is transferred to the wafer, and the embedded groove 150 and the micro-groove 170 are formed on the wafer. The etching can be plasma reactive etching.

[0226] There are various optional implementation methods when setting the embedded groove 150. For example, refer to Figure 13, one or more micro-grooves 170 are provided on one side of the embedded groove 150 facing the resonance region 121. Alternatively, one or more micro-grooves 170 are provided on one side of the embedded groove 150 facing away from the resonance region 121. Alternatively, one or more micro-grooves 170 are provided on one side of the embedded groove 150 facing the resonance region 121, and one or more micro-grooves 170 are provided on one side of the embedded groove 150 facing away from the resonance region 121. The micro-grooves 170 can be provided on one or both sides of the embedded groove 150. When filling with a liquid polymer, it is easy to enter the embedded groove 150 but difficult to enter the micro-grooves 170, and the inside of the micro-grooves 170 may be empty.

[0227] In the case where a plurality of micro-grooves 170 are provided on one side of the embedded groove 150 facing the resonance region 121, refer to Figure 14 , since a release fluid will react with the substrate layer 110 later, the micro-grooves 170 on the side of the embedded groove 150 facing the resonance region 121 will communicate with the cavities 111 of the substrate layer 110. Finally, the micro-grooves 170 on the side of the substrate layer 110 of the finished chip 100 facing the resonance region 121 cannot be seen, while the micro-grooves 170 and the openings 171 on the side of the piezoelectric layer 120 facing the resonance region 121 can be seen. In the case where a plurality of micro-grooves 170 are provided on one side of the embedded groove 150 facing away from the resonance region 121, the micro-grooves 170 on the side of the finished chip 100 facing away from the resonance region 121 can be seen on both the substrate layer 110 and the piezoelectric layer 120.

[0228] When setting the cross-sectional shape and dimensional characteristics of the embedded groove 150, reference can be made to the description of the embodiment of the chip 100 above, and details will not be repeated.

[0229] In some embodiments, refer to Figure 20 、 Figure 21 , curing the polymer 140a and planarizing the filling side of the polymer 140a, specifically including: Step 741, as shown in (a) and (b) in Figure 20 , pre-baking the wafer filled with the polymer 140a;

[0230] Step 742, as shown in (c) in Figure 20 , performing photolithography and development to remove the polymer 140a outside the extended space 153 of the embedded groove 150;

[0231] Step 743, combined with Figure 20 in (d), performing dry stripping to remove the polymer 140a outside the embedded groove 150;

[0232] Step 744, planarizing the filling side of the polymer 140a;

[0233] Step 745, completely baking the wafer to cure the polymer 140a.

[0234] Among them, the extended space 153 of the embedded groove 150 refers to the space formed by the wall surface of the embedded groove 150 extending along the thickness direction (Z direction) of the substrate layer 110.

[0235] As Figure 20 shown in (a) of [reference], spin-coat the liquid polymer 140a on one side of the opening 151 of the embedded groove 150 on the wafer, so that the liquid polymer 140a is well filled in the embedded groove 150. As Figure 20 shown in (b) of [reference], there will be a part of the liquid polymer 140a on the wafer surface. Perform pre-baking to volatilize the solvent in the liquid polymer 140a to a certain extent and enhance the adhesion between the liquid polymer 140a and the wall surface of the embedded groove 150. The pattern of the photomask is adapted to the shape of the embedded groove 150. Place the wafer on the lithography machine and align the wafer with the photomask, and then perform exposure. As Figure 20 shown in (c) of [reference], and then through development, remove the polymer 140a outside the extended space 153 of the embedded groove 150. There is still excess polymer 140a above the embedded groove 150. As Figure 20 shown in (d) of [reference], use dry etching to remove the polymer 140a outside the embedded groove 150. Flatten the side filled with the polymer 140a to form a flat surface on the piezoelectric layer 120. The polymer 140a exists in the embedded groove 150, preparing for the subsequent formation of the electrode layer 130 on the piezoelectric layer 120. Perform full baking to cure the polymer 140a, enhance the adhesion ability of the polymer 140a, and improve the corrosion resistance ability to form a reliable release barrier layer 140.

[0236] In some embodiments, referring to Figure 22 and Figure 23 , curing the polymer 140a and flattening the filling side of the polymer 140a specifically includes: step 741a, performing full baking on the wafer filled with the polymer 140a to cure the polymer 140a; step 742a, flattening the filling side of the polymer 140a.

[0237] As Figure 22 shown in (a) and (b) of [reference], spin-coat the liquid polymer 140a on one side of the opening 151 of the embedded groove 150 on the wafer, so that the liquid polymer 140a is well filled in the embedded groove 150, and there will be a part of the liquid polymer 140a on the wafer surface. As Figure 22As shown in (c) therein, complete baking cures the polymer 140a, enhancing the adhesion ability of the polymer 140a and improving the corrosion resistance. A chemical mechanical planarization (CMP) process can be used for planarization to form a flat surface on the piezoelectric layer 120, preparing for subsequent formation of the electrode layer 130 on the piezoelectric layer 120. The polymer 140a is present in the pre-embedded groove 150 to form a reliable release barrier layer 140.

[0238] In some embodiments, planarizing the filling side of the polymer 140a specifically includes one or more of photolithography development, dry etching, and chemical mechanical polishing. By the above methods, the filling side of the polymer 140a can be planarized to form a flat surface on the piezoelectric layer 120, preparing for subsequent formation of the electrode layer 130 on the piezoelectric layer 120.

[0239] In some embodiments, referring to Figure 7 (d) and (e) therein, an electrode layer 130 is fabricated on the resonant region 121 of the piezoelectric layer 120, and a conductive portion 130a is fabricated on the non-resonant region 122 of the piezoelectric layer 120. The conductive portion 130a is connected and conducts with the electrode layer 130, enabling the electrode layers 130 of multiple acoustic wave resonators 100a to be cascaded together in a series-parallel manner to form a filter circuit.

[0240] It should be noted that the foregoing embodiments of the chip 100 are applicable to the preparation method of the chip 100 in the embodiments of the present application, and will not be elaborated herein.

[0241] Finally, it should be noted that the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that: include: a substrate layer, a piezoelectric layer, an electrode layer, and a release barrier layer; The piezoelectric layer and the substrate layer are stacked and bonded, and the piezoelectric layer has a resonance region; The chip has a pre-buried groove connecting the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, the pre-buried groove is arranged around the resonance area, and the pre-buried groove forms an opening on the piezoelectric layer; The electrode layer is disposed on the resonance region; The substrate layer has a concave cavity arranged opposite to the resonance zone, the resonance zone and the bottom surface of the concave cavity are spaced apart in the thickness direction of the substrate layer, and the embedded groove is connected to the concave cavity; The release barrier layer is made of a polymer and is disposed in the embedded groove to limit the transverse dimension of the cavity.

2. The chip according to claim 1, characterized in that: The electrode layer includes an interdigital transducer, and the interdigital transducer is arranged on a side of the resonance region facing away from the substrate layer; Or, the electrode layer includes an interdigital transducer, and the interdigital transducer is arranged on a side of the resonance region facing the substrate layer; Alternatively, the electrode layer includes a first electrode plate and a second electrode plate, the first electrode plate is disposed on a side of the resonance region facing away from the substrate layer, and the second electrode plate is disposed on a side of the resonance region facing the substrate layer.

3. The chip according to claim 1 or 2, characterized in that: The base material layer includes a substrate and a dielectric layer stacked together, the dielectric layer is located between the substrate and the piezoelectric layer, the piezoelectric layer and the dielectric layer are stacked and bonded, the embedded groove connects the piezoelectric layer, the dielectric layer and the substrate along the thickness direction of the base material layer, and the concave cavity is formed on the substrate; Or, the base material layer includes a substrate and a dielectric layer stacked together, the dielectric layer is located between the substrate and the piezoelectric layer, the piezoelectric layer and the dielectric layer are stacked and bonded, the embedded groove connects the piezoelectric layer and the dielectric layer along the thickness direction of the base material layer, and the cavity is formed on the dielectric layer; Alternatively, the base material layer includes a substrate, the piezoelectric layer and the substrate are stacked and bonded, the embedded groove is connected to the substrate along the thickness direction of the base material layer, and the cavity is formed on the substrate.

4. The chip according to claim 3, characterized in that: The material of the substrate includes one or more of silicon, silicon carbide, diamond, sapphire, aluminum nitride, ceramic, lithium tantalate, and lithium niobate.

5. The chip according to any one of claims 1 to 4, characterized in that: The embedded groove includes a plurality of sub-grooves distributed around the resonance zone and connected end to end in sequence; the release barrier layer includes a plurality of transverse barrier portions, and the plurality of transverse barrier portions are filled in the plurality of sub-grooves in a one-to-one correspondence; Alternatively, the embedded groove includes a plurality of sub-grooves distributed around the resonance zone and arranged in sequence; the release barrier layer includes a plurality of transverse barrier portions, and the plurality of transverse barrier portions are filled in the plurality of sub-grooves in a one-to-one correspondence.

6. The chip according to any one of claims 1 to 5, characterized in that: The release barrier layer is arranged along a circle, an ellipse or a polygon; and / or, the longitudinal depth of the release barrier layer ranges from 1 micron to 50 microns; and / or, the width of the release barrier layer in a top view is greater than or equal to 10 micrometers; and / or, the polymer includes one or more of polyimide, polydimethylsiloxane, polyvinylidene fluoride, benzocyclobutene, polyethylene terephthalate, and photoresist; And / or, the release barrier layer is formed by spin coating the polymer to fill the embedded groove, curing the polymer and planarizing the filled side of the polymer; And / or, the polymer has a Young's modulus of less than 10 GPa after curing.

7. The chip according to any one of claims 1 to 6, characterized in that: The chip has one or more micro grooves connecting the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more micro grooves are connected to the embedded groove.

8. The chip according to claim 7, characterized in that: A plurality of the microgrooves are arranged at intervals along the edge of the resonance region; And / or, the cross-sectional shape of the microgroove in the top view is circular, elliptical, polygonal or X-shaped; And / or, the length of the microgroove in the top view is less than or equal to 10 micrometers; And / or, the cross-sectional area of ​​the microgroove in a top view is less than or equal to 100 square micrometers; And / or, a communication port is formed between the micro groove and the embedded groove, and the length of the communication port is less than or equal to 10 microns; And / or, a communication opening is formed between the micro groove and the embedded groove, and a cross-sectional area of ​​the communication opening is less than or equal to 100 square microns.

9. The chip according to any one of claims 1 to 8, characterized in that: The material of the piezoelectric layer includes one or more of lithium niobate, lithium tantalate, aluminum nitride, zinc oxide, and quartz in each tangential direction; And / or, a plurality of release holes are provided on the resonance zone, and the plurality of release holes are communicated with the concave cavity.

10. An electronic device, characterized in that: The invention comprises a printed circuit board and a chip as claimed in any one of claims 1 to 9, wherein the chip is arranged on the printed circuit board.

11. A method for preparing a chip according to any one of claims 1 to 9, characterized in that: include: Wafers with laminated bonding of piezoelectric layers and substrate layers; Etching a pre-buried groove on the wafer, wherein the pre-buried groove connects the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, the pre-buried groove is arranged around the resonance region of the piezoelectric layer, and the pre-buried groove forms an opening on the piezoelectric layer; Spin coating a polymer on the piezoelectric layer so that the polymer fills the embedded groove; Curing the polymer and planarizing the filled side of the polymer so that the polymer in the embedded groove forms a release barrier layer; Fabricating an electrode layer on the resonance region; Making a release hole penetrating the piezoelectric layer; The release fluid passes through the release hole and reacts with the substrate layer by etching to form a cavity on the substrate layer, so that the resonance zone and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer, and the lateral size of the cavity is limited by the release barrier layer.

12. The method for preparing a chip according to claim 11, characterized in that: The step of curing the polymer and planarizing the filled side of the polymer specifically includes: pre-baking the wafer filled with the polymer; photolithography development to remove the polymer outside the extended space of the embedded groove; dry stripping to remove the polymer outside the embedded groove; planarizing the filled side of the polymer; and completely baking the wafer to cure the polymer; Or, the curing of the polymer and planarizing the filled side of the polymer specifically comprises: completely baking the wafer filled with the polymer to cure the polymer and planarizing the filled side of the polymer; Alternatively, the planarization of the filled side of the polymer may specifically include one or more of photolithography, dry etching, and chemical mechanical polishing.

13. The method for preparing a chip according to claim 11 or 12, characterized in that: The method of etching a pre-buried groove on the wafer specifically includes: etching a pre-buried groove and one or more micro grooves on the wafer, wherein the one or more micro grooves connect the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more micro grooves are connected to the pre-buried groove.

14. The method for preparing a chip according to claim 13, characterized in that: One or more microgrooves are provided on the side of the pre-buried groove facing the resonance zone; And / or, one or more microgrooves are provided on a side of the pre-buried groove facing away from the resonance zone.

Images