Command configuration method and unit, display processor and electronic equipment

Abstract

The invention provides a command configuration method and unit, a display processor and electronic equipment, and relates to the field of data transmission. The command configuration unit includes: a read data channel including a buffer configured with a plurality of buffer regions and a selector; a plurality of command interfaces, wherein the command interfaces are respectively configured to respectively correspond to different buffer areas; each command interface is used for being connected with the image processing module; the selector is configured to receive the read data and store the read data into the corresponding buffer area according to the identification information; and each command interface is configured to acquire the read data from the corresponding buffer area and configure the image processing module based on a configuration command in the read data. The utilization rate of the bus bandwidth can be improved through the command configuration unit, so that the efficiency of performing command configuration on each module of the display processor is improved.

Description

Command configuration method, unit, display processor and electronic device Technical Field

[0001] The present application relates to the field of data transmission, and in particular to a command configuration method, unit, display processor and electronic device. Background Art

[0002] The DPU (Display Processor Unit) configures parameters for each image processing module within the DPU according to control commands sent by the CPU (Central Process Unit), thereby processing image data and sending it to the display device.

[0003] Currently, the DPU can use DMA (Direct Memory Access) to transmit control commands. The DPU reads control commands from DRAM (Dynamic Random Access Memory) through DMA technology and transmits them back to the DPU. The DPU parses the control commands to obtain configuration parameters. The DPU's image processing modules are configured according to the configuration parameters, allowing the DPU to perform corresponding functions.

[0004] The transmission bus bandwidth of DMA technology for reading control commands from DRAM can reach 128 bits or 256 bits, while the interface bus width of the DPU for receiving control commands is only 32 bits (bits). This results in DMA technology only being able to use the 32-bit bus bandwidth to transmit control commands to the DPU, and the transmission bus bandwidth cannot be fully utilized.

[0005] As requirements for image dynamic range, frame rate, and resolution increase, the number of image processing modules required by the DPU increases, increasing the CPU's burden on configuring the DPU. Furthermore, the DPU shares a command configuration system with other modules and circuits in the device, all of which read commands from DRAM based on DMA. If the DPU cannot fully utilize its own transmission bandwidth or bus bandwidth, the overall performance of the device in which it resides will be affected.

[0006] Summary of the Invention

[0007] In view of this, the present application aims to provide a command configuration method, unit, display processor and electronic device to improve the bandwidth utilization of the display processor and to improve the efficiency of command configuration of each module of the display processor.

[0008] In a first aspect, an embodiment of the present application provides a command configuration method, comprising: a read data channel, comprising a buffer and a selector, the buffer being connected to the selector, the buffer being configured with multiple buffer areas; the selector being used to connect to a memory that outputs read data, the read data comprising a configuration command and identification information, the configuration command comprising parameters for configuring each image processing module in a display processor, the identification information representing the buffer area corresponding to the read data; multiple command interfaces, each of the command interfaces being respectively connected to the buffer, and each of the command interfaces being respectively configured to correspond to a different buffer area; each of the command interfaces being used to connect to the image processing module; wherein the selector is configured to receive the read data and store the read data into a corresponding buffer area according to the identification information; each of the command interfaces being configured to obtain the read data from the corresponding buffer area, and to configure the image processing module based on the configuration command in the read data.

[0009] In an embodiment of the present application, the command interface can obtain configuration commands from read data and configure the image processing module. Therefore, when transmitting read data and read requests, the read data does not need to be transmitted according to the interface bandwidth of the image processing module. Instead, the data can be transmitted according to the bandwidth of the transmission bus, which is larger than the interface bit width of the image processing module. This improves the utilization of the transmission bandwidth and thus enhances the configuration efficiency of the display processor. Furthermore, through the aforementioned command configuration unit, multiple configuration command requests or parsing can be performed in parallel, further improving the configuration efficiency of the display processor.

[0010] In one embodiment, the command configuration unit also includes: a read request channel, the read request channel includes multiple read request generators, each of the read request generators corresponds to a different command interface; each of the read request generators is used to send a read request to the memory; the memory is configured to send the read data to the buffer in response to the read request.

[0011] In an embodiment of the present application, multiple read request generators are configured in a read request channel, and different read request generators correspond to different command interfaces respectively. Thus, each read request channel can generate read requests corresponding to different command interfaces respectively, and the generation and issuance of multiple read requests are carried out in parallel. Compared with the method of generating and issuing read requests one by one, the generation efficiency of read requests can be effectively improved, thereby improving the efficiency of obtaining configuration commands for each image processing module, and further improving the configuration efficiency of the image processing module.

[0012] In one embodiment, the read request channel further includes a read request arbitrator; the read request arbitrator is connected to each of the read request generators and is used to connect to the memory; the read request arbitrator is configured to control the output order of each of the read requests based on a preset output priority rule.

[0013] Some image processing modules have high real-time requirements, and the memory needs to receive read requests one by one. Therefore, in an embodiment of the present application, a read request arbiter is set in the read request channel so that the read requests corresponding to the command interface with higher priority can be output to the memory first to read the read data, so as to meet the real-time requirements of each image processing module for configuration command acquisition.

[0014] In one embodiment, the read data channel further includes: an address buffer, connected to the buffer and each of the command interfaces, respectively, the address buffer being configured to store the write address of the read data in the buffer area and the read address of the read data read out of the buffer area; the command interface being configured to read the read data from the buffer area according to the write address; and the selector being configured to store the read data into the corresponding buffer area according to the read address and the identification information.

[0015] In the embodiment of the present application, an address buffer is used to record the read address and the write address, thereby enabling the command interface to accurately obtain the read data from the buffer, thereby improving the accuracy of configuring the image processing module.

[0016] In one embodiment, the read data channel also includes a base address memory group, the base address memory group includes multiple base address memories, and the address buffer is connected to each command interface through each base address memory; the base address memory is used to provide the write address to the command interface connected to the base address memory after the read data is stored in the buffer area.

[0017] In an embodiment of the present application, write addresses are recorded based on a base address memory group, so that the command interface only needs to receive the write address stored in the corresponding base address memory, eliminating the need for additional judgment logic, thereby improving the configuration efficiency of the command interface. In one embodiment, the read data channel also includes a buffered read arbiter; the buffered read arbiter is respectively connected to the buffer and each of the command interfaces; the buffered read arbiter is configured to instruct each of the command interfaces to obtain the read data from the buffer.

[0018] In an embodiment of the present application, only one command interface is usually allowed to read the buffer at the same time, and a buffer read arbiter is set to instruct each command interface to obtain read data from the buffer in turn, thereby reducing the possibility of data loss and reading errors and improving the accuracy of display processor configuration.

[0019] In one embodiment, each of the command interfaces includes a command buffer 121 and a command parser, the command buffer 121 is connected to the buffer, and the command buffer 121 is connected to the command parser; the command parser is used to connect to the image processing module; the command buffer 121 is used to store the read data obtained from the buffer; the command parser is used to output the read data to the image processing module in a preset format to configure the image processing module.

[0020] In the embodiment of the present application, command buffer 121 can temporarily store data output to the display processor module, allowing the command parser to read and output the read data from command buffer 121 in a preset format. Through command buffer 121 and the command parser, the command interface can perform data conversion, converting configuration commands into data usable by the image processing module. As a result, the bandwidth of the read data before transmission to the image processing module can be greater than the bandwidth of the image processing module, fully utilizing the bandwidth of the transmission bus and improving the configuration efficiency of the image processing module.

[0021] In one embodiment, the command parser includes a first parser or a second parser; the configuration command includes a coefficient command, and the coefficient command is used to configure an image processing module having a three-dimensional lookup table; the second parser is configured to output the read data to the image processing module according to the size of the output bandwidth of the second parser; the output bandwidth of the second parser in each of the command interfaces matches the bandwidth of each of the image processing modules having the three-dimensional lookup table in the display processor.

[0022] In an embodiment of the present application, an image processing module includes a 3D LUT (3D Look Up Table), and the coefficient commands it receives configure the three-dimensional lookup table. Different coefficient commands have different bandwidths. If the coefficient commands are transmitted with the same bandwidth, the transmission bandwidth may not be fully utilized. Therefore, a second parser is configured in the command interface, and the output bandwidth of each second parser is matched with the bandwidth of each image processing module with a three-dimensional lookup table in the display processor. Thus, image processing modules with different bandwidths can all be parsed by a corresponding second parser, so that the output coefficient commands can match each image processing module, and the configuration of the system command can be completed at one time without multiple configurations or introduction of invalid data, etc., thereby fully utilizing the bandwidth.

[0023] In one embodiment, the buffer areas corresponding to the command interfaces share the storage space of the buffer, and the storage space corresponding to each buffer area is allocated according to the amount of read data corresponding to each command interface in the buffer.

[0024] In this embodiment, the size of the storage space corresponding to the cache area is dynamically allocated according to the amount of read data. In different situations of read data transmission, sufficient storage space can be allocated for the read data, thereby meeting the needs of read data transmission in different scenarios and expanding the scope of application of the command configuration unit.

[0025] An embodiment of the present application also provides a command configuration method, which is applied to a command configuration unit, wherein the command configuration unit includes: a read data channel, the read data channel includes a buffer and a selector, the buffer is connected to the selector, and the buffer is configured with multiple buffer areas; the selector is used to connect to a memory that outputs read data, the read data includes a configuration command and identification information, the configuration command includes parameters for configuring a display processor, and the identification information represents the buffer area corresponding to the read data; multiple command interfaces, each of the command interfaces is connected to the buffer, and each of the command interfaces is configured to correspond to a different buffer area; each of the command interfaces is used to connect to the display processor; the command configuration method includes: receiving the read data through the selector; storing the read data into the corresponding buffer area according to the identification information of the received read data through the selector; obtaining the read data from the buffer area corresponding to the command interface through the command interface; and configuring the display processor based on the configuration command in the read data through the command interface.

[0026] In a third aspect, an embodiment of the present application provides a display processor, comprising: a command configuration unit as described in any one of the first aspects; and a plurality of image processing modules, each connected to the command configuration unit.

[0027] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a display processor as described in the third aspect; a controller and a memory, the memory being connected to the controller and the display processor, respectively; the controller being configured to generate the read data and store the read data into the memory; the memory being used to output the read data to the display processor in response to a read request from the display processor.

[0028] In one embodiment, the memory is configured with a plurality of storage areas, each of the storage areas corresponds to a different command interface; each storage area is configured to store read data corresponding to each command interface.

[0029] In a fifth aspect, an embodiment of the present application provides an image display system, comprising: an electronic device as described in any one of the fourth aspects; and a display device, communicatively connected to the electronic device, for displaying image data output by the display processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0031] FIG1 is a schematic diagram of a command configuration unit provided in an embodiment of the present application;

[0032] FIG2 is a schematic diagram of a buffer storage space provided by an embodiment of the present application;

[0033] FIG3 is a schematic diagram of an expansion of a command configuration unit provided in an embodiment of the present application;

[0034] FIG4 is a schematic diagram of a buffered read arbiter readout provided in an embodiment of the present application.

[0035] FIG5 is a schematic diagram of a read request channel operation according to an embodiment of the present application;

[0036] FIG6 is a schematic diagram of receiving and parsing read data according to an embodiment of the present application;

[0037] FIG7 is a flowchart of a command configuration method provided in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of a display processor provided in an embodiment of the present application;

[0039] FIG9 is a schematic diagram of an electronic device provided in one embodiment of the present application;

[0040] FIG10 is a schematic diagram of an image display system provided in an embodiment of the present application.

[0041] Icon: command configuration unit 100; read data channel 110; selector 111; buffer 112; address cache 113; base address memory group 114; buffered read arbitrator 115; command interface 120; command cache 121; first parser 122; second parser 123; read request channel 130; read request generator 131; read request arbitrator 132; display processor 200; image processing module 210; electronic device 300; controller 310; memory 320; display system 400; display device 410. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0043] Please refer to FIG1 , which is a schematic diagram of a command configuration unit 100 according to an embodiment of the present application. The command configuration unit 100 includes a read data channel 110 and a plurality of command interfaces 120 .

[0044] The read data channel 110 includes a buffer 112 and a selector 111 . The buffer 112 is connected to the selector 111 and is configured with multiple buffer areas. The selector 111 is used to connect to a memory that outputs read data.

[0045] The buffer 112 can be various types of memories, such as SRAM (Static Random-Access Memory), DRAM (Dynamic Random Access Memory), PSRAM (Pseudo Static Random-Access Memory), etc.

[0046] After generating the configuration command, the DPU stores the configuration command in a memory for the DPU to read from the memory. The image processor DPU includes multiple image processing modules, and the configuration command is used to configure different image processing modules.

[0047] Please refer to Figure 2, which is a schematic diagram of the buffer storage space provided in one embodiment of the present application. In this embodiment, since there are multiple command interfaces 120, the storage space of the buffer 112 can be divided into multiple buffer areas, each corresponding to a command interface 120, so that each buffer area can be used to store the read data corresponding to each command interface 120. The size of the buffer area can be set as required. For example, the size of a buffer area can be 256 bytes, 512 bytes, etc.

[0048] In some embodiments, the buffer areas corresponding to each command interface share the space of the buffer, and the storage space corresponding to each buffer area is dynamically allocated according to the number of read data corresponding to each command interface in the buffer. For example, there are 10 command interfaces, corresponding to 10 buffer areas, and the 10 buffer areas share the storage space of one buffer. A buffer can store 10 read data. If the storage space is evenly divided, the 10 buffer areas are allocated to the space for storing 1 read data. In this embodiment, storage space can be allocated to each buffer area according to the number of read data input to the buffer and the command interface corresponding to each read data. The maximum storage space allocated to a buffer area can be equal to the storage space of the buffer, and the minimum can be 0. For example, when 9 read data input are data corresponding to command interface 1, and 1 read data is data corresponding to command interface 2, the buffer area corresponding to command interface 1 can be allocated to the storage space for storing 9 read data, and the buffer area corresponding to command interface 2 can be allocated to the storage space for storing 1 read data. The other buffer areas are not allocated storage space, that is, 0. The above is only an example and should not be used as a limitation to this application.

[0049] In this embodiment, the read data includes configuration commands and identification information. The configuration commands include parameters for configuring each image processing module in the display processor. For details, please refer to the prior art and will not be elaborated here. The identification information identifies the buffer area corresponding to the read data and can be information that identifies the buffer area, such as an address or number. Furthermore, since the buffer area corresponds to the command interface, the identification information also identifies the command interface.

[0050] At the same time, in order to store each read data into the corresponding buffer area, a selector 111 can be set between the buffer 112 and the memory outside the command configuration unit 100, and the selector 111 can store the data into the corresponding buffer area according to the identification information.

[0051] A plurality of command interfaces 120 are respectively connected to the buffer 112 , and each of the command interfaces 120 is configured to correspond to a different buffer area; each of the command interfaces 120 is used to connect to the image processing module.

[0052] In an embodiment of the present application, the selector 111 is configured to receive read data and store the read data in a corresponding buffer area according to the identification information; each command interface 120 is configured to obtain the read data from the corresponding buffer area and configure the image processing module based on the configuration command in the read data. Thus, before the configuration command is output to each image processing module of the display processor, the read data can be transmitted between the memory and the buffer 112 according to the bandwidth of the transmission bus (such as 128 bits, 256 bits, etc.), and stored by the delay buffer 112. Each command interface 120 is connected to the image processing module to convert the read data into data that meets the bandwidth of the image processing module (such as 32 bits). Through the parallel operation of multiple command interfaces 120, the transmitted read data can be processed in a timely manner. Through the buffer 112, the transmission of read data can better utilize the bandwidth of the transmission bus, and through the command interface 120, the transmitted read data can be used. The parallel operation of multiple command interfaces 120 can improve the configuration efficiency of multiple image processing modules. Therefore, the command configuration unit 100 can improve bandwidth utilization and configuration efficiency of image processing modules.

[0053] In some embodiments, the command configuration unit 100 is configured with a control unit (not shown in the figure). The control unit can be a control circuit or a combination of multiple control circuits. The control unit is configured with various control logics to control the coordinated operation of various components of the command configuration unit 100 through the control logic. In some embodiments, the control unit can be a controller of a display processor.

[0054] Please refer to FIG. 3 , which is a schematic diagram of an expansion of the command configuration unit 100 provided in an embodiment of the present application.

[0055] In one embodiment, the command configuration unit 100 may further include: a read request channel 130, the read request channel 130 includes multiple read request generators 131, each read request generator 131 corresponds to a different command interface 120; each read request generator 131 is used to send a read request to the memory; the memory is configured to send read data to the buffer 112 in response to the read request.

[0056] The display processor obtains configuration commands by sending read requests to an external memory. In this embodiment of the present application, there are multiple command interfaces 120. If the display processor were to generate read requests one by one, the efficiency of generating read requests would be low, and the utilization of the transmission bus bandwidth would also be low. Therefore, in this embodiment, multiple read request generators 131 can be provided for different command interfaces 120 to generate multiple read requests in parallel, and then send the read requests to the memory to obtain read data. This reduces the waiting time when generating read requests, improves the efficiency of generating read requests, and thus improves the configuration efficiency of the image processing module.

[0057] In the aforementioned embodiment, the number of the read request generators 131 , the command interfaces 120 , and the buffer areas may be the same as the number of the image processing modules in the display processor.

[0058] In one embodiment, the read request channel 130 may further include a read request arbitrator 132; the read request arbitrator 132 is connected to each read request generator 131 and is used to connect to the memory; the read request arbitrator 132 is configured to control the output order of each read request based on a preset output priority rule.

[0059] Display processors typically read memory sequentially, meaning read requests are typically issued one at a time. For example, when using an Advanced eXtensible Interface (AXI) bus as the transmission bus, the AXI interface only allows one read request to be issued simultaneously. However, some image processing modules in the display processor have high real-time requirements. If multiple read requests are generated simultaneously and the requests of these image processing modules are configured to wait for output, the subsequently acquired read data may not meet the requirements of these image processing modules.

[0060] Therefore, for this type of image processing module, a read request arbiter 132 can be configured to connect the output of each read request generator 131 to the read request arbiter 132. The read requests are arbitrated by the read request arbiter 132 before being output to the memory. Output priority rules are configured in the read request arbiter 132 to control the output order of the read requests based on the output priority rules.

[0061] The priority rules can be configured according to the requirements of the image processing module in the display processor. The read request arbitrator 132 can be an arbitration circuit that implements polling arbitration, weighted polling arbitration, etc. The arbitration circuit can refer to the existing technology and will not be described here.

[0062] In one embodiment, the read data channel 110 further includes an address buffer 113. The address buffer 113 is connected to the buffer 112 and each command interface 120, and is configured to store the write address of the read data in the buffer area and the read address of the read data read out of the buffer area.

[0063] In this embodiment, read data is stored in the buffer area of ​​the buffer 112. However, the same buffer area may store multiple read data. Therefore, the read data in the buffer area needs to be distinguished to distinguish between read data that can be read and read data that can be overwritten. Therefore, an address buffer can be provided, and the address buffer is connected to the buffer 112 and each command interface 120. The address buffer is used to record the write address of the read data in the buffer area and the read address of the read data after it is read. This allows the command interface 120 to determine whether there is any unread read data in the buffer 112 based on the write address and the read address. If there is any unread read data, the read data can be obtained from the buffer 112.

[0064] Accordingly, after determining the corresponding buffer area through identification information, the selector 111 may obtain a read address corresponding to the buffer area to determine the storage space in the buffer area that can be overwritten.

[0065] In the above embodiment, the address buffer 113 can be implemented by an existing buffer, which will not be elaborated here.

[0066] In some embodiments, the read data channel 110 may further include a base address memory group 114 . The base address memory group 114 includes a plurality of base address memories. The address buffer 113 is connected to each command interface 120 through each base address memory.

[0067] The command interface 120 may not have the function of determining the read address and the write address. In this embodiment, a base address memory may be set to obtain the readable write address of the buffer area from the corresponding buffer of the address cache 113 through the base address memory and provide it to the corresponding command interface 120.

[0068] The base address memory may be an existing memory with a storage function. For example, the base address memory may be a FIFO (First Input First Output) memory, a register, or the like.

[0069] In one embodiment, the read data channel 110 may further include a buffered read arbiter 115 . The buffered read arbiter 115 is connected to the buffer 112 and each command interface 120 . The buffered read arbiter 115 is configured to instruct each command interface 120 to obtain read data from the buffer 112 .

[0070] Similar to the principle of the read request arbiter 132, when the command interface 120 reads the buffer 112, usually only one command interface 120 is allowed to read the buffer 112 at the same time. Accordingly, in this embodiment, if multiple command interfaces 120 need to read the buffer 112 at the same time, the buffer read arbiter 115 can be used to instruct each command interface 120 to read in sequence to reduce the possibility of data loss and reading errors.

[0071] Next, the command interface 120 currently allowed to receive read data can be configured to obtain read data with priority, and the read request arbiter 132 can preferentially instruct the command interface with priority to obtain read data. For example, referring to FIG4 , after the buffered read arbiter determines the command interface to obtain read data, it will feed back the command interface and the write address of the read data to the buffer, so that the command interface can obtain the read data from the buffer area of ​​the buffer according to the write address.

[0072] In the embodiment of the present application, the read data is in a format that adapts to the bandwidth of the transmission bus and may not be directly connected to the image processing module. The command interface 120 needs to convert the data into a data format that can be used by the image processing module. This conversion process is time-consuming, and in this case, the command interface 120 may not be able to receive or be allowed to receive the read data. Accordingly, in this embodiment, the command interface 120 that is allowed to receive read data can be given priority to obtain the read data.

[0073] In some embodiments, the preset read priority rules can also be configured according to the real-time requirements of the read data corresponding to the image processing module of each command interface 120, or in other ways. The buffered read arbitrator 115 can refer to the existing arbitration circuit, which will not be expanded here.

[0074] In one embodiment, each command interface 120 may include a command buffer 121 and a command parser. The command buffer 121 is connected to the buffer 112 . The command buffer 121 is connected to the command parser. The command parser is used to connect to the image processing module.

[0075] Since the bandwidth of the transmission bus may not match the interface bandwidth of the display processor, the command interface 120 needs to convert the bandwidth of the read data so that the configuration commands in the read data can be used to configure the image processing module in the display processor.

[0076] In this embodiment, command buffer 121 is used to store read data obtained from buffer 112. The command parser is used to output the read data to the image processing module in a preset format to configure the image processing module. The preset format can be the size of the data, for example, 4 bytes, 32 bytes, etc. The data size corresponding to the preset format is the same as the interface bandwidth of the image processing module.

[0077] Command buffer 121 can temporarily store read data. This allows for storing multiple read data items, reducing storage pressure on buffer 112. Furthermore, the size of data corresponding to the preset format is typically smaller than the size of a single read data item, making it difficult for the command parser to convert the read data all at once. Temporarily storing read data in command buffer 121 reduces the possibility of data loss. Thus, command buffer 121 and the command parser allow read data to be transmitted before being output to the display processor, rather than at the interface bandwidth of the display processor. This transmission bandwidth is typically greater than the interface bandwidth of the display processor, thereby improving bandwidth utilization during read data transmission.

[0078] In one embodiment, the command parser includes a first parser 122 or a second parser 123 .

[0079] In the display processor, configuration commands include common commands and coefficient commands. The first parser 122 is used to convert common commands into a preset format, and the second parser 123 is used to convert coefficient commands. The image processing modules configured based on common commands typically have the same interface bandwidth. Therefore, the output bandwidth of each first parser 122 is the same and corresponds to the bandwidth of the display processor module.

[0080] The coefficient command is used to configure the image processing module including the 3D LUT in the display processor. The interface width of such display processor modules may be different. For example, the width of some display processor modules is 36 bits, and that of others is 48 bits. If the output bandwidth of the command parser is uniform and 32 bits, the command parser needs to send the same configuration command twice, which may make it impossible to fully utilize the bandwidth in the second transmission.

[0081] The second parser 123 is configured to output the read data to the image processing module according to the size of the output bandwidth of the second parser 123; the output bandwidth of the second parser 123 in each command interface 120 matches the bandwidth of each image processing module with a three-dimensional lookup table in the display processor.

[0082] In the embodiments of the present application, for different image processing modules including 3D LUTs, the command interface 120 in the corresponding command interface 120 can be configured as the second parser 123, and the output bandwidth of the second parser 123 can be configured to match the bandwidth of the image processing module. As a result, for such image processing modules including 3D LUTs, there is no need to transmit a single configuration command multiple times, effectively utilizing the interface bandwidth and improving the efficiency of coordination with the image processing module.

[0083] The command configuration unit 100 can convert the bit width of read data into a bit width acceptable to the image processing module interface. This allows for transmission of read data and read requests based on the bandwidth of a transmission bus that is larger than the bit width of the image processing module interface. This improves transmission bandwidth utilization and enhances display processor configuration efficiency. Furthermore, the command configuration unit 100 allows for the request or parsing of multiple configuration commands to be performed in parallel, further enhancing display processor configuration efficiency.

[0084] For ease of understanding, an example is provided herein for illustration, which should not be construed as limiting the present application. Referring to Figures 5 and 6 , Figure 5 is a schematic diagram illustrating the operation of a read request channel according to an embodiment of the present application, and Figure 6 is a schematic diagram illustrating the reception and parsing of read data according to an embodiment of the present application.

[0085] In this example, the number of command interfaces 120 is configured to be 20, corresponding to 20 read request generators 131 and 20 buffer areas. The read request arbiter 132 uses a circuit corresponding to weighted round-robin arbitration. The buffer area can store 256 bytes of data. The interface width between the command interface 120 and the image processing module is 4 bytes, and the transmission bus between the memory and the command configuration unit 100 is 32 bytes.

[0086] First, as shown in Figure 5, each read request generator 131 generates a read request corresponding to each image processing module according to the control of the display processor controller. The read request may include an identifier and / or address corresponding to the storage area of ​​the read data in the memory, and is sent to the memory through the read request arbitrator 132.

[0087] 6, the selector 111 determines the corresponding buffer area based on the identification information of the read data obtained from the memory and allocates a write address, and then stores the read data into the corresponding buffer area. For another example, the size of each buffer area is 256 bytes, and the read and write unit is 64 bytes.

[0088] Then, the write address and the read address are provided to the base address memory, which determines the write address of the read data to be read and provides the write address to the corresponding command interface 120. The read and write unit is 64 bytes, so 64 bytes of read data can be written each time.

[0089] The buffer read arbiter 115 controls each command interface 120 to obtain read data from the buffer area of ​​the buffer 112 according to a preset read priority rule. In addition, if there is read data to be read out of the buffer area, the address buffer 113 records the corresponding read address.

[0090] The read data acquired by each command interface 120 is stored in the command buffer 121, and waits for the command parser to convert the read data into a preset format and output it to the image processing module to configure the image processing module. The command buffer 121 can read the buffer 112 at a bandwidth of 64 bytes, and each command interface can output the converted read data at a 4-byte rate. The command interface with the second parser can parse read data including coefficient commands, while the command interface with the first parser can parse read data including general commands.

[0091] Based on the same inventive concept, an embodiment of the present application further provides a command configuration method, which includes a command configuration unit 100 that can be applied to the aforementioned embodiment.

[0092] Please refer to Figure 7, which is a flowchart of a command configuration method provided in an embodiment of the present application. The command configuration method includes:

[0093] S210, receiving read data through the selector.

[0094] S220 , storing the read data into a corresponding buffer area according to the identification information of the received read data through a selector.

[0095] S230 , obtaining read data from a buffer area corresponding to the command interface through the command interface.

[0096] S240: Configure the display processor based on the configuration command in the read data through the command interface.

[0097] In one embodiment, before the selector receives the read data, each read request generator 131 may send a read request to the memory, so that the memory sends the read data to the buffer in response to the read request.

[0098] In one embodiment, after each read request generator 131 sends a read request to the memory, the output order of each read request may be controlled by the read request arbiter 132. The read request arbiter 132 is configured to control the output order of each read request based on a preset output priority rule.

[0099] In one embodiment, after the selector stores the read data in the corresponding buffer area based on the identification information of the received read data, the address buffer 113 may also store the write address of the read data in the buffer area and the read address of the read data read from the buffer area. Accordingly, S230 includes obtaining the read data from the buffer area corresponding to the command interface using the command interface and the write address.

[0100] In one embodiment, after the address buffer 113 stores the write address of the read data in the buffer area and the read address of the read data read out of the buffer area, the base address memory may also provide a write address for the command interface connected to the base address memory.

[0101] In one embodiment, obtaining read data from a buffer area corresponding to the command interface through the command interface may further include: obtaining read data from the buffer according to a read priority rule preset in the buffer read arbiter 115 .

[0102] In one embodiment, the display processor is configured based on the configuration commands in the read data through the command interface, including: storing the read data obtained from the buffer based on the command buffer 121; and outputting the read data to the image processing module in a preset format based on the command parser to configure the image processing module.

[0103] In one embodiment, outputting read data to an image processing module in a preset format based on a command parser includes: parsing a configuration command including a coefficient command based on a second parser 123. The coefficient command is used to configure an image processing module having a three-dimensional lookup table. The second parser 123 is configured to output the read data to the image processing module based on an output bandwidth of the second parser 123; the output bandwidth of the second parser 123 in each command interface matches the bandwidth of each image processing module having a three-dimensional lookup table in the display processor.

[0104] Based on the same inventive concept, an embodiment of the present application further provides a display processor. Referring to FIG8 , FIG8 is a schematic diagram of a display processor provided by an embodiment of the present application, the display processor comprising: a command configuration unit 100 and a plurality of image processing modules 210 .

[0105] Multiple image processing modules 210 are respectively connected to the command interface of the command configuration unit 100. The command configuration unit 100 provided in any of the above embodiments may be referred to, and the image processing module 210 may refer to the image processing module in the existing display processor, which will not be expanded here.

[0106] Based on the same inventive concept, an embodiment of the present application further provides an electronic device. Referring to FIG9 , FIG9 is a schematic diagram of an electronic device 300 provided in an embodiment of the present application. The electronic device 300 includes a display processor 200 , a controller 310 , and a memory 320 .

[0107] The display processor 200 may be the display processor 200 provided in the aforementioned embodiment. For details, please refer to the above text and will not be elaborated here.

[0108] The controller and the memory may be existing devices. For example, the controller 310 may be a CPU, and the memory 320 may be a DRAM. The controller, the memory, and the display processor 200 are connected to each other through a bus image.

[0109] In the embodiment of the present application, the controller 310 is configured to generate read data and store the read data in the memory; the memory 320 is configured to output the read data to the display processor 200 in response to a read request from the display processor. The functions of the controller 310 and the memory 320 in the electronic device can be referred to in the prior art and will not be further described here.

[0110] In one embodiment, the memory 320 is configured with multiple storage areas, each storage area corresponds to a different command interface; each storage area is configured to store read data corresponding to each command interface.

[0111] By partitioning the memory 320 , read data can be obtained from a corresponding storage area according to identification information corresponding to the command interface in the read request, so as to configure the display processor.

[0112] Based on the same inventive concept, an embodiment of the present application further provides an image display system. Referring to FIG. 10 , FIG. 10 is a schematic diagram of an image display system provided in an embodiment of the present application. The image display system 400 includes an electronic device 300 and a display device 410. The electronic device 300 may be any of the electronic devices provided in the aforementioned embodiments.

[0113] The display device 410 is connected to the electronic device 300 for communication, and is used to receive and display image data output by the display processor in the electronic device 300 .

[0114] In some embodiments, the display device may be disposed within the electronic device as a part of the electronic device structure.

[0115] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0116] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A command configuration unit, characterized in that: include: A read data channel, comprising a buffer and a selector, wherein the buffer is connected to the selector, and the buffer is configured with a plurality of buffer areas; the selector is used to be connected to a memory for outputting read data, wherein the read data comprises a configuration command and identification information, wherein the configuration command comprises parameters for configuring each image processing module in the display processor, and the identification information represents a buffer area corresponding to the read data; A plurality of command interfaces, each of which is connected to the buffer, and each of which is configured to correspond to a different buffer area; Each of the command interfaces is used to connect to the image processing module; Wherein, the selector is configured to receive the read data and store the read data into a corresponding buffer area according to the identification information; Each of the command interfaces is configured to obtain the read data from the corresponding buffer area, and configure the image processing module based on the configuration command in the read data.

2. The command configuration unit according to claim 1, characterized in that: The command configuration unit further includes: a read request channel, the read request channel includes a plurality of read request generators, each of the read request generators corresponds to a different command interface; Each of the read request generators is used to send a read request to the memory; the memory is configured to send the read data to the buffer in response to the read request.

3. The command configuration unit according to claim 2, characterized in that: The read request channel further includes a read request arbitrator; the read request arbitrator is connected to each of the read request generators and is used to connect to the memory; The read request arbitrator is configured to control the output order of each of the read requests based on a preset output priority rule.

4. The command configuration unit according to claim 1, characterized in that: The read data channel further includes: an address buffer connected to the buffer and each of the command interfaces, respectively, the address buffer being configured to store a write address of the read data in the buffer area and a read address of the read data read out of the buffer area; The command interface is configured to read the read data from the buffer area according to the write address; The selector is configured to store the read data into a corresponding buffer area according to the read address and the identification information.

5. The command configuration unit according to claim 4, characterized in that: The read data channel further comprises a base address memory group, the base address memory group comprises a plurality of base address memories, and the address buffer is connected to each of the command interfaces respectively through each of the base address memories; The base address memory is used to provide the write address for the command interface connected to the base address memory after the read data is stored in the buffer area.

6. The command configuration unit according to claim 4, characterized in that: The read data channel also includes a buffer read arbitrator; the buffer read arbitrator is connected to the buffer and each of the command interfaces respectively; The buffer read arbitrator is configured to instruct each of the command interfaces to obtain the read data from the buffer.

7. The command configuration unit according to claim 1, characterized in that: The buffer areas corresponding to the command interfaces share the storage space of the buffer, and the storage space corresponding to each buffer area is allocated according to the amount of read data corresponding to each command interface in the buffer.

8. The command configuration unit according to any one of claims 1 to 7, characterized in that: Each of the command interfaces comprises a command buffer and a command parser, wherein the command buffer is connected to the buffer, and the command buffer is connected to the command parser; the command parser is used to connect to the image processing module; The command buffer is used to store the read data obtained from the buffer; The command parser is used to output the read data to the image processing module in a preset format to configure the image processing module.

9. The command configuration unit according to claim 8, characterized in that: The command parser includes a first parser or a second parser; The configuration command includes a coefficient command, and the coefficient command is used to configure an image processing module having a three-dimensional lookup table; The second parser is configured to output the read data to the image processing module according to the size of the output bandwidth of the second parser; The output bandwidth of the second parser in each of the command interfaces matches the bandwidth of each of the image processing modules having the three-dimensional lookup table in the display processor.

10. A display processor, characterized in that: include: The command configuration unit according to any one of claims 1 to 9; A plurality of image processing modules are respectively connected to the command configuration unit.

11. An electronic device, characterized in that: include: The display processor as claimed in claim 10; A controller and a memory, wherein the memory is connected to the controller and the display processor respectively; The controller is configured to generate the read data and store the read data in the memory; The memory is configured to output the read data to the display processor in response to a read request of the display processor.

12. A command configuration method, characterized in that: Applied to a command configuration unit, the command configuration unit comprises: a read data channel, the read data channel comprises a buffer and a selector, the buffer is connected to the selector, the buffer is configured with a plurality of buffer areas; the selector is used to connect to a memory that outputs read data, the read data comprises a configuration command and identification information, the configuration command comprises a parameter for configuring a display processor, the identification information represents a buffer area corresponding to the read data; a plurality of command interfaces, each of the command interfaces is respectively connected to the buffer, and each of the command interfaces is respectively configured to correspond to a different buffer area; each of the command interfaces is used to connect to the display processor; The command configuration method comprises: receiving the read data through the selector; storing the read data into a corresponding buffer area according to the identification information of the received read data by the selector; Acquire the read data from the buffer area corresponding to the command interface through the command interface; The display processor is configured through the command interface based on the configuration commands in the read data.

Images