Semiconductor packaging structure and manufacturing method thereof

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor package structure includes: a substrate; the first tube core is positioned on the substrate, and an active surface of the first tube core is opposite to the substrate; a second die on the active surface of the first die, the second die being electrically connected to the first die through a plurality of conductive terminals; and a sealing structure on the active surface of the first die, the sealing structure surrounding the plurality of conductive terminals and abutting the second die, thereby forming a cavity between the first die and the second die.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of May 12, 2020, application number 202010401528.5, and invention name “Semiconductor packaging structure and manufacturing method thereof”. Technical Field

[0003] The present disclosure relates to a package of a micro-electromechanical system (MEMS) device, and more particularly to a package of a large die size MEMS device that increases product yield. Background Art

[0004] A piezoelectric micromachined ultrasonic transducer (PMUT) is a MEMS device that operates in response to the flexural motion of a thin membrane coupled to a thin piezoelectric film rather than the thickness mode motion of a piezoelectric ceramic plate as in a bulk piezoelectric ultrasonic transducer. It should be noted that a PMUT is a type of micromachined ultrasonic transducer (MUT). Compared to bulk piezoelectric ultrasonic transducers, PMUTs can offer various advantages such as increased bandwidth, flexible geometry, intrinsic acoustic impedance matching with water or air, reduced voltage requirements, mixing with different resonant frequencies, and the possibility of integration with supporting electronic circuits (especially for miniaturized high-frequency applications). Summary of the invention

[0005] In some embodiments, the present disclosure provides a semiconductor packaging structure, which includes: a substrate; a first tube core, the first tube core is located on the substrate, wherein the active surface of the first tube core is facing away from the substrate; a second tube core, the second tube core is located on the active surface of the first tube core, and the second tube core is electrically connected to the first tube core through a plurality of conductive terminals; and a sealing structure, the sealing structure is located on the active surface of the first tube core, the sealing structure surrounds the plurality of conductive terminals and is adjacent to the second tube core, thereby forming a cavity between the first tube core and the second tube core.

[0006] In some embodiments, the present disclosure provides a semiconductor packaging structure, which includes: a substrate; a first tube core, the first tube core is located on the substrate; a second tube core, the second tube core is located on the first tube core, the second tube core has a plurality of unit areas, each of the unit areas has a membrane part, a transmitting part connected to the membrane part, and a receiving part connected to the membrane part; and a sealing structure, the sealing structure surrounds the plurality of unit areas.

[0007] In some embodiments, the present disclosure provides a method for manufacturing a semiconductor packaging structure, the method comprising: (1) setting a first tube core and a second tube core; (2) bonding the second tube core to the first tube core through a plurality of conductive terminals; (3) forming a sealing structure on the first tube core surrounding the plurality of conductive terminals and adjacent to the second tube core, thereby forming a cavity between the first tube core and the second tube core. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 When reading the following detailed description, various aspects of the present disclosure can be easily understood according to the following detailed description. It should be noted that various features may not necessarily be drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0009] Figure 1 A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0010] Figure 1A According to some embodiments of the present disclosure, Figure 1 A top view of the semiconductor package structure viewed from the AA interface.

[0011] Figure 1B According to some embodiments of the present disclosure, Figure 1 A top view of the semiconductor package structure viewed from the AA interface.

[0012] Figure 2 A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0013] Figure 3 A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0014] Figure 4 A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E Some embodiments of the present disclosure are shown Figure 1 A cross-sectional view of a semiconductor package structure.

[0016] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E and Fig. 6F Some embodiments of the present disclosure are shown Figure 2 A cross-sectional view of a semiconductor package structure.

[0017] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F Some embodiments of the present disclosure are shown Figure 3 A cross-sectional view of a semiconductor package structure.

[0018] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F Some embodiments of the present disclosure are shown Figure 4 A cross-sectional view of a semiconductor package structure.

[0019] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E and Fig.9F Some embodiments of the present disclosure are shown Figure 4 A cross-sectional view of a semiconductor package structure. DETAILED DESCRIPTION

[0020] Throughout the drawings and detailed description, common reference numerals are used to refer to the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0021] Spatial descriptions such as "above", "below", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "higher", "lower", "upper", "above", "below", etc. are specified with respect to the orientation of a component or a group of components or a plane of a component or a group of components for the one or more components as shown in the relevant drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that such arrangement does not deviate from the advantages of the embodiments of the present disclosure.

[0022] Conventional PMUT packaging operations utilize eutectic wafer bonding, such as AlGe, as signal connections between the PMUT die and the CMOS die. Eutectic wafer bonding also provides a vacuum cavity for individual PMUT cells including at least a membrane, a transducer surface including a transmitting portion and a receiving portion.

[0023] In some applications where the size of the PMUT die increases, the number of PMUT cells per PMUT die and thus the number of eutectic bonding sites per PMUT die inevitably increases. In the scenario of high eutectic bonding sites per PMUT die, the eutectic bonding technology has a strong impact on the PMUT packaging yield. Such applications include ultrasound equipment for medical sensing, where the sensing resolution is positively correlated with the size of the PMUT die.

[0024] The present disclosure provides a PMUT packaging structure without eutectic bonding. Conventional eutectic bonding is replaced by a bump structure, such as a solder bump and / or a copper pillar. The layout of the PMUT package is also changed. In the present disclosure, an air cavity is formed to cover multiple PMUT units, while conventionally, a vacuum cavity is formed by eutectic bonding to cover a single PMUT unit.

[0025] refer to Figure 1 , Figure 1 1 shows a cross-sectional view of a semiconductor package structure 10 according to some embodiments of the present disclosure. The semiconductor package structure 10 includes a substrate 100, a die 101 disposed on the substrate 100 and having a back side 101B connected to the substrate 100, for example. An active surface 101A of the die 101 is opposite to the back side 101B and faces away from the substrate 100. In some embodiments, as Figure 1 As shown, electrical connections such as bond wires 135 connect the active surface 101A of the die 101 with the upper surface of the underlying substrate 100 .

[0026] The substrate 100 may include circuitry and / or a redistribution layer (RDL) structure ( Figure 1 1 and 1 ). The substrate 100 may include a solder mask (SM) structure, one or more conductive pads, one or more patterned conductive traces, and one or more interconnects (e.g., one or more through-holes). The substrate 100 may include ceramics, semiconductor materials (e.g., silicon, high-resistance silicon, high-resistivity silicon, or other suitable semiconductor materials), dielectric materials, glass, or other suitable materials.

[0027] In some embodiments, the die 101 connected to the substrate 100 may include an application specific integrated circuit (ASIC) die. The semiconductor package structure 10 further includes a die 102 stacked on an active surface 101A of the die 101. The die 102 and the die 101 are electrically connected through a number of conductive terminals 102A disposed on a surface 102A' of the die 102. An electrical signal generated from the die 102 can be transmitted to the die 101 through the conductive terminals 102A. In addition, the die 102 is bonded to the die 101 through the conductive terminals 102A.

[0028] In some embodiments, die 102 may include a piezoelectric material, which may be exemplified as aluminum nitride (AlN), however, it should be understood that many materials that exhibit piezoelectric behavior may be utilized alternatively without departing from the teachings of the present invention. By way of example and not limitation, the material may be selected for use from a group of materials that exhibit piezoelectric behavior, including apatite, barium titanate (BaTiO 3 ), Berlin Stone (AlPO 4 ), various ceramic materials, aluminum phosphate, gallium nitride (GaN), gallium orthophosphate, lanthanum gallium silicate, lead tantalate scandate, lead magnesium niobate (PMN), lead zirconate titanate (PZT), lithium tantalate, polyvinylidene fluoride (PVDF), potassium sodium tartrate, quartz (SiO 2 ), zinc oxide (ZnO), and other materials and combinations. By way of example and not limitation, one class of ceramic materials that exhibit piezoelectric properties is a ceramic structure that exhibits a perovskite tungsten bronze structure, including BaTiO 3 , KNbO 3 , Ba 2 NeA 5 O 5 、LiNbO 3 、SrTiO 3 、Pb(ZrTi)O 3 , Pb 2 Kb 5 O 15 、LiTaO 3 、BiFeO 3 、Na x WO 3 In some embodiments, the vertical protrusion area of ​​die 102 is smaller than the vertical protrusion area of ​​die 101 , for example, the vertical protrusion area of ​​a PMUT die is smaller than that of an ASIC die.

[0029] The semiconductor package structure 10 further includes a sealing structure 120 disposed on the active surface 101A of the die 101 and abutting the edge of the die 102 at the surface 102A′. Figure 1 From the cross-sectional view shown, the sealing structure 120 clamps or laterally surrounds the conductive terminal 102A at the surface 102A' of the tube core 102. From the perspective of the top view, as will be described in the present disclosure Figure 1A and Figure 1BAs shown in , the sealing structure 120 can completely surround the conductive terminal 102A from all sides of the tube core 102. In some embodiments, the height of the sealing structure 120 is greater than the spacing between the tube core 101 and the tube core 102, and therefore, the sealing structure 120 can effectively seal the space between the tube core 101 and the tube core 102 from all sides of the tube core 102. The cavity 130 can be defined by the surface 102A' of the tube core 102, the active surface 101A of the tube core 101, and the sidewalls of the sealing structure 120. A plurality of conductive terminals 102A connecting the tube core 101 and the tube core 102 are accommodated in the cavity 130, or are sealed in the cavity 130. In some embodiments, the sealing structure 120 can be composed of a high viscosity dielectric material, such as a high viscosity polymer, which prevents contamination of the surface 102A' of the tube core 102 during application.

[0030] In some embodiments, the cavity 130 is filled with air or is an air cavity. Unlike conventional PMUT packages, the cavity 130 of the present disclosure is an air cavity with a pressure substantially higher than a vacuum level. In contrast, due to the fact that ultrasound can only propagate through a medium, vacuum cavities are widely used in PMUT packages to guide ultrasound propagation away from the vacuum cavity. Compared to vacuum cavity counterparts, the air cavity adopted in the present disclosure can propagate more ultrasound in proportion in the direction toward the cavity 130, thereby generating reflections at material interfaces and in heterogeneous materials. In order not to generate excessive noise caused by reflections, the present disclosure further provides an absorption layer 131 between the back side 101B and the substrate 100, and the absorption layer is configured to absorb ultrasound propagating toward the substrate 100. In some embodiments, a die attach layer ( Figure 1 ) to connect the die 101 and the substrate 100. In some embodiments, multiple die attach layers ( Figure 1 For example, a die attach layer may be disposed between the substrate 100 and the absorption layer 131, and another die attach layer may be disposed between the absorption layer 131 and the die 101. In some embodiments, the sealing structure 120 may be a weir structure.

[0031] In some embodiments, Figure 1 As shown, the conductive terminal 102A may be made of a solder material, for example, a solder joint may be used to electrically and mechanically connect the tube die 102 and the tube die 101. The semiconductor package structure 10 further includes an encapsulation material 111 covering the back side 102B' of the tube die 102. The encapsulation material 111 may further cover the sidewalls of the tube die 102 and the sealing structure 120. Figure 1As shown, the semiconductor package structure 10 may further include another encapsulant 112 on the substrate 100, which encapsulates the die from the sidewalls of the die 101 and a portion of the active surface 101A. In addition to surrounding the plurality of conductive terminals 102A between the die 102 and the die 101, the encapsulant 112 may further contact and surround the encapsulant 111. In some embodiments, both the encapsulant 111 and the encapsulant 112 are in contact with the sealing structure 120. In some embodiments, the material of the encapsulant 111 may be different from the material of the encapsulant 112, for example, the encapsulant 112 may be composed of epoxy resin, resin, or molding material with various fillers, while the encapsulant 111 may be composed of silicone or epoxy resin without any fillers. In some embodiments, the material of the encapsulant 111 may be selected to have an impedance substantially close to the impedance of the human body with respect to ultrasound.

[0032] refer to Figure 1A , Figure 1A According to some embodiments of the present disclosure, Figure 1 The die 102 includes a plurality of unit regions 150, each of the unit regions 150 includes a membrane portion 150A, and a transducer interface having at least a receiving portion 1502A / 102A and a transmitting portion 1502B / 102A. The receiving portion 1502A / 102A may include a conductive line 1502A electrically coupling a layer of the membrane portion 150A and a conductive terminal 102A, and the transmitting portion 1502B / 102A may include another layer of the membrane portion 150A electrically coupling a conductive line 1502B of the conductive terminal 102A. For example, referring to Figure 1 and Figure 1A , the receiving portion 1502A / 102A and the transmitting portion 1502B / 102A electrically connect the membrane portion 150A to the active surface 101A of the die 101 so that each of the PMUT cells can individually communicate with the die 101. As previously discussed, the conductive terminals 102A can be formed of solder material.

[0033] like Figure 1A As shown, by way of example and not limitation, the die 102 may include a five-by-two array of PMUT cell regions 150, and the sealing structure 120 surrounds the five-by-two array of PMUT cell regions 150. In other words, the sealing structure surrounds a plurality of PMUT cell regions 150 without separating adjacent PMUT cell regions 150. Figure 1A The circular PMUT shape seen in FIG. 1 is not intended to be construed as a circular PMUT shape, but the present disclosure may be implemented in a range of geometric shapes without departing from the present disclosure. Figure 1B , Figure 1B According to some embodiments of the present disclosure, Figure 1 A top view of the semiconductor package structure viewed from the AA interface. Figure 1B Similar to Figure 1A , except that the membrane portion 150A may be quadrangular rather than circular. By way of example and not limitation, the receiving portion 1502A / 102A may be connected to the short side of the membrane portion 150A, and the transmitting portion 1502B / 102A may be connected to the long side of the membrane portion 150A.

[0034] refer to Figure 2 , Figure 2 1 shows a cross-sectional view of a semiconductor package structure 20 according to some embodiments of the present disclosure. The semiconductor package structure 20 is similar to the semiconductor package structure 10, but has a different sealing structure 120 / 120' and a different conductive terminal 102A. Figure 2 As shown, in addition to the solder joint 1022A, the conductive terminal 102A may further include a copper pillar 1021A extending from the active surface 101A of the die 101 toward the die 102. In some embodiments, one copper pillar 1021A is connected to one solder joint 1022A, and the solder joint is configured to electrically and mechanically connect the die 102 and the die 101. The sealing structure 120 / 120' of the semiconductor package structure 20 includes a dielectric wall 120' disposed on the active surface 101A of the die 101 and a dam structure 120 sealed between the dielectric wall 120' and the sidewall or edge of the die 102. Figure 2 As shown, the aspect ratio of the dielectric wall 120' is greater than the aspect ratio of the conductive terminal 102A, so as to utilize the dam structure 120 to seal the space between the tube die 102 and the tube die 101. Under the condition of similar occupied area, the height of the dielectric wall 120' is greater than the height of the conductive terminal 102A. The dam structure 120, the dielectric wall 120', the tube die 101 and the tube die 102 completely define a cavity 130 that accommodates a plurality of conductive terminals 102A. As previously described, the cavity 130 is filled with air or the cavity is an air cavity.

[0035] Figure 3 1 shows a cross-sectional view of a semiconductor package structure 30 according to some embodiments of the present disclosure. The semiconductor package structure 30 is similar to the semiconductor package structure 20, but the arrangement of the encapsulation material 112 and the sealing structure 120 / 120' of the semiconductor package structure is different. Figure 3As shown, the upper surface of the encapsulant 112 is substantially coplanar with the dielectric wall 120' of the sealing structure 120 / 120'. The encapsulant 111 of the semiconductor package structure 30 is positioned on the substantially coplanar upper surface of the encapsulant 112 and the dielectric wall 120' of the sealing structure 120 / 120' without being surrounded by the encapsulant 112. The encapsulant 111 may also cover the back side 102B' of the die 102, the sidewalls of the die 102, and the dam structure 120 of the sealing structure 120 / 120'.

[0036] Figure 4 1 shows a cross-sectional view of a semiconductor package structure 40 according to some embodiments of the present disclosure. The semiconductor package structure 40 is similar to the semiconductor package structure 30, but does not contain the encapsulation material 112. Figure 4 As shown, encapsulant 111 covers not only die 102 but also die 101 below die 102. Considering the mechanical properties of the film portion of die 102, a molding material operation that may exert pressure on the object to be molded is prevented from being applied over die 102. Therefore, a relatively soft encapsulant 111 such as silicone is used for general molding of semiconductor package structure 40.

[0037] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E Some embodiments of the present disclosure are shown Figure 1 FIG. 1 is a cross-sectional view of a semiconductor package structure 10. Figure 5A In the embodiment of the present invention, a die 102, such as a MEMS die or a PMUT die, is provided, and a ball drop operation is performed on the PMUT die bumps. Figure 1A and Figure 1B As shown, an array of conductive terminals 102A is arranged on the surface 102A' of the die 102 according to the positions of the plurality of unit regions 150. Figure 5B In the embodiment of the present invention, the die attach layer ( Figure 5B 101B) is bonded to the substrate 100 at the back side 101B of the substrate 100. In the current operation, the semiconductor substrate 100 may be in the form of a strip or panel. A plurality of dies 101 are picked and placed on the substrate 100. Subsequently, conductive wires 135 are formed by a wire bonding operation to electrically connect the active surface 101A of the die 101 and the conductive pads or conductive traces (not shown) of the substrate 100. Optionally, an absorption layer 131 configured to absorb ultrasonic waves passing through the die 102 may be formed between the die 101 and the substrate 100.

[0038] exist Figure 5CIn the embodiment, an open cavity molding operation is applied to form an encapsulant 112 on the substrate 100 that surrounds the tube core 101 and encapsulates the bonding wires 135. The active surface 101A of the tube core 101 is not covered by the encapsulant 112 and is ready to be connected with the tube core 102. As previously described, the encapsulant 112 formed by the open cavity mode can be a resin, an epoxy resin, or a molding material with various fillers. The thickness of the encapsulant 112 is designed to be greater than the sum of the thicknesses of the tube core 101 and the tube core 102. Figure 5D In the embodiment, the die 102 implanted with the conductive terminals 102A is bonded to the active surface 101A of the die 101 by a reflow operation. In some embodiments, the size of the die 102 is smaller than the size of the die 101, so that all the conductive terminals 102A on the die 102 can be bonded to the corresponding conductive pads on the die 101, wherein a portion of the active surface 101A of the die 101 is occupied by the encapsulation material 112. In an embodiment of the present invention, a low-residue flux reflow or a flux-free reflow (e.g., formic acid reflow) can be used to reduce or minimize the volume of flux after the reflow operation.

[0039] exist Figure 5E In the process, a sealing structure 120 is formed on the active surface 101A of the tube core 101, and the sealing structure surrounds the conductive terminal 102A. The sealing structure can be a dam structure composed of a high-viscosity dielectric material that does not flow under the tube core 102 and does not contaminate the active components of the tube core 102, such as the piezoelectric surface, the membrane surface, or the transducer surface. In some embodiments, forming the sealing structure 120 includes performing a dispensing operation. Then, more fluid encapsulant 111 is applied to cover the back side of the tube core 102 and the fluid encapsulant is restricted by the encapsulant 112. Because the sealing structure 120 is formed before the encapsulant 111 is applied, such encapsulant 111 may not enter the space between the tube core 102 and the tube core 101, thereby creating a cavity 130 that accommodates multiple conductive terminals 102A. In some embodiments, the cavity 130 is an air cavity. Subsequently, the substrate 100 is separated from the encapsulant 112 by a packaging saw operation, and a Figure 1 A semiconductor package structure 10 is provided.

[0040] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E Some embodiments of the present disclosure are shown Figure 2 FIG. 2 is a cross-sectional view of a semiconductor package structure 20. Fig. 6AIn the present invention, a wafer (e.g., a wafer including multiple die 101 regions) is set, and a copper pillar bumping operation is performed at the wafer level to form multiple copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die regions 101 regions. The solder paste is then reflowed to form solder bumps 1022A. The combination of solder bumps 1022A and copper pillars 1021A may be referred to as conductive terminals 102A of the semiconductor package structure 20. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A, a reduced solder paste volume may be used. In the present invention, a copper pillar bumping operation is performed at the wafer level to form multiple copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die regions 101. The solder paste is then reflowed to form solder bumps 1022A. The combination of solder bumps 1022A and copper pillars 1021A may be referred to as conductive terminals 102A of the semiconductor package structure 20. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A. Figure 6B In the process, a patterned dielectric layer is formed on a wafer having a plurality of die 101 regions. From a cross-sectional view, a dielectric wall 120' is formed by a photoresist patterning operation to surround the conductive terminal 102A in each of the die 101 regions. Subsequently, the wafer is segmented to form a plurality of separate dies 101.

[0041] exist Figure 6C In the present embodiment, the separated dies 101 are bonded to the substrate at the back side 101B of the substrate 100. In the present operation, the semiconductor substrate 100 may be in the form of a strip or a panel. A plurality of dies 101 are picked and placed on the substrate 100. Subsequently, a conductive wire 135 is formed by a wire bonding operation to electrically connect the active surface 101A of the die 101 and a conductive pad or conductive trace (not shown) of the substrate 100. Optionally, a conductive pad configured to absorb the active surface 101A of the die 101 and the conductive pad 135 may be formed between the die 101 and the substrate 100. Fig. 6E The ultrasonic wave absorbing layer 131 is shown in FIG. Fig.6D In the embodiment of the present invention, an open-mouth molding operation is applied to form an encapsulant 112 on the substrate 100 that surrounds the die 101 and encapsulates the bonding wires 135. In some embodiments, the height of the dielectric wall 120' is greater than the height of the conductive terminals 102A, so that the protrusions of the molding shell used in the open-mouth molding operation can abut the top of the dielectric wall 120' without contacting the top of the conductive terminals 102A. The active surface 101A of the die 101 is not covered by the encapsulant 112 and is ready to be bonded to the die 102 (at Fig. 6E As previously described, the encapsulant 112 formed by the open cavity mode can be a resin, epoxy resin or a molding material with various fillers. The thickness of the encapsulant 112 is designed to be greater than the sum of the thicknesses of the tube core 101 and the tube core 102.

[0042] exist Fig. 6EIn the embodiment of the present invention, a reflow operation is performed to bond another die 102 (e.g., a MEMS die or a PMUT die) to the die 101 at the surface 102A' of the other die 102. On the substrate 100, a plurality of dies 102 are picked and placed on top of a plurality of dies 101. In an embodiment of the present invention, a low-residue flux reflow or a flux-free reflow (e.g., formic acid reflow) may be used to reduce or minimize the volume of flux after the reflow operation. Fig. 6F In the embodiment of the present invention, a weir structure 120 is formed to separate the dielectric wall 120' from the edge or sidewall of the tube core 102. The sealing structure 120 / 120' surrounds the conductive terminal 102A. The weir structure 120 can be composed of a high viscosity dielectric material that does not flow under the tube core 102 and does not contaminate the active components of the tube core 102, such as the piezoelectric surface, the membrane surface, or the transducer surface. In some embodiments, forming the weir structure 120 includes performing a dispensing operation. Then, more fluid encapsulant 111 is applied to cover the back of the tube core 102 and the fluid encapsulant is limited by the encapsulant 112. Because the sealing structure 120 / 120' is formed before the encapsulant 111 is applied, such encapsulant 111 may not enter the space between the tube core 102 and the tube core 101, thereby creating a cavity 130 that accommodates multiple conductive terminals 102A. In some embodiments, the cavity 130 is an air cavity. Subsequently, the substrate 100 is separated from the encapsulation material 112 by a packaging saw operation, and the Figure 2 A semiconductor package structure 20 is provided.

[0043] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F Some embodiments of the present disclosure are shown Figure 3 FIG. 3 is a cross-sectional view of a semiconductor package structure 30. Fig. 7A In the process, a wafer (e.g., a wafer including multiple die 101 regions) is set, and a copper pillar bumping operation is performed at the wafer level to form multiple copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die regions 101 regions. The solder paste is then reflowed to form solder bumps 1022A. The combination of solder bumps 1022A and copper pillars 1021A may be referred to as conductive terminals 102A of the semiconductor package structure 30. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A, a reduced solder paste volume may be used. In the process, a copper pillar 102A may be formed on the wafer level to form a plurality of copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die regions 101. The solder paste is then reflowed to form solder bumps 1022A. The combination of solder bumps 1022A and copper pillars 1021A may be referred to as conductive terminals 102A of the semiconductor package structure 30. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A. Figure 7BIn the process, a patterned dielectric layer is formed on a wafer having a plurality of die 101 regions. From a cross-sectional view, a dielectric wall 120' is formed by a photoresist patterning operation to surround the conductive terminal 102A in each of the die 101 regions. Subsequently, the wafer is segmented to form a plurality of separate dies 101.

[0044] exist Figure 7C In the present embodiment, the separated dies 101 are bonded to the substrate at the back side 101B of the substrate 100. In the present operation, the semiconductor substrate 100 may be in the form of a strip or a panel. A plurality of dies 101 are picked and placed on the substrate 100. Subsequently, a conductive wire 135 is formed by a wire bonding operation to electrically connect the active surface 101A of the die 101 and a conductive pad or conductive trace (not shown) of the substrate 100. Optionally, a conductive pad configured to absorb the active surface 101A of the die 101 and the conductive pad 135 may be formed between the die 101 and the substrate 100. Fig. 7E The ultrasonic wave absorbing layer 131 is shown in FIG. Fig.7D In the embodiment of the present invention, a flat die molding operation is applied to form an encapsulant 112 on the substrate 100 that surrounds the die 101 and encapsulates the bonding wires 135. In some embodiments, the upper surface of the encapsulant 112 is substantially coplanar with the upper surface of the dielectric wall 120'. In some embodiments, the upper surface of the encapsulant 112 may be non-coplanar with the upper surface of the dielectric wall 120', for example by having a step gap. The active surface 101A of the die 101 is not covered by the encapsulant 112 and is ready to be bonded to the die 102 (at the Fig. 7E As previously described, the encapsulant 112 formed by the open cavity mode can be a resin, epoxy resin or a molding material with various fillers. The thickness of the encapsulant 112 is designed to be greater than the sum of the thicknesses of the tube core 101 and the conductive terminal 102A.

[0045] exist Fig. 7E In the embodiment of the present invention, a reflow operation is performed to bond another die 102 (e.g., a MEMS die or a PMUT die) to the die 101 at the surface 102A' of the other die 102. On the substrate 100, a plurality of dies 102 are picked and placed on top of a plurality of dies 101. In an embodiment of the present invention, a low-residue flux reflow or a flux-free reflow (e.g., formic acid reflow) may be used to reduce or minimize the volume of flux after the reflow operation. Figure 7FIn the process, a dam structure 120 is formed to separate the dielectric wall 120' from the edge or sidewall of the tube core 102. The sealing structure 120 / 120' surrounds the conductive terminal 102A. The dam structure 120 can be composed of a high viscosity dielectric material that does not flow under the tube core 102 and does not contaminate the active components of the tube core 102, such as the piezoelectric surface, the membrane surface or the transducer surface. Then, more fluid encapsulant 111 is applied to cover the back side of the tube core 102 and the fluid encapsulant is confined by the encapsulant 112. Because the sealing structure 120 / 120' is formed before the encapsulant 111 is applied, such encapsulant 111 may not enter the space between the tube core 102 and the tube core 101, thereby creating a cavity 130 that accommodates multiple conductive terminals 102A. In some embodiments, the cavity 130 is an air cavity. Subsequently, the substrate 100 is separated from the encapsulant 112 by a packaging saw operation, and a Figure 3 A semiconductor package structure 30 is provided.

[0046] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F Some embodiments of the present disclosure are shown Figure 4 FIG. 4 is a cross-sectional view of a semiconductor package structure 40. Fig. 8A In the present invention, a wafer (e.g., a wafer including multiple die 101 regions) is set, and a copper pillar bumping operation is performed at the wafer level to form multiple copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die regions 101 regions. The solder paste is then reflowed to form solder bumps 1022A. The combination of the solder bumps 1022A and the copper pillars 1021A may be referred to as conductive terminals 102A of the semiconductor package structure 40. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A, a reduced solder paste volume may be used. In the present invention, a copper pillar bumping operation is performed at the wafer level to form multiple copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die regions 101. The solder paste is then reflowed to form solder bumps 1022A. The combination of the solder bumps 1022A and the copper pillars 1021A may be referred to as conductive terminals 102A of the semiconductor package structure 40. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A, a reduced solder paste volume may be used. Figure 8B In some embodiments, the wafer level is performed to bond another die 102 (eg, a MEMS die or a PMUT die) to the wafer containing the plurality of die 101 regions at the surface 102A′ of the other die 102 by a reflow operation. Figure 8B Compared with the operation in the previous figure, no encapsulation material is formed after the die 102 is bonded to the die 101 area on the wafer, and a flux cleaning operation can be performed in the current embodiment to remove flux residues near the solder joints, such as Figure 8C Then, the wafer having the plurality of die 101 regions 101 is separated to form a plurality of dies 101 , each of which is bonded to at least die 102 .

[0047] exist Fig.8D In the embodiment, the separated dies 101 are bonded to the substrate 100 at their back sides 101B. In the current operation, the semiconductor substrate 100 may be in the form of a strip or a panel. A plurality of dies 101 are picked and placed on the substrate 100. Subsequently, a conductive wire 135 is formed by a wire bonding operation to electrically connect the active surface 101A of the die 101 and a conductive pad or conductive trace (not shown) of the substrate 100. Optionally, an absorption layer 131 configured to absorb ultrasonic waves passing through the die 102 may be formed between the die 101 and the substrate 100. In the embodiment, the semiconductor substrate 100 may be bonded to the back side 101B of the separated dies 101. In the embodiment, the semiconductor substrate 100 may be bonded to the back side 101B of the separated dies 101. In the embodiment, the semiconductor substrate 100 may be bonded to the back side 101B of the separated dies 101. Fig. 8E In the embodiment, a sealing structure 120 is formed on the active surface 101A of the tube core 101, and the sealing structure surrounds the conductive terminal 102A. The sealing structure can be a weir structure composed of a high viscosity dielectric material that does not flow under the tube core 102 and does not contaminate the active components of the tube core 102, such as the piezoelectric surface, the membrane surface, or the transducer surface. Fig.8F In the embodiment of the present invention, more fluid encapsulant 111 is then applied over substrate 100 to encapsulate die 101 and die 102. Because sealing structure 120 is formed before encapsulant 111 is applied, such encapsulant 111 may not enter the space between die 102 and die 101, thereby creating cavity 130 that accommodates multiple conductive terminals 102A. In some embodiments, cavity 130 is an air cavity. Subsequently, substrate 100 is separated from encapsulant 111 by a package saw operation, and a package is obtained. Figure 4 A semiconductor package structure 40 is provided.

[0048] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E and Fig.9F Some embodiments of the present disclosure are shown Figure 4 FIG. 4 is a cross-sectional view of a semiconductor package structure 40. Fig.9A In the process, a wafer (e.g., a wafer including multiple die 101 regions) is set, and a copper pillar bumping operation is performed at the wafer level to form multiple copper pillars 1021A and solder paste on each of the copper pillars 1021A in each of the die 101 regions. The solder paste is then reflowed to form solder bumps 1022A. The combination of solder bumps 1022A and copper pillars 1021A may be referred to as conductive terminals 102A of a semiconductor package structure 40. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A, a reduced solder paste volume may be used. Subsequently, the wafer having multiple die 101 regions is separated to form multiple separated die 101. In the process, a plurality of copper pillars 1021A and copper pillars 1021A are formed on the wafer level. The solder paste is then reflowed to form solder bumps 1022A. The combination of solder bumps 1022A and copper pillars 1021A may be referred to as conductive terminals 102A of a semiconductor package structure 40. In some embodiments, in order to prevent excessive solder from contaminating the active surface 101A of the die 101 and causing bridging between adjacent conductive terminals 102A. Fig. 9BIn the embodiment, the separated dies 101 are bonded to the substrate 100 at the back side 101B of the separated dies 101. In the current operation, the semiconductor substrate 100 may be in the form of a strip or a panel. A plurality of separated dies 101 are picked and placed on the substrate 100. Optionally, a substrate 102 configured to absorb the heat from the die 102 (in the substrate 100) may be formed between the die 101 and the substrate 100. Fig. 9C ) an absorbing layer 131 for emitting ultrasonic waves.

[0049] exist Fig. 9C In the embodiment, another die 102 (e.g., a MEMS die or a PMUT die) is bonded to each of the separated dies 101 at a surface 102A' of the other die 102 by a reflow operation. Compared with the operation in the previous figure, no encapsulation material is formed after the die 102 is bonded to the die 101. In the current embodiment, a flux cleaning operation can be performed to remove flux residues near the solder joints, such as Fig. 9C As shown. Fig.9D In the embodiment, conductive wires 135 are formed by a wire bonding operation to electrically connect active surface 101A of die 101 and conductive pads or conductive traces (not shown) of substrate 100 .

[0050] exist Fig.9E In the embodiment, a sealing structure 120 is formed on the active surface 101A of the tube core 101, and the sealing structure surrounds the conductive terminal 102A. The sealing structure can be a weir structure composed of a high viscosity dielectric material that does not flow under the tube core 102 and does not contaminate the active components of the tube core 102, such as the piezoelectric surface, the membrane surface, or the transducer surface. Fig.9F In the embodiment of the present invention, more fluid encapsulant 111 is then applied over substrate 100 to encapsulate die 101 and die 102. Because sealing structure 120 is formed before encapsulant 111 is applied, such encapsulant 111 may not enter the space between die 102 and die 101, thereby creating cavity 130 that accommodates multiple conductive terminals 102A. In some embodiments, cavity 130 is an air cavity. Subsequently, substrate 100 is separated from encapsulant 111 by a package saw operation, and a package is obtained. Figure 4 A semiconductor package structure 40 is provided.

[0051] As used herein and not otherwise defined, the terms "substantially," "substantially," "approximately," and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may encompass instances where the event or situation occurs precisely as well as instances where the event or situation occurs close to occurring. For example, when used in conjunction with a numerical value, the terms may encompass a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to a position difference of two surfaces positioned along the same plane within a few microns, such as a position difference positioned along the same plane within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

[0052] As used herein, the singular terms "a / an" and "the" may include plural referents unless the context clearly indicates otherwise. In the description of some embodiments, another component disposed "on" or "over" a component may encompass the case where the former component is directly located on (e.g., physically in contact with) the latter component as well as the case where one or more intermediate components are positioned between the former component and the latter component.

[0053] Although the present disclosure has been described and shown with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the spirit and scope of the present disclosure as defined by the claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically shown. The specification and the drawings should be considered illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material formations, methods or processes suitable for the goals, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or rearranged to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless otherwise expressly indicated herein, the order and grouping of operations are not limited.

Claims

1. A semiconductor packaging structure, include: a first tube core; a second tube die, the second tube die is located on the first tube die, the second tube die includes a plurality of unit regions, Each of the cell regions is connected to the first die via a conductive terminal; as well as A sealing structure surrounds the plurality of cell regions, wherein the sealing structure, the first die, and the second die form an air cavity for accommodating the conductive terminal. 2 . The semiconductor package structure according to claim 1 , further comprising an encapsulation material surrounding the first die, and the sealing structure is separated from the encapsulation material. 3 . The semiconductor package structure according to claim 2 , wherein the encapsulant has a sidewall that is not perpendicular to a top surface of the first die. 4 . The semiconductor package structure according to claim 3 , wherein the sealing structure has a curved surface facing the sidewall of the encapsulant. 5 . The semiconductor package structure according to claim 2 , wherein a gap is provided between the encapsulation material and the sealing structure, and a top surface of the first die is exposed through the gap. The semiconductor package structure according to claim 1 , wherein the sealing structure covers a portion of a sidewall of the second die. 7 . The semiconductor package structure according to claim 1 , each of the unit regions includes a membrane portion, a receiving portion connected to the membrane portion, and a transmitting portion connected to the membrane portion.

8. A semiconductor packaging structure, include: a first tube core; a second tube die, the second tube die is located on the first tube die, and the second tube die is connected to the first tube die via a conductive terminal; as well as A sealing structure, wherein the sealing structure, the first tube core and the second tube core form an air cavity for accommodating the conductive terminal, and the sealing structure includes a first portion vertically overlapping with the second tube core. 9 . The semiconductor package structure according to claim 8 , wherein the sealing structure comprises a second portion that does not vertically overlap with the second die. 10 . The semiconductor package structure according to claim 9 , wherein the second portion of the sealing structure is located below a horizontally extending line of a bottom surface of the second die. 11 . The semiconductor package structure according to claim 8 , wherein the second die is a micro-electromechanical system die or a piezoelectric micro-machined ultrasonic transducer. 12 . The semiconductor package structure according to claim 8 , further comprising an encapsulation material surrounding the first die, and the first portion of the sealing structure is separated from the encapsulation material. 13 . The semiconductor package structure according to claim 12 , wherein a height of a top of the encapsulant relative to a top surface of the first die is higher than a height of a top of the sealing structure relative to the top surface of the first die.

14. A semiconductor packaging structure, include: a first tube core; A second die is located on the first die, and the second die is connected to the first die via a plurality of conductive terminals; as well as A sealing structure, the sealing structure, the first tube core and the second tube core form an air cavity accommodating the plurality of conductive terminals, wherein the sealing structure contacts a side wall of the second tube core. 15 . The semiconductor package structure according to claim 14 , wherein a height of a top of one of the plurality of conductive terminals relative to a top surface of the first die is lower than a height of a top of the sealing structure relative to the top surface of the first die.

16. The semiconductor package structure according to claim 14, wherein the plurality of conductive terminals include a first conductive terminal adjacent to the sealing structure, and the first conductive terminal has a sidewall facing the sealing structure, wherein the distance between the sidewall of the first conductive terminal and the sidewall of the sealing structure is non-uniform.

17. The semiconductor packaging structure according to claim 14, wherein the plurality of conductive terminals include a first conductive terminal adjacent to the sealing structure and a second conductive terminal adjacent to the first conductive terminal, and a first distance between the sealing structure and the first conductive terminal is different from a second distance between the first conductive terminal and the second conductive terminal. The semiconductor package structure according to claim 14 , wherein the first distance is smaller than the second distance. 19 . The semiconductor package structure of claim 14 , wherein the sealing structure contacts a bottom surface of the second die.

20. A semiconductor packaging structure, include: a first tube core; A second tube die is located on the first tube die, and the second tube die is connected to the first tube die via a conductive terminal; as well as An encapsulant surrounds the first die and is spaced apart from the second die.

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