Stress compensation method for a support-free arrangement of a silicon structure

Abstract

The invention relates to a method for stress compensation of a silicon structure arranged without support in a cavity formed in a monocrystalline silicon semiconductor substrate, comprising the following steps: forming a cavity in the monocrystalline silicon semiconductor substrate by means of a monocrystalline silicon semiconductor layer of the silicon semiconductor substrate spanning the cavity, according to the invention, a polycrystalline silicon semiconductor layer is formed such that it is arranged directly on the monocrystalline silicon semiconductor layer at least in sections, by structuring the monocrystalline silicon semiconductor layer spanning the cavity and / or the polycrystalline silicon semiconductor layer, at least one unsupported silicon structure is formed, which is arranged in the region of the cavity and is connected to the silicon semiconductor substrate surrounding the cavity via at least one attachment structure. The invention also relates to a semiconductor element and a sensor.

Description

Technical Field

[0001] The invention relates to a method for compensating stresses in a silicon structure arranged unsupported in a cavity formed in a monocrystalline silicon semiconductor substrate, a semiconductor component and a sensor. Background Art

[0002] The published patent application DE 10 2004 043 356 A1 discloses a sensor element having a cavity formed by a recess.

[0003] The published document DE 10 2019 210 285 A1 discloses a method for producing a buried cavity in a semiconductor substrate.

[0004] Patent document US10,626,008B2 discloses a micro-electromechanical device.

[0005] Publication CN 103 604 538A discloses a method for manufacturing a MEMS pressure sensor.

[0006] Publication CN 105 486 435A discloses a method for manufacturing a MEMS polysilicon nano-membrane pressure sensor chip.

[0007] Publication US 2010 / 0006840 A1 discloses a method for manufacturing a MEMS / NEMS structure. Summary of the invention

[0008] The object of the present invention is to provide a concept for compensating for stresses in silicon structures which are arranged unsupported in cavities formed in a monocrystalline silicon semiconductor substrate.

[0009] This object is achieved by means of the present invention. Advantageous embodiments of the present invention are the subject of further developments.

[0010] According to a first aspect, a method for compensating stress of a silicon structure arranged unsupported in a cavity formed on a single-crystal silicon semiconductor substrate is provided, comprising the following steps:

[0011] - forming a cavity in a single crystal silicon semiconductor substrate using a single crystal silicon semiconductor layer of the silicon semiconductor substrate that spans the cavity,

[0012] - forming the polycrystalline silicon semiconductor layer in such a way that it is arranged at least in sections directly on the monocrystalline silicon semiconductor layer,

[0013] By structuring the silicon semiconductor layer across the cavity, at least one free-standing silicon structure is formed which is arranged in the region of the cavity and is connected to the silicon semiconductor substrate surrounding the cavity via at least one attachment structure.

[0014] According to a second aspect, there is provided a semiconductor device having:

[0015] A single crystal silicon semiconductor substrate, in which a cavity is formed using a single crystal silicon semiconductor layer of the silicon semiconductor substrate spanning the cavity, wherein a polycrystalline silicon semiconductor layer is directly arranged at least in sections on the single crystal silicon semiconductor layer spanning the cavity, wherein at least one silicon structure arranged unsupported in the cavity region is formed, wherein the silicon structure is formed by the silicon semiconductor layer spanning the cavity and the silicon structure is connected to the silicon semiconductor substrate surrounding the cavity via at least one attachment structure.

[0016] According to a third aspect, a sensor is provided, comprising a semiconductor element according to the second aspect and a sensor element arranged on a freestanding silicon structure of the semiconductor element and comprising a semiconductor layer system.

[0017] The following abbreviations or names may be used in the text below:

[0018] MEMS: micro-electro-mechanical systems.

[0019] ASIC: application-specific integrated circuit (English: application-specific integrated circuit).

[0020] The semiconductor layer may be simply referred to as a layer.

[0021] Silicon can be abbreviated as Si.

[0022] Single crystal can be abbreviated as single crystal.

[0023] Polycrystalline can be abbreviated as polycrystalline.

[0024] The semiconductor substrate may be simply referred to as a substrate.

[0025] The groove can also be referred to by the English concept "trench".

[0026] The trench structure can therefore be referred to as a channel structure.

[0027] The single crystal silicon semiconductor layer of the silicon semiconductor substrate spanning the cavity may also be simply referred to as a single crystal silicon semiconductor layer.

[0028] The semiconductor substrate is a single crystal silicon semiconductor substrate even if this is not explicitly stated.

[0029] The substrate is, for example, a silicon wafer.

[0030] For example, in an epitaxial reactor or in the case of polycrystalline silicon, the deposition of silicon and the growth of a monocrystalline and / or polycrystalline silicon layer can also be carried out by deposition by means of, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD) or atomic layer deposition (ALD) or sputtering processes. Alternatively, a polycrystalline silicon layer can first be deposited and optionally structured so that before a further silicon layer is applied in the epitaxial reactor, regions with monocrystalline silicon and regions with polycrystalline silicon are present on a substrate surface. Depending on the crystallinity of the substrate surface, the further layer grows monocrystalline and / or polycrystalline on the substrate surface in the epitaxial reactor.

[0031] LPCVD: Low Pressure Chemical Vapor Deposition,

[0032] PECVD: Plasma Enhanced Chemical Vapor Deposition,

[0033] APCVD: Atmospheric Pressure Chemical Vapor Deposition,

[0034] ALD: Single atomic layer deposition.

[0035] The solution described here is based on the fact that stress compensation is generated for the single-crystalline silicon semiconductor layer spanning the cavity and / or for at least one single-crystalline silicon structure arranged unsupported in the cavity region and connected to the surrounding substrate via at least one attachment structure for stress decoupling by means of a polycrystalline silicon semiconductor layer grown directly on the single-crystalline silicon semiconductor layer spanning the cavity (the polycrystalline silicon semiconductor layer can optionally be applied in an epitaxial reactor). Therefore, the polycrystalline silicon semiconductor layer is a stress compensation layer and has a stress compensation function.

[0036] According to the prior art described above, there are methods that make it possible to produce a cavity completely surrounded by monocrystalline silicon (monokristallines Silizium). If the monocrystalline silicon layer spanning the cavity is structured in such a way that the MEMS and / or ASIC structures / circuits provided can be implemented on this layer in a stress-decoupled manner relative to the surrounding monocrystalline silicon substrate, there may be a risk that the additional layers or layer sequences provided / necessary for implementing the MEMS and / or ASIC structures / circuits lead to bending of the monocrystalline silicon structures arranged in a stress-decoupled manner relative to the monocrystalline silicon substrate in the cavity region. In particular, in the case of large areas of unsupported monocrystalline silicon regions (here, for example, unsupported monocrystalline silicon structures that are only partially connected to the surrounding substrate) and small distances between the unsupported monocrystalline silicon structures and the bottom of the cavity surrounding the unsupported monocrystalline silicon structures, contact between the unsupported monocrystalline silicon structures and the silicon substrate may occur, which may deteriorate or eliminate the desired stress decoupling advantages. Furthermore, the temperature dependence of the MEMS and / or ASIC (measurement) signals may be impaired by the bending of the free-standing single-crystal silicon structure, which would require additional effort for a corresponding correction of the (measurement) signals.

[0037] By arranging a polysilicon region, currently a polysilicon semiconductor layer, on a monocrystalline silicon layer that at least partially spans the cavity, in particular at least in the region of the stress-decoupled monocrystalline silicon region, and thus in the region of the unsupported monocrystalline silicon structure, the bending of the monocrystalline silicon structure arranged in the cavity region caused by the additional layer arranged on the unsupported monocrystalline silicon structure can be compensated. For example, by corresponding doping and / or deposition conditions and / or by a subsequent annealing step in a defined atmosphere, in particular polycrystalline silicon layers can be produced, which can produce additional compressive stresses or tensile stresses, which can resist or compensate for the bending of the unsupported monocrystalline silicon structure, in general, the bending of the monocrystalline silicon layer that at least partially spans the cavity. In addition, by depositing / growing one or more polycrystalline silicon layers, in particular in an epitaxial reactor, a polycrystalline silicon layer with a thickness of several microns to tens of microns can be produced in a short time. In addition, these polycrystalline silicon layers can be used to at least partially change / influence the surface mobility of silicon atoms and thus change / influence the precipitation behavior.

[0038] Thus, by depositing / growing a polysilicon layer at least partially directly on at least one single-crystalline silicon structure arranged unsupported in the cavity region, a silicon layer is produced, which allows stress compensation of the single-crystalline silicon structure arranged unsupported and other layers deposited / grown on the single-crystalline silicon structure arranged unsupported. These other layers can, for example, consist of materials used according to standards for realizing, for example, MEMS and / or ASIC structures / circuits. For example, the following materials are listed: SiO2, Si3N4, SiRiN (silicon-rich silicon nitride), SiON (silicon oxynitride), doped / undoped polysilicon, gold, platinum, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, titanium tungsten, copper, tungsten, chromium, nickel, lead zirconate titanate (PZT), metal silicide, aluminum oxide, aluminum optionally with additives such as silicon and / or copper. In addition, metal silicides used according to standards in MEMS and / or ASIC structures / circuits, for example in the region of electrical contact structures / contact structures, such as titanium silicide, tantalum silicide, platinum silicide, can also be listed.

[0039] In one embodiment of the method, it is provided that forming the cavity by means of a single-crystalline silicon semiconductor layer spanning the cavity also includes forming a polycrystalline silicon semiconductor layer, wherein silicon is deposited directly on the single-crystalline silicon semiconductor layer in such a way that a polycrystalline silicon semiconductor layer is produced.

[0040] This results in the technical advantage that, for example, a polycrystalline silicon semiconductor layer can be effectively arranged on a single-crystalline silicon semiconductor layer at least partially spanning the cavity and / or on a single-crystalline silicon structure arranged free-standing in the region of the cavity.

[0041] In one embodiment of the method, silicon is deposited directly on a single-crystalline silicon semiconductor layer and / or a single-crystalline silicon substrate in such a way that a polycrystalline silicon starting layer is formed, wherein the polycrystalline silicon starting layer is subsequently structured in such a way that the silicon starting layer is removed in one or more regions of the single-crystalline silicon semiconductor layer and / or the single-crystalline silicon substrate, wherein, after the starting layer is structured, further silicon is deposited in such a way that in one or more regions where polycrystalline silicon of the polycrystalline silicon starting layer is present on the single-crystalline silicon semiconductor layer and / or the single-crystalline silicon substrate, the deposited further silicon polycrystal grows, and in one or more regions where the polycrystalline silicon starting layer has been removed, the deposited further silicon single crystal grows.

[0042] This results in the technical advantage, for example, that polysilicon regions for stress compensation / stress influencing can be formed in and / or on a monocrystalline silicon substrate and / or in and / or on a monocrystalline free-standing silicon structure.

[0043] "In" or "on" is understood here as follows: there may be polycrystalline silicon regions surrounded by single crystal silicon and / or there may be single crystal silicon regions surrounded by polycrystalline silicon (-> in) and / or there may be polycrystalline silicon regions arranged directly on a single crystal silicon basis (e.g. a silicon substrate) and / or directly on an unsupported silicon structure (-> on).

[0044] In one embodiment of the method, it is provided that, in order to form a cavity, starting from the surface of a single-crystalline silicon semiconductor substrate, a trench structure having a plurality of trenches is produced in the single-crystalline silicon semiconductor substrate, wherein before producing the trench structure, a polycrystalline silicon starting layer is produced at least in sections directly on the surface of the single-crystalline silicon semiconductor substrate, so that after the cavity is formed, the single-crystalline silicon semiconductor layer of the silicon semiconductor substrate spanning the cavity has at least in sections a polycrystalline silicon starting layer on the surface, wherein additional silicon is deposited on the single-crystalline silicon semiconductor layer spanning the cavity and having at least in sections a polycrystalline silicon starting layer on the surface, so that in the area where polycrystalline silicon of the polycrystalline silicon starting layer is present on the single-crystalline silicon semiconductor layer, the deposited silicon polycrystal grows, and in the area where there is no polycrystalline silicon starting layer, the deposited silicon single crystal grows.

[0045] This results in, for example, the following technical advantage: a polycrystalline silicon semiconductor layer can be formed efficiently.

[0046] In one embodiment of the method, it is provided that, after at least sectionally producing a polysilicon starting layer, etching of silicon is performed in a single-crystal silicon semiconductor substrate starting from the bottom region of the trench, so that a continuous cavity is formed below the trench structure starting from the bottom region of the trench and an unsupported gate structure is formed from single-crystal silicon, which gate structure has at least sectionally a polysilicon starting layer on the surface, wherein the trench is closed by depositing a further silicon layer on the gate structure spanning the cavity.

[0047] This results in, for example, the following technical advantage: the trench can be effectively closed.

[0048] In one embodiment of the method, it is provided that after the trenches have been closed, an annealing step is carried out in a hydrogen-containing atmosphere in order to transfer silicon atoms in the trench structure in such a way that the silicon semiconductor layer spanning the cavity is monocrystalline adjacent to the cavity and polycrystalline on its surface.

[0049] This results in the following technical advantage, for example: silicon atoms can be efficiently transferred in the trench structure, so that a silicon semiconductor layer is efficiently formed which is monocrystalline adjacent to the cavity and polycrystalline at the surface.

[0050] In one embodiment of the method, provision is made for the trench structure to be produced after at least sectionally producing the polysilicon starting layer, wherein after producing the trench structure an additional polysilicon starting layer is also deposited on the side walls of the trench.

[0051] This results in, for example, the technical advantage that silicon also grows polycrystalline on the side walls of the trench. This also results in, for example, the technical advantage that the trench can be effectively closed.

[0052] In one embodiment of the method, it is provided that a polysilicon starting layer is at least sectionally produced on a single-crystal silicon semiconductor substrate before producing a (final) trench structure, in that a first trench structure having a plurality of first trenches is produced in the single-crystal silicon semiconductor substrate, wherein silicon is subsequently deposited in such a way that the plurality of first trenches are at least partially filled with polysilicon to produce a first trench structure at least partially filled with polysilicon, wherein the (final) trench structure is subsequently produced starting from the bottom of the areas of the first trenches of the first trench structure that are not completely filled into the single-crystal silicon semiconductor substrate.

[0053] This results in the following technical advantage, for example: trenches of a trench structure can be efficiently produced. A trench produced in this way has in particular polycrystalline and monocrystalline silicon on its side walls, so that silicon can grow locally polycrystalline and / or monocrystalline on the side walls of the trench as explained above.

[0054] In one embodiment of the method, an unsupported single-crystalline silicon structure is attached to a surrounding single-crystalline silicon semiconductor substrate via at least one attachment structure, wherein a polycrystalline silicon semiconductor layer is arranged such that it is at least sectionally arranged directly on the unsupported single-crystalline silicon structure and / or directly on a section of the single-crystalline silicon semiconductor layer spanning the cavity including the attachment structure.

[0055] This results in, for example, the technical advantage of effective stress decoupling of the structure from the semiconductor substrate and additional stress compensation in regions free of supporting structures.

[0056] In one embodiment of the method, it is provided that, after forming and optionally structuring the polycrystalline silicon semiconductor layer, silicon is deposited on the silicon semiconductor layer in order to grow at least one further polycrystalline silicon semiconductor layer.

[0057] This results in the technical advantage that a particularly effective stress compensation can be achieved. The polysilicon semiconductor layer forms a starting layer for the further silicon to be grown.

[0058] The same applies analogously to the semiconductor components and sensors with regard to the method, and vice versa.

[0059] This means, in particular, that method features result from corresponding semiconductor component features and / or sensor features, and vice versa.

[0060] The semiconductor component according to the second aspect is produced, for example, by means of the method according to the first aspect.

[0061] The term “directly” means “direkt.” This means that there are no further layers between the polycrystalline silicon semiconductor layer and the monocrystalline silicon semiconductor layer.

[0062] The sensor is, for example, a pressure sensor, in particular a capacitive pressure sensor.

[0063] The monocrystalline and / or polycrystalline silicon semiconductor layer spanning the cavity forms, for example, a diaphragm, in particular a diaphragm of a sensor. A free-standing silicon structure is to be understood as a structure which is produced from monocrystalline and / or polycrystalline silicon semiconductor layers and is arranged free-standing in the region of the cavity, wherein further layers or layer sequences can be arranged on the free-standing silicon structure for realizing MEMS and / or ASIC structures / circuits.

[0064] In one embodiment of the method, after forming the polycrystalline silicon semiconductor layer or after forming the at least one further polycrystalline silicon semiconductor layer, a sensor element is arranged on a single crystal and / or polycrystalline silicon semiconductor layer, in particular on a free-standing silicon structure. The sensor element comprises, for example, a semiconductor layer system.

[0065] In one embodiment of the method, it is provided that, for forming the cavity, a trench structure having a plurality of trenches is produced in the monocrystalline silicon semiconductor substrate starting from the upper side of the monocrystalline silicon semiconductor substrate.

[0066] In one embodiment of the method, the method comprises the following steps:

[0067] By structuring the silicon semiconductor layer spanning the cavity and / or structuring the polycrystalline silicon semiconductor layer, at least one silicon structure is formed which is arranged free-standing in the cavity region and is connected to a monocrystalline silicon semiconductor substrate surrounding the cavity via at least one attachment structure.

[0068] The expression "at least one" means "one or more".

[0069] The embodiments and examples described here can be combined with one another in any desired manner, even if this is not explicitly stated. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The present invention is further explained below based on preferred embodiments. In the accompanying drawings:

[0071] Figures 1 to 19 each showing a step in the method according to the first aspect,

[0072] Fig. 20 Two schematically described scanning electron microscope images (SEM images) are shown,

[0073] Fig.21 A semiconductor element is shown.

[0074] Fig. 22 a flow chart showing a method according to the first aspect, and

[0075] Fig.23A sensor is shown.

[0076] In the following, the same reference numerals may be used for the same features. DETAILED DESCRIPTION

[0077] Figure 1 A single crystal silicon semiconductor substrate 101 is shown, in which a cavity 103 is formed. Above the cavity 103 is a free-standing gate 105 made of single crystal silicon, which is formed from the silicon semiconductor substrate 101.

[0078] Figure 2 The closure of the cavity 103 is shown by applying monocrystalline silicon 201 by epitaxial silicon deposition on the unsupported monocrystalline silicon gate 105 in such a way that a monocrystalline silicon layer 203 is produced that spans the cavity 103 and is completely closed, which can be used, for example, as a diaphragm. After the production of the monocrystalline silicon layer 203 spanning the cavity 103, an annealing step can be performed, for example, which allows, due to the precipitation of silicon atoms, to produce a flat / planar (side) wall 301 of the cavity 103, as in Figure 3 as shown in .

[0079] On the single crystal silicon layer 203 spanning the cavity 103, for example, Figure 4 As shown in FIG. 1 , an additional semiconductor layer system 401 is applied, which can be used to realize a MEMS and / or ASIC structure / circuit. After the MEMS and / or ASIC structure / circuit is produced, for example, at least one trench structure 402 can be subsequently produced by the additional semiconductor layer system 401 and / or the single-crystal silicon layer 203 spanning the cavity 103, the trench structure having at least one trench 404 with any geometric size and / or any shape or having a plurality of trenches 404 with any geometric size and / or shape, Figure 4 and Figure 5 , it is indicated by hatching that the trench structure opens into the cavity 103 below the single-crystalline silicon layer 203 and that a free-standing (stress-decoupled) silicon structure 407 can be produced in the single-crystalline silicon layer 203 by means of the trench structure, above which the additional semiconductor layer system 401 is arranged. The free-standing silicon structure 407 can produce a stress-decoupled sensing and / or circuit region 409 above the silicon structure 407, which is stress-decoupled relative to the surrounding single-crystalline silicon semiconductor substrate 101 and / or relative to the surrounding additional semiconductor layer system 401. Such a stress-decoupled sensing and / or circuit region 409 can reduce / avoid influences on MEMS and / or ASIC (measurement) signals, for example, caused by AVT (Aufbau und Verbindungstechnik, building and connection technology) processes.

[0080] The free-standing silicon structure 407 together with the sensor and / or circuit region 409 arranged thereon is attached to the silicon substrate 101 surrounding the free-standing silicon structure and / or to the additional semiconductor layer system 401 surrounding the free-standing silicon structure via an attachment structure 411. The attachment structure 411, for example, resiliently attaches the free-standing silicon structure 407 and thus also the sensor and / or circuit region 409. The attachment of the silicon structure 407 to the silicon substrate 101 via the attachment structure 411 can, for example, be a flexible attachment and / or an elastic attachment and / or a resilient attachment and / or a lateral attachment and / or a vertical attachment.

[0081] The scheme described here is based on Figure 5 It is provided that, by arranging the polysilicon layer 501 at least partially directly on the single-crystalline silicon layer 203 spanning the cavity 103, a silicon layer is provided which allows stress compensation of the unsupported single-crystalline silicon structure 407, in particular of optional further layers of the layer system 401 produced on the unsupported single-crystalline silicon structure 407 and / or on the polysilicon layer 501. These further layers can, for example, consist of materials such as are used in accordance with standards for realizing, for example, MEMS and / or ASIC structures / circuits. The following materials are listed by way of example: SiO2, Si3N4, SiRiN (silicon-rich silicon nitride), SiON (silicon oxynitride), doped / undoped polysilicon, gold, platinum, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, titanium tungsten, copper, tungsten, chromium, nickel, lead zirconate titanate (PZT), metal silicide, aluminum oxide, aluminum optionally with additives such as silicon and / or copper. Furthermore, metal silicides such as those used as standard in MEMS and / or ASIC structures / circuits, for example in the region of electrical contact structures, such as titanium silicide, tantalum silicide, platinum silicide, may be cited.

[0082] Alternatively or additionally, circuit components of MEMS and / or ASIC structures / circuits may also be arranged at least in places in the free-standing and stress-compensated single-crystal silicon structure 407 .

[0083] therefore, Figure 5 A semiconductor component 503 is shown in the sense of the embodiment described here.

[0084] with Figure 5 In contrast to the illustration in FIG. 5 , the polysilicon layer 501 for stress compensation is not arranged completely on the single-crystalline silicon layer 203, but may be present, for example, only locally, for example in the region of a (flexible, elastic, resilient, lateral) attachment structure 411, which connects the stress-decoupled silicon structure 407 to the surrounding single-crystalline silicon substrate 101, which is, for example, a silicon wafer, as shown in FIG. Figure 6 as shown in .

[0085] Figure 7The use of a polysilicon layer 501 for stress compensation in the sensing and / or circuit area 409 is shown. In this regard, for example, instead of or in addition to Figure 6 In the depiction shown in , the polysilicon layer 501 is disposed directly on the free-standing silicon structure 407 .

[0086] After the cavity 103 spanned by the single-crystal silicon layer 203 is produced on the single-crystal silicon substrate 101, a polysilicon layer can be deposited directly onto the single-crystal silicon layer 203, for example, by means of an LPCVD deposition method (Low Pressure Chemical Vapor Deposition, LPCVD) and structured accordingly. This can produce, for example, a morphology on the silicon substrate surface, which can have an influence on the additional layer system 401 to be applied subsequently and the associated production process for realizing MEMS and / or ASIC structures / circuits and therefore must be taken into account.

[0087] exist Figure 8 and Fig. 9 The polysilicon layer 501 is shown in the figure, one in the region of the attachment structure 411 and one in the unsupported sensor and / or circuit region 409. In this case, a polysilicon starting layer is first produced and structured, for example by an LPCVD deposition method, and then silicon is grown in an epitaxial reactor in such a way that silicon polycrystals grow in the region where the polysilicon starting layer is present, and silicon single crystals grow in the region where the polysilicon starting layer has been removed. In this way, single crystal and / or polycrystalline silicon layers or single crystal and / or polycrystalline silicon regions arranged directly adjacent to each other can be produced, which layers can be several micrometers to tens of micrometers thick. With the help of a grinding and / or polishing process performed later, it can be achieved that the regions of single crystal and / or polycrystalline growth, in particular, have no or only very small undulating morphologies with respect to each other and have flat surfaces and low surface roughness. In the figure, the polycrystalline silicon layer 501 is shown in the figure, one in the region of the attachment structure 411 and the other in the unsupported sensor and / or circuit region 409 ... Fig. 9 1 and 2. A schematic diagram of a scanning electron microscope image 901 (REM: Rasterelektronenmikroskop) can also be seen, which illustrates how polysilicon 905 grows in an epitaxy generator on a polysilicon starting layer 903 deposited directly on a monocrystalline silicon substrate 101, with a tendency to form columnar structures. As already mentioned above, after the growth of monocrystalline and / or polycrystalline silicon layers, for example in an epitaxy reactor, a planarization or a flat / planar configuration of the polycrystalline and / or monocrystalline silicon surface with a low roughness can be carried out by carrying out an optional grinding and / or polishing process.

[0088] exist Figures 10 to 131 shows an embodiment of a method in which, before the production of the trench mask 1001 (e.g. with SiO2) and the production of the trench structure 403 in the monocrystalline silicon substrate 101, a polysilicon starting layer 1003 is provided at least in places, which can be structured together with the monocrystalline silicon substrate 101. After the trench structure 403 has been introduced into the monocrystalline silicon substrate 101, an optional passivation layer 1005, e.g. made of SiO2, is applied at least to the surface of the trench 405 of the trench structure 403 and the passivation layer 1005 is at least partially removed from the bottom 1007 of the trench 405, as in Fig.10 as shown in .

[0089] Then you can Fig.11 As shown in FIG. 1 , silicon is etched in the silicon substrate 101 starting from the bottom 1007 of the trench 405 by means of a substantially isotropic etching method, such as a plasma etching method. This may cause the etching fronts of adjacent trenches 405 to overlap and may result in a free-standing silicon gate structure 105 (see FIG. 1 ). Figure 1 ). For example, the etching process which proceeds substantially isotropically can also be carried out in such a way that the etching fronts starting from adjacent trenches 405 do not overlap at least in sections.

[0090] As in Fig.12 As shown in , now, after removal of the trench mask 1001 and optionally sidewall passivation, the deposition of silicon can be carried out in the epitaxial reactor, for example, in such a way that silicon grows polycrystalline on the polysilicon surface and grows monocrystalline on the monocrystalline silicon surface. When all inlets through the silicon gate 105 are closed by the growing silicon, the silicon growth on the trench walls and on the walls of the cavity 103 stops. If a polysilicon start layer 1003 is provided on the upper side of the silicon substrate 101 in the region of the silicon gate 105, the closing of the silicon gate 105 is essentially carried out by polysilicon. After the silicon gate 105 is closed, an annealing step can optionally be carried out in a reducing atmosphere, for example hydrogen, or in an atmosphere comprising nitrogen and / or oxygen and / or an inert gas.

[0091] Annealing particularly causes silicon atoms on the silicon surface to migrate preferably toward locations with a lower energy level. In particular in trenches 405 in which at least two opposing walls have a small mutual distance, the migration of silicon atoms may result in trenches 405 being completely filled with silicon atoms. Fig.12 As shown in FIG. 1 , the silicon gate 105 is enclosed by polycrystalline silicon. The transfer of silicon atoms in the trench 405 may result in the generation of polycrystalline and single-crystalline filling regions, and the silicon layer 203 spanning the cavity 103 may be constructed in a single-crystalline manner adjacent to the cavity 103, while in the region of the cavity 103, at least partially on the surface of the silicon layer, it may be constructed in a polycrystalline manner, as shown in FIG. Fig.13 as shown in .

[0092] exist Figures 14 to 16 An embodiment of the method is shown in FIG. 1 , in which polysilicon sidewalls are present up to a defined trench depth, while monocrystalline silicon sidewalls are present at a deeper trench depth, such as in FIG. Fig.14 Such a trench structure 403 can be realized by Fig.10 Starting with the description of the present invention, after the introduction of the trench structure 403, i.e. after the introduction of the trench 405, an additional deposition of an additional polysilicon start layer 1401 is carried out into the polysilicon start layer 1003 and into the silicon substrate 103 in such a way that the deposition of the additional polysilicon start layer 1401 also takes place on the side walls 1403 of the trench 405. Subsequently, an anisotropic silicon trench process is now carried out, for example, so that the removal of the additional polysilicon start layer 1401 and the gradual etching into the monocrystalline silicon substrate 101 take place at the bottom of the trench 405, while the polycrystalline side walls 1403 remain in the upper part of the trench 405.

[0093] In an alternative embodiment, for example, the first trench of the first trench structure in the monocrystalline silicon substrate 101 can be completely filled with polycrystalline silicon, followed by an optional CMP step (CMP: Chemisch mechanisches Polieren, chemical mechanical polishing) and the production of a hard mask, for example, from SiO2, with the aid of which the trench 405 is produced through the first trench completely filled with polycrystalline silicon into the monocrystalline silicon substrate 101, wherein the side walls of the trench 405 are subsequently passivated by SiO2, which is removed at the bottom of the trench 405 and by which an isotropic silicon etching process can be carried out to form the cavity 103 in the silicon substrate 101. In this alternative embodiment variant, a trench 405 with a side wall 1403 that is partially polycrystalline can also be produced.

[0094] With targeting Fig.12 Similarly, polysilicon sealing can now be performed, as in Fig.15 If the annealing as described above is now optionally continued again, a silicon layer 203 can be produced across the cavity 103, which has alternating regions of polycrystalline silicon regions and monocrystalline silicon regions in the silicon layer 203, which is polycrystallinely structured at the surface by depositing a polycrystalline silicon layer 501 and can consist of monocrystalline silicon adjacent to the cavity, as in Fig.16 as shown in .

[0095] In this method Fig.17In another embodiment shown in FIG. 1 , the deposition of the polysilicon layer 1701 can be carried out after the production of the free-standing single-crystalline silicon gate 105, for example by LPCVD deposition, wherein the polysilicon layer is deposited on all freely accessible single-crystalline silicon surfaces. The cavity 103 can then be closed with polysilicon by depositing silicon in an epitaxial generator. In this embodiment, the growth of polysilicon 1801 is carried out in the trench 405 and in the cavity 103 until the silicon gate 105 is finally closed (see FIG. 1 ). Fig.18 ) An additional annealing step for transferring the silicon can optionally also be carried out here.

[0096] As in Fig.19 As shown in , for example, in another embodiment, when sealing the unsupported silicon gate 105 in the epitaxy generator, polysilicon and monocrystalline silicon sealing regions and thus also polysilicon and monocrystalline silicon surface regions are generated, depending on where polysilicon and / or monocrystalline silicon regions were present on the surface of the silicon gate 105 before the sealing process. The same applies analogously to regions outside the silicon layer 201.

[0097] Regarding the implementation of the stress compensation layer, it can be provided, for example, that the polysilicon layer 501 for stress compensation is constructed by multiple layer deposition in an epitaxial generator, such as in Fig. 20 In this case, each individual deposition can be carried out with different deposition conditions and layer thicknesses and, for this purpose, can be doped differently. Here, “doped differently” refers in particular to the choice of dopant and / or the choice of dopant concentration and / or the dopant distribution gradient in the layer.

[0098] Fig. 20 Two schematically depicted SEM images 2001 and 2003 are shown. They are schematic because they are not original images.

[0099] According to the first SEM image 2001, only a single silicon layer is grown on the silicon substrate 101, preferably in an epitaxy generator. Depending on whether the silicon starting layer in the region is monocrystalline or polycrystalline, the deposited silicon grows monocrystalline or polycrystalline during deposition. The first SEM image 2001 shows, by way of example, a state in which only a simple deposition of a further polycrystalline silicon layer takes place on the polycrystalline silicon starting layer 2002 arranged directly on the monocrystalline silicon substrate 101 and a polycrystalline silicon layer 2005 is produced.

[0100] According to the second SEM image 2003, on the silicon substrate 101, in the region of the polysilicon starting layer 2002 applied directly on the silicon substrate 101, four polysilicon layers 2007, 2009, 2011 and 2013 are preferably grown in sequence in an epitaxy generator, for example. Thus, 4 polysilicon layer depositions are performed. These polysilicon layers 2007, 2009, 2011 and 2013 are additional polysilicon layers in the sense of this specification. In this example and in the previous examples, under the appropriate selection of the manufacturing process and process control, the deposition of silicon in an epitaxy generator can be advantageously used to be able to simultaneously produce single crystal and polysilicon regions, which can be advantageously used for manufacturing MEMS and / or ASIC structures / circuits on / in the silicon substrate 101 and / or for stress compensation of unsupported silicon structures 407.

[0101] After the silicon layer 203 is formed across the cavity 103, the production of the additional semiconductor layer system 401 can be carried out, which can be used to realize MEMS and / or ASIC structures / circuits (see Fig. 9 ).

[0102] Fig.21 Continuing with the schematically described scanning electron microscope image 2013, a region of the single-crystalline silicon layer 203 is shown by way of example, in which a further stress-compensating layer or a further stress-compensating layer system 2101 consisting of a plurality of alternating layer materials may be arranged between the polysilicon layer 501 or the polysilicon layer system (as shown by way of example in the second scanning electron microscope image 2003) and the single-crystalline silicon layer 203. Silicon oxide, silicon nitride, silicon oxynitride, silicon carbide may be cited as materials for the at least one further stress-compensating layer 2101, wherein the layer composition and the thickness of the materials cited by way of example may vary as desired, and the layers may be combined with each other as desired in the stress-compensating layer system, wherein the layers may also be present in different numbers in the stress-compensating layer system 2101.

[0103] The further stress-compensating layers 2101 can be arranged directly on the monocrystalline silicon layer 203, in particular directly on the free-standing silicon structures 407. The structuring of these further stress-compensating layers 2101 is advantageously carried out together with the polycrystalline silicon starting layers 903, 2002, wherein the monocrystalline silicon layer 203 can be exposed again at least in places on the surface, so that during the subsequent deposition of silicon layers in the epitaxy generator, in the region of the further stress-compensating structures 2101, the deposited silicon layer grows polycrystalline and, for example, forms a polycrystalline silicon layer 501, 905, 2005 or a polycrystalline silicon layer system 2007, 2009, 2011, 2013, while in the region outside the further stress-compensating layers 2101, the deposited silicon layer grows monocrystalline. Alternatively or additionally, further stress-compensating layers can also be arranged in the region of the attachment structure 411 and / or in the region outside the cavity 103 between the polycrystalline silicon starting layer 903, 2002 and the monocrystalline silicon layer 203.

[0104] Fig. 22 A flow chart showing a method for stress compensation of a silicon structure arranged unsupported in a cavity formed in a single-crystal silicon semiconductor substrate comprises the following steps:

[0105] A cavity 2201 is formed in the single crystal silicon semiconductor substrate through the single crystal silicon semiconductor layer of the silicon semiconductor substrate spanning the cavity.

[0106] The polycrystalline silicon semiconductor layer is formed 2203 in such a way that it is arranged at least in sections directly on the single-crystalline silicon semiconductor layer,

[0107] By structuring 2207 the silicon semiconductor layer spanning the cavity, at least one free-standing silicon structure is formed 2205 which is arranged in the region of the cavity and connected to the silicon semiconductor substrate surrounding the cavity via at least one attachment structure.

[0108] Fig.23 A sensor 2301 is shown, comprising a semiconductor element 2303 according to the second aspect and comprising a sensor element 2307 arranged on the semiconductor element 2303 and comprising a semiconductor layer system 2305 .

[0109] Note that Fig.23 The elements shown in FIG. 23 are of a schematic nature only. The semiconductor element 2303 may be, for example, the semiconductor element 503 .

[0110] The embodiments described in this specification can also be advantageously used, for example, when manufacturing a silicon diaphragm spanning a cavity, to influence the layer stress or stress conditions of the silicon diaphragm, so that, for example, the sensing sensitivity and / or measurement sensitivity and / or the measurement signal and / or the measurement signal change of the pressure sensor can be influenced.

[0111] It should further be noted that after at least one single-crystal region has been grown outside the produced cavity, the method can be carried out again in this single-crystal region.

[0112] In summary, the approach described here is based in particular on providing stress compensation and thus compensating for the bending of a single-crystal silicon structure in the region of a single-crystal silicon structure which is arranged unsupported and therefore stress-decoupled relative to a surrounding single-crystal silicon substrate (which is processed from the single-crystal silicon substrate and on which further layers can be deposited for producing at least one sensor structure) by applying at least one polycrystalline silicon layer directly to the single-crystal silicon structure, whose layer stress can be influenced by introducing at least one dopant and / or by selecting deposition conditions and / or subsequent annealing conditions.

Claims

1. A method for compensating stress of a silicon structure (407) arranged unsupported in a cavity (103) formed in a single-crystal silicon semiconductor substrate (101), comprising the following steps: A cavity (103) is formed (2201) in the single crystal silicon semiconductor substrate (101) through a single crystal silicon semiconductor layer (203) of the silicon semiconductor substrate (101) that spans the cavity (103), forming (2203) a polycrystalline silicon semiconductor layer (501) in such a way that it is arranged at least in sections directly on the single-crystalline silicon semiconductor layer (203), By structuring (2207) the single-crystal silicon semiconductor layer (203) spanning the cavity (103) and / or the polycrystalline silicon semiconductor layer (501), at least one unsupported silicon structure (407) is formed (2205), which is arranged in the area of ​​the cavity (103) and connected to the silicon semiconductor substrate (101) surrounding the cavity (103) via at least one attachment structure (411).

2. The method according to claim 1, wherein: After forming (2201) the cavity (103) together with the single crystal silicon semiconductor layer (203) of the silicon semiconductor substrate (101) spanning the cavity (103), the polycrystalline silicon semiconductor layer (501, 905, 2005) is formed (2203), wherein silicon is deposited directly on the single crystal silicon semiconductor layer (203) of the silicon semiconductor substrate (101) spanning the cavity (103) at least in the region of the cavity (103) so that the polycrystalline silicon semiconductor layer (501, 905, 2005) is grown at least locally.

3. The method according to claim 2, wherein: Silicon is deposited directly onto the single crystal silicon semiconductor layer (203) so as to form a polycrystalline silicon starting layer (903, 1003, 2002), wherein the polycrystalline silicon starting layer (903, 1003, 2002) is structured so that the polycrystalline silicon starting layer (903, 1003, 2002) is removed in one or more regions of the single crystal silicon semiconductor layer (203), wherein silicon is deposited onto the structured silicon starting layer (903, 1003, 2002) after the structuring so that the polycrystalline silicon of the polycrystalline silicon starting layer (903, 1003, 2002) is present in one or more regions on the single crystal silicon semiconductor layer (203), the deposited silicon polycrystal grows, and the deposited silicon single crystal grows in one or more regions where the polycrystalline silicon starting layer (903, 1003, 2002) has been removed.

4. A method according to any one of the preceding claims, wherein: In order to form (2201) the cavity (103), a trench structure (403) having a plurality of trenches (405) is produced in the single-crystal silicon semiconductor substrate (101).

5. The method according to claim 4, wherein: Before generating the trench structure (403), a polysilicon starting layer (903, 1003, 2002) is generated at least in sections on the single crystal silicon semiconductor substrate (101), so that after forming (2201) the cavity (103), the single crystal silicon semiconductor layer (203) of the single crystal silicon semiconductor substrate (101) that spans the cavity (103) at least in sections has the polysilicon starting layer (903, 1003, 2002), wherein another silicon Deposited onto a single crystal silicon semiconductor layer (203) spanning the cavity (103) and having at least a section thereof having the polycrystalline silicon starting layer (903, 1003, 2002), so that in an area where polycrystalline silicon of the polycrystalline silicon starting layer (903, 1003, 2002) exists on the single crystal silicon semiconductor layer (203), the deposited silicon polycrystal grows, and in an area where the polycrystalline silicon starting layer (903, 1003, 2002) is not present, the deposited silicon single crystal grows.

6. The method according to claim 5, wherein: After at least partially producing the polycrystalline silicon starting layer (903, 1003, 2002) and the trench structure (403), etching of silicon is performed in the single-crystal silicon semiconductor substrate (101) starting from the bottom area of ​​the trench (405) forming the trench structure (403), so that the cavity (103) is formed below the trench structure (403), wherein the trench (405) is closed by depositing additional silicon onto the silicon semiconductor layer (203) of at least partial single-crystal and / or polycrystalline structure spanning the cavity (103).

7. The method according to claim 6, wherein: After the trench (405) has been closed by the additional silicon, annealing is performed to transfer silicon atoms in the region of the trench structure (403) in such a way that the silicon semiconductor layer (203) spanning the cavity (103) is structured monocrystalline adjacent to the cavity (103) and polycrystalline on its surface.

8. The method according to any one of claims 5 to 7, wherein: The trench structure (403) is produced after the polysilicon starting layer (903, 1003, 2002) is produced at least in sections, wherein after the trench structure (403) is produced, an additional polysilicon starting layer (1401) is produced on the sidewalls (1403) of the trench (405).

9. A method according to any one of the preceding claims as dependent on claim 4, wherein: After the trench structure (403) has been produced, a (further) polysilicon starting layer is deposited on the side walls of the trench, wherein the further silicon is deposited such that silicon grows polycrystalline on the side walls having the (further) polysilicon starting layer.

10. The method according to any one of claims 4 to 9, wherein: The polysilicon starting layer (903, 1003, 2002) is at least partially produced on the single crystal silicon semiconductor substrate (101) before producing the trench structure (403), in the manner of producing a first trench structure having a plurality of first trenches in the single crystal silicon semiconductor substrate (101), wherein silicon is deposited in such a way that the plurality of first trenches are at least partially filled with polysilicon to produce a first trench structure at least partially filled with polysilicon, wherein the trench (405) of the trench structure (403) is produced through the at least partially filled first trenches of the first trench structure until entering the single crystal silicon semiconductor substrate (101).

11. A method according to any one of the preceding claims, wherein: After forming (2203) the polycrystalline silicon semiconductor layer (501, 905, 2005), silicon is deposited thereon to grow at least one further polycrystalline silicon semiconductor layer.

12. A method according to any one of the preceding claims, wherein: The polycrystalline silicon semiconductor layer is arranged such that it is arranged at least in sections directly on the freestanding single-crystalline silicon structure and / or at least in sections directly on a section of the single-crystalline silicon semiconductor layer spanning the cavity and comprising the attachment structure.

13. A semiconductor element (503, 2303) having: A single crystal silicon semiconductor substrate (101), in which a cavity (103) is formed by a single crystal silicon semiconductor layer (203) of the silicon semiconductor substrate (101) spanning the cavity (103), wherein: A polycrystalline silicon semiconductor layer (501, 905, 2005) is arranged directly at least in sections on the single-crystalline silicon semiconductor layer (203) spanning the cavity (103), or a polycrystalline silicon semiconductor layer system (2007, 2009, 2011, 2013) is arranged directly at least in sections, At least one silicon structure (407) is formed in the region of the cavity (103) and is arranged unsupported. The silicon structure (407) is formed from a polycrystalline silicon semiconductor layer (501, 905, 2005) arranged at least in sections directly on the semiconductor layer (203) crossing the cavity (103) or a polycrystalline silicon semiconductor layer system (2007, 2009, 2011, 2013) arranged at least in sections directly on the semiconductor layer (203) crossing the cavity (103), and the silicon structure (407) is connected to a silicon semiconductor substrate (101) surrounding the cavity (103) via at least one attachment structure (411).

14. The semiconductor element (503, 2303) according to claim 13, wherein: The polycrystalline silicon semiconductor layer is arranged such that it is at least sectionally arranged directly on the freestanding single-crystalline silicon structure and / or at least sectionally arranged directly on a section of the single-crystalline silicon semiconductor layer spanning the cavity and containing the attachment structure.

15. Sensor (2301) comprising a semiconductor element (503, 2303) according to claim 13 or 14 and comprising a sensor element (2307) arranged on the semiconductor element (503, 2303) and comprising a semiconductor layer system (401, 2305).

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