Clock frequency self-calibration method, system, equipment and medium
By gradually adjusting the bit logic value of the OSC control signal in the frequency adjustment circuit and calculating the count value to be calibrated under the standard clock, self-calibration of the clock frequency is solved, and the calibration time and cost are significantly reduced.
Patent Information
- Application Number
- CN202510111402.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-23
AI Technical Summary
In the prior art, the clock frequency calibration method is inefficient, time-consuming and costly. Especially when the frequency value is close to two extremes, multiple calibrations are required to achieve the frequency value that meets the requirements.
By setting the logic values of Bit[N] to Bit[0] of the OSC control signal in the frequency adjustment circuit, and calculating the count value to be calibrated through a counter under the standard clock, the logic value is gradually adjusted to achieve self-calibration of the clock frequency, and finally, a total of N+1 calibrations are performed to achieve the target frequency.
This method greatly saves the number of automatic calibrations, quickly reaches the value closest to the target frequency, and significantly reduces test time and cost.
Smart Images
Figure CN120029412A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a clock frequency self-calibration method, system, device and medium. Background Art
[0002] In the existing technical field and market field, the working clock sources inside the chip are divided into: an external crystal oscillator (External Crystal Oscillator XOSC), the XOSC clock frequency is very stable and accurate, but because it is generally a quartz crystal oscillator, the quartz crystal oscillator is large and expensive, so XOSC is generally not selected as the working clock inside the chip; an internal clock oscillator, but due to the process deviation limitations used in the chip manufacturing process, the actual clock frequency will deviate between chips within a certain range. Most IPs used in the chip design process have certain requirements for the clock, and the design standard will also have an allowable clock deviation. If the actual clock frequency deviation is greater than this range, it will affect the chip performance and even cause it to fail to work properly. This requires internal clock calibration in the chip CP test phase or FT phase to calibrate it to a range that meets the requirements.
[0003] The clock calibration method used in the prior art is: 1. By changing different clock frequencies and measuring the current clock frequency on an external machine until the clock frequency meets the deviation range, but this traditional calibration method is time-consuming and the calibration cost is very high. 2. Design an automatic iterative calibration logic inside the chip, which no longer requires an external machine to measure the clock and modify the clock frequency externally. Instead, by inputting a standard clock, the count difference between the calibration clock and the clock to be calibrated is automatically calculated by a counter internally to see if the difference is within the deviation range. If it is within the deviation range, the calibration is automatically exited, otherwise the next calibration is automatically performed until it iterates to a value that meets the calibration frequency. However, this method is inefficient. If the frequency value happens to be at two extremes, more calibrations are required to obtain a frequency value that meets the requirements, and the iterative method is still relatively time-consuming.
[0004] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention
[0005] The main purpose of the present invention is to provide a clock frequency self-calibration method, system, device and medium, aiming to solve the technical problem of how to achieve efficient clock frequency self-calibration.
[0006] To achieve the above object, the present invention provides a clock frequency self-calibration method, the clock frequency self-calibration method comprising:
[0007] Set the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, wherein the OSC control signal consists of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0];
[0008] Adjust the initial logic values of Bit[N-1] to Bit[0] in sequence, and use the initial logic value of the currently adjusted control signal as the current pre-processing logic value;
[0009] When the standard clock passes through counter one and counts to a predetermined count value, determining a count value to be calibrated of the clock to be calibrated passed through counter two;
[0010] adjusting the current preprocessing logic value according to the predetermined count value and the count value to be calibrated;
[0011] After the adjustment is completed, the logic value of Bit[N-1] is determined to be the logic value of Bit[0];
[0012] The clock frequency is self-calibrated according to the logic value of Bit[N] to the logic value of Bit[0].
[0013] Optionally, the step of setting the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit includes:
[0014] Determine the highest frequency control signal from the OSC control signal in the frequency adjustment circuit;
[0015] The highest frequency control signal is used as Bit[N], and the logic value of Bit[N] is set.
[0016] Optionally, after the step of setting the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, the method further comprises:
[0017] The logic value of the Bit[N] is set to 1, and the initial logic values of Bit[N-1] to Bit[0] in the OSC control signal are set to 0.
[0018] Optionally, the step of adjusting the current preprocessing logic value according to the predetermined count value and the count value to be calibrated includes:
[0019] Calculating a target count value according to the predetermined count value, the standard clock frequency and the target clock frequency;
[0020] The current pre-processing logic value is adjusted according to the target count value and the count value to be calibrated.
[0021] Optionally, the step of adjusting the current preprocessing logic value according to the target count value and the count value to be calibrated includes:
[0022] Determining whether the count value to be calibrated is greater than the target count value;
[0023] If so, it is determined that the clock frequency to be calibrated is greater than the target clock frequency, and the current pre-processing logic value is maintained.
[0024] Optionally, after the step of determining whether the count value to be calibrated is greater than the target count value, the following steps are included:
[0025] If not, it is determined that the clock frequency to be calibrated is less than the target clock frequency, and the current pre-processing logic value is adjusted from 0 to 1.
[0026] In addition, to achieve the above object, the present invention further proposes a clock frequency self-calibration system, the clock frequency self-calibration system comprising:
[0027] A determination module, used to set the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, wherein the OSC control signal consists of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0];
[0028] An adjustment module, used for adjusting the initial logic values of Bit[N-1] to Bit[0] in sequence, and using the initial logic value of the currently adjusted control signal as the current pre-processing logic value;
[0029] The adjustment module is further used to determine the count value to be calibrated counted by the clock to be calibrated through the counter 2 when the standard clock passes through the counter 1 to count to a predetermined count value;
[0030] The adjustment module is further used to adjust the current pre-processing logic value according to the predetermined count value and the count value to be calibrated;
[0031] The adjustment module is further used to determine the logic value of Bit[N-1] to the logic value of Bit[0] after the adjustment is completed;
[0032] The calibration module is used to realize self-calibration of the clock frequency according to the logic value of Bit[N] to the logic value of Bit[0].
[0033] In addition, to achieve the above-mentioned purpose, the present invention also proposes a clock frequency self-calibration device, which includes: a memory, a processor, and a clock frequency self-calibration program stored in the memory and executable on the processor, wherein the clock frequency self-calibration program is configured to implement the steps of the clock frequency self-calibration method as described above.
[0034] In addition, to achieve the above purpose, the present invention also proposes a medium, on which a clock frequency self-calibration program is stored, and when the clock frequency self-calibration program is executed by a processor, the steps of the clock frequency self-calibration method described above are implemented.
[0035] The present invention first sets the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, the OSC control signal is composed of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N], and the lowest frequency control signal is recorded as Bit[0], then adjusts the initial logic values of Bit[N-1] to Bit[0] in sequence, and uses the initial logic value of the currently adjusted control signal as the current pre-processing logic value, and then when the standard clock passes through counter one to count to a predetermined count value, determines the count value to be calibrated of the clock to be calibrated by counter two, and adjusts the current pre-processing logic value according to the predetermined count value and the count value to be calibrated, and after the adjustment is completed, determines the logic value of Bit[N-1] to the logic value of Bit[0], and finally realizes the self-calibration of the clock frequency according to the logic value of Bit[N] to the logic value of Bit[0]. In the present invention, the logic value of the corresponding bit is determined one by one until the logic value of Bit[0] is determined, and finally a total of N+1 calibrations are performed to make the final frequency value reach the target frequency. The method finally reaches the value closest to the target frequency with a very short number of automatic calibrations, which greatly saves test time and cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 It is a structural schematic diagram of a self-calibration device for clock frequency of a hardware operating environment involved in an embodiment of the present invention;
[0037] Figure 2 It is a flowchart of a first embodiment of a clock frequency self-calibration method of the present invention;
[0038] Figure 3 FIG. 4 is a structural block diagram of a first embodiment of a clock frequency self-calibration system according to the present invention.
[0039] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0040] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.
[0041] Reference Figure 1 , Figure 1 The figure is a schematic diagram of the structure of a self-calibration device for the clock frequency of a hardware operating environment involved in an embodiment of the present invention.
[0042] like Figure 1As shown, the clock frequency self-calibration device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM), or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk storage. The memory 1005 may also be a storage system independent of the aforementioned processor 1001.
[0043] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the clock frequency self-calibration device, and may include more or less components than those shown in the figure, or combine certain components, or arrange the components differently.
[0044] like Figure 1 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a self-calibration program for a clock frequency.
[0045] exist Figure 1 In the clock frequency self-calibration device shown, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the clock frequency self-calibration device of the present invention can be set in the clock frequency self-calibration device, and the clock frequency self-calibration device calls the clock frequency self-calibration program stored in the memory 1005 through the processor 1001, and executes the clock frequency self-calibration method provided in an embodiment of the present invention.
[0046] The embodiment of the present invention provides a clock frequency self-calibration method, referring to Figure 2 , Figure 2 FIG. 4 is a flow chart of a first embodiment of a clock frequency self-calibration method according to the present invention.
[0047] In this embodiment, the clock frequency self-calibration method includes the following steps:
[0048] Step S10: setting the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, wherein the OSC control signal consists of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0].
[0049] It is easy to understand that the execution subject of this embodiment can be a clock frequency self-calibration system with functions such as data processing, network communication and program running, or other computer equipment with similar functions, etc., and this embodiment is not limited.
[0050] It should be noted that the internal logic of the chip only has logic 0 and 1. The frequency adjustment inside the clock to be calibrated is actually to adjust the logic 0 and 1 of multiple control signals (i.e., Bit[0] to Bit[N]) in the crystal oscillator (oscillator OSC) control signal in the frequency adjustment circuit. In the prior art, an OSC with an N-bit frequency control signal has a total of 2^N frequency changes. Based on this, this embodiment calibrates the clock with fewer calibration times.
[0051] It should also be noted that the OSC control signal consists of Bit[0] to Bit[N], that is, the OSC control signal has N+1 control signals (i.e., composed of N+1 bits), Bit[0] is the first control signal, and Bit[N] is the N+1th control signal. It is necessary to select the highest frequency control signal from the OSC control signal, use the highest frequency control signal as Bit[N], and set the logic value of Bit[N], set the logic value of Bit[N] to 1 (i.e., set the highest frequency control signal in the N+1 control signals to logic 1), and pre-set the initial logic values of Bit[N-1] to Bit[0] to 0. Among them, the lowest frequency control signal is Bit[0]. Refer to the following table, which is the initial logic table for the automatic calibration clock frequency inside the chip:
[0052] Bit[N] Bit[N-1] ...... Bit[1] Bit[0] 1 0 0 0 0
[0053] Step S20: sequentially adjust the initial logic values of Bit[N-1] to Bit[0], and use the initial logic value of the currently adjusted control signal as the current pre-processing logic value.
[0054] It should also be understood that a standard precise clock (i.e., standard clock) is inputted into the chip from the outside, and the counter 1 (i.e., counter 1) inside the chip uses the clock to count the fixed count value A (i.e., the predetermined count value). The clock to be calibrated inside the chip uses counter 2 (i.e., counter 2).
[0055] The logic value of the corresponding bit needs to be determined one by one until the logic value of Bit[0] is determined. Since the logic value of Bit[N] is fixed in advance, the initial logic values of Bit[N-1]-Bit[0] need to be changed in sequence.
[0056] In this embodiment, if the initial logic value of Bit[N-1] (ie, the Nth control signal) is adjusted, the initial logic value of Bit[N-1] is used as the current pre-processing logic value.
[0057] Step S30: when the standard clock passes through counter 1 to count to a predetermined count value, determining the count value to be calibrated counted by counter 2 of the clock to be calibrated.
[0058] It should also be noted that a predetermined count value corresponding to the standard clock needs to be preset, and after the counter 1 reaches the set count value A, the current count value B of the counter 2 (ie, the count value to be calibrated) is recorded.
[0059] Step S40: adjusting the current pre-processing logic value according to the predetermined count value and the count value to be calibrated.
[0060] Further, the target count value is calculated according to the predetermined count value, the standard clock frequency (ie, the external clock frequency) and the target clock frequency (ie, A*external clock frequency=C*target clock frequency); and the current preprocessing logic value is adjusted according to the target count value and the count value to be calibrated.
[0061] It should be understood that the target count value C is the count value that should be reached after calibration to reach the target clock frequency. The target count value needs to be calculated through the predetermined count value, standard clock frequency (ie, external clock frequency) and target clock frequency, and the target count value C is set inside the chip.
[0062] Further, the processing method of adjusting the current preprocessing logic value according to the target count value and the count value to be calibrated is to determine whether the count value to be calibrated is greater than the target count value;
[0063] If so, it is determined that the clock frequency to be calibrated is greater than the target clock frequency, and the current preprocessing logic value is kept as 0; if not, it is determined that the clock frequency to be calibrated is less than the target clock frequency, and the current preprocessing logic value is adjusted from 0 to 1.
[0064] In the specific implementation, compare B and C. If B is greater than C, it means that the clock frequency of the current frequency range is higher than the target clock frequency and needs to be adjusted downward, then Bit[i] cannot be logic 1, but must be logic 0. If B is less than C, it means that the clock frequency of the current frequency range is lower than the target clock frequency and needs to be adjusted upward, then Bit[i] must be logic 1. In this way, the value of Bit[i] is determined, and Bit[i] is any control signal from Bit[N-1] to Bit[0].
[0065] Step S50: After the adjustment is completed, the logic value of Bit[N-1] is determined to be the logic value of Bit[0].
[0066] It should be noted that after fixing the logic value of Bit[N], the logic value of Bit[N-1] is changed to repeat the above operations of step S20-step S40, and the logic value of the corresponding bit is determined one by one until the logic value of Bit[0] is determined, and finally a total of N+1 calibrations are performed.
[0067] Step S60: Implement self-calibration of the clock frequency according to the logic value of Bit[N] to the logic value of Bit[0].
[0068] It should also be noted that after the logic value of Bit[0] is adjusted, its corresponding frequency value must be the closest to the target frequency.
[0069] In this embodiment, the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit is first set, and the OSC control signal is composed of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0]. Then, the initial logic values of Bit[N-1] to Bit[0] are adjusted in sequence, and the initial logic value of the currently adjusted control signal is used as the current pre-processing logic value. After that, when the standard clock passes through counter 1 to count to a predetermined count value, the count value to be calibrated counted by counter 2 of the clock to be calibrated is determined, and the current pre-processing logic value is adjusted according to the predetermined count value and the count value to be calibrated. After the adjustment is completed, the logic value of Bit[N-1] is determined to be the logic value of Bit[0]. Finally, the self-calibration of the clock frequency is implemented according to the logic value of Bit[N] to the logic value of Bit[0]. In this embodiment, the logic value of the corresponding bit is determined one by one until the logic value of Bit[0] is determined, and finally a total of N+1 calibrations are performed to make the final frequency value reach the target frequency. This method finally reaches the value closest to the target frequency with an extremely short number of automatic calibration times, which greatly saves test time and cost.
[0070] Reference Figure 3 , Figure 3 FIG. 4 is a structural block diagram of a first embodiment of a clock frequency self-calibration system according to the present invention.
[0071] like Figure 3 As shown, the clock frequency self-calibration system proposed in the embodiment of the present invention includes:
[0072] The determination module 3001 is used to set the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, wherein the OSC control signal consists of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0];
[0073] An adjustment module 3002 is used to adjust the initial logic values of Bit[N-1] to Bit[0] in sequence, and use the initial logic value of the currently adjusted control signal as the current pre-processing logic value;
[0074] The adjustment module 3002 is further configured to determine the count value to be calibrated counted by the clock to be calibrated by the counter 2 when the standard clock counts to a predetermined count value by the counter 1;
[0075] The adjustment module 3002 is further used to adjust the current pre-processing logic value according to the predetermined count value and the count value to be calibrated;
[0076] The adjustment module 3002 is further used to determine the logic value of Bit[N-1] to the logic value of Bit[0] after the adjustment is completed;
[0077] The calibration module 3003 is used to implement self-calibration of the clock frequency according to the logic value of Bit[N] to the logic value of Bit[0].
[0078] Other embodiments or specific implementations of the clock frequency self-calibration system of the present invention may refer to the above-mentioned method embodiments, which will not be described in detail here.
[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.
[0080] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.
[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.
[0082] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A clock frequency self-calibration method, characterized in that: The clock frequency self-calibration method comprises the following steps: Set the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, wherein the OSC control signal consists of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0]; Adjust the initial logic values of Bit[N-1] to Bit[0] in sequence, and use the initial logic value of the currently adjusted control signal as the current pre-processing logic value; When the standard clock passes through counter one and counts to a predetermined count value, determining a count value to be calibrated of the clock to be calibrated passed through counter two; adjusting the current preprocessing logic value according to the predetermined count value and the count value to be calibrated; After the adjustment is completed, the logic value of Bit[N-1] is determined to be the logic value of Bit[0]; The clock frequency is self-calibrated according to the logic value of Bit[N] to the logic value of Bit[0].
2. The method according to claim 1, characterized in that The step of setting the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit includes: Determine the highest frequency control signal from the OSC control signal in the frequency adjustment circuit; The highest frequency control signal is used as Bit[N], and the logic value of Bit[N] is set.
3. The method according to claim 2, characterized in that After the step of setting the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, the method further comprises: The logic value of the Bit[N] is set to 1, and the initial logic values of Bit[N-1] to Bit[0] in the OSC control signal are set to 0.
4. The method according to claim 3, characterized in that The step of adjusting the current preprocessing logic value according to the predetermined count value and the count value to be calibrated comprises: Calculating a target count value according to the predetermined count value, the standard clock frequency and the target clock frequency; The current pre-processing logic value is adjusted according to the target count value and the count value to be calibrated.
5. The method according to claim 4, characterized in that The step of adjusting the current preprocessing logic value according to the target count value and the count value to be calibrated comprises: Determining whether the count value to be calibrated is greater than the target count value; If so, it is determined that the clock frequency to be calibrated is greater than the target clock frequency, and the current pre-processing logic value is maintained.
6. The method according to claim 5, characterized in that After the step of determining whether the count value to be calibrated is greater than the target count value, the method further comprises: If not, it is determined that the clock frequency to be calibrated is less than the target clock frequency, and the current pre-processing logic value is adjusted from 0 to 1.
7. A clock frequency self-calibration system, characterized in that: The clock frequency self-calibration system comprises: A determination module, used to set the logic value of Bit[N] in the OSC control signal in the frequency adjustment circuit, wherein the OSC control signal consists of N+1 bits, wherein the highest frequency control signal is recorded as Bit[N] and the lowest frequency control signal is recorded as Bit[0]; An adjustment module, used for adjusting the initial logic values of Bit[N-1] to Bit[0] in sequence, and using the initial logic value of the currently adjusted control signal as the current pre-processing logic value; The adjustment module is further used to determine the count value to be calibrated counted by the clock to be calibrated through the counter 2 when the standard clock passes through the counter 1 to count to a predetermined count value; The adjustment module is further used to adjust the current pre-processing logic value according to the predetermined count value and the count value to be calibrated; The adjustment module is further used to determine the logic value of Bit[N-1] to the logic value of Bit[0] after the adjustment is completed; The calibration module is used to realize self-calibration of the clock frequency according to the logic value of Bit[N] to the logic value of Bit[0].
8. A clock frequency self-calibration device, characterized in that: The device comprises: a memory, a processor, and a clock frequency self-calibration program stored in the memory and executable on the processor, wherein the clock frequency self-calibration program is configured to implement the steps of the clock frequency self-calibration method according to any one of claims 1 to 6.
9. A medium, characterized in that The medium stores a clock frequency self-calibration program, and when the clock frequency self-calibration program is executed by a processor, the steps of the clock frequency self-calibration method according to any one of claims 1 to 6 are implemented.