Self-adaptive starting clock system of Retimer chip

Abstract

The invention relates to the field of chip clocks, and provides a self-adaptive starting clock system of a Retimer chip, which comprises an external reference clock detection module used for detecting the frequency of an external differential clock according to configuration information, generating a marking signal and outputting the external differential clock; the internal clock generation module is used for providing a stable internal differential clock; and the control selection module is used for selecting the external differential clock or the internal differential clock as the clock of the Retimer chip according to the configuration information and the mark signal. According to the method, starting and clock schemes of different types of servers can be supported in a self-adaptive mode, for different power supply, voltage and reference clock schemes, the reference clock, the power supply voltage and the like can be detected in a self-adaptive mode, the most appropriate starting scheme can be automatically selected, and the system safety of the whole server is guaranteed.

Description

Technical Field

[0001] The invention relates to the field of chip clocks, and in particular to an adaptive starting clock system of a Retimer chip. Background Art

[0002] As the transmission rate of PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) increases, the use of traditional circuit boards for transmission has the problem of signal loss. In order to compensate for the signal loss, Retimer chips are produced. Retimer chips are mainly used in various servers, but facing various different servers, the compatibility of Retimer chips is a very strict challenge. In particular, the clock system of Retimer chips is difficult to be compatible with hundreds of different manufacturers, different specifications, and different startup schemes.

[0003] The existing Retimer chip clock system has the following disadvantages: 1) Lack of a local clock. When the external reference clock fails, the entire Retimer chip will not work, and it will also affect the next-level chip of the Retimer chip, causing the failure of the entire server system.

[0004] 2) There is a lack of detection circuit for the external reference clock, and the quality of the external reference clock cannot be monitored. When the external reference clock has clock quality problems such as jitter and drift, the Retimer chip will fail.

[0005] 3) In the existing Retimer chip, when the external reference clock fails, there is no solution to save or escape, resulting in a scenario where the external reference clock fails and the entire Retimer chip hangs. Summary of the invention

[0006] In view of the problems existing in the prior art, an adaptive startup clock system of a Retimer chip is provided, which is mainly used in Retimer chips on various servers. Facing clock and startup schemes of various manufacturers, it can be well compatible with various server startup and clock schemes.

[0007] The present invention proposes an adaptive start clock system of a Retimer chip, comprising: An external reference clock detection module, used to detect the frequency of the external differential clock according to the configuration information, generate a flag signal and output the external differential clock; Internal clock generation module, providing stable internal differential clock; The control selection module is used to select an external differential clock or an internal differential clock as the clock of the Retimer chip according to the configuration information and the flag signal.

[0008] As a preferred solution, the adaptive startup clock system further includes a chip initialization configuration module for providing configuration information; the configuration information includes clock selection mode and clock frequency requirement information.

[0009] As a preferred solution, the adaptive start-up clock system further includes a reset control module for providing a reset signal according to an external reset circuit.

[0010] As a preferred solution, the external reference clock detection module includes: A clock receiving module, used for receiving an external differential clock; A first configuration information receiving module, used to receive clock selection mode and clock frequency requirement information; The clock detection and output module is used to detect the external differential clock according to the clock selection mode and the clock frequency requirement information, and control the output of the external differential clock and the flag signal according to the detection result.

[0011] As a preferred solution, the clock detection and output module includes: A detection enabling module, used for enabling an external reference clock detection module according to a clock selection mode; A reference frequency generation module, used to generate a reference clock with a fixed frequency; A frequency detection module, used for receiving an external differential clock and a reference clock, and detecting a mode and a frequency of the external differential clock; A clock frequency requirement information storage module, used for storing clock frequency requirement information; The clock determination module is used to control the output of the external differential clock and the flag signal according to the mode, frequency and clock frequency requirement information of the external differential clock.

[0012] As a preferred solution, in the clock determination module, controlling the output of the external differential clock and the flag signal specifically includes: The mode of the external differential clock includes a same-frequency clock or a spread-spectrum clock, and outputs an external differential clock and a flag signal that meet the requirements according to the determination method of the same-frequency clock or the spread-spectrum clock; The same-frequency clock determination method includes: determining whether the frequency of the external differential clock is the same as the reference clock, and if so, outputting the external differential clock and a flag signal; The detection of the spread spectrum clock judgment method includes: judging whether the frequency deviation of the external differential clock is within the frequency deviation range limited by the clock frequency requirement information, and if so, outputting the external differential clock and the flag signal.

[0013] As a preferred solution, the control selection module includes: A first clock receiving module, used for receiving an external differential clock and a flag signal output by an external reference clock detection module; A second clock receiving module, used for receiving an internal differential clock; A second configuration information receiving module, used for receiving a clock selection mode and a reset signal; The clock adaptive output module is used to select the corresponding clock output according to the clock selection mode, reset signal and flag signal.

[0014] As a preferred solution, the specific working process of the clock adaptive output module includes: When the clock selection mode is the first mode, the internal differential clock output is selected; When the clock selection mode is the second mode, select the external differential clock output; When the clock selection mode is the third mode, the corresponding clock is adaptively selected and output; wherein the adaptive selection and output of the corresponding clock is implemented based on the reset signal and the flag signal.

[0015] As a preferred solution, the specific process of adaptively selecting and outputting the corresponding clock includes: When the reset signal is high, the internal differential clock is output; When the reset signal is low and the flag signal is high, the external differential clock is output, otherwise the internal differential clock is output.

[0016] As a preferred solution, the adaptive start-up clock system further includes a clock output module, which is used to output the clock selected by the control selection module to the next-level chip of the Retimer chip.

[0017] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: the present invention can adaptively support the startup and clock schemes of different types of servers. In the face of different power supplies, voltages and reference clock schemes, the present invention can adaptively select the most appropriate startup scheme according to the timing relationship between the reset signal and the reference clock, thereby ensuring the system security of the entire server. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the adaptive start clock system proposed by the present invention.

[0019] Figure 2 Schematic diagram of an external reference clock detection module in an embodiment of the present invention.

[0020] Figure 3 Schematic diagram of a clock detection and output module in an embodiment of the present invention.

[0021] Figure 4FIG. 4 is a schematic diagram of a control selection module in an embodiment of the present invention.

[0022] Figure 5 A timing diagram of adaptively selecting and outputting corresponding clocks in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limitations on the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0024] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be arbitrarily combined with each other. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0025] The terms "first" and "second" in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any variation thereof are intended to cover non-exclusive protection. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0026] In order to solve the problems existing in the existing Retimer chip clock system, the present invention proposes an adaptive startup clock system of the Retimer chip, which can adaptively support the startup and clock schemes of different types of servers. Facing different power supplies, voltages and reference clock schemes, the present invention can adaptively detect the reference clock and power supply voltage, etc., and can automatically select the most appropriate startup scheme to ensure the system security of the entire server.

[0027] Please refer to Figure 1The adaptive start-up clock system of the Retimer chip mainly includes an external reference clock detection module, an internal clock generation module and a control selection module. Specifically, The external reference clock detection module is mainly used to detect the frequency of the external differential clock according to the configuration information, generate a flag signal and output the external differential clock. It should be noted that the external differential clock and the flag signal will be output only when the quality of the external differential clock meets the quality requirements of PCIe.

[0028] The internal clock generation module is mainly used to provide a stable internal differential clock. In one embodiment, the internal clock generation module can be implemented using an analog circuit. The module outputs a stable 100M differential clock and can be used as a reliable internal clock source to provide a clock to the Retimer chip when the external differential clock is unstable.

[0029] The control selection module is used to select an external differential clock or an internal differential clock as the clock of the Retimer chip according to the configuration information and the flag signal.

[0030] The adaptive startup clock system can select a clock providing mode through pre-configuration information, and can adaptively switch to an internal differential clock when the quality of the external differential clock does not meet the requirements.

[0031] Furthermore, the adaptive startup clock system also includes a chip initialization configuration module, which is mainly used to provide configuration information. In this embodiment, the configuration information provided mainly includes clock selection mode and clock frequency requirement information, wherein the clock selection mode mainly includes three types: 2bit 00: only select the internal differential clock; 2bit 01: only select the external differential clock; 2bit 10: adaptively select the clock. The clock frequency requirement information includes two ppm ranges: ppm:0 requires the clock frequency deviation to be (99.04M--100.06M); ppm:1 requires the clock frequency deviation to be (99.5M--100.5M).

[0032] In practical applications, the configuration information in the one-time programmable memory eFuse is read through bus control, converted into register information, and provided to the external reference clock detection module and the control selection module.

[0033] Please refer to Figure 2An embodiment of the present invention provides a specific implementation method of an external reference clock detection module, which includes a clock receiving module, a first configuration information receiving module and a clock detection and output module, wherein the clock receiving module is used to receive an external differential clock; the first configuration information receiving module is used to receive a clock selection mode and clock frequency requirement information; the clock detection and output module is used to detect the external differential clock according to the clock selection mode and the clock frequency requirement information, and control the output of the external differential clock and the flag signal according to the detection result.

[0034] For details, please refer to Figure 3 The clock detection and output module includes a detection enable module, a reference frequency generation module, a frequency detection module, a clock frequency requirement information storage module and a clock judgment module, wherein: The detection enable module mainly determines whether to enable the external reference clock detection module according to the clock selection mode to detect the external differential clock. In this embodiment, when the clock selection mode is 2bit 00, that is, only the internal differential clock is selected, the external reference clock detection module does not need to be enabled. When the clock selection mode is 2bit 01 or 2bit 10, the external reference clock detection module needs to be enabled to work.

[0035] The reference frequency generation module is mainly used to generate a reference clock with a fixed frequency and provide it to the frequency detection module. In one embodiment, a 1G clock is generated as a reference clock for subsequent detection. The frequency detection module receives an external differential clock and combines it with a reference clock to complete external differential clock frequency detection and mode judgment, etc., wherein the mode of the external differential clock includes a same frequency clock or a spread spectrum clock. The clock frequency requirement information storage module is used to receive and store the clock frequency requirement information from the configuration information.

[0036] The clock judgment module judges whether the external differential clock meets the quality requirements based on the clock frequency requirement information and the detected external differential clock frequency, and then controls the output of the external differential clock and the flag signal.

[0037] Specifically, after the detection enable module is enabled, the external differential clock signal is detected to determine whether it belongs to the same frequency clock or the spread spectrum clock, and the output flag signal is determined according to the type of the external differential clock. Specifically, the same frequency clock determination method includes: determining whether the frequency of the external differential clock is the same frequency as the reference clock, if so, outputting the external differential clock and a high-level flag signal, otherwise outputting the external differential clock and a low-level flag signal. The spread spectrum clock determination method includes: determining whether the external differential clock frequency deviation is within the frequency deviation range limited by the clock frequency requirement information (in this embodiment, ppm:0 requires the clock frequency deviation to be within (99.04M--100.06M); ppm:1 requires the clock frequency deviation to be within (99.5M--100.5M)), if so, outputting the external differential clock and a high-level flag signal, otherwise outputting the external differential clock and a low-level flag signal.

[0038] The quality detection of the external differential clock can be realized based on the external reference clock detection module, thereby providing a reliable external differential clock for use by the subsequent control selection module.

[0039] Please refer to Figure 4 The control selection module mainly includes a first clock receiving module, a second clock receiving module, a second configuration information receiving module, and a clock adaptive output module, wherein the first clock receiving module is used to receive the external differential clock and the flag signal output by the external reference clock detection module; the second clock receiving module is used to receive the internal differential clock; the second configuration information receiving module is used to receive the clock selection mode and the reset signal, and the reset signal is provided externally; the clock adaptive output module is used to select the corresponding clock output according to the clock selection mode, the reset signal and the flag signal.

[0040] In the control selection module, its work mainly depends on the clock selection mode, that is, when the clock selection mode is 2bit 00, only the internal differential clock output is selected; when the clock selection mode is 2bit 01, only the external differential clock output is selected; when the clock selection mode is 2bit 10, the corresponding clock output is adaptively selected, wherein the adaptive selection and output of the corresponding clock is based on the reset signal and the flag signal.

[0041] Please refer to Figure 5 , which shows a timing diagram of adaptively selecting and outputting the corresponding clock in an embodiment, that is, when the clock selection mode is 2bit 10, the reset signal is detected. If the reset signal is low, the internal differential clock is output. If the reset signal is high, the flag signal is further judged. At this time, if the flag signal is high, the external differential clock is output. If the flag signal is low, the internal differential clock is output.

[0042] It should be supplemented that the adaptive start clock system also includes a reset control module, which is used to provide a reset instruction according to an external reset circuit, generate a reset signal and provide it to the control selection module, thereby realizing adaptive selection and outputting a corresponding clock.

[0043] Furthermore, the adaptive start-up clock system also includes a clock output module, which is used to output the clock selected by the control selection module to the next-level chip of the Retimer chip.

[0044] The adaptive start clock system proposed in the embodiment of the present invention has the following advantages: (1) It provides a reliable built-in clock method that can generate a reliable internal differential clock. In addition to providing a clock to the Retimer itself, it can also output it to the next-level chip of the Retimer chip.

[0045] (2) It provides a method for detecting and judging an external reference clock, which effectively solves the problem that the Retimer chip itself lacks monitoring of the external reference clock and provides a new solution for the stable operation of the entire Retimer chip.

[0046] (3) It provides a reliable escape or avoidance method, that is, when the external differential clock of the Retimer chip fails, it can adaptively switch to the internal differential clock. The system can flexibly adapt to the Retimer chip and effectively solve the compatibility issues of different chip manufacturers by adaptively selecting the internal differential clock or the external differential clock.

[0047] Furthermore, the features, structures or characteristics described in the present application may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the terms "connect", "couple" and "connected to" are used to specify electrical connections between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there are no intermediate elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein may be arranged and designed in various different configurations.

[0048] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An adaptive startup clock system for a Retimer chip, characterized in that: include: An external reference clock detection module, used to detect the frequency of the external differential clock according to the configuration information, generate a flag signal and output the external differential clock; Internal clock generation module, providing stable internal differential clock; The control selection module is used to select an external differential clock or an internal differential clock as the clock of the Retimer chip according to the configuration information and the flag signal.

2. The adaptive startup clock system of the Retimer chip according to claim 1, characterized in that: It also includes a chip initialization configuration module for providing configuration information; the configuration information includes clock selection mode and clock frequency requirement information.

3. The adaptive startup clock system of the Retimer chip according to claim 1 or 2, characterized in that: A reset control module is also included, which is used to provide a reset signal according to an external reset circuit.

4. The adaptive startup clock system of the Retimer chip according to claim 2, characterized in that: The external reference clock detection module comprises: A clock receiving module, used for receiving an external differential clock; A first configuration information receiving module, used to receive clock selection mode and clock frequency requirement information; The clock detection and output module is used to detect the external differential clock according to the clock selection mode and the clock frequency requirement information, and control the output of the external differential clock and the flag signal according to the detection result.

5. The adaptive startup clock system of the Retimer chip according to claim 4, characterized in that: The clock detection and output module comprises: A detection enabling module, used for enabling an external reference clock detection module according to a clock selection mode; A reference frequency generation module, used to generate a reference clock with a fixed frequency; A frequency detection module, used for receiving an external differential clock and a reference clock, and detecting a mode and a frequency of the external differential clock; A clock frequency requirement information storage module, used for storing clock frequency requirement information; The clock determination module is used to control the output of the external differential clock and the flag signal according to the mode, frequency and clock frequency requirement information of the external differential clock.

6. The adaptive startup clock system of the Retimer chip according to claim 5, characterized in that: In the clock determination module, controlling the output of the external differential clock and the flag signal specifically includes: The mode of the external differential clock includes a same-frequency clock or a spread-spectrum clock, and outputs an external differential clock and a flag signal that meet the requirements according to the determination method of the same-frequency clock or the spread-spectrum clock; The same-frequency clock determination method includes: determining whether the frequency of the external differential clock is the same as the reference clock, and if so, outputting the external differential clock and a flag signal; The detection of the spread spectrum clock judgment method includes: judging whether the frequency deviation of the external differential clock is within the frequency deviation range limited by the clock frequency requirement information, and if so, outputting the external differential clock and the flag signal.

7. The adaptive startup clock system of the Retimer chip according to claim 3, characterized in that: The control selection module comprises: A first clock receiving module, used for receiving an external differential clock and a flag signal output by an external reference clock detection module; A second clock receiving module, used for receiving an internal differential clock; A second configuration information receiving module, used for receiving a clock selection mode and a reset signal; The clock adaptive output module is used to select the corresponding clock output according to the clock selection mode, reset signal and flag signal.

8. The adaptive startup clock system of the Retimer chip according to claim 7, characterized in that: The specific working process of the clock adaptive output module includes: When the clock selection mode is the first mode, the internal differential clock output is selected; When the clock selection mode is the second mode, select the external differential clock output; When the clock selection mode is the third mode, the corresponding clock is adaptively selected and output; wherein the adaptive selection and output of the corresponding clock is implemented based on the reset signal and the flag signal.

9. The adaptive startup clock system of the Retimer chip according to claim 8, characterized in that: The specific process of adaptively selecting and outputting the corresponding clock includes: When the reset signal is high, the internal differential clock is output; When the reset signal is low and the flag signal is high, the external differential clock is output, otherwise the internal differential clock is output.

10. The adaptive startup clock system of the Retimer chip according to claim 1 or 2, characterized in that: It includes a clock output module, which is used to output the clock selected by the control selection module to the next level chip of the Retimer chip.

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