Memory management method and device

Abstract

The embodiment of the invention provides a memory management method and device, and relates to the technical field of computers. The memory management method comprises the following steps: acquiring address information of one or more memory spaces accessed in a sampling period; based on the obtained one or more pieces of address information, counting first access times of the one or more memory pages to obtain popularity data of each memory page; wherein each memory page is used for indicating a memory space corresponding to the memory page; and performing memory management based on the popularity data of each memory page. The memory management efficiency can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a memory management method and device. Background Art

[0002] Memory is an important component of a computer, also known as internal memory and main memory. It can be used to store the calculation data in the CPU and the data exchanged with peripherals such as hard disks, which has an important impact on the performance of the computer. With the development of computer technology, memory can be accessed through page tables to improve access efficiency. Among them, the page table is used to indicate the mapping relationship between the virtual address space and the physical address space. The memory space pointed to by the mapping relationship indicated by the page table can be called a memory page. Access to memory pages can be reflected in the page table. In this way, according to the difference in the frequency of users accessing memory pages, the heat data of the memory can be determined for memory management (such as memory classification decisions, memory data migration, etc.).

[0003] In the related art, the access flag (AccessFlag, AF) field of the page table descriptor can be set when accessing a memory page to indicate that the page table is accessed. The page table descriptors of all memory pages to be identified are traversed during the hot page identification cycle to obtain the number of accesses to each memory page to be identified, and the heat data of the memory page to be identified is determined based on the number of accesses.

[0004] However, it takes too long to traverse the page table descriptors corresponding to all memory pages to be identified, especially when there are more memory pages to be identified, the time taken is longer, resulting in the problem of untimely hot page identification and low memory management efficiency. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a memory management method and device. The memory management method can determine the heat data of the corresponding memory page by counting the address information of the accessed memory space, and then perform memory management based on the heat data, without traversing the page table descriptor corresponding to each memory page, thereby reducing time consumption and improving memory management efficiency.

[0006] In a first aspect, an embodiment of the present application provides a memory management method, the method comprising: obtaining address information of one or more memory spaces accessed within a sampling period; based on the obtained one or more address information, counting the first access times of one or more memory pages to obtain heat data of each memory page; wherein each memory page is used to indicate the memory space corresponding to the memory page; and performing memory management based on the heat data of each memory page.

[0007] In the embodiment of the present application, by acquiring the address information of the memory space accessed during the sampling period, and based on the collected address information, counting the number of accesses to the memory space accessed, the heat data of one or more memory pages indicating the memory space accessed is obtained, and then memory management is performed based on the heat data of each memory page. In this way, the heat data of the corresponding memory page can be obtained for memory management by collecting and counting the address information of the memory space accessed, without traversing the page table descriptor corresponding to each memory page, thereby greatly reducing the time consumption and improving the efficiency of memory management. In addition, the scheme of the embodiment of the present application does not introduce additional processes that have a negative impact on memory access (such as page missing exceptions), which can avoid the negative impact of memory management on business performance and further improve the efficiency of memory management.

[0008] According to the first aspect, address information of one or more memory spaces accessed within a sampling period is obtained, including: determining a second access count of a target access in accesses to the one or more memory spaces; and obtaining address information of one or more memory spaces accessed through the target access within the sampling period when the second access count satisfies a sampling threshold.

[0009] The embodiment of the present application adds a trigger condition regarding the access frequency of the memory, and increases the sampling frequency in scenarios where the memory is frequently accessed, thereby improving the accuracy of hot page statistics and ensuring more accurate memory management.

[0010] According to the first aspect, or any implementation method of the first aspect above, when the second access number meets the sampling threshold, the address information of one or more memory spaces accessed through the target access within the sampling period is obtained, including: when the second access number meets the sampling threshold, the address information of one or more memory spaces most recently accessed through the target access is obtained; the second access number is reset, and the second access number of the target access in the access to the one or more memory spaces is determined until the sampling period ends.

[0011] In the embodiment of the present application, each time address information collection is completed, a new second access number is determined by resetting the second access number, thereby improving the matching degree between the second access number and the actual access situation, ensuring that the collection result of the address information is more matched with the actual access situation, thereby improving the accuracy of the heat data, and further improving the accuracy of memory management.

[0012] According to the first aspect, or any implementation of the first aspect above, the target access includes at least one of the following: a load operation, a store operation, an access resulting in a memory access cache miss, and an access resulting in an address translation lookup miss.

[0013] In the embodiments of the present application, frequent access scenarios may include frequent reading and writing scenarios, and / or scenarios where PMU events are frequently triggered. In this way, the applicable scenarios are expanded and the memory management efficiency is further improved.

[0014] According to the first aspect, or any implementation of the first aspect above, based on the obtained one or more address information, the first access times of one or more memory pages are counted to obtain the heat data of each memory page, including: according to the format requirements of the custom data packet in the statistical analysis extension (SPE), the one or more address information obtained are respectively constructed into SPE address packets to obtain an SPE address packet sequence; the SPE address packet sequence is written out to the SPE cache; based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page.

[0015] In the embodiment of the present application, the SPE path is reused to write out the acquired address information, and there is no need to specially design a write path, thereby reducing the complexity of implementation and the complexity of software development, and facilitating the convenience of memory management.

[0016] According to the first aspect, or any implementation of the first aspect above, based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page, including: in the case of SPE cache overflow, based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page.

[0017] In the embodiment of the present application, the sampling period is controlled by overflow of the SPE cache, storage cost and sampling requirement are taken into consideration, and logic settings for managing data of different sampling periods are avoided, thereby further improving memory management efficiency.

[0018] According to the first aspect, or any implementation of the first aspect above, the address information includes: an address in a translation lookaside buffer (TLB), and / or an address for remote access.

[0019] In the embodiment of the present application, the address in the existing TLB is used as the address information to explore the hot page semantics of the TLB, that is, the more times a page is accessed, the greater the probability of its existence in the TLB, and the more times multiple sampling is taken. In this way, the information of the TLB can be fully utilized without the need to develop additional logic for recording the number of accesses, thereby ensuring that memory management is more convenient. In addition, the address of remote access is used as the address information to ensure that the scenario in which the remote memory is transformed into a hot page as the access situation changes can be identified, thereby improving the accuracy of hot page identification and the accuracy of memory management.

[0020] In a second aspect, an embodiment of the present application provides a memory management device, which includes: an address sampling module, used to obtain address information of one or more memory spaces accessed within a sampling period; a heat determination module, used to count the first access times of one or more memory pages based on the obtained one or more address information, and obtain heat data of each memory page; wherein each memory page is used to indicate the memory space corresponding to the memory page; and a memory management module, used to perform memory management based on the heat data of each memory page.

[0021] According to the second aspect, the address sampling module is specifically used to: determine the second access number of the target access in the access to one or more memory spaces; when the second access number meets the sampling threshold, obtain the address information of one or more memory spaces accessed by the target access within the sampling period.

[0022] According to the second aspect, or any implementation method of the second aspect above, the address sampling module is specifically used to: when the second access number meets the sampling threshold, obtain the address information of one or more memory spaces most recently accessed through the target access; reset the second access number, and execute the second access number of the target access in the access to one or more memory spaces until the sampling period ends.

[0023] According to the second aspect, or any implementation of the second aspect above, the target access includes at least one of the following: a load operation, a store operation, an access resulting in a memory access cache miss, and an access resulting in an address translation lookup miss.

[0024] According to the second aspect, or any implementation of the second aspect above, the heat determination module is specifically used to: construct the acquired one or more address information into SPE address packets according to the format requirements of the custom data packet in the statistical analysis extension (SPE) to obtain an SPE address packet sequence; write the SPE address packet sequence to the SPE cache; based on the SPE address packet sequence in the SPE cache, count the first access times of one or more memory pages to obtain heat data of each memory page.

[0025] According to the second aspect, or any implementation of the second aspect above, the heat determination module is specifically used to: in the event of an SPE cache overflow, based on the SPE address packet sequence in the SPE cache, count the first access times of one or more memory pages to obtain heat data for each memory page.

[0026] According to the second aspect, or any implementation of the second aspect, the address information includes: an address in a translation lookaside buffer (TLB), and / or an address for remote access.

[0027] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0028] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a memory; the processor and the memory are connected; the memory is used to store one or more programs; when the one or more programs are executed by one or more processors, the one or more processors implement a method such as the first aspect and any one of the implementation methods of the first aspect.

[0029] In a fourth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0030] In a fifth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0031] In the sixth aspect, an embodiment of the present application provides a chip, which includes one or more interface circuits and one or more processors; the interface circuit is used to receive signals from a memory of an electronic device and send signals to the processor, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device executes the instructions of the method in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0033] Figure 1 It is a schematic diagram of setting the page table descriptor;

[0034] Figure 2 is a structural block diagram of a hierarchical memory system provided by an embodiment of the present application;

[0035] Figure 3 is a structural block diagram of a memory management device provided in an embodiment of the present application;

[0036] Figure 4It is a flowchart of a memory management method provided in an embodiment of the present application;

[0037] Figure 5 It is one of the example diagrams of the SPE address packet sequence provided in the embodiment of the present application;

[0038] Figure 6 It is one of the example diagrams of the SPE address packet sequence provided in the embodiment of the present application;

[0039] Figure 7 It is one of the example diagrams of the SPE address packet sequence provided in the embodiment of the present application;

[0040] Figure 8 This is one of the example diagrams of the processing process of a memory management method provided in an embodiment of the present application;

[0041] Fig. 9 This is one of the example diagrams of the processing process of a memory management method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0044] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0045] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0046] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0047] Hot page identification technology can obtain the heat data of memory pages and is a key technology for memory management. For example, Figure 1 This is a schematic diagram of setting the page table descriptor. Figure 1 As shown, a page table is a data structure that records mapping relationships that can realize the association between virtual address space (VA) and physical address space. For example, the physical page mapped by the page table entry page in the fourth-level page table level 3 is the physical address space, and the physical address space mapped by the page table entry table in the first-level page table level 0 can be mapped through the page table entry in the next-level page table level 1. The page table entry can correspond to a 64-bit page table description (64-bit page descriptor), in which bit 10 (i.e., the 11th bit) is the page table descriptor, and the page table descriptor can be used to indicate whether the physical address space mapped by the page table is accessed. On this basis, the heat data of the memory page can be obtained by setting the page table descriptor, which can specifically include the following steps (1) to (4):

[0048] (1) Before obtaining the heat data, clear the AF of the page table descriptor of the managed memory, that is, set AF=0; the memory with AF=0 can be called the target memory;

[0049] (2) During the sampling period, the hardware (such as a processor) accesses the target memory, and the hardware sets the AF of the page table descriptor of the target memory to 1; for example, Figure 1 The memory page used to indicate the target memory is the level 3 of the four-level page table. When accessing the physical page corresponding to the page table entry page of the level 3 of the page table, the hardware sets the corresponding page table descriptor AF;

[0050] (3) The software traverses all managed page table descriptors to obtain information about pages that have been accessed during the sampling period;

[0051] (4) Steps (1) to (3) are one sampling. After multiple sampling cycles, the number of visits to each managed page is obtained to form heat statistics.

[0052] However, scanning the page table to obtain the page table descriptor takes a long time. The larger the managed memory, the more the software needs to scan. For example, in the cloud scenario, considering the bandwidth of the subsequent memory migration, the page table needs to be broken up first. In this way, it takes seconds to fully scan the page table of 100G memory specifications.

[0053] In another example, based on the page fault synchronization exception function provided by the hardware, page information can be recorded in the exception handling. Specifically, the following steps can be included:

[0054] (1) Clear the read / write execution permissions of the page table entries for the page table descriptor of the managed memory;

[0055] (2) During management, memory read / write access triggers a page fault and is reported;

[0056] (3) Receive the reported page fault exception, process the exception address and record the page information;

[0057] (4) During the management period, heat statistics are generated based on the page information recorded in the exception handling of multiple page faults.

[0058] However, this has a serious impact on business performance. Each page fault introduces an additional software process. The kernel takes an average of 0.2us to process a 4k page fault, and 12.5s for 100G memory. In addition, to reduce the impact of page faults on business, the scanning cycle and the managed page range are usually restricted, resulting in limited accuracy of heat statistics and inaccurate memory management.

[0059] The embodiment of the present application provides a memory management method to solve the above problems. The method obtains the address information of the memory space accessed during the sampling period, and based on the collected address information, counts the number of accesses to the accessed memory space, obtains the heat data for indicating one or more memory pages of the accessed memory space, and then performs memory management based on the heat data of each memory page. In this way, the heat data of the corresponding memory page can be obtained by collecting and counting the address information of the accessed memory space for memory management, without traversing the page table descriptor corresponding to each memory page, thereby greatly reducing the time consumption and improving the efficiency of memory management. In addition, the scheme of the embodiment of the present application does not introduce additional processes that have a negative impact on memory access (such as page fault exceptions), which can avoid the negative impact of memory management on business performance and further improve the efficiency of memory management.

[0060] Before describing the technical solution of the embodiment of the present application, the operating platform of the memory management method of the embodiment of the present application is first described in conjunction with the accompanying drawings. The embodiment of the present application can be applied to platforms such as hierarchical memory systems and memory management devices where memory management scenarios exist. In the specific implementation of the embodiment of the present application, the hierarchical memory system can run in the hot and cold page identification nodes of public clouds and private clouds. For example, Figure 2 is a structural block diagram of a hierarchical memory system provided by an embodiment of the present application. Figure 2As shown, the system may include: a virtual machine (VM), a management layer (Hypervisor), hardware including proximal memory DRAM, and a memory node including remote pooled memory (a node different from the hot and cold page identification node, i.e., memory managed in the form of a memory pool in the remote end). The virtual machine is used to provide cloud services, and the management layer is used to perform memory management, which may specifically include performing cold and hot page identification, determining a decision strategy based on the identification results, and migrating memory based on the decision strategy. Migrating memory, for example, may be migrating cold pages and / or hot pages between proximal memory DRAM and remote pooled memory.

[0061] For example, in a public cloud scenario, there are differences in the memory usage frequency of sold virtual machines. Cloud vendors use a hierarchical memory system to manage the memory of the sold virtual machines. The data in the hot memory with high usage frequency is stored in the local DRAM, that is, the proximal DRAM. The data in the memory with low usage frequency or not used is migrated and stored in the remote pooled memory or medium, so as to achieve the effect of improving the utilization rate of the local DRAM. The main steps of hierarchical memory management are divided into hot and cold page identification, decision-making strategy and memory migration. The memory management method provided in the embodiment of the present application is used to optimize the identification of hot and cold pages. A method for identifying hot pages can be provided on the chip, and hot page information, that is, the heat data of the memory page, can be provided to support the software to make decisions and memory migration for memory management.

[0062] It should be understood that Figure 2 The system shown is only one example of a hierarchical memory system, and the hierarchical memory system may have more or fewer components than shown, may combine two or more components, or may have a different configuration of components. Figure 2 The various components shown in the EMBODIMENTS 2000 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.

[0063] In one example, for memory management in IT technology, for example, in the field of high performance computing (HPC), operations have high demands on data throughput, and high bandwidth memory (HBM) is used to meet the operation requirements. The memory management method provided in the embodiment of the present application can be deployed in HBM to accelerate the identification of hot data used in the operation, so as to achieve a smaller HBM capacity to meet the high performance operation requirements.

[0064] In one example, for the storage field, the memory management method provided by the embodiments of the present application can identify the heat of memory pages, save the data in the hottest memory pages in the memory, save the data in the less hot memory pages in the solid-state drive (SSD), and save the data in the cold memory pages in the mechanical hard disk / tape memory, so as to meet the same storage capacity while reducing the media cost.

[0065] Exemplarily, Figure 3 is a structural block diagram of a memory management device provided by the embodiments of the present application. As Figure 3 shown, the memory management device can run in Figure 2 the hierarchical management system shown, or can run on an electronic device for memory management. In a specific application, the electronic device may include a mobile terminal, a computer, a wearable intelligent terminal, etc. The memory management device may specifically include:

[0066] An address sampling module 301, configured to obtain address information of one or more memory spaces accessed within a sampling period;

[0067] A heat determination module 302, configured to count the first access times of one or more memory pages based on the obtained one or more address information, so as to obtain the heat data of each memory page; wherein each memory page is used to indicate the memory space corresponding to the memory page;

[0068] A memory management module 303, configured to perform memory management based on the heat data of each memory page.

[0069] It should be understood that Figure 3 the device shown is only an example of the memory management device, and the memory management device may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. Figure 3 The various components shown in

[0070] can be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application specific integrated circuits. Figures 4 to 8 The following specifically describes the memory management method provided by the embodiments of the present application with reference to

[0071] Exemplarily, Figure 4 is a flowchart of a memory management method provided by the embodiments of the present application. As Figure 4 shown, a memory management method may specifically include:

[0072] S401, obtaining address information of one or more memory spaces accessed within a sampling period.

[0073] In a specific application, the sampling period may be one or more, and the address information may be sampled or acquired once or multiple times in one sampling period, and one sampling is used to acquire the address information of one memory space.

[0074] In an optional implementation, the address information includes: an address in a translation lookaside buffer (TLB), and / or an address for remote access.

[0075] Exemplarily, TLB is used to cache the page table mapping relationship of the accessed memory page until the TLB capacity is insufficient and it is replaced by the page table mapping relationship of the updated memory page. TLB is a cache that can improve the speed of virtual address to physical address conversion; the access speed is very fast, comparable to that of a register. In other words, the physical address of the memory page is stored in a TLB table entry, and subsequent accesses to the same linear address (Linear Address, logical address, i.e., the middle layer between the virtual address space and the physical address conversion) can directly obtain the physical address from the TLB table entry to access the physical address space indicated by the physical address, which is called a TLB hit. The more frequently the memory page is accessed, the higher the heat, the greater the probability of being cached in the TLB, and the greater the number of times it is sampled.

[0076] The remote access address is used to indicate the remote memory, for example, it can be the above Figure 2 The address in the remote pooled memory is shown. It can be understood that the access delay of the remote memory is greater than the access delay of the near memory. The specific remote memory and near memory can be set according to application requirements, and the embodiment of the present application does not limit this.

[0077] In the embodiment of the present application, the address in the existing TLB is used as the address information to explore the hot page semantics of the TLB, that is, the more times a page is accessed, the greater the probability of its existence in the TLB, and the more times multiple sampling is taken. In this way, the information of the TLB can be fully utilized without the need to develop additional logic for recording the number of accesses, thereby ensuring that memory management is more convenient. In addition, the address of remote access is used as the address information to ensure that the scenario in which the remote memory is transformed into a hot page as the access situation changes can be identified, thereby improving the accuracy of hot page identification and the accuracy of memory management.

[0078] S402, based on the obtained one or more address information, count the first access times of one or more memory pages to obtain heat data of each memory page; wherein each memory page is used to indicate a memory space corresponding to the memory page.

[0079] In an optional implementation, obtaining address information of one or more memory spaces accessed during a sampling period may specifically include the following steps:

[0080] determining a second access count of a target access in accesses to the one or more memory spaces;

[0081] When the second access number satisfies the sampling threshold, address information of one or more memory spaces accessed by the target access within the sampling period is obtained.

[0082] In an optional implementation, the target access includes at least one of the following: a load operation, a store operation, an access resulting in a memory access cache miss, and an access resulting in an address translation lookup miss.

[0083] Exemplarily, a memory read, i.e., a load operation, refers to reading data from memory into a register. A memory write, i.e., a store operation, refers to writing data from a register into memory. Both load operations and store operations are micro-operations (uops). Memory access cache misses and address translation lookup misses are events detected by a performance monitor unit (PMU), and may be referred to as PMU events.

[0084] Memory access cache misses, for example, can be LLC (L3, the third level cache obtained by memory hierarchy division) miss. LLC miss means that when LLC cannot read data, data is read from double rate synchronous dynamic random access memory (DDR). There are several levels of cache in the CPU, and each level of cache is faster than the next level of cache. The last level of cache is called LLC (Last Level Cache); after LLC is the memory.

[0085] An access that does not hit the address translation lookup can be, for example, a TLB miss. A TLB miss can include when the CPU accesses a virtual address / linear address, the CPU will first look up the upper 20 bits of the virtual address in the TLB (20 is x86-specific and has different values ​​for different architectures). If there is no corresponding entry in the table, it is called a TLB miss, and the corresponding physical address needs to be calculated by accessing the page table in the slow RAM.

[0086] In the embodiments of the present application, frequent access scenarios may include frequent reading and writing scenarios, and / or scenarios where PMU events are frequently triggered. In this way, the applicable scenarios are expanded and the memory management efficiency is further improved.

[0087] Exemplarily, the second access number of the target access can be counted by setting a counter, and each time the counter is triggered, it is equivalent to a count of the second access number. For example, the counter can be decremented or incremented. The trigger condition is the above-mentioned target access. Based on this, the counter decrements to 0 or increases to the sampling threshold, triggering a hot page sampling, that is, the acquisition of address information, and collecting several address information in the TLB.

[0088] In the embodiment of the present application, a trigger condition for the access frequency of the memory is added, and the sampling frequency is increased in the scenario where the memory is frequently accessed, thereby improving the accuracy of the hot page statistics and ensuring more accurate memory management. For example, this can enhance the characteristics of the statistical profiling extension (SPE) under the ARM architecture, that is, adding a trigger condition for the access frequency of the memory on the basis of the existing SPE.

[0089] In an optional implementation, based on the acquired one or more address information, the first access times of one or more memory pages are counted to obtain the heat data of each memory page, which may specifically include the following steps:

[0090] According to the format requirements of the custom data packet in the statistical analysis extension (SPE), the acquired one or more address information are respectively constructed into SPE address packets to obtain an SPE address packet sequence;

[0091] Write out the SPE address packet sequence to the SPE buffer;

[0092] Based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page.

[0093] Among them, statistical profiling extension (SPE): SPE provides hardware support for statistical sampling under the ARM architecture (a processor architecture).

[0094] For example, Figure 5 This is one of the example diagrams of the SPE address packet sequence provided in the embodiment of the present application. Figure 5As shown, this embodiment is equivalent to writing out address information: after triggering sampling, the address information in the collected TLB is constructed as (SPEaddress packet). Specifically, the header position in the SPE address packet constructs a header index (headerINDEX) to indicate that the address written is a custom address, which is described as "IMPLEMENTATION DEFINEaddress", and fills the address in the collected TLB into the payload field, which is the data in the packet. For example, in the SPE address packet sequence example 1, the header corresponding to the first byte, the data corresponding to byte "1" and byte "2" are one SPE address packet; the header corresponding to byte "3" and the data corresponding to byte "4" are another SPE address packet, and these two SPE address packets contain different address information. After sampling addresses in several TLBs, several SPE address packet sequences are constructed, and the end of the sequence, that is, the last byte, ends with a sequence end packet (End Packet), such as 0x01 in the SPE address packet sequence example 1, or ends with a timestamp packet (TS Packet), such as TS[63:56] in the SPE address packet sequence example 2. In this way, it is equivalent to using the existing transmission mechanism of the ARM architecture (a processor architecture). Accordingly, the specific structure of the data in the address packet meets the format requirements of the custom data packet in the SPE in the ARM architecture. In addition, the first identifier added in the payload field in the address packet can indicate that the address packet is an address in the TLB. It can be understood that in addition to the address packet in the embodiment of the present application, the SPE address packet sequence can also contain other data under the ARM architecture.

[0095] For example, Figure 6 This is one of the example diagrams of the SPE address packet sequence provided in the embodiment of the present application. Figure 6 As shown in the figure, when the collected address information is the address of remote access, the SPE address packet sequence is Figure 5 The structure shown is similar to that shown in FIG. 1 , except that the second identifier added to the payload field in the address packet indicates that the address packet is a remote access address. The same parts will not be described here, see the above Figure 5 Description of embodiments.

[0096] Understandably, Figure 5 and Figure 6 The marking method for different address information in the embodiment is only an example. Any method that can indicate that the address information in the data packet is an address in the TLB or an address for remote access can be used in this application, and this implementation does not impose any restrictions on this.

[0097] For example, Figure 7This is one of the example diagrams of the SPE address packet sequence provided in the embodiment of the present application. Figure 7 As shown, when both the address in the TLB and the address of the remote access are sampled, the SPE address packet sequence may include data packets marked as the address of the remote access and data packets marked as the address in the TLB, for example, SPE address packet sequence example 5 or SPE address packet sequence example 6. It is understandable that Figure 7 The order relationship between the data packets of the remote access address and the data packets of the address in the TLB is only an example and does not constitute a restriction on the order between the data packets of different addresses in the SPE address packet sequence. The order between different data packets depends on the actual sampling situation.

[0098] In the embodiment of the present application, the SPE path is reused to write out the acquired address information, and there is no need to specially design a write path, thereby reducing the complexity of implementation and the complexity of software development, and facilitating the convenience of memory management.

[0099] In an optional implementation, when the second access count satisfies the sampling threshold, acquiring address information of one or more memory spaces accessed by the target access within the sampling period may specifically include the following steps:

[0100] When the second access count satisfies the sampling threshold, acquiring address information of one or more memory spaces most recently accessed through the target access;

[0101] The second access count is reset, and the second access count of the target access in the access to the one or more memory spaces is determined until the sampling period ends.

[0102] Exemplarily, the target access may include at least one of the following: a load operation, a store operation, an access with a memory access cache miss, and an access with an address translation lookup miss. The address information of a sampling, such as a packet sequence, may be taken as a record and written to a designated cache, such as an SPE buffer. After the record is written out, the counter is reset and the next sampling is started until the sampling cycle ends.

[0103] In the embodiment of the present application, each time address information collection is completed, a new second access number is determined by resetting the second access number, thereby improving the matching degree between the second access number and the actual access situation, ensuring that the collection result of the address information is more matched with the actual access situation, thereby improving the accuracy of the heat data, and further improving the accuracy of memory management.

[0104] In an optional implementation, based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page, which may specifically include the following steps:

[0105] In the case of SPE cache overflow, the first access times of one or more memory pages are counted based on the SPE address packet sequence in the SPE cache to obtain the heat data of each memory page.

[0106] For example, several sampling records are written until the SPE buffer overflows and an interrupt is reported. In this way, all sampled page information, i.e., address information, of this sampling cycle can be extracted, and the number of address information corresponding to each memory page can be counted, i.e., the number of times each memory page is accessed can be obtained, and thus the heat data of each memory page can be obtained.

[0107] In the embodiment of the present application, the sampling period is controlled by the overflow of the SPE buffer, the storage cost and the sampling requirement are taken into consideration, and the logic setting for managing data of different sampling periods is avoided, thereby further improving the memory management efficiency.

[0108] S403, performing memory management based on the heat data of each memory page.

[0109] For example, in public cloud scenarios, memory costs are high, but customer memory utilization is low. Improving memory utilization, making full use of sold but unused memory, and reducing memory costs have become important issues for cloud vendors. Using tiered memory and making tenants unaware of memory over-division is one of the solutions. By identifying memory usage in real time, obtaining memory page heat data, and then determining hot and cold memory pages, memory can be upgraded and downgraded dynamically. Hot data that customers use frequently, that is, data in hot memory, is stored in local memory, and cold data that is not currently in use, that is, data in cold memory, is stored remotely or in other media.

[0110] Alternatively, memory management can be as described above Figure 2 The application of the heat data of memory pages in the IT field and the storage field in the embodiment is detailed in the above Figure 2 The description of the embodiments will not be repeated here.

[0111] For example, Figure 8 FIG. 1 is one of the example diagrams of the processing process of a memory management method provided in an embodiment of the present application. Figure 8 As shown, the processing process of the memory management method may include:

[0112] Step 1, based on the access operation to the memory space, collect address information;

[0113] Step 2: filter the address information according to the access type to obtain the address information corresponding to the access of the target type;

[0114] Step 3: Write a custom address package based on the address information corresponding to the target type of access.

[0115] The target type of access may include at least one of the following: a load operation, a store operation, an access with a memory access cache miss, and an access with an address translation lookup miss. The custom address packet is an SPE address packet sequence. Figure 8 Embodiment and above Figure 4 Embodiment and Figure 4 The optional embodiments are similar except that Figure 8 The embodiment filters the address information through step 2, thereby ensuring that the address information includes the address in the translation lookaside buffer (TLB) and / or the address of the remote access. For the same part, see the above Figure 4 Embodiment and Figure 4 The description of the optional embodiments will not be repeated here.

[0116] Fig. 9 FIG. 1 is one of the example diagrams of the processing process of a memory management method provided in an embodiment of the present application. Fig. 9 As shown, the processing process of the memory management method may include:

[0117] Step 1, based on the sampling threshold, set a counter;

[0118] Step 2, trigger counter-1 until counter == 0; wherein the trigger condition includes target access to the memory space;

[0119] Step 3, based on the access operation to the memory space, collect address information;

[0120] Step 4, based on the address information corresponding to the access of the target type, write out the collected address information, reset the counter (reload counter), and execute step 1 again until the sampling period ends.

[0121] Fig. 9 Embodiment and above Figure 4 Embodiment and Figure 4 The optional embodiments are similar except that Fig. 9 The embodiments are integrated and described in different ways for easy understanding. For the same parts, please refer to the above Figure 4 Embodiment and Figure 4 The description of the optional embodiments will not be repeated here.

[0122] The embodiment of the present application provides a memory management method to solve the above problems. The method obtains the address information of the memory space accessed during the sampling period, and based on the collected address information, counts the number of accesses to the accessed memory space, obtains the heat data for indicating one or more memory pages of the accessed memory space, and then performs memory management based on the heat data of each memory page. In this way, the heat data of the corresponding memory page can be obtained by collecting and counting the address information of the accessed memory space for memory management, without traversing the page table descriptor corresponding to each memory page, thereby greatly reducing the time consumption and improving the efficiency of memory management. In addition, the scheme of the embodiment of the present application does not introduce additional processes that have a negative impact on memory access (such as page fault exceptions), which can avoid the negative impact of memory management on business performance and further improve the efficiency of memory management.

[0123] In addition, this application Figure 2 The system shown, and Figure 3 In order to implement the functions of the memory management method in the above-mentioned embodiment of the present application, the device shown includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0124] This embodiment also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the memory management method in the above-mentioned embodiment.

[0125] This embodiment also provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the memory management method in the above-mentioned embodiment.

[0126] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0127] Any content of each embodiment of the present application, as well as any content of the same embodiment, can be freely combined. Any combination of the above content is within the scope of the present application.

[0128] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0129] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A memory management method, It is characterized in that The method comprises: Obtain address information of one or more memory spaces accessed during a sampling period; Based on the acquired one or more address information, count the first access times of one or more memory pages to obtain heat data of each memory page; wherein each memory page is used to indicate the memory space corresponding to the memory page; Memory management is performed based on the heat data of each memory page.

2. The method according to claim 1, It is characterized in that The acquiring of address information of one or more memory spaces accessed within a sampling period includes: Determine a second access count of the target access in the accesses to the one or more memory spaces; When the second access number satisfies a sampling threshold, address information of one or more memory spaces accessed by the target access within a sampling period is obtained.

3. The method according to claim 2, It is characterized in that The acquiring, when the second access number satisfies the sampling threshold, address information of one or more memory spaces accessed by the target access within a sampling period includes: When the second access number satisfies a sampling threshold, acquiring address information of one or more memory spaces most recently accessed through the target access; The second access count is reset, and the step of determining the second access count of the target access in the accesses to the one or more memory spaces is performed until the sampling period ends.

4. The method according to claim 2 or 3, It is characterized in that The target access includes at least one of the following: a load operation, a store operation, an access resulting from a memory access cache miss, and an access resulting from an address translation lookup miss.

5. The method according to any one of claims 1 to 4, It is characterized in that The method of counting the first access times of one or more memory pages based on the acquired one or more address information to obtain the heat data of each memory page includes: According to the format requirements of the custom data packet in the extended SPE through statistical analysis, the acquired one or more address information are respectively constructed into SPE address packets to obtain an SPE address packet sequence; Writing the SPE address packet sequence to the SPE buffer; Based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page.

6. The method according to claim 5, It is characterized in that The method of counting the first access times of one or more memory pages based on the SPE address packet sequence in the SPE cache to obtain the heat data of each memory page includes: In the case that the SPE cache overflows, the first access times of one or more memory pages are counted based on the SPE address packet sequence in the SPE cache to obtain the heat data of each memory page.

7. The method according to any one of claims 1 to 6, It is characterized in that The address information includes: an address in a translation lookaside buffer (TLB), and / or an address for remote access.

8. A memory management device, It is characterized in that The device comprises: An address sampling module, used to obtain address information of one or more memory spaces accessed within a sampling period; A heat determination module, used to count the first access times of one or more memory pages based on the acquired one or more address information, and obtain heat data of each memory page; wherein each memory page is used to indicate a memory space corresponding to the memory page; The memory management module is used to perform memory management based on the heat data of each memory page.

9. The device according to claim 8, It is characterized in that The address sampling module is specifically used for: Determine a second access count of the target access in the accesses to the one or more memory spaces; When the second access number satisfies a sampling threshold, address information of one or more memory spaces accessed by the target access within a sampling period is obtained.

10. The device according to claim 9, It is characterized in that The address sampling module is specifically used for: When the second access number satisfies a sampling threshold, acquiring address information of one or more memory spaces most recently accessed through the target access; The second access count is reset, and the step of determining the second access count of the target access in the accesses to the one or more memory spaces is performed until the sampling period ends.

11. The device according to claim 9 or 10, It is characterized in that The target access includes at least one of the following: a load operation, a store operation, an access resulting from a memory access cache miss, and an access resulting from an address translation lookup miss.

12. The device according to any one of claims 8 to 11, It is characterized in that The heat determination module is specifically used for: According to the format requirements of the custom data packet in the extended SPE through statistical analysis, the acquired one or more address information are respectively constructed into SPE address packets to obtain an SPE address packet sequence; Writing the SPE address packet sequence to the SPE buffer; Based on the SPE address packet sequence in the SPE cache, the first access times of one or more memory pages are counted to obtain the heat data of each memory page.

13. The device according to claim 12, It is characterized in that The heat determination module is specifically used for: In the case that the SPE cache overflows, the first access times of one or more memory pages are counted based on the SPE address packet sequence in the SPE cache to obtain the heat data of each memory page.

14. The device according to any one of claims 8 to 13, It is characterized in that The address information includes: an address in a translation lookaside buffer (TLB), and / or an address for remote access.

15. An electronic device, It is characterized in that include: Processor and memory; The processor is connected to the memory; The memory is used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

16. A computer-readable storage medium, It is characterized in that It comprises a computer program, characterized in that when the computer program is run on an electronic device, the electronic device executes the method as claimed in any one of claims 1 to 7.

17. A chip, It is characterized in that It comprises one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory of an electronic device and send the signal to the processor, the signal comprising a computer instruction stored in the memory; when the processor executes the computer instruction, the electronic device executes the method described in any one of claims 1 to 7.

18. A computer program product, It is characterized in that The invention comprises a computer program, which, when executed by an electronic device, enables the electronic device to execute the method according to any one of claims 1 to 7.

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