A memory and its control method

Abstract

The present invention provides a memory and its control method, including a storage medium, the storage medium includes: a plurality of data areas, where host data is stored in the data areas; and at least one auxiliary decoding area, where preset data is stored full in the auxiliary decoding area, and the preset data is written synchronously with the host data; a data filling module, connected to the auxiliary decoding area and performing generation and writing of the preset data; a voltage switching module, the voltage switching module includes multiple levels of adjustable output voltages and is used to trigger a voltage-repeated reading operation of the host data when the reading of the host data fails; an error analysis module, connected to the auxiliary decoding area and the voltage switching module, and obtaining the number of error bits of the preset data and the number of error bits of the storage page under each reading voltage; a decoding control module, connected to the voltage switching module and the error analysis module, when the host data still cannot be read after traversing the reading voltages, using the reading voltage corresponding to the minimum number of error bits of the storage page as the intermediate voltage of the soft decoding process.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory and a control method thereof. Background Art

[0002] With the advancement of flash memory technology, storage solutions using flash memory as a storage medium have gradually surpassed mechanical hard drives to become the mainstream storage product. Flash memory represents data by the amount of charge in the storage cells. However, with factors such as increased usage, temperature fluctuations, and frequent reads, the charge in the storage cells can change, leading to errors in the stored data. Therefore, the use of error correction technology in flash memory devices is inevitable.

[0003] When error correction fails and triggers a data reread, the system typically needs to perform multiple read operations to attempt to recover the data. This process not only continuously consumes the storage system's bandwidth and computing resources, but also creates a conflict between error correction accuracy and processing efficiency. Prioritizing error correction efficiency can lead to insufficient error correction capabilities, potentially marking otherwise repairable storage units as bad blocks, resulting in wasted storage resources. Pursuing higher error correction accuracy significantly increases resource overhead, slowing decoding speeds and potentially impacting the overall performance of the storage system due to resource contention. This lack of balance makes it difficult for the error correction process to simultaneously meet the requirements of high reliability and high efficiency. Summary of the Invention

[0004] The object of the present invention is to provide a memory and a control method thereof, which can improve both data readout capability and data readout efficiency and maximize the utilization of storage resources.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory, comprising:

[0007] A storage medium, wherein a plurality of storage pages are provided in the storage medium, and the storage pages include:

[0008] a plurality of data areas, wherein host data is stored in the data areas; and

[0009] at least one auxiliary decoding area, wherein the auxiliary decoding area is filled with preset data, and the preset data is written synchronously with the host data;

[0010] a data filling module, connected to the auxiliary decoding area, and executing generation and writing of the preset data;

[0011] A voltage switching module, the voltage switching module including a multi-level adjustable output voltage and used to trigger a voltage-switching rereading operation of the host data when the host data reading fails;

[0012] An error analysis module, connected to the auxiliary decoding area and the voltage switching module, and obtaining the number of error bits of the preset data and the number of error bits of the storage page at each read voltage; and

[0013] A decoding control module, connected to the voltage switching module and the error analysis module, when the host data is still not read out after traversing the read voltages, uses the read voltage corresponding to the minimum number of error bits of the storage page as the intermediate voltage of the soft decoding process.

[0014] In an embodiment of the present invention, the storage page further includes a plurality of check areas, check codes are stored in the check areas, and the check codes and the host data are written and read synchronously, wherein the check codes are redundant data generated by LDPC encoding the host data.

[0015] In an embodiment of the present invention, the storage page is divided into at least one decoded unit, the decoded unit is the smallest storage unit for obtaining the intermediate voltage, wherein the decoded unit includes the data area, the check area and the auxiliary decoding area, and the number of the data area, the check area and the auxiliary decoding area is equal, and in the storage page, a plurality of the auxiliary decoding areas are evenly and discontinuously distributed in the storage page.

[0016] In an embodiment of the present invention, the check area is adjacent to the associated data area, wherein the storage page is the smallest storage unit for obtaining the intermediate voltage, and the auxiliary decoding area is a continuous storage area in the decoded unit.

[0017] In an embodiment of the present invention, a check bit capacity table is stored in the memory, a plurality of standard capacity data are stored in the check bit capacity table, the memory further includes an initialization module, the initialization module is triggered when the memory is powered on for the first time, and the initialization module selects one of the standard capacity data as the capacity of the check area in the storage page according to the capacity of the storage page and the capacity of the data area, and makes the capacity of the auxiliary decoding area in the storage page greater than zero.

[0018] In an embodiment of the present invention, at least one preset data format for generating the preset data is stored in the data filling module, and the data filling module includes:

[0019] A data generation unit, generating at least one group of data according to the preset data format and using it as the preset data; and

[0020] A data writing unit, connected to the auxiliary decoding area, and performing continuous writing of the preset data until the auxiliary decoding area is filled.

[0021] In an embodiment of the present invention, the error analysis module includes a first calculation unit, which is connected to the auxiliary decoding area, the voltage switching module and the data area, and the first calculation unit is triggered to output when reading out the host data, wherein the first calculation unit outputs the number of first error bits of the preset data compared with the original data, wherein the original data is a backup data of the data generated by the data generation unit, and the original data is stored in a storage area with a fixed and known address in the data area.

[0022] In an embodiment of the present invention, the error analysis module includes a second calculation unit, which is connected to the first calculation unit and outputs the number of second error bits of the storage page according to the number of the auxiliary decoding areas in the storage page and the number of first error bits.

[0023] In an embodiment of the present invention, the memory further includes an error correction module, which is started in the hard decoding process and the soft decoding process, wherein the error correction module is started when there is risk data in the soft decoding process, and the risk data is soft data adjacent to the decision threshold in the soft decoding process.

[0024] The present invention provides a control method for a memory. Based on a memory as described above, the method includes the following steps:

[0025] While writing host data to the data area, generate preset data and write the preset data to the auxiliary decoding area;

[0026] When the reading of the host data fails, switch the reading voltage of the host data and reread the host data;

[0027] While reading out the host data, read out the preset data, obtain the number of error bits of the preset data, and at the same time, according to the number of error bits of the preset data, obtain the number of error bits of the storage page; and

[0028] When traversing the reading voltages and still not reading out the host data, use the reading voltage corresponding to the minimum number of error bits of the storage page as the intermediate voltage of the soft decoding process.

[0029] As described above, the present invention provides a memory and its control method, which effectively solves the reliability challenges faced by high-density flash memories through an innovative storage architecture and an intelligent error correction mechanism. Through the collaborative optimization of the three-zone division structure of the storage page and the dynamic voltage regulation technology, as well as the hierarchical error correction strategy, the present invention achieves a balance between error correction accuracy and system efficiency, providing key technical support for the new generation of high-density storage devices. The memory and its control method provided by the present invention not only have high verification efficiency, but also the optimized design of the decoding unit improves the error localization accuracy, thereby reducing the average number of voltage retry times by 40% and the false positive rate of bad blocks by 60%. Through the hardware-accelerated parallel processing architecture, the error correction delay is controlled within 50 μs and the read / write bandwidth utilization rate is increased by 35% in the typical working scenario of QLC flash memories. Even in the case of decoding failure, the present invention can estimate the number of error bits, thereby accurately judging the wear degree of the current storage page, which is beneficial to subsequent product optimization and problem tracing.

[0030] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a schematic diagram of a distribution structure of an auxiliary decoding area in an embodiment of the present invention.

[0033] Figure 2 It is a schematic diagram of another distribution structure of an auxiliary decoding area in an embodiment of the present invention.

[0034] Figure 3 It is a schematic diagram of the structure of a controller in an embodiment of the present invention.

[0035] Figure 4 It is a schematic diagram of the structure of a data filling module in an embodiment of the present invention.

[0036] Figure 5 It is a schematic diagram of the structure of an error analysis module in an embodiment of the present invention.

[0037] Figure 6 It is a schematic diagram of the structure of a decoding control module in an embodiment of the present invention.

[0038] Figure 7 [[ID=D36]]It is a schematic diagram of the structure of a soft decoding unit in an embodiment of the present invention.

[0039] Figure 8 This is a schematic structural diagram of a scrambling control module in an embodiment of the present invention.

[0040] Figure 9 This is a flowchart of a control method for a memory in an embodiment of the present invention.

[0041] In the figure: D1, host data; 100, storage medium; 110, storage block; 120, storage page; 121, data area; 122, check area; 123, auxiliary decoding area; E, decoded unit; 200, controller; 210, initialization module; 220, timing control module; 230, data filling module; 231, data generation unit; 232, data writing unit; 240, voltage switching module; 250, error analysis module; 251, first calculation unit; 252, second calculation unit; 260, decoding control module; 261, hard decoding unit; 262, soft decoding unit; 2621, left bias module; 2622, right bias module; 2623, rereading module; 2624, logic processing module; 270, error correction module; 280, scrambling control module; 281, scrambling unit; 282, descrambling unit. Specific embodiments

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0043] The storage medium 100 of the memory provided by the present invention is a flash memory. Specifically, the memory provided by the present invention may be a NAND flash memory, or an eMMC storage chip, a UFS storage chip, etc. Please refer to Figure 1 and Figure 3As shown, the host data is user data or system data of the memory, where the user data can be the data that the host wants to write into the memory. In a storage device with a flash memory as the storage medium 100, the host data has a write process and a read process. In the write process, the host data is first scrambled, and the data sequence is disrupted in a regular manner. The scrambled host data is encoded with parity bits added. In this embodiment, the encoding method can be LDPC code. The host data is the information bits of the LDPC code, and parity bits are added to the host data after encoding the host data. The host data and the parity bits are written into the storage medium 100 together. In the process of reading the host data, the host data read from the storage medium 100 is first decoded, the parity bits are parsed, and it is judged whether the read host data is incorrect. If it is incorrect, for example, a bit flip occurs, the parity bits are used to correct the read host data. After the host data is successfully corrected, it is then de-scrambled by performing an inverse scrambling process on the read host data. After de-scrambling, the host data is successfully read out.

[0044] For the memory provided by the present invention, please refer to Figure 1 and Figure 2 As shown, the memory includes a storage medium 100. The storage medium 100 is a NAND flash memory. And the storage medium 100 includes a plurality of storage blocks 110. The storage block 110 includes a plurality of storage pages 120. The storage page 120 includes a plurality of data areas 121, a plurality of parity areas 122, and at least one auxiliary decoding area 123. The data area 121 is used to store host data. The parity area 122 is used to store the parity code of the host data. Preset data is stored in the auxiliary decoding area 123, and the preset data is written synchronously with the host data. The parity code is redundant data generated by encoding the host data through LDPC, and specifically is the parity bits of LDPC encoding. Among them, the parity code and the host data are written and read synchronously. The data format of the preset data is pre-designed by designers. For example, the preset data is 0×A5. In the present invention, the parity area 122 and the associated data area 121 are adjacent to each other in the storage page 120. The association between the parity area 122 and the data area 121 means that the parity code in the parity area 122 is generated by encoding the host data in the data area 121. In the present invention, the auxiliary encoding area is distributed in the storage page 120 in a preset manner. In the present invention, a plurality of decoded units E are provided in the memory, and the decoded unit E is the smallest storage unit for obtaining an intermediate voltage. That is, for different decoded units E, an intermediate voltage is obtained again. The decoded unit E includes at least one data area 121, at least one parity area 122, and at least one auxiliary decoding area 123.

[0045] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, there are multiple auxiliary coding regions, and the auxiliary coding regions are evenly and discontinuously distributed in the storage page 120. In this embodiment, in the decoding unit E, the number of data regions 121, check regions 122, and auxiliary decoding regions 123 is equal. As Figure 1 shown, for example, the decoding unit E includes 1 data region 121, 1 check region 122, and 1 auxiliary decoding region 123. In another embodiment of the present invention, the decoding unit E includes one auxiliary coding region, multiple data regions 121, and multiple check regions 122, and the auxiliary decoding region 123 is a continuous storage area in the decoding unit E. For example, as Figure 2 shown, the decoding unit E is a storage page 120. The decoding unit E includes 4 data regions 121, 4 check regions 122, and 1 auxiliary decoding region 123.

[0046] Please refer to Figure 1 and Figure 2 shown, in an embodiment of the present invention, the capacity of the data region 121 is a fixed capacity, and the capacity of the data region 121 can be determined during the manufacturing process of the memory. For example, the capacity of the data region 121 is 4KB. In this embodiment, a data region 121 with a fixed and known address is set to store the check bit capacity table. Multiple standard capacity data are stored in the check bit capacity table. For example, capacity data such as 296byte, 362byte, 390byte, 448byte, 462byte, 484byte, 530byte, etc. are stored in the check bit capacity table. In this embodiment, the capacity of the check region 122 is any capacity data stored in the check bit capacity table. Specifically, when the memory is powered on and used for the first time, the memory can be initialized, and a capacity data is selected from the check bit capacity table as the capacity of the check region 122. It should be noted that in the present invention, the capacity of each data region 121 is equal, while the capacity of each check region 122 is set after the first power-on, and it is not limited that the capacity of each check region 122 is equal. In this embodiment, based on the ability to form an auxiliary decoding region 123 with a non-zero storage capacity in the decoding unit E, the capacity of the check region 122 is set. In the present invention, the capacity of the storage page 120 is formed during the product manufacturing process and is a fixed parameter of the memory. For example, as Figure 1 shown, the capacity of the storage page 120 is 18976byte. And 4 check regions 122 and 4 data regions 121 are set in the storage page 120. The capacity of the data region 121 is 4KB, then the check region 122 can select a capacity of 530byte. Therefore, the total capacity of the data region 121 and the check region 122 in the storage page 120 is 18504byte. And the remaining space in the storage page 120 is 18976byte minus 18504byte, specifically 472byte. For Figure 1For the layout structure of the auxiliary decoding area 123 shown, the storage capacity of each auxiliary decoding area 123 is 118 bytes. For Figure 2 For the layout structure of the auxiliary decoding area 123 shown, the storage capacity of the auxiliary decoding area 123 is 472 bytes. In this embodiment, each storage page 120 is provided with at least one auxiliary decoding area 123, and the capacity of the auxiliary decoding area 123 is greater than zero.

[0047] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, the memory further includes a controller 200, and the controller 200 is electrically connected to the storage medium 100. The controller 200 includes an initialization module 210, a timing control module 220, a data filling module 230, a voltage switching module 240, an error analysis module 250, a decoding control module 260, an error correction module 270, and a scrambling control module 280. The initialization module 210 is used to set the capacity of the check area 122 in the decoded unit E, and is used to obtain the capacity of the auxiliary decoding area 123 in the decoded unit E. The timing control module 220 is used to generate the working clock signals of each module and each unit in the controller 200, and adjust the working timing of each operation in the controller 200. The data filling module 230 is used to write preset data into the auxiliary decoding area 123 in the decoded unit E while writing host data. The voltage switching module 240 is used to control the read voltage for rereading host data. The error analysis module 250 is used to obtain the number of error bits of the preset data, the decoded unit E, and even the storage page 120 during error correction decoding. The decoding control module 260 is used to perform a hard decoding process and a soft decoding process during the host data reading process. The error correction module 270 is used to further correct and analyze low-reliability soft data in the soft decoding process. The scrambling control module 280 is used to perform and control the scrambling process and the descrambling process of the host data.

[0048] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, the initialization module 210 is triggered when the memory is powered on for the first time. The initialization module 210 selects a standard capacity data from the parity bit capacity table as the capacity of the parity check area 122 in the storage page 120 according to the capacity of the storage page 120 and the capacity of the data area 121, and makes the capacity of the auxiliary decoding area 123 in the storage page 120 greater than zero. In the step of obtaining the storage capacity of the parity check area 122, the capacity of the parity check area 122 can be set in units of the decoded unit E, or can be set in units of the storage page 120. For setting the capacity of the parity check area 122 in units of the decoded unit E, for example, 2 decoded units E are set in the storage page 120, and the capacity of the storage page 120 is 18000 bytes, then the total capacity of one decoded unit E is 9000 bytes. Among them, in the same decoded unit E, the capacities of multiple parity check areas 122 are equal. It should be noted that the capacities of multiple decoded units E in the storage page 120 are equal. Among them, the capacity of the parity check area 122 satisfies that the capacity of the auxiliary decoding area 123 in the decoded unit E is greater than zero. For setting the capacity of the parity check area 122 in units of the storage page 120, the capacities of multiple parity check areas 122 are equal, and the capacity of the parity check area 122 satisfies that the capacity of the auxiliary decoding area 123 in the decoded unit E is greater than zero. It should be noted that if the capacity of the auxiliary decoding area 123 is a non-integer, the calculation result can be rounded to make the capacity of any auxiliary decoding area 123 an integer.

[0049] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, the timing control module 220 outputs timing signals for data filling, reading host data, switching the voltage to reread host data, hard decoding process, soft decoding process, scrambling process, etc. Specifically, during the process of writing host data, first, a scrambling process is performed on the host data. Then, the scrambled host data is encoded to generate a check code. Next, preset data is generated. Then, the host data is written into the data area 121, the check code is written into the check area 122, and the preset data is written into the auxiliary decoding area 123. During the process of reading out host data, first, the host data and the check code are read out, and it is determined whether the host data conforms to the information recorded by the check code. If it conforms to the information of the check code, the host data is successfully read out; if it does not conform to the information of the check code, the reading of the host data fails. Then, error correction is performed on the read host data. If the number of error bits of the host data exceeds the error correction capability of the error correction module 270, the hard decoding process is started. In the hard decoding process, the reading voltage of the host data is switched, and the host data is reread until all reading voltages are traversed or the host data is read out. Among them, while switching the reading voltage and rereading the host data, the preset data is read out, and the number of error bits of the preset data is obtained. Then, the number of error bits of the storage page 120 is obtained according to the number of error bits of the preset data. When the host data is not read out even after all reading voltages are traversed, the soft decoding process is started. In the soft decoding process, error correction is performed on unreliable soft data according to the reliability of the soft data in the soft decoding process. When the error correction of the soft data is successful, the host data is successfully read out; when the error correction of the soft data fails, the decoding fails, and the current storage page 120 is a bad page. In this embodiment, the timing control module 220 provides timing signals for each process of reading and writing host data and control components.

[0050] Please refer to Figures 1 to 4As shown, in an embodiment of the present invention, the data filling module 230 is connected to the auxiliary decoding area 123 and performs the generation and writing of preset data. In this embodiment, at least one preset data format for generating preset data is stored in the data filling module 230. The data sequence in the preset data format is determined. Specifically, the preset data format can be a data sequence with determined content, such as the preset data format being 0x5A. The preset data format can also be a format requirement for determining the data sorting method, such as the preset data format satisfying that 0 and 1 are distributed at intervals, 00 and 11 are distributed at intervals, and so on. In this embodiment, the data filling module 230 includes a data generation unit 231 and a data writing unit 232. The data generation unit 231 generates at least one set of data according to the preset data format and uses it as the preset data. The data writing unit 232 is connected to the auxiliary decoding area 123 and performs continuous writing of the preset data until the auxiliary decoding area 123 is filled. It should be noted that in this embodiment, the preset data refers to all the data that fills the auxiliary decoding area 123. The preset data can be composed of a set of data that conforms to the preset data format, or can be composed of multiple sets of data that conform to the preset data format. Subsequently, obtaining the number of error bits of the preset data refers to obtaining the number of error bits of the data stored in the auxiliary decoding area 123. In this embodiment, after the preset data is generated, while filling the preset data into the auxiliary decoding area 123, the preset data is also filled into the backup area as the original data for backing up the preset data. The address of the backup area is fixed and known.

[0051] Please refer to Figures 1 to 3 , Figure 6As shown, in an embodiment of the present invention, when the controller 200 receives a read instruction from the host, it reads the host data from the corresponding address. When the number of error bits of the host data exceeds the error correction capability of the error correction module 270, a hard decoding process is enabled. In this embodiment, the decoding control module 260 includes a hard decoding unit 261 and a soft decoding unit 262. Among them, the hard decoding unit 261 is connected to the voltage switching module 240 and rereads the host data according to the read voltage output by the voltage switching module 240. The voltage switching module 240 is enabled when an uncorrectable error occurs. Specifically, it is determined that a read voltage table is stored in the data area 121 of the address, and multiple read voltage data are stored in the read voltage table. In this embodiment, the error correction method of the error correction module 270 can be error correction according to the LDPC code. The voltage switching module 240 selects a read voltage from the reread voltage table as the new read voltage of the host data and rereads the host data. If the reading is successful, the hard decoding process of the host data ends. If the reading fails, the read voltage is continued to be changed and the rereading process of the host data is repeated. Among them, each time the host data is read, the number of error bits of the current storage page 120 or the current decoding unit E is obtained and recorded. Specifically, the number of error bits of the current storage page 120 or the current decoding unit E is obtained respectively when the data is read for the first time and each time the read voltage is changed subsequently. In this embodiment, the reading of the host data and the acquisition of the number of error bits can be coordinated by establishing a task queue and timing coordination. The coordination and activation of each task can also be realized by sending signals after the tasks are completed.

[0052] Please refer to Figures 1 to 3 As shown, it should be noted that when the host data is read for the first time, the read voltage of the data can be the default voltage in the read voltage table or the most suitable read voltage calculated by the system itself when the memory is in the offline state. The factors affecting whether the read voltage is the most suitable read voltage include temperature and the wear degree of the storage medium 100. Specifically, the voltage for reading the host data for the first time can be obtained by machine training when the memory is in the offline state, or a voltage parameter comparison table can be generated through verification tests before leaving the factory to obtain the read voltage to be used under each temperature range and wear degree of the storage medium 100. According to the temperature and the wear degree of the storage medium 100, the most suitable read voltage for reading the host data for the first time is determined.

[0053] Please refer to Figures 1 to 3 、 Figure 5As shown, in an embodiment of the present invention, the error analysis module 250 includes a first calculation unit 251 and a second calculation unit 252. The first calculation unit 251 is connected to the auxiliary decoding area 123, the voltage switching module 240, and the data area 121, and the first calculation unit 251 is triggered to output when reading out host data. Specifically, the first calculation unit 251 outputs the first number of error bits of the preset data compared to the original data, where the original data is the backup data generated by the data generation unit 231, and the original data is stored in a storage area with a fixed and known address in the data area 121. The second calculation unit 252 is connected to the first calculation unit 251 and outputs the second number of error bits of the storage page 120 according to the number of auxiliary decoding areas 123 in the storage page 120 and the first number of error bits. Regarding the distribution uniformity of the auxiliary decoding areas 123 in the storage page 120, as Figure 1 and Figure 2 shown, for example, 4 decoded units E are set in the storage page 120, then the second number of error bits is the sum of the number of error bits of the multiple decoded units E. And according to the first number of error bits and the space occupancy ratio of the auxiliary decoding area 123 in the decoded unit E, the number of error bits of the decoded unit E can be obtained. In some embodiments of the present invention, multiple auxiliary decoding areas 123 can also be set in the decoded unit E. When calculating the number of error bits of the decoded unit E, it is calculated based on the sum of the first number of error bits of the multiple auxiliary decoding areas 123 and the space occupancy ratio of the multiple auxiliary decoding areas 123 in the decoded unit E.

[0054] Please refer to Figures 1 to 3 、 Figure 5 shown. It should be noted that in the hard decoding process, when the host data of the decoded unit E is read out, the error analysis module 250 obtains the number of error bits of the decoded unit E. Specifically, while the preset data is filled into the auxiliary decoding area 123, the original data is read out, the preset data and the original data are compared, and the number of error bits of the preset data is obtained. Then, according to the number of error bits of the preset data, the number of error bits of the storage page 120 is obtained. In this embodiment, as Figure 1 shown, the storage units in the decoded unit E have the same storage medium 100 and the same storage environment. Therefore, the situation of the decoded unit E is simulated according to the situation of the auxiliary decoding area 123. Specifically, for example, if the number of error bits of the auxiliary decoding area 123 is 10, then for the storage page 120 structure as Figure 1 shown, according to the byte ratio of the auxiliary decoding area 123 in the decoded unit E, the number of error bits of the decoded unit E is obtained. For example, if the auxiliary decoding area 123 occupies one-tenth of the storage area of the decoded unit E, then the number of error bits of the decoded unit E is 100. And as Figure 1As shown, for example, 4 decoded units E are set in a storage page 120. The number of error bits of each decoded unit E is obtained respectively, and finally the number of error bits of the storage page 120 is the sum of the number of error bits of all the decoded units E. In another embodiment of the present invention, as Figure 2 shown in the structure of the storage page 120, a storage page 120 is a decoded unit E. For example, the number of error bits in the auxiliary decoding area 123 is 50. And the auxiliary decoding area 123 accounts for, for example, one-fifth in the decoded unit E. Then the number of error bits of the decoded unit E is 250. For the first embodiment, the number of error bits of the storage page 120 can be simulated with higher accuracy. For the second embodiment, the number of error bits of the storage page 120 can be simulated with less resource occupancy. After traversing all the read voltages, the number of error bits of the storage page 120 is calculated at each read voltage, and the read voltage corresponding to the minimum number of error bits is the intermediate voltage of the soft decoding process.

[0055] Please refer to Figures 1 to 3 、 Figure 6 and Figure 7As shown, in an embodiment of the present invention, the soft decoding unit 262 is connected to the error analysis module 250 and performs the soft decoding process of the memory based on the intermediate voltage. The soft decoding unit 262 includes a left bias module 2621, a right bias module 2622, a rereading module 2623, and a logic processing module 2624. In this embodiment, the left bias module 2621 outputs at least one left bias according to the intermediate voltage, where the left bias is less than the intermediate voltage. The right bias module 2622 outputs at least one right bias according to the intermediate voltage, where the right bias is greater than the intermediate voltage. For example, if the intermediate voltage is 3V, the left bias module 2621 can output voltages from 0 to 3V, and the right bias module 2622 can output voltages greater than 3V. The bias amount of the bias module is fixed, and the bias amounts of the left bias module 2621 and the right bias module 2622 are equal. Specifically, the left bias and the right bias can be symmetrically set. For example, when the intermediate voltage is 3V, the left biases are 2.7V and 2.4V, and the right biases are 3.3V and 3.6V. The bias amount is fixed at, for example, 0.3V to avoid introducing additional delays due to dynamic adjustment. The rereading module 2623 is connected to the left bias module 2621 and the right bias module 2622, and rereads the host data under the left bias and the right bias respectively, and outputs the left-biased data under the left bias and the right-biased data under the right bias. The logic processing module 2624 is connected to the rereading module 2623 and performs an exclusive OR operation on the left-biased data and the right-biased data to obtain the soft data of the soft decoding process. If the soft data is 1, it means that the bit voltage is sensitive and the data needs to be key error corrected. If the soft data is 0, it means that the bit is stable and the data has high credibility. Specifically, if the reread data is read as "1" under the intermediate voltage but read as "0" under the left bias, it indicates that the charge amount of the corresponding storage unit is close to the critical value and the reliability is low. For data with low reliability, the data can be further error corrected through LDPC decoding. If the first soft decoding fails, the bias range can be extended or the bias amount can be adjusted to cover a wider voltage drift range. In an embodiment of the present invention, when the minimum number of error bits is greater than the decoding ability of the soft decoding unit 262, the soft decoding process can be directly skipped, a decoding failure is reported, and the corresponding storage page 120 is scrapped.

[0056] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, in the hard decoding process and the soft decoding process, the error correction module 270 is activated. The error correction module 270 is configured to implement the data decoding function through the low-density parity-check (LDPC) algorithm. In the soft decoding process, the decision threshold is, for example, 1. When the soft data is 1 or a value close to 1, it means that the soft data is at risk and is risk data. At this time, the error correction module 270 can perform targeted error correction on the risk data. In the soft decoding process, if any risk data error correction fails, a decoding failure is reported to the host and the current host data cannot be read out.

[0057] Please refer to Figures 1 to 3 andFigure 8 As shown, in an embodiment of the present invention, the scrambling control module 280 includes a scrambling unit 281 and a descrambling unit 282. The scrambling unit 281 performs a scrambling process on the data sequence of the host data before the host data is written into the storage medium 100, and specifically, before generating the parity bits for the host data. The descrambling unit 282 performs a descrambling process that is the reverse of the scrambling process on the read data after the host data is successfully read from the storage medium 100, so that the host can read the accurate host data.

[0058] Please refer to Figures 1 to 3 and Figure 9 As shown, the present invention provides a control method for a memory, and the control method includes steps S100 to S400.

[0059] S100. While writing host data into the data area 121, generate preset data and write the preset data into the auxiliary decoding area 123.

[0060] S200. When the reading of the host data fails, switch the reading voltage of the host data and reread the host data.

[0061] S300. While reading the host data, read the preset data, obtain the number of error bits of the preset data, and at the same time, according to the number of error bits of the preset data, obtain the number of error bits of the storage page 120.

[0062] S400. When traversing the reading voltage and the host data has still not been read, use the reading voltage corresponding to the minimum number of error bits of the storage page 120 as the intermediate voltage for the soft decoding process.

[0063] Please refer to Figures 1 to 3 and Figure 9As shown, in an embodiment of the present invention, in step S100, preset data is generated according to a preset data structure. While writing the preset data into the auxiliary decoding area 123, the preset data is also written into the backup area. The auxiliary decoding area 123 is filled with the preset data. In step S200, the host data is read out for the first time according to the default voltage or the voltage of offline training. If the reading of the host data fails, the reading voltage is switched from the reading voltage meter, and the host data is reread at the switched reading voltage. In step S300, while reading out the host data, the error analysis module 250 obtains the number of error bits of the currently decoded unit E, and then obtains the number of error bits of the current storage page 120. In an embodiment of the present invention, in step S400, after the hard decoding process fails, the soft decoding process is started with the reading voltage corresponding to the minimum number of error bits as the intermediate voltage. When the soft decoding process fails, the memory reports decoding failure. In another embodiment of the present invention, in step S400, when the hard decoding process fails, the minimum second number of error bits is obtained. When the minimum second number of error bits exceeds the decoding ability of the soft decoding process, the decoding is ended, and the memory directly reports decoding failure.

[0064] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that, Comprising: A storage medium, in which a plurality of storage pages are provided, and the storage pages include: A plurality of data areas, in which host data is stored; A plurality of check areas, in which check codes are stored, and the check codes are written and read out synchronously with the host data, wherein the check codes are redundant data generated by LDPC encoding the host data; and At least one auxiliary decoding area, which is filled with preset data, and the preset data is written synchronously with the host data; A data filling module, connected to the auxiliary decoding area, and performing generation and writing of the preset data; A voltage switching module, the voltage switching module includes a multi-stage adjustable output voltage, and is used to trigger a voltage-repeated reading operation of the host data when the reading of the host data fails; An error analysis module, connected to the auxiliary decoding area and the voltage switching module, and obtaining the number of error bits of the preset data and the number of error bits of the storage page at each read voltage; and A decoding control module, connected to the voltage switching module and the error analysis module, when the host data is still not read out after traversing the read voltages, uses the read voltage corresponding to the minimum number of error bits of the storage page as the intermediate voltage of the soft decoding process, wherein at least one decoded unit is provided in the memory, the decoded unit is the smallest storage unit for obtaining the intermediate voltage, and the decoded unit includes the data area, the check area and the auxiliary decoding area; Wherein, the capacity of the check area is set when the memory is powered on for the first time, and the capacity of the check area is set based on the condition that the capacity of the auxiliary decoding area in the decoded unit is greater than zero.

2. The memory according to claim 1, characterized in that The storage page is divided into at least one decoded unit, the decoded unit is the smallest storage unit for obtaining the intermediate voltage, and the decoded unit includes the data area, the check area and the auxiliary decoding area, and the number of the data area, the check area and the auxiliary decoding area is equal, wherein in the storage page, a plurality of the auxiliary decoding areas are evenly and discontinuously distributed in the storage page.

3. The memory according to claim 2, wherein The check area is adjacent to the associated data area, wherein the storage page is the smallest storage unit for obtaining the intermediate voltage, and the auxiliary decoding area is a continuous storage area in the decoded unit.

4. A memory according to claim 1, wherein, The memory stores a check bit capacity table, in which a plurality of standard capacity data are stored, the memory further includes an initialization module, the initialization module is triggered when the memory is powered on for the first time, and the initialization module selects one of the standard capacity data as the capacity of the check area in the storage page according to the capacity of the storage page and the capacity of the data area, and makes the capacity of the auxiliary decoding area in the storage page greater than zero.

5. A memory according to claim 1, wherein At least one preset data format for generating the preset data is stored in the data filling module, and the data filling module includes: A data generation unit, generating at least one group of data according to the preset data format and using it as the preset data; A data writing unit, connected to the auxiliary decoding area, and performing continuous writing of the preset data until the auxiliary decoding area is filled.

6. A memory according to claim 5, characterized in that, The error analysis module includes a first calculation unit, the first calculation unit is connected to the auxiliary decoding area, the voltage switching module and the data area, and the first calculation unit is triggered to output when reading the host data, wherein the first calculation unit outputs the first error bit number of the preset data compared with the original data, wherein the original data is a backup data of the data generated by the data generation unit, and the original data is stored in a storage area with a fixed and known address in the data area.

7. A memory according to claim 6, characterized in that, The error analysis module includes a second calculation unit, the second calculation unit is connected to the first calculation unit, and outputs the second error bit number of the storage page according to the number of the auxiliary decoding areas in the storage page and the first error bit number.

8. A memory according to claim 1, characterized in that, The memory further includes an error correction module, which is started in the hard decoding process and the soft decoding process, wherein the error correction module is started when there is risk data in the soft decoding process, and the risk data is soft data adjacent to the decision threshold in the soft decoding process.

9. A control method for a memory, based on a memory as described in claim 1, characterized in that Including the following steps: While writing host data to the data area, generating preset data and writing the preset data into the auxiliary decoding area; When the reading of the host data fails, switching the reading voltage of the host data and rereading the host data; While reading the host data, reading the preset data and obtaining the error bit number of the preset data, and at the same time, obtaining the error bit number of the storage page according to the error bit number of the preset data; And When traversing the reading voltage and the host data has not been read yet, using the reading voltage corresponding to the minimum storage page error bit number as the intermediate voltage of the soft decoding process.

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