Instruction processing device, system and processing method based on RISC-V architecture

Abstract

The present application provides an instruction processing device, system, and processing method based on the RISC-V architecture. The device includes: a processor core and an instruction co-processing module. The processor core includes: a decoding module, a distribution module, and an operation module connected in sequence; the decoding module includes an extended instruction interface encoding unit; the decoding module is used to integrate the extended interface signal output by the extended instruction interface encoding unit into an integration result and send it to the distribution module; the extended interface signal is a pre-configured extensible interface signal; the distribution module is used to distribute instructions to the operation module based on the integration result; the instruction control unit in the operation module is used to receive the instruction distributed by the distribution module, perform vector processing operations to generate operation results, and send the operation results to the instruction co-processing module; the instruction co-processing module is used to interact with the instruction control unit to perform corresponding processing operations. This solution meets the ever-changing business needs and makes the device more flexible.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular, to an instruction processing device, system, and processing method based on the RISC-V architecture. Background Art

[0002] With the rapid development of modern computing systems, RISC-V, as an open-source instruction architecture, is modular and extensible, allowing developers to add different extended instruction sets based on their needs. The "V" extension is the officially defined vector extension instruction set within the RISC-V architecture, providing the RISC-V processor with the fundamental capabilities for vector operations. This extended instruction set covers a range of basic vector operation instructions, such as vector loads, stores, arithmetic operations, and logical operations, and can be used in standard server and application processor platform profiles. Other platforms, including embedded platforms, can also choose to implement subsets of these extensions to meet different application requirements.

[0003] At present, the official standard "V" extended instructions in related technologies cannot meet the needs of some special application scenarios, or the efficiency of using basic instructions in some scenarios is low, which affects the computing performance of the processor. Summary of the Invention

[0004] The embodiments of the present application provide an instruction processing device, system, and processing method based on the RISC-V architecture.

[0005] In a first aspect of an embodiment of the present application, an instruction processing device based on a RISC-V architecture is provided, the instruction processing device comprising: a processor core and an instruction co-processing module, the processor core comprising: a decoding module, a distribution module, and an operation module connected in sequence;

[0006] The decoding module includes an extended instruction interface encoding unit; the decoding module is used to integrate the extended interface signal output by the extended instruction interface encoding unit to obtain an integration result and send it to the distribution module; the extended interface signal is a pre-configured expandable interface signal;

[0007] The distribution module is used to: distribute instructions to the operation module according to the integration result;

[0008] The operation module includes an instruction control unit, which is used to: receive instructions distributed by the distribution module, control the operation module to perform vector processing operations to generate operation results and send the operation results to the instruction co-processing module;

[0009] The instruction co-processing module is used to interact with the instruction control unit and perform corresponding processing operations according to the calculation results.

[0010] A second aspect of the embodiments of the present application provides an instruction processing system, including the instruction processing device provided in the above embodiments.

[0011] A third aspect of the embodiments of the present application provides an instruction processing method based on the RISC-V architecture, the method comprising:

[0012] The extended interface signal output by the extended instruction interface encoding unit is integrated to obtain an integrated result; the extended interface signal is a pre-configured expandable interface signal; the integrated result includes an instruction;

[0013] Distributing instructions to the operation module according to the integration result;

[0014] Execute vector processing operations according to the distributed instructions to generate operation results;

[0015] Execute corresponding processing operations according to the calculation results.

[0016] In an embodiment of the present application, an instruction processing device, system, and processing method based on the RISC-V architecture are provided. The device includes: a processor core and an instruction co-processing module. The processor core includes: a decoding module, a distribution module, and an operation module connected at one time. The decoding module includes an extended instruction interface encoding unit, which is used to integrate the extended interface signal output by the extended instruction interface encoding unit to obtain an integration result and send it to the distribution module; the extended interface signal is a pre-configured extensible interface signal; the distribution module is used to distribute the instruction to the operation module based on the integration result; the operation module includes an instruction control unit, which is used to receive the instruction distributed by the distribution module, control the operation module to perform vector processing operations to generate operation results, and send the operation results to the instruction co-processing module; the instruction co-processing module is used to interact with the instruction control unit and perform corresponding processing operations based on the operation results. Compared with the existing technology, the technical solution in this application sets up an extended instruction interface encoding unit in the decoding module, so that users can flexibly design instructions with different needs according to different scenarios, meet the ever-changing business needs, and make the device more flexible. In addition, through the orderly collaboration between the decoding module, the distribution module and the operation module, the delay of instruction processing is reduced, and the effective execution of vector processing operations is guaranteed. Through the interaction between the instruction co-processing module and the instruction control unit, the system can flexibly process different instructions. This interaction mechanism can dynamically adjust the processing strategy according to the specific instruction type and business needs, thereby accelerating the computing performance of the processing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram of the structure of a computer device provided in one embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of an instruction processing device provided in one embodiment of the present application;

[0020] Figure 3 A flowchart of an instruction processing method provided in one embodiment of the present application;

[0021] Figure 4 A schematic structural diagram of an instruction processing device provided in another embodiment of the present application.

[0022] Description of reference numerals:

[0023] Processor core-10; decoding module-11; distribution module-12; operation module-13; instruction co-processing module-20; extended instruction interface encoding unit-111; instruction control unit-131. DETAILED DESCRIPTION

[0024] In the process of implementing this application, the inventors found that the traditional standard "V" extended instructions cannot meet the needs of some special application scenarios, or the efficiency of using basic instructions in some scenarios is low, thereby affecting the computing performance of the processor.

[0025] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0026] Based on the above-mentioned defects, the present application provides an instruction processing device based on the RISC-V architecture. Compared with the related technologies, the technical solution in the present application sets an extended instruction interface encoding unit in the decoding module, so that users can flexibly design instructions with different needs according to different scenarios, meet the ever-changing business needs, and make the device more flexible. In addition, through the orderly collaboration between the decoding module, the distribution module and the operation module, the delay of instruction processing is reduced, and the effective execution of vector processing operations is guaranteed. Through the interaction between the instruction co-processing module and the instruction control unit, the system can flexibly process different instructions. This interaction mechanism can dynamically adjust the processing strategy according to the specific instruction type and business needs, thereby accelerating the computing performance of the processing device.

[0027] See Figure 1 , a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 1 As shown, the computer device includes a processor, memory, a network interface, a display screen, and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium may be, for example, a magnetic disk. The non-volatile storage medium stores files (which may be files to be processed or processed files), an operating system, and computer programs. The internal memory provides an operating environment for the operating system and computer programs stored in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When executed by the processor, the computer program implements an instruction processing method. The display screen of the computer device may be a liquid crystal display or an electronic ink display screen. The input device of the computer device may be a touch layer covering the display screen, or may be buttons, a trackball, or a touchpad provided on the computer device housing, or may be an external keyboard, touchpad, or mouse.

[0028] See Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of the instruction processing device based on the RISC-V architecture provided in the embodiment of this application. Figure 2 As shown, the instruction processing device includes: a processor core 10 and an instruction co-processing module 20, and the processor core 10 includes: a decoding module 11, a distribution module 12 and a calculation module 13 connected in sequence.

[0029] The decoding module 11 includes an extended instruction interface encoding unit 111; the decoding module 11 is used to integrate the extended interface signal output by the extended instruction interface encoding unit to obtain an integration result and send it to the distribution module; the extended interface signal is a pre-configured expandable interface signal; the distribution module 12 is used to: distribute instructions to the operation module according to the integration result; the operation module 13 includes an instruction control unit 131, and the instruction control unit 131 is used to: receive instructions distributed by the distribution module, control the operation module to perform vector processing operations to generate operation results and send the operation results to the instruction co-processing module 20; the instruction co-processing module 20 is used to: interact with the instruction control unit and perform corresponding processing operations according to the operation results.

[0030] It's important to note that the processor core (CORE) represents the core of the processor and is a key component of the entire processing system, responsible for coordinating and controlling the execution of instructions. The decoder module (CORE_DECODE) is a module within the processor core responsible for decoding input instructions and identifying their type and operation.

[0031] The decoding module may include an extended instruction interface encoding unit (VNICE_DECODE). The extended instruction interface encoding unit is a custom decoding unit. Users can use this unit to perform custom instruction encoding. For example, custom encoding can be performed according to different application scenarios or different requirements. It is a key part for implementing flexible custom extended instructions.

[0032] The dispatch module receives the integrated results of the extended interface signals from the decoding module in the processor core. These integrated results contain processed instruction information and serve as the basis for subsequent operations. Based on the received integrated results, the dispatch module analyzes and determines the instructions and accurately dispatches them to the computation modules. It acts as an instruction dispatcher, ensuring that each instruction is correctly routed to the appropriate computation module for processing, thus ensuring the orderly execution of the instruction processing flow.

[0033] By accurately distributing instructions, the dispatch module establishes a communication bridge between the decoding module and the calculation module, coordinating the work between the two modules, improving the efficiency and coordination of the entire instruction processing device, and avoiding confusion and errors during instruction processing. The dispatch module is the key link connecting the decoding module and the calculation module in the instruction processing device, playing a vital role in ensuring that instructions are processed and executed correctly and efficiently.

[0034] The aforementioned arithmetic module can be a vector processing unit (VPU), which is primarily used to process vector arithmetic instructions and improve data parallel processing capabilities. This arithmetic module provides computing power for the entire device and performs corresponding arithmetic operations in response to arithmetic instructions. These operations can include various types of addition, subtraction, multiplication, division, etc.

[0035] The instruction control unit (VNICE_CTRL) is located inside the operation module and is a control module related to custom extensions. It is used to control the operation module to perform corresponding operations based on the instruction encoding information passed by the extended instruction interface encoding unit VNICE_DECODE.

[0036] The instruction co-processing module (VNICE_CORE) is the core part of the custom extended instruction processing. It interacts with the instruction control unit VNICE_CTRL and participates in the specific implementation of the instruction function.

[0037] The operation request signal is used to instruct the execution of an operation, and the operation request signal may include operation data and operation mode.

[0038] Specifically, users can customize instruction encoding according to different application scenarios, obtain a variety of extended interface signals, and pre-configure them in the extended instruction interface encoding unit. The decoding module will integrate the output extended interface signals to obtain an integrated result, which includes processed instruction information, and send the integrated result to the distribution module. After receiving the integration module, the distribution module analyzes and judges the instructions and accurately distributes the instructions to the operation module. The operation module includes an instruction control unit, which then controls the computing resources in the operation module through the instruction control unit to perform vector processing operations on the instructions, thereby obtaining operation results. The operation module can send the operation results to the instruction co-processing module outside the processor core. The instruction co-processing module interacts with the instruction control unit in the operation module and performs corresponding processing operations.

[0039] The above calculation results may be expressed in the form of text, a table, or an image. This embodiment does not impose any limitation on the form of expression of the calculation results.

[0040] In an embodiment of the present application, an instruction processing device based on a RISC-V architecture is provided, the device comprising: a processor core and an instruction co-processing module, the processor core comprising: a decoding module, a distribution module, and an operation module connected at one time. The decoding module comprises an extended instruction interface encoding unit, the decoding module being configured to integrate an extended interface signal outputted by the extended instruction interface encoding unit to obtain an integration result and send the integration result to the distribution module; the extended interface signal being a pre-configured, extensible interface signal; the distribution module being configured to distribute instructions to the operation module based on the integration result; the operation module comprising an instruction control unit, the instruction control unit being configured to receive instructions distributed by the distribution module, control the operation module to perform vector processing operations to generate operation results, and send the operation results to the instruction co-processing module; the instruction co-processing module being configured to interact with the instruction control unit and perform corresponding processing operations based on the operation results. Compared with the existing technology, the technical solution in this application sets up an extended instruction interface encoding unit in the decoding module, so that users can flexibly design instructions with different needs according to different scenarios, meet the ever-changing business needs, and make the device more flexible. In addition, through the orderly collaboration between the decoding module, the distribution module and the operation module, the delay of instruction processing is reduced, and the effective execution of vector processing operations is guaranteed. Through the interaction between the instruction co-processing module and the instruction control unit, the system can flexibly process different instructions. This interaction mechanism can dynamically adjust the processing strategy according to the specific instruction type and business needs, thereby accelerating the computing performance of the processing device.

[0041] In an optional embodiment of the present application, the extended instruction interface encoding unit is used to:

[0042] Receive the vnice instruction code input from the external module;

[0043] According to the pre-configured instruction encoding rules, the vnice instruction code is analyzed for characteristics and the extended interface signal is output.

[0044] It is understood that in an instruction processing device based on the RISC-V architecture, the vnice instruction code is a set of instructions used to implement specific functions. External modules may include, for example, a program memory, an instruction generator, etc. The external module sends the compiled vnice instruction code to the extended instruction interface encoding unit in the decoding module. These vnice instruction codes are generally in binary encoding form, representing different operations and functions. These vnice instruction codes can be customized by users based on different actual application scenarios and different needs, and are used to implement vector operations, etc. Users can use customized instruction codes to manipulate these control signal combinations to implement various instruction functions.

[0045] The above instruction encoding rules can be predefined instruction encoding specifications, which can include the format of the instruction code, the meaning of each field, and the corresponding operation. Through these rules, the system can parse the instruction code and understand its specific function, thereby outputting the extended interface signal.

[0046] Optionally, the vnice instruction code may consist of fields such as an opcode, operand address, and function code. The opcode specifies the basic type of instruction, such as addition or multiplication; the operand address indicates the location of the data involved in the operation; and the function code further details the instruction operation, such as whether to use a mask and which rounding mode to use.

[0047] During the process of outputting extended interface signals, the various fields of the vnice instruction code may be parsed to determine the characteristic information of the vnice instruction, and then the extended interface signals are output based on the characteristic information of the vnice instruction. These extended interface signals can interact with the distribution module and operation module in the device, thereby providing the necessary control information for the execution of subsequent instructions.

[0048] These characteristics include, but are not limited to, operation type, operand information, and special functions. Operation types include arithmetic, logical, data transfer, and other types. Operand information can include determining the number, type (integer, floating-point, etc.), and source (register, memory, etc.) of operands involved in the operation. Special functions can include identifying whether the instruction has special functions, such as whether to use masks or whether to perform saturation operations.

[0049] The extended instruction interface encoding unit in the embodiment of the present application can receive customized vnice instruction codes, enabling developers to create corresponding exclusive instructions based on specific needs, breaking the limitations of traditional instruction sets, greatly improving the flexibility of the instruction system, and can output extended interface signals to provide detailed instruction information for subsequent modules, making it easier for the distribution module to accurately distribute instructions to the corresponding operation modules, reducing the delay in instruction processing, and greatly improving the efficiency of instruction processing.

[0050] In an optional embodiment of the present application, the extended interface signal includes:

[0051] At least one first operand interface signal, at least one second operand interface signal, at least one result register interface signal and at least one other interface signal; the first operand interface signal is used to represent the enable control, source indication and mutual exclusion constraint of the first operand of the vnice instruction; the second operand interface signal is used to represent the enable control and source limitation of the second operand of the vnice instruction; the result register interface signal is used to represent the enable control, update type indication, mutual exclusion constraint and read operation indication of the result register of the vnice instruction; the other interface signals are used to indicate the legality judgment, instruction type identification and mask use identification of the vnice instruction.

[0052] It should be noted that the aforementioned extended interface signals may include input signals and output signals. Input signals refer to signals transmitted from an external module to the extended command interface encoding unit, while output signals refer to signals output by the extended command interface encoding unit (VNICE_DECODE unit). See Table 1 below, which shows the contents of the extended interface signals (VNICE_DECODE interface signals):

[0053] Table 1

[0054]

[0055] The signal names in the table above are the names of the VNICE_DECODE interface signals, which are the identifiers of each extended interface signal. The direction indicates the direction of signal transmission. "Input" means that the external signal is input to the VNICE_DECODE unit, such as "dec_vnice_instr" receiving the instruction code; "Output" means that the module outputs the signal to the outside, such as various "dec_vnice_ " signal, used to convey the result of instruction-related characteristic judgment. "Bit width" refers to the number of binary bits occupied by the signal. For example, "dec_vnice_instr" has a bit width of 32, which can represent multiple instruction codes. Most output signals have a bit width of 1 and are used to indicate "yes" or "no" judgment results. "Description" is used to characterize the functional meaning of each signal. For example, it can determine the vnice instruction's requirements for operands (op1, op2), the source of the operands, the operation on the result register (rd), the legality of the instruction, whether it is a vnice instruction, and whether v0 is used as a mask.

[0056] The first operand interface signals are those related to operand op1 and include dec_vnice_op1_en, dec_vnice_op1_scalar_reg_fpu, dec_vnice_op1_scalar_reg_int, and dec_vnice_op1_vector_reg. The second operand interface signals are those related to operand op2 and include dec_vnice_op2_en. The result register interface signals include dec_vnice_rd_en, dec_vnice_rd_scalar_reg_fpu, dec_vnice_rd_scalar_reg_int, dec_vnice_rd_vector_reg, and dec_vnice_rd_mac. Other interface signals include dec_vnice_ilgl, dec_vnice_op, and dec_vnice_vm.

[0057] It should be noted that among the first operand interface signals, dec_vnice_op1_en, with a bit width of 1, is used to indicate whether the vnice instruction requires operand op1. dec_vnice_op1_scalar_reg_fpu is used to indicate whether operand op1 of the vnice instruction originates from a scalar register of the floating-point unit (FPU). dec_vnice_op1_scalar_reg_int is used to indicate whether op1 originates from an integer register (rs1). dec_vnice_op1_vector_reg is used to indicate whether op1 originates from a vector register of the virtual processing unit (VPU).

[0058] The three signals mentioned above must be mutually exclusive, meaning that operand op1 can only have one source at a time. For example, when the dec_vnice_op1_scalar_reg_fpu signal is 1 (indicating that op1 comes from the FPU scalar register), the dec_vnice_op1_scalar_reg_int and dec_vnice_op1_vector_reg signals must be 0. Multiple signals cannot be 1 at the same time to avoid confusion about the source of op1's data.

[0059] For the second operand interface signal, dec_vnice_op2_en, its bit width is 1, which is used to indicate whether the vnice instruction requires operand op2, and the source of operand op2 is only one type, which is a vector register. This is different from the multiple possible sources of operand op1, and is relatively clearer and more single.

[0060] For the result register (RD) interface signals, dec_vnice_rd_en (bit width 1) indicates whether the VNICE instruction updates the RD (result register). dec_vnice_rd_scalar_reg_fpu (bit width 1) indicates whether the RD updated by the VNICE instruction is an FPU register. dec_vnice_rd_scalar_reg_int (bit width 1) indicates whether the updated RD is a scalar register. dec_vnice_rd_vector_reg (bit width 1) indicates whether the updated RD is a vector register. Users must ensure that these three signals related to RD updates are mutually exclusive, meaning that RD can only update one type of register. dec_vnice_rd_mac (bit width 1) indicates whether the VNICE instruction reads RD.

[0061] Similar to the rules for operand op1, these three signals must also be mutually exclusive. Operand rd can only update one type of register after the instruction executes. For example, when dec_vnice_rd_scalar_reg_fpu is 1, the other two signals must be 0 to ensure uniqueness of the update target.

[0062] For other interface signals, dec_vnice_ilgl, bit width 1, indicates whether the vnice instruction is an illegal instruction. dec_vnice_op, bit width 1, indicates whether it is a vnice instruction. dec_vnice_vm, bit width 1, indicates whether the instruction uses v0 as a mask.

[0063] In the embodiment of the present application, by setting at least one first operand interface signal, at least one second operand interface signal, at least one result register interface signal and at least one other interface signal, it is possible to meet the special requirements of instruction processing in different application scenarios and improve the flexibility and accuracy of instruction processing. For example, in image processing applications, it may be necessary to use a mask to selectively process certain parts of an image. This function can be achieved by setting the corresponding mask control interface signal. It can also accurately inform the operation module of the specific operation that needs to be performed, ensuring that the instruction is executed accurately and without error. For example, when a vector addition operation is required, the corresponding addition operation interface signal will be activated. After the operation module receives the signal, it will perform the vector addition operation.

[0064] In an optional embodiment of the present application, the instruction co-processing module interacts with the instruction control unit via a co-processing interface signal;

[0065] The co-processing interface signal includes at least one of the following: a clock signal, a handshake interaction signal, a transmission flag signal, an instruction and configuration signal, an operand signal, an output result and flag signal; the clock signal is used to represent the clock reference for the instruction co-processing module to perform operations; the handshake interaction signal is used to represent the validity of the input data and the readiness status of the module to receive data, as well as the validity of the output data and the readiness status of the downstream module to receive data; the transmission flag signal is used to represent the flag information of the data transmission; the operand signal is used to represent the operand information; the operand information includes at least one item: a vector operand and a scalar operand; the output result and flag signal are used to represent the attribute information of the operation process and the operation result information.

[0066] It should be noted that the aforementioned extended interface signals may include input signals and output signals. Input signals refer to signals transmitted from an external module to the instruction co-processing module (VNICE_CORE module), while output signals refer to signals output by the instruction co-processing module. See Table 2 below, which shows the specific contents of the co-processing interface signals (VNICE_IF interface signals):

[0067] Table 2

[0068]

[0069] The above directions indicate the direction of signal transmission. "Input" refers to the external signal input to the VNICE_DECODE unit, such as "dec_vnice_instr" receiving the instruction code; "Output" refers to the signal output by the VNICE_CORE module to the outside. "Bit width" refers to the number of binary bits occupied by the signal, and "Description" is used to characterize the functional meaning of each co-processing interface signal (VNICE_IF interface signal).

[0070] The clock signal is vnice_clk, which is a 1-bit input signal. As a clock signal, it provides a timing reference for the operation of the entire VNICE-CORE module. All logic operations are synchronized based on this clock signal.

[0071] The handshake interaction signals include: i_vnice_valid, i_vnice_ready, vnice_wbck_valid, and o_vnice_wbck_ready. i_vnice_valid is a 1-bit input signal and serves as the valid signal for the VNICE input handshake. When high (logic 1), it indicates that the input data and instructions are valid and can be processed. i_vnice_ready is a 1-bit output signal and serves as the ready signal for the VNICE input handshake. When high, it indicates that the VNICE module is ready to receive input data and instructions. Input data and instructions can only be successfully transmitted and processed when both i_vnice_valid and i_vnice_ready are high. vnice_wbck_valid is a 1-bit output signal and serves as the valid signal for the VNICE output handshake. When high, it indicates that the operation result output by the instruction co-processing module is valid. o_vnice_wbck_ready is a 1-bit input signal that serves as the ready signal for the VNICE output handshake. When high, it indicates that the receiver is ready to receive the computation results from the instruction coprocessor. Similarly, the output results can only be successfully transmitted when both o_vnice_wbck_valid and o_vnice_wbck_ready are high.

[0072] Transfer flags include i_vnice_beat. i_vnice_beat is a 2-bit input signal that signals the start and end of a vnice. It indicates the transfer phase based on the VLMUL (vector length multiplier) value. When VLMUL > 1, there are multiple VLEN (vector length) transfers: 01 indicates the first VLMUL transfer; 00 indicates a middle VLMUL transfer; and 10 indicates the last VLMUL transfer. When VLMUL <= 1, it indicates a single VLEN transfer; 11 indicates a single VLMUL transfer.

[0073] Instructions and configuration signals include: i_vnice_instr, i_vnice_csr_vlmul, i_vnice_csr_vsew, i_vnice_csr_rounding_mode, and i_vnice_fpu_rounding_mode. i_vnice_instr is a 32-bit input signal and is the VNICE instruction code, containing the specific instruction to be executed. i_vnice_csr_vlmul is a 3-bit input signal and is the VNICE VLMULL control status register (CSR) signal. It indicates the currently configured VLMUL mode, which is used to determine the length multiplier for vector operations. i_vnice_csr_vsew is a 3-bit input signal and is the VNICE VSew control status register (CSR) signal. It indicates the currently configured element width, that is, the bit width of each element in the vector. i_vnice_csr_rounding_mode is a 2-bit input signal, which is the rounding control status register (CSR) signal of Vnice, indicating the rounding mode used by the current configuration, used for rounding operations of integer operations. i_vnice_fpu_rounding_mode is a 3-bit input signal, which is the floating-point rounding control status register (CSR) signal of Vnice, indicating the floating-point rounding type used by the current configuration, used for rounding operations of floating-point operations.

[0074] Operand signals include: i_vnice_vs1, i_vnice_vs2, i_vnice_rs1, and i_vnice_vd. i_vnice_vs1 is a VLEN-bit input signal and is the vs1 operand of vnice, serving as one input operand for vector operations. i_vnice_vs2 is a VLEN-bit input signal and is the vs2 operand of vnice, serving as the other input operand for vector operations. i_vnice_rs1 is a GLEN-bit input signal and is the rs1 operand of vnice, typically serving as a scalar operand. i_vnice_vd is a VLEN-bit input signal and is the vd operand of vnice, used to store the result of vector operations.

[0075] The output result and flag signals include: o_vnice_wbck_wdat, o_vnice_wbck_vxsat, o_vnice_wbck_fflag, and o_vnice_active. Among them, o_vnice_wbck_wdat is the VLEN bit output signal, which is the operation result signal output by vnice and contains the final result of the vector operation.

[0076] o_vnice_wbck_vxsat is a 1-bit output signal that indicates operation saturation. When high, it indicates that saturation has occurred during the operation, meaning that the result exceeds the representable range. o_vnice_wbck_fflag is a 5-bit output signal that indicates whether an exception such as overflow, underflow, or division by zero has occurred during a floating-point operation. o_vnice_active is a 1-bit output signal used to control the clock. When vnice is in operation, this flag must be raised to indicate that the module is performing an operation.

[0077] In the embodiment of the present application, by setting a clock signal, a unified time base can be provided for the entire system, so that each module can execute the corresponding operation in an orderly manner according to the clock signal, and by setting a handshake interaction signal, reliable data transmission can be ensured, and different modules can be used to process speed differences. By setting a transmission flag signal, data transmission website can be guaranteed, and complex transmission modes can be supported. Setting instructions and configuration signals can achieve instruction diversity and scalability, setting operand signals can provide operation data, support multiple operation types, and setting output results and flag signals can feedback the operation results to indicate the operation status, thereby meeting the special requirements of instruction processing in different application scenarios and improving the flexibility and accuracy of instruction processing.

[0078] In an optional embodiment of the present application, the above-mentioned operand signal includes: a data element status signal; the data element status signal is used to indicate whether the current data element in the vector operand is in an active state; the value of the data element status signal is determined according to different combinations of the vector length, the vector length multiplier and the data element width; the value includes a set of data element status values ​​for each current bit in the vector operand, and the data element status values ​​include 1 and 0.

[0079] When the data element state value is 1, a group of data elements representing the current position is in an active state; when the data element state value is 0, a group of data elements representing the current position is in an inactive state.

[0080] In this embodiment, the data element status signal is the i_vnice_element_active signal, which is used to indicate which data elements in the vector operand are active, that is, which elements will participate in the specific vector operation. The i_vnice_element_active signal is a signal related to sew (element width) and is used to indicate whether the current data element is active. Specifically, its value varies according to different combinations of vector length (VLEN, Vector Length), vector length multiplier (VLMUL), and element width (Vector Element Stride Width, VSEW).

[0081] VLEN represents the length of the vector. For example, VLEN = 128 means the vector contains 128 bits of data. VLMUL is the vector length multiplier. Here, VLMUL = 1 means the vector length is the standard VLEN value. VSEW refers to the vector element width, which determines the number of bits each element in the vector occupies.

[0082] In this embodiment, each bit of the i_vnice_element_active signal corresponds to a set of elements in the vector. When a bit is 1, it indicates that the corresponding data element is in an active state and will participate in subsequent operations; when a bit is 0, it indicates that the corresponding data element is in an inactive state and does not participate in the operation. The signal bit width is VLEN / 8 because the signal controls the active state of the element in bytes.

[0083] For example, when VSEW = 8, indicating that the width of each element is 8 bits, a 128-bit vector contains a total of 128 / 8 = 16 elements. i_vnice_element_active = 16'b1111111111111111 indicates that all 16 elements are active and participate in vector operations.

[0084] When VSEW = 16, each element is 16 bits wide, and a 128-bit vector contains 128 / 16 = 8 elements. Because i_vnice_element_active is controlled in bytes, a 16-bit wide element corresponds to a 2-bit i_vnice_element_active signal. i_vnice_element_active = 16'b0000000011111111 indicates that the four 16-bit elements corresponding to the last eight bytes are active, while the first four 16-bit elements are not involved in the operation.

[0085] When VSEW = 32, each element is 32 bits wide. A 128-bit vector contains 128 / 32 = 4 elements. Each 32-bit wide element corresponds to the 4-bit i_vnice_element_active signal. i_vnice_element_active = 16'b0000000000001111 indicates that the 32-bit element corresponding to the last 4 bytes is active, while the first 32-bit elements are not involved in the operation.

[0086] When VSEW=64, each element is 64 bits wide. A 128-bit vector contains 128 / 64 = 2 elements. Each 64-bit wide element corresponds to the 8-bit i_vnice_element_active signal. i_vnice_element_active = 16'b0000000000000011 indicates that the 64-bit element corresponding to the last two bytes is active, and the first 64-bit element does not participate in the calculation.

[0087] In the embodiment of the present application, by setting the i_vnice_element_active signal, the data elements participating in the operation in the vector can be flexibly controlled according to different element widths, thereby improving the efficiency and flexibility of vector operations.

[0088] In an optional embodiment of the present application, the instructions and configuration signals include a vector length multiplier configuration signal, a vector element width configuration signal, a first mode configuration signal, and a second mode configuration signal;

[0089] The vector length multiplier configuration signal is used to indicate the configuration of the vector length multiplier; the vector element width configuration signal is used to indicate the configuration of the data element width; the first mode configuration signal is used to indicate the configuration of the rounding mode of the conventional operation; the second mode configuration signal is used to indicate the configuration of the rounding mode of the floating-point operation.

[0090] It should be noted that the above-mentioned vector length multiplier configuration signal can be i_vnice_csr_vlmul, which is used to configure vector length multiplier (LMUL) related information and determine the proportional relationship between the effective length of the vector operand and the standard vector length, which has an important impact on the amount of vector data involved in the operation and the scale of the operation.

[0091] The signal encoding rules of i_vnice_csr_vlmul comply with the RISCV "V" extension standard, as shown in Table 3 below:

[0092] Table 3

[0093]

[0094] In the table above, vmul[2:0] is a 3-bit binary code used to select different vector operation configuration modes. Different codes correspond to different parameter settings. LMUL is used to represent the vector length multiplier, representing the ratio of the effective length of the vector operand to the standard vector length (VLEN), such as 1 / 8, 1 / 4, etc. #groups refers to the number of groups, indicating the number of vector register groups. VLMAX represents the maximum number of elements in each group. Its value is calculated based on the ratio of VLEN (vector length) to SEW (vector element width), and the calculation method and value vary in different configurations. Registers grouped with register n: Indicates the other registers grouped with register n. For example, reserved indicates reservation, and also indicates whether a single or multiple registers are grouped with n.

[0095] As another example, the vector element width configuration signal can be i_vnice_csr_vsew, which is used to configure the vector element width (VSEW). Its value affects the size of the vector elements, which in turn affects the number of elements in the vector and the control of active elements by the i_vnice_element_active signal. Both provide necessary configuration parameters for instruction execution, assisting the i_vnice_instr instruction code in determining the specific operation method and scale, and therefore belong to the instruction and configuration signal types.

[0096] The signal encoding rules of i_vnice_csr_vsew comply with the RISCV "V" extension standard, as shown in Table 4 below:

[0097] Table 4

[0098]

[0099] The above vsew[2:0] is a 3-bit binary code used to select the vector element width. Different code values ​​determine the specific width configuration. SEW represents the vector element width, measured in bits. When vsew[2:0] is 000, SEW is 8 bits; when it is 001, SEW is 16 bits; when it is 010, SEW is 32 bits; and when it is 011, SEW is 64 bits. When the highest bit of vsew[2:0] is 1 (i.e., 1XX), the code is reserved and does not correspond to a specific element width setting.

[0100] The first mode configuration signal can be i_vnice_csr_rounding_mode, and the second mode configuration signal can be i_vnice_fpu_rounding_mode. i_vnice_csr_rounding_mode configures the rounding mode for regular operations, determining how fractional parts are handled during calculations, such as rounding, ceiling, or floor. Different rounding modes affect the accuracy of the final calculation result. i_vnice_fpu_rounding_mode primarily configures the rounding mode for floating-point operations. In floating-point operations, when results need to be converted or truncated, they must be processed according to a specific rounding mode. This signal specifies this mode to ensure that the floating-point calculation results meet the required accuracy. These two signals, similar to i_vnice_csr_vlmul and i_vnice_csr_vsew, assist instruction execution by providing specific configuration parameters for the operation, and are therefore considered instructions and configuration signals.

[0101] The signal encoding rules of i_vnice_csr_rounding_mode comply with the RISCV "V" extension standard, as shown in Table 5 below:

[0102] Table 5

[0103]

[0104] It should be noted that Table 5 above is used to define the rounding modes and rounding increments corresponding to different encodings, as follows: vxrm[1:0] is a 2-bit binary code used to select different rounding modes. Abbreviation is the abbreviation of the rounding mode. For example, "rnu," ​​"rne," "rdn," and "rod." Rounding Mode is a detailed description of the rules for each rounding mode. Rounding Increment, r, is the calculation method for the rounding increment under each rounding mode. For example, in the "rnu" mode, the rounding increment is v[d-1]; the "rne" mode has different judgment conditions to determine the rounding increment. This table is mainly used in related operations to select the appropriate rounding mode and calculate the rounding increment based on the vxrm[1:0] code to ensure the precision and accuracy of the operation results.

[0105] The signal encoding rules of the above i_vnice_csr_rounding_mode comply with the RISCV "V" extension standard, as shown in Table 6 below:

[0106] Table 6

[0107]

[0108] This table contains information about rounding modes, including three columns: Rounding Mode, Mnemonic, and Meaning. Rounding modes use binary numbers to represent different rounding options, such as "000" and "001." Mnemonics are shorthand symbols assigned to each rounding mode, such as "RTZ" and "RDN," for easy memorization and reference. Meanings explain the operating rules of each rounding mode. For example, "RTZ" means round toward zero, "RDN" means round down (toward negative infinity), and "RMM" means round toward the nearest value, or toward the largest absolute value if the distances are equal. Invalid modes are also indicated, along with their reserved uses. This table provides a reference for selecting the appropriate rounding mode in calculations, helping to accurately process calculation results.

[0109] In the embodiment of the present application, by setting the vector length multiplier configuration signal, the vector element width configuration signal, the first mode configuration signal and the second mode configuration signal, the mode of vector operation can be flexibly configured to adapt to different computing requirements and facilitate the storage and processing of data in vector operations.

[0110] In an optional embodiment of the present application, the operand signal further includes: a first data transmission signal and a second data transmission signal.

[0111] The first data transmission signal is used to transmit the corresponding operand according to the current instruction type; the second data transmission signal is used to write back the original value of the data element in the inactive state in the mask scenario;

[0112] When the rdmac instruction is executed, the second data transmission signal is used to transmit data to the destination register.

[0113] It should be noted that the first data transmission signal may be i_vnice_rs1, an input signal that has both integer and floating-point transmission capabilities. Depending on the current instruction type, it transmits integer operands for integer instructions and floating-point operands for floating-point instructions, providing a data source for the operation.

[0114] The second data transfer signal, i_vnice_vd, is also an input signal used to write back the original values ​​of inactive data elements in masked scenarios. Data originates only from vector registers. When executing the rdmac instruction, this signal is independent of the vector length (vl), vector mask (vm), and v0, and always transfers the data to the destination register vd.

[0115] In the embodiment of the present application, by setting the first data transmission signal and the second data transmission signal, the system can selectively process vector elements according to mask rules when performing vector operations, thereby improving the flexibility and accuracy of vector operations, enhancing the versatility and applicability of the system, and meeting different types of computing needs.

[0116] In an optional embodiment of the present application, the output result and flag signal include: an operation saturation flag signal and a floating point exception flag signal;

[0117] The operation saturation flag signal is used to determine whether to write back the data element according to the data element status signal; the floating point exception flag signal is used to determine whether to write back the data element according to the data element status signal;

[0118] If the data element status signal indicates that the corresponding element does not need to be written back, the operation saturation flag signal and the floating-point exception flag signal will not be set. The operation saturation flag signal is updated and takes effect after each vector length multiplication operation is completed; the floating-point exception flag signal is updated and takes effect after the last vector length multiplication operation is executed.

[0119] It should be noted that the aforementioned operation saturation flag signal can be o_vnice_wbck_vxsat, an output signal representing the operation saturation flag. This flag is combined with the i_vnice_element_active signal to determine whether to write back the element. If i_vnice_element_active indicates that the corresponding element does not need to be written back, this flag will not be set. Furthermore, this flag is updated and takes effect after each VLMUL (vector length multiplier) operation, indicating whether saturation occurred during the operation.

[0120] The floating-point exception flag signal can be o_vnice_wbck_fflag, an output signal that represents the VNICE floating-point exception flag. Similar to o_vnice_wbck_vxsat, it also uses i_vnice_element_active to determine whether to write back the corresponding element. If the corresponding element does not need to be written back, this flag is not set. However, it takes effect only after the last VLMUL writeback, indicating whether an exception has occurred in a floating-point operation.

[0121] In the embodiment of the present application, an operation saturation flag signal is set to accurately reflect whether saturation occurs during the operation. In some numerical calculations, saturation occurs when the result of the operation exceeds the range that can be represented by the data type. Through this flag signal, the system can be informed of this situation in a timely manner, avoid the output of erroneous data due to result overflow, and provide accurate information for subsequent processing. In addition, a floating-point exception flag signal is set to feedback various abnormal conditions that occur in floating-point operations, such as division by zero, overflow, underflow, etc. These abnormal conditions may frequently occur in fields such as scientific computing and graphics processing. Capturing and feeding back these abnormalities in a timely manner will help the system to perform corresponding processing and ensure the accuracy and reliability of the operation results.

[0122] On the other hand, the present invention also provides an instruction processing method, see Figure 3 As shown, the instruction processing method includes the following steps 201 to 204:

[0123] Step 201: Integrate the extended interface signal output by the extended instruction interface encoding unit to obtain an integration result; the extended interface signal is a pre-configured expandable interface signal; the integration result includes instructions.

[0124] Step 202: Distribute the instructions to the operation module according to the integration result.

[0125] Step 203: Execute vector processing operations according to the distributed instructions to generate operation results.

[0126] Step 204: Execute corresponding processing operations according to the calculation results.

[0127] Please note that, see Figure 4 As shown in the figure, taking the decoding module as the CORE-DECODE module, the extended instruction interface encoding unit as the VNICE_DECODE unit, the operation module as the VPU, the distribution module as the DISP module, the instruction control unit as the VNICE-CORE unit, and the instruction co-processing module as the VNICE-CORE module as an example, the VNICE_DECODE unit in the CORE-DECODE module outputs pre-configured extendable interface signals. These signals contain various information related to the instruction, such as the instruction operation type, operand information, and control parameters for special functions. The CORE-DECODE module analyzes and processes these extended interface signals, integrating them into a complete and easy-to-understand integrated result. The core component of this integrated result is the instruction, which clearly describes the specific operation to be performed by the system and the various parameters and conditions required to execute it.

[0128] The DISP module receives the integrated results from the CORE-DECODE module and extracts instructions from them. Based on the instruction's specific content, such as the operation type and the target operation module, the DISP module accurately sends the instruction to the operation module. This step ensures that the instruction is correctly delivered to the module responsible for executing the operation, avoiding incorrect or chaotic instruction distribution.

[0129] After receiving instructions from the DISP module, the VPU performs the corresponding vector processing operations according to the instructions. This may include basic operations such as vector addition, subtraction, multiplication, and division, as well as specialized vector operations such as vector masking and vector reduction. During the execution of the operation, the operation module processes the input operands according to the parameters and conditions specified in the instruction, ultimately generating the result.

[0130] The VNICE-CORE module or other related modules receive the computation results generated by the computation module. Based on the specific results, the system performs appropriate processing operations. These operations may include storing the results in a specified memory location or register, performing conditional judgments based on the results to determine the subsequent execution flow, or triggering exception handling mechanisms (e.g., overflow or error in the computation results).

[0131] The above instruction processing flow achieves accurate processing and execution of extended instructions through collaboration between multiple modules, ensuring that the system can complete various vector processing tasks efficiently and reliably.

[0132] Compared with the prior art, the instruction processing method based on the RISC-V architecture in this embodiment has an extended instruction interface encoding unit set in the decoding module, so that users can flexibly design instructions with different needs according to different scenarios, meet the ever-changing business needs, and make the device more flexible. In addition, through the orderly collaboration between the decoding module, the distribution module and the operation module, the delay of instruction processing is reduced, and the effective execution of vector processing operations is guaranteed. In addition, through the interaction between the instruction co-processing module and the instruction control unit, the system can flexibly process different instructions. This interactive mechanism can dynamically adjust the processing strategy according to the specific instruction type and business needs, thereby accelerating the computing performance of the processing device.

[0133] On the other hand, an embodiment of the present application also provides an instruction processing system, which includes an instruction processing device based on the RISC-V architecture provided in the above embodiment.

[0134] Compared with the prior art, the processing system of the present application is equipped with an arbitration module, which can generate authorization signals and core identifiers to the corresponding target cores in order of priority, so that each processor core can access the resources of the operation processing unit in sequence to perform operation operations. There is no need to configure an independent operation unit for each core, thereby realizing computing resource sharing in multi-core mode, and then sending the operation results to the target core through the first multiplexer, which greatly reduces the hardware cost.

[0135] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0136] In one embodiment, a computer device is provided. The internal structure diagram of the computer device can be as follows: Figure 1 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, an instruction processing method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the instruction processing method as described above is implemented.

[0137] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above instruction processing method can be implemented.

[0138] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0139] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0140] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0142] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0143] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. An instruction processing device based on RISC-V architecture, characterized in that: The instruction processing device includes: a processor core and an instruction co-processing module, wherein the processor core includes: a decoding module, a distribution module and a calculation module connected in sequence; The decoding module includes an extended instruction interface encoding unit; the decoding module is used to integrate the extended interface signal output by the extended instruction interface encoding unit to obtain an integration result and send it to the distribution module; the extended interface signal is a pre-configured expandable interface signal; The distribution module is used to: distribute instructions to the operation module according to the integration result; The operation module includes an instruction control unit, which is used to: receive instructions distributed by the distribution module, control the operation module to perform vector processing operations to generate operation results and send the operation results to the instruction co-processing module; The instruction co-processing module is used to interact with the instruction control unit and perform corresponding processing operations according to the operation results; wherein the extended instruction interface encoding unit is used to: Receive the vnice instruction code input from the external module; According to the pre-configured instruction encoding rules, the vnice instruction code is analyzed for characteristics and the extended interface signal is output; the extended interface signal includes: at least one first operand interface signal, at least one second operand interface signal, at least one result register interface signal, and at least one other interface signal; The first operand interface signal is used to represent the enable control, source indication and mutual exclusion constraint of the first operand of the vnice instruction; The second operand interface signal is used to represent the enable control and source limitation of the second operand of the vnice instruction; The result register interface signal is used to represent the enable control, update type indication, mutual exclusion constraint and read operation indication of the result register of the vnice instruction; The other interface signals are used to indicate the legality judgment of the vnice instruction, the instruction type identifier and the mask use identifier.

2. The device according to claim 1, characterized in that The instruction co-processing module interacts with the instruction control unit via a co-processing interface signal; the co-processing interface signal further comprises at least one of the following: a clock signal, a handshake interaction signal, a transmission flag signal, an instruction and configuration signal, an operand signal, an output result and flag signal; The clock signal is used to represent the clock reference for the instruction co-processing module to perform operations; The handshake interaction signal is used to indicate the validity of input data and the readiness of the module to receive data, as well as the validity of output data and the readiness of the downstream module to receive data; The transmission flag signal is used to represent flag information of data transmission; the operand signal is used to represent operand information; the operand information includes at least one item: a vector operand and a scalar operand; The output result and the flag signal are used to represent the operation process attribute information and the operation result information.

3. The device according to claim 2, characterized in that The operand signals include: a data element status signal; the data element status signal is used to indicate whether a current data element in the vector operand is in an active state; the value of the data element status signal is determined according to different combinations of vector length, vector length multiplier and data element width; the value includes a set of data element status values ​​for each current bit in the vector operand, and the data element status value includes 1 and 0; When the data element state value is 1, a group of data elements representing the current position is in an active state; when the data element state value is 0, a group of data elements representing the current position is in an inactive state.

4. The device according to claim 2, characterized in that The instructions and configuration signals include a vector length multiplier configuration signal, a vector element width configuration signal, a first mode configuration signal, and a second mode configuration signal; The vector length multiplier configuration signal is used to indicate the configuration of the vector length multiplier; The vector element width configuration signal is used to indicate the configuration data element width; The first mode configuration signal is used to indicate the rounding mode of the conventional operation; The second mode configuration signal is used to indicate the configuration of a rounding mode of a floating-point operation.

5. The device according to claim 2, characterized in that The operand signal also includes: a first data transmission signal and a second data transmission signal; the first data transmission signal is used to transmit the corresponding operand according to the current instruction type; the second data transmission signal is used to write back the original value of the data element in the inactive state in the mask scenario; wherein, when executing the rdmac instruction, the second data transmission signal is used to transfer the data to the destination register.

6. The device according to claim 3, characterized in that The output result and flag signal include: an operation saturation flag signal and a floating point exception flag signal; The operation saturation flag signal is used to determine whether to write back the data element according to the data element status signal; the floating point exception flag signal is used to determine whether to write back the data element according to the data element status signal; Wherein, if the data element status signal indicates that the corresponding element does not need to be written back, the operation saturation flag signal and the floating-point exception flag signal will not be set; Each time a vector length multiplication operation is completed, the operation saturation flag signal is updated and becomes effective; When the last vector length multiplication operation is performed, the floating point exception flag signal is updated and becomes valid.

7. A processing system, characterized in that include: An instruction processing device as claimed in any one of claims 1 to 6.

8. A method for processing an instruction, characterized in that: Applied to the instruction processing device according to any one of claims 1 to 6, the method comprises: Integrating the extended interface signal output by the extended instruction interface encoding unit to obtain an integration result; the extended interface signal is a pre-configured expandable interface signal; the integration result includes an instruction; Distributing the instructions to the computing module in the instruction processing device based on the RISC-V architecture according to the integration result; Execute vector processing operations according to the distributed instructions to generate operation results; Execute corresponding processing operations according to the calculation results.

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