ATE test method for JESD204B interface ADC

Abstract

The invention discloses an ATE test method for a JESD204B interface ADC. The method comprises the steps of clock tree design, test data transmission and acquisition scheme design, test board and ATE interaction scheme design and ATE processing of acquired data. According to the invention, a clock tree design scheme of combining an onboard clock and an external clock is adopted, so that high flexibility is achieved; aDC sampling data is received through the FPGA on the test board and then is transmitted to the ATE, so that high-efficiency collection of test data is realized; meanwhile, an ATE sends a control signal and a clock signal to control FPGA transmission data, distinguishing of different ADC core sampling data is achieved, and a reference clock is provided for FPGA and ATE data transmission; and finally, processing and analyzing the data through ATE. Through the method provided by the invention, the collection of the test data of the JESD204B interface ADC can be efficiently completed, then the dynamic and static parameter test of the ADC is completed, the test efficiency is improved, the test time is shortened, and the ATE test requirement is met.

Description

Technical Field

[0001] The invention relates to an ATE test method for JESD204B interface ADC, belonging to the technical field of integrated circuit testing. Background Art

[0002] As electronic systems continue to increase their requirements for data acquisition speed and accuracy, especially in the fields of communications, medical imaging, industrial automation, etc., the demand for high-speed and high-precision ADCs continues to grow. At the same time, the development of semiconductor manufacturing technology has also continuously promoted the development of ADC performance towards high speed and high precision. As ADC performance improves, the demand for high-data-rate interfaces also increases, and the interface protocol is updated at a faster speed, from low-speed serial ports to parallel ports to high-speed serial ports, and the interface transmission rate continues to develop. The JESD204B protocol can achieve a single lane rate of 12.5Gbps and supports up to 8 lanes. It has the advantages of fast transmission rate and few pins, and is widely used in ADCs, DACs, and RF chips. However, the JESD204B protocol interface is more complex, and the number of parameters when the device is working is also increasing exponentially, which brings difficulties to ATE-based testing. Using ATE's high-speed board to directly decode and process JESD204B interface ADC data has problems of low efficiency and poor stability, which seriously affects test efficiency. Therefore, it is necessary to study new ATE test methods for JESD204B interface ADCs to improve test efficiency and stability. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide an ATE test method for JESD204B interface ADC, to use FPGA to receive ADC data, and to transmit it to ATE, thereby improving data acquisition efficiency and test stability.

[0004] The technical solution of the present invention is: an ATE test method for JESD204B interface ADC, comprising:

[0005] Arrange the test FPGA, ADC, crystal oscillator and clock chip on the test board: the crystal oscillator is connected to the clock chip to provide a clock source to the clock chip; the clock chip is connected to the test FPGA and ADC at the same time to provide clock signals to the test FPGA and ADC respectively; the JESD204B interface of the test FPGA is connected to the JESD204B interface of the ADC to test the data transmission between the FPGA and the ADC;

[0006] The test FPGA is connected to ATE at the same time for data transmission; the external signal source instrument is connected to the clock chip to provide a reference clock for the clock chip; the external signal source instrument is connected to the ADC to provide a reference clock for the ADC; the external signal source instrument is connected to ATE for ATE to control and read the status of the external signal source instrument;

[0007] The clock tree is designed by combining the onboard clock with the external clock to provide a reference clock for testing data transmission between the FPGA and the ADC.

[0008] After the ADC samples the data, the test FPGA receives the ADC sampled data according to the clock signal of the clock tree, and decodes and caches the sampled data;

[0009] ATE sends control signals and clock signals to the test FPGA to control the data transmission and transmission timing between FPGA and ATE; at the same time, FPGA sends the current operation status signal of FPGA to ATE;

[0010] ATE processes the acquired ADC sampling data, calculates dynamic parameters and static parameters, and completes the test.

[0011] Preferably, the ADC is connected to the ATE at the same time, so that the ATE can configure and read the status of the ADC;

[0012] The clock chip is also connected to ATE, so that ATE can configure and read the status of the clock chip.

[0013] Preferably, when designing a clock tree by combining an onboard clock with an external clock, there are two ways:

[0014] The crystal oscillator is used to provide a clock source for the clock chip, which generates the ADC sampling clock, the ADC JESD204B interface working clock, and the JESD204B interface working clock of the test FPGA.

[0015] The external signal source instrument provides a sampling clock for the ADC; at the same time, the external signal source instrument provides a clock source for the clock chip, and then the clock chip is the working clock for the JESD204B interface of the ADC chip and the JESD204B interface of the test FPGA.

[0016] Preferably, the JESD204B interface of the ADC encodes the obtained sampling data so that the high and low bits of adjacent sampling points of the ADC are distributed in different Lanes for transmission with the test FPGA; after the JESD204B interface of the FPGA receives the data, it completes decoding by reorganizing the data obtained from different Lanes to obtain correct data of continuous sampling points.

[0017] Preferably, when the data transmission rate between the ADC and the FPGA via the JESD204B interface does not match the data transmission rate between the FPGA and the ATE, the data is cached by the test FPGA and then sent to the ATE.

[0018] Preferably, the ATE sends a control signal and a clock signal to the test FPGA to control the data transmission and transmission timing between the FPGA and the ATE, specifically:

[0019] When the ADC chip contains multiple ADC cores, the ATE sends a control signal to the test FPGA to control the test FPGA to send sampling data of different ADC cores to the ATE;

[0020] ATE sends a clock signal to the test FPGA, providing a reference clock for data transmission between the test FPGA and ATE, ensuring that ATE correctly obtains the transmission data.

[0021] Preferably, the FPGA sends a current operating status signal of the FPGA to the ATE for fault location and program debugging.

[0022] Preferably, after ATE calculates the dynamic parameters and the static parameters, it determines whether the obtained parameters meet the requirements of the product test specification and gives a determination result.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] The present invention uses FPGA to obtain ADC sampling data and then transmits it to ATE. Compared with the traditional ATE method of directly obtaining ADC data through a high-speed board and performing decoding and processing, it has the following beneficial effects:

[0025] (1) The method of the present invention allows ATE to obtain ADC sampling data faster and more stably, thereby improving test efficiency and reducing component test time;

[0026] (2) The method of the present invention does not rely on ATE high-speed boards, which can significantly reduce costs;

[0027] (3) The method of the present invention can be transferred to the testing of different types of ADC and DAC products, and reduces the requirements for ATE, thus having wider applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the testing environment of the method of the present invention;

[0029] Figure 2 This is a schematic diagram of ADC sampling data acquired by FPGA in the present invention;

[0030] Figure 3This is a schematic diagram of FPGA transmission data acquired by ATE in the present invention. DETAILED DESCRIPTION

[0031] The technical problem solved by the present invention is that the conventional high-speed board card of ATE is directly used to decode and process the ADC data of the JESD204B interface, which has the problems of low efficiency and poor stability. The present invention designs an ATE test method for the ADC of the JESD204B interface, adopts FPGA to receive the ADC data, and transmits it to ATE, thereby improving the data acquisition efficiency and the test stability. Specifically, the method of the present invention includes: clock tree design, test data transmission and acquisition scheme design, test board and ATE interaction scheme design, ATE processing of the acquired data, etc. The present invention adopts a clock tree design scheme combining an onboard clock with an external clock, which has high flexibility; the ADC sampling data is received by the FPGA on the test board, and then transmitted to the ATE, so as to realize the efficient acquisition of the test data; at the same time, the control signal and the clock signal are sent by ATE to control the FPGA transmission data, so as to realize the distinction of the sampling data of different ADC cores, and provide a reference clock for the data transmission between FPGA and ATE. Through the method of the present invention, the acquisition of the ADC test data of the JESD204B interface can be completed efficiently, and then the dynamic parameters and static parameters of the ADC can be tested, the test efficiency can be improved, the test time can be reduced, and the ATE test requirements can be met.

[0032] The meanings of the English abbreviations involved in the present invention are as follows:

[0033] JESD204B: A high-speed serial interface;

[0034] ADC: Analog-to-Digital Converter;

[0035] DAC: Digital-to-Analog Converter;

[0036] ATE:Automatic Test Equipment,Automatic test equipment;

[0037] FPGA: Field-Programmable Gate Array, field programmable gate array;

[0038] Lane: physical channel for data transmission;

[0039] FIFO: First-In First-Out;

[0040] DDR: Double Data Rate SDRAM, double data rate SDRAM;

[0041] IP core: Intellectual Property Core, Chinese name "intellectual property core", refers to a pre-designed, reusable circuit function module.

[0042] The purpose of the present invention is achieved through the following technical solutions:

[0043] An ATE test method for JESD204B interface ADC, the steps of which include:

[0044] Step S0: Test environment layout:

[0045] Arrange the test FPGA, ADC, crystal oscillator and clock chip on the test board: the crystal oscillator is connected to the clock chip to provide a clock source to the clock chip; the clock chip is connected to the test FPGA and ADC at the same time to provide clock signals to the test FPGA and ADC respectively; the JESD204B interface of the test FPGA is connected to the JESD204B interface of the ADC to test the data transmission between the FPGA and the ADC;

[0046] The test FPGA is connected to ATE at the same time for data transmission; the external signal source instrument is connected to the clock chip to provide a reference clock for the clock chip; the external signal source instrument is connected to the ADC to provide a reference clock for the ADC; the external signal source instrument is connected to ATE for ATE to control and read the status of the external signal source instrument.

[0047] Step S1: clock tree design, using a clock tree design scheme combining an onboard clock with an external clock.

[0048] Step S2: Test data transmission and acquisition scheme design, receive ADC sampling data through FPGA on the test board, decode and cache the data, and then transmit the decoded data to ATE to achieve efficient collection of test data.

[0049] Step S3: Design the interaction scheme between the test board and ATE. Send control signals to FPGA through ATE to distinguish the sampling data of different ADC cores and control the data transmission of FPGA. Send clock signals to FPGA through ATE to provide a reference clock for data transmission between FPGA and ATE. Send relevant status signals to ATE through FPGA to indicate the current operating status of FPGA.

[0050] Step S4: ATE processes the acquired ADC sampling data, calculates dynamic parameters and static parameters, and performs testing.

[0051] Furthermore, in step S1, the clock tree design refers to providing reference clocks for ADC sampling, ADC's JESD204B interface, and FPGA's JESD204B interface. In order to ensure the normal operation of the system, the above clocks must be from the same source.

[0052] Furthermore, in step S1, the clock tree design scheme combining the onboard clock and the external clock includes a crystal oscillator, a clock chip that meets the JESD204B interface clock requirements, a signal source, and peripheral resistors, capacitors and other components required for the normal operation of the system. The specific clock scheme is as follows:

[0053] Select a suitable clock chip that meets the JESD204B interface clock requirements. At the same time, the clock source of the clock chip must be either a crystal oscillator or an external signal source.

[0054] Solution 1: Onboard clock solution. The crystal oscillator provides the clock source for the clock chip, which then generates the ADC sampling clock, the ADC chip JESD204B interface working clock, and the FPGA chip JESD204B interface working clock.

[0055] Solution 2: The ADC sampling clock is provided by the signal source, and the reference clock of the signal source (usually 10MHz) provides the clock source for the clock chip. The clock chip then generates the ADC chip JESD204B interface working clock and the test FPGA chip JESD204B interface working clock for data transmission between the ADC and the test FPGA.

[0056] It should be pointed out that the above clock tree design only discusses the working clock of the JESD204B interface of the FPGA chip. The normal working clock of the FPGA chip is provided by other means, which does not belong to the scope of the present invention and is not discussed in detail in the present invention.

[0057] In step S2, the test data transmission and acquisition scheme design refers to sending the ADC sampling data to the FPGA chip through the JESD204B interface. The FPGA chip uses the JESD204B interface to receive relevant data and decode the data. Then, the FPGA's FIFO IP core or other storage forms are used to cache the received data and send it to ATE.

[0058] In step S2, the decoding of data means that the JESD204B interface will encode the ADC sampling data, and the high and low bits of adjacent ADC sampling points will be distributed in different lanes for transmission. After receiving the data, the FPGA needs to decode the data and reorganize the data obtained from different lanes to obtain the correct data of continuous sampling points.

[0059] In step S2, the caching means that when the data rate transmitted between the ADC and the FPGA via JESD204B does not match the data rate transmitted between the FPGA and the ATE, the data is first cached through the FIFO IP core of the FPGA or other storage forms, and then sent to the ATE.

[0060] In step S2, the cache method is not limited to the FIFO IP core of the FPGA, and can also include other storage types such as DDR for data storage. The storage rate must meet the data transmission rate between the ADC and the FPGA through JESD204B and the data transmission rate between the FPGA and the ATE.

[0061] In step S2, the amount of data stored in the FIFO or other storage forms in the cache needs to be determined according to the ADC type and ATE test requirements. If a single cache cannot meet the data volume requirements, it can be solved by multiple caches. However, the multiple cache data needs to meet the ATE test requirements for data.

[0062] In step S2, transmitting the decoded data to ATE means that the FPGA on the test board is connected to ATE through a data channel, and then the data is sent to ATE through the data channel.

[0063] In step S3, the test board and ATE interaction scheme design includes status indication signals and control signals between FPGA and ATE, and reference clock signals for data transmission between FPGA and ATE.

[0064] In step S3, the control signal is sent to the FPGA through ATE to distinguish the sampling data of different ADC cores and control the FPGA transmission data. It means that one ADC chip may contain multiple ADC cores. The control signal is sent to the FPGA through ATE to control the FPGA to send the sampling data of different ADC cores to ATE, thereby realizing the test of different ADC cores.

[0065] In step S3, sending a clock signal to the FPGA through ATE to provide a reference clock for data transmission between the FPGA and ATE means that the ATE sends a clock signal to the FPGA to provide a reference clock for data transmission between the FPGA and ATE to ensure that the ATE can correctly obtain the FPGA transmission data.

[0066] In step S3, the sending of relevant status signals to ATE via FPGA to indicate the current operating status of FPGA means that through the interconnection path between FPGA and ATE, FPGA can send its own status signal to ATE to indicate the current operating status of FPGA, which can be used for fault location, program debugging, etc.

[0067] In step S4, the ATE processes the acquired ADC sampling data, calculates dynamic parameters and static parameters, and performs tests, which means that the ATE uses the acquired ADC sampling data to calculate dynamic parameters and static parameters according to relevant product test specifications to implement tests on relevant parameters.

[0068] Example:

[0069] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0070] Figure 1 The figure is a schematic diagram of the overall framework of the method of the present invention. The method of the present invention is described in detail by taking the AD9208 test as an example. AD9208 has two ADC cores, the sampling rate is up to 3GSPS, and the sampling accuracy is 14bit. The selection of each major component is as follows: the clock chip is HMC7044, the FPGA is XCKU060, the ATE is UltraFlex, the signal source is required to meet the ADC sampling clock requirements, and the selection of other non-major components must meet the system operation requirements, which are not listed in detail here. Figure 1 The arrows in the figure represent signal transmission, and their specific meanings are as follows:

[0071] ①: The crystal oscillator is the clock source provided by the clock chip;

[0072] ②: The signal source is the clock source provided by the clock chip;

[0073] ③: The signal source is the sampling clock and analog signal provided by the ADC;

[0074] ④: The clock chip provides the sampling clock and JESD204B interface clock for the ADC chip;

[0075] ⑤: The clock chip provides the JESD204B interface working clock for the FPGA and the status signal from the clock chip to the FPGA;

[0076] ⑥: FPGA configuration signal to the clock chip;

[0077] ⑦: The signal transmitted from ADC to FPGA through JESD204B interface and the status signal from ADC to FPGA;

[0078] ⑧: FPGA configuration signal to ADC;

[0079] ⑨: ATE configuration signal for clock chip;

[0080] ⑩: Status signal from the clock chip to ATE;

[0081] : ATE configuration signal to ADC;

[0082] : The status signal from the ADC to the ATE;

[0083] : The control signal from the ATE to the signal source;

[0084] : The ADC sampling signal and working status signal from the FPGA to the ATE;

[0085] : The control signal and data transfer clock signal from the ATE to the FPGA;

[0086] An ATE test method for JESD204B interface ADCs, the steps of which include:

[0087] Step S1: Design a clock scheme based on the clock chip HMC7044.

[0088] Scheme 1: The crystal oscillator provides the source clock for the HMC7044, and then the HMC7044 generates the AD9208 sampling clock, the JESD204B interface clock of the AD9208, and the JESD204B interface working clock of the FPGA.

[0089] Scheme 2: The signal source provides the sampling clock of the AD9208, and the reference clock of the signal source provides the source clock for the HMC7044. Then the HMC7044 generates the JESD204B interface clock of the AD9208 and the JESD204B interface working clock of the FPGA.

[0090] Clock Scheme 1 does not require a signal source, reducing the dependence on the signal source, being more flexible, and facilitating debugging. Clock Scheme 2 provides a wider range of sampling frequency selection by using the signal source to provide the sampling clock. Combining the two clock schemes can combine the advantages of both.

[0091] Step S2: In the design of the test data transmission and acquisition scheme, the signal source provides an analog signal to AD9208, and then AD9208 sends the sampled signal to FPGAXCKU060 through the JESD204B interface. XCKU060 receives the sampled data of ADC through the JESD204B interface and decodes the data. The specific decoding rules are based on the AD9208 encoding rules. In this example, XCKU060 uses the FIFO IP core to cache the received data and then transmit it to UltraFlex. The FIFO IP core is set to asynchronous reading and writing, the write byte length is 112bit, the depth is 32768, and the clock is provided by the JESD204B interface; the read byte length is 14bit, the depth is 262144, and the clock is provided by UltraFlex. The data volume required for the AD9208 dynamic parameter test can be satisfied by one FIFO buffer. The data volume required for the static parameter test requires multiple FIFO buffers. In this example, UltraFlex is used to collect XCKU060 FIFO IP core buffer data five times to obtain the data volume required for the static parameter test. Figure 2 The schematic diagram of ADC sampling data obtained by FPGA shows that XCKU060 can stably collect ADC sampling data. Figure 3 The schematic diagram of FPGA transmission data obtained by ATE shows that UltraFlex can stably obtain the sampled data transmitted by XCKU060, which illustrates the effectiveness of the test data transmission and acquisition solution proposed in the present invention.

[0092] Step S3: UltraFlex interacts with XCKU060 through the signal channel on the test board, including the following three aspects:

[0093] 1) UltraFlex sends a control signal to XCKU060 to control XCKU060 to send the sampling data of one of the two ADC cores of AD9208 to UltraFlex. For example, if UltraFlex sends 0 to XCKU060 through the data channel, XCKU060 sends the sampling data of the first ADC core of AD9208 to UltraFlex; if UltraFlex sends 1 to XCKU060 through the data channel, XCKU060 sends the sampling data of the second ADC core of AD9208 to UltraFlex.

[0094] 2) UltraFlex sends a data transmission reference clock to XCKU060 to provide a clock for the XCKU060 FIFO IP core read operation so that UltraFlex can correctly receive the data transmitted by XCKU060.

[0095] 3) XCKU060 can send its own status signal to UltraFlex to facilitate UltraFlex to monitor the current running status of the program.

[0096] Step S4: UltraFlex processes the acquired AD9208 sampling data. The data required for static parameter testing is acquired through multiple samplings. ATE needs to splice and organize the acquired data. Finally, ATE is used to calculate dynamic parameters and static parameters according to relevant specifications for testing.

[0097] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. An ATE test method for JESD204B interface ADC, characterized in that include: Arrange the test FPGA, ADC, crystal oscillator and clock chip on the test board: the crystal oscillator is connected to the clock chip to provide a clock source to the clock chip; The clock chip is connected to the test FPGA and ADC at the same time, providing clock signals to the test FPGA and ADC respectively; the JESD204B interface of the test FPGA is connected to the JESD204B interface of the ADC, which is used to test the data transmission between the FPGA and the ADC; The test FPGA is connected to ATE at the same time for data transmission; The external signal source instrument is connected to the clock chip to provide a reference clock for the clock chip; The external signal source instrument is connected to the ADC to provide a reference clock for the ADC; The external signal source instrument is connected to ATE, so that ATE can control and read the status of the external signal source instrument; The clock tree is designed by combining the onboard clock with the external clock to provide a reference clock for testing data transmission between the FPGA and the ADC. After the ADC samples the data, the test FPGA receives the ADC sampled data according to the clock signal of the clock tree, and decodes and caches the sampled data; ATE sends control signals and clock signals to the test FPGA to control the data transmission and transmission timing between FPGA and ATE; at the same time, FPGA sends the current operation status signal of FPGA to ATE; ATE processes the acquired ADC sampling data, calculates dynamic parameters and static parameters, and completes the test.

2. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: The ADC is connected to the ATE at the same time, so that the ATE can configure and read the status of the ADC. The clock chip is also connected to ATE, so that ATE can configure and read the status of the clock chip.

3. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: There are two ways to design a clock tree by combining an onboard clock with an external clock: The crystal oscillator is used to provide a clock source for the clock chip, which generates the ADC sampling clock, the ADC JESD204B interface working clock, and the JESD204B interface working clock of the test FPGA. The external signal source instrument provides a sampling clock for the ADC; at the same time, the external signal source instrument provides a clock source for the clock chip, and then the clock chip provides a working clock for the JESD204B interface of the ADC chip and the JESD204B interface of the test FPGA.

4. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: The ADC's JESD204B interface encodes the sampled data so that the high and low bits of adjacent sampling points of the ADC are distributed in different lanes for transmission to the test FPGA. After the FPGA's JESD204B interface receives the data, it completes decoding by reorganizing the data obtained from different lanes to obtain the correct data of continuous sampling points.

5. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: In the case where the data transmission rate between the ADC and FPGA through the JESD204B interface does not match the data transmission rate between the FPGA and ATE, the data is cached by the test FPGA and then sent to the ATE.

6. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: ATE sends control signals and clock signals to the test FPGA to control the data transmission and transmission timing between FPGA and ATE, specifically: When the ADC chip contains multiple ADC cores, the ATE sends a control signal to the test FPGA to control the test FPGA to send sampling data of different ADC cores to the ATE; ATE sends a clock signal to the test FPGA, providing a reference clock for data transmission between the test FPGA and ATE, ensuring that ATE correctly obtains the transmission data.

7. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: FPGA sends the current running status signal of FPGA to ATE for fault location and program debugging.

8. The ATE test method for JESD204B interface ADC according to claim 1, characterized in that: After ATE calculates the dynamic parameters and static parameters, it determines whether the obtained parameters meet the product test specification requirements and gives the judgment result.

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