Phase alignment test method for serial transmitting end of FPGA high-speed interface transmitter
By connecting the serial transmitter of the high-speed interface transmitter of the FPGA to the high-speed board channel of the ATE machine, and using EDA tools and ATE machines for parameter setting, code stream loading and channel sampling, efficient testing of the phase alignment function of the embedded high-speed serial transmitter in FPGA is achieved, solving the problem of lack of efficient testing methods in the existing technology.
Patent Information
- Application Number
- CN202510034485.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-05-23
AI Technical Summary
There is a lack of efficient methods in the prior art to test the phase alignment function of the FPGA embedded high-speed serial transmitter.
A method for phase alignment testing of serial transmitter ends of FPGA high-speed interface transmitter is proposed. By connecting the serial transmitter of the high-speed interface transmitter of the tested FPGA to the high-speed card channel of the ATE machine, the parameters and configuration are set using EDA tools, and the code stream loading, channel sampling and delay calculation are performed through the ATE machine to realize the test of phase alignment function.
It reduces the complexity of phase alignment testing, improves testing efficiency, get rid of dependence on other instruments, reduces testing costs, and improves the reliability of FPGA embedded high-speed serial transmitters in multi-aggregation and protocol applications.
Smart Images
Figure CN120029836A_ABST
Abstract
Description
Background Art
[0002] Field Programmable Gate Array (FPGA) has been widely used in product design and prototype verification. FPGA has built-in high-speed serial transceivers, PCIE, Ethernet and other unit modules and IP cores, with the characteristics of miniaturization, low cost, high performance, and flexible design. FPGA has built-in high-speed serial transmitter, which converts multiple low-speed parallel signals into high-speed serial signals at the high-speed serial data transmitter, and converts the serial signals back into low-speed parallel signals at the high-speed serial data receiver through the transmission medium (optical cable, copper wire or PCB trace). For the high-speed serial transmitter embedded in FPGA, sometimes it is necessary to synchronize multiple channels, so the delay between channels needs to be less than a certain number of UIs, or even one UI. However, in most cases, the phase delay of the high-speed transmitter is not fixed, and multiple UIs will be generated. Therefore, the FPGA transmitter has an integrated phase alignment function. After such a situation occurs, the phase alignment will be used to complete the phase calibration of the slave channel and the master channel. After completing this operation, the output stream phase delay between different channels must be less than a certain range, so as to reduce the channel binding pressure at the receiving end and ensure the correct receiving function. Phase alignment technology can absorb the skew between two or more channels and transmit data to the user just like a single link transmission. The phase alignment function of the high-speed serial transmitter embedded in the FPGA has been widely used in communication protocols such as XAUI and PCIExpress to achieve high-speed data interconnection, improve the overall stability of the system, reduce the attenuation and distortion of signal transmission, and improve the reliability of long-distance transmission. However, there is currently no efficient method to complete the test of the phase alignment function of the high-speed serial transmitter embedded in the FPGA. Summary of the invention
[0001] In order to solve the above-mentioned problem in the prior art, that is, there is currently no method for efficiently completing the test of the phase alignment function of the FPGA embedded high-speed serial transmitter, the present invention proposes a serial transmitter phase alignment test method for the FPGA high-speed interface transmitter; the method comprises:
[0002] Connect the serial transmission end of the high-speed interface transmitter embedded in the tested FPGA to the high-speed board channel of the ATE machine; connect the parallel data end of the high-speed interface transmitter embedded in the tested FPGA to the first digital channel of the ATE machine, connect the control port of the tested FPGA to the second digital channel of the ATE machine, and connect the configuration port of the tested FPGA to the third digital channel of the ATE machine;
[0003] Use EDA tools to set parameters and configure the serial transmitter; after the FPGA under test is configured, an FPGA configuration file is generated;
[0004] After the ATE machine powers on the serial transmitter of the high-speed interface transmitter embedded in the FPGA under test, it configures the FPGA configuration file and the FPGA under test, and then loads the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies the code pattern to the FPGA under test;
[0005] The high-speed board channel of the ATE machine performs channel sampling on the serial transmitting end of the high-speed interface transmitter embedded in the tested FPGA to obtain sampling data, and performs verification and calculation of the delay between channels after decoding and converting the sampling data.
[0006] In a preferred implementation, the parameters set for the serial transmitter using an EDA tool include: channel rate, encoding mode, and equalization parameters.
[0007] In a preferred implementation, the serial transmission end of the high-speed interface transmitter embedded in the FPGA under test is connected to the high-speed board channel of the ATE machine through AC coupling.
[0008] In a preferred embodiment, configuring the serial transmitter using an EDA tool also includes:
[0009] The EDA tool turns on the phase alignment function of the FPGA under test and enables the built-in 8b / 10b encoding function inside the FPGA under test.
[0010] In a preferred embodiment, the ATE machine applies a code pattern to the FPGA under test further comprising:
[0011] After the ATE machine configures the FPGA configuration file and the FPGA under test and then loads the configuration code stream of the FPGA configuration file into the FPGA under test, the ATE machine sends a clock to the serial transmitter of the FPGA under test and performs a reset operation, and at the same time sets the transmission rate of the FPGA under test;
[0012] After the reset operation is completed, the ATE machine applies a code pattern to the parallel interface of the FPGA under test, and then the serial transmitter of the FPGA under test outputs data.
[0013] In a preferred embodiment, decoding and converting the sampled data includes:
[0014] The sampled data is decoded using the built-in 8b / 10b decoding function of the high-speed card channel of the ATE machine. After decoding, the serial-to-parallel conversion is performed according to the transmission rate to obtain the converted data, and then the converted data is verified.
[0015] In a preferred embodiment, verifying the converted data includes:
[0016] If the code pattern of the converted data matches the code pattern applied by the ATE machine to the FPGA under test, the converted data is considered to meet the verification.
[0017] In a preferred embodiment, calculating the inter-channel delay based on the sampled data includes:
[0018] When the ATE machine powers on the serial transmitter of the high-speed interface transmitter embedded in the FPGA under test, the ATE machine runs the ATE test program and uses the eye diagram capture function of the high-speed board channel to calculate the delay of the main channel based on the sampled data; if the delay of the main channel is less than the set threshold, it is considered to meet the verification; the main channel is specified by the FPGA under test.
[0019] A second aspect of the present invention provides a serial transmitter phase alignment test system for an FPGA high-speed interface transmitter, the system comprising:
[0020] The device connection module is used to connect the serial transmission end of the high-speed interface transmitter embedded in the tested FPGA to the high-speed board channel of the ATE machine; connect the parallel data end of the high-speed interface transmitter embedded in the tested FPGA to the first digital channel of the ATE machine, connect the control port of the tested FPGA to the second digital channel of the ATE machine, and connect the configuration port of the tested FPGA to the third digital channel of the ATE machine;
[0021] The parameter setting module is used to set parameters and configure the serial transmitter using EDA tools; after the FPGA under test is configured, an FPGA configuration file is formed;
[0022] The code stream loading module is used to configure the FPGA configuration file and the FPGA under test after the serial transmitting end of the high-speed interface transmitter embedded in the FPGA under test is powered on by the ATE machine, and then load the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies the code pattern to the FPGA under test;
[0023] The sampling and verification module is used to use the high-speed board channel of the ATE machine to perform channel sampling on the serial transmitting end of the high-speed interface transmitter embedded in the tested FPGA to obtain sampling data, perform verification after decoding and conversion of the sampling data, and calculate the delay between channels.
[0024] The third aspect of the present invention proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned serial transmitter phase alignment test method of the FPGA high-speed interface transmitter.
[0025] Beneficial effects of the present invention:
[0026] (1) The present invention implements the phase alignment function test of the FPGA embedded high-speed serial transmitter through ATE machine delay and function test, reduces the complexity of the phase alignment test, and improves the test efficiency of the phase function;
[0027] (2) The present invention eliminates the reliance of the FPGA embedded high-speed serial transmitter test on other instruments and meters, improves the test efficiency of the high-speed serial transceiver, and reduces the test cost;
[0028] (3) The present invention provides a mass production test method for the phase alignment function of an embedded high-speed serial transmitter in an FPGA. The method monitors the delay and function of different code types between the channels of the embedded high-speed serial transmitter in the FPGA through the high-speed board channel of the ATE machine, realizes the function and performance test of the phase alignment of the embedded high-speed serial transmitter in the FPGA, and improves the reliability of the embedded high-speed serial transmitter in the field of multi-aggregation and protocol application. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0030] Figure 1 It is a schematic diagram of a serial transmitting end phase alignment test method of an FPGA high-speed interface transmitter according to an embodiment of the present invention;
[0031] Figure 2 It is a schematic diagram of a connection method between a tested FPGA and an ATE machine according to an embodiment of the present invention;
[0032] Figure 3 This is a schematic diagram of applying code data to an ATE machine according to an embodiment of the present invention;
[0033] Figure 4 It is a hardware schematic diagram of a serial transmitting end phase alignment test method of an FPGA high-speed interface transmitter according to an embodiment of the present invention;
[0034] Figure 5 It is a schematic diagram of a universal test software platform for a serial transmitter phase alignment test method of an FPGA high-speed interface transmitter according to an embodiment of the present invention;
[0035] Figure 6 The present invention is a schematic diagram of a general test system architecture for a method for testing phase alignment of a serial transmitter of an FPGA high-speed interface transmitter according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant invention and are not intended to limit the invention. Additionally, it should be noted that for the sake of convenience in description, only the parts related to the relevant invention are shown in the drawings.
[0037] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.
[0038] The present invention provides a method for testing the phase alignment of the serial transmission end of an FPGA high-speed interface transmitter, and the method includes:
[0039] Connect the serial transmission end of the high-speed interface transmitter embedded in the FPGA under test to the high-speed board card channel of the ATE machine; connect the parallel data end of the high-speed interface transmitter embedded in the FPGA under test to the first digital channel of the ATE machine, connect the control port of the FPGA under test to the second digital channel of the ATE machine, and connect the configuration port of the FPGA under test to the third digital channel of the ATE machine;
[0040] Use an EDA tool to set parameters and configure the serial transmission end; after the FPGA under test is configured, an FPGA configuration file is formed;
[0041] After the ATE machine powers on the serial transmission end of the high-speed interface transmitter embedded in the FPGA under test, it configures the FPGA configuration file and the FPGA under test, and then loads the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies a pattern to the FPGA under test.
[0042] The high-speed board card channel of the ATE machine samples the serial transmission end of the high-speed interface transmitter embedded in the FPGA under test to obtain sampled data, decodes and converts the sampled data, and then performs verification and calculates the inter-channel delay.
[0043] To more clearly illustrate the method for testing the phase alignment of the serial transmission end of the FPGA high-speed interface transmitter of the present invention, the following will be combined with Figure 1 Expand and describe each step in the embodiment of the present invention in detail.
[0044] The method for testing the phase alignment of the serial transmission end of the FPGA high-speed interface transmitter in the first embodiment of the present invention is described in detail as follows:
[0045] As Figure 2As shown, based on the mass production test requirements of the phase alignment function of the serial transmitter of the high-speed interface embedded in the FPGA, when designing the test board, the serial transmitter (TXP and TXN) of the high-speed interface transmitter embedded in the tested FPGA is connected to the high-speed board channel of the ATE machine; the parallel data end of the high-speed interface transmitter embedded in the tested FPGA is connected to the first digital channel of the ATE machine, the control port of the tested FPGA is connected to the second digital channel of the ATE machine, and the configuration port of the tested FPGA is connected to the third digital channel of the ATE machine;
[0046] In this embodiment, the serial transmission end of the high-speed interface transmitter embedded in the FPGA under test is connected to the high-speed board channel of the ATE machine through AC coupling.
[0047] Use EDA tools to set parameters and configure the serial transmitter; after the FPGA under test is configured, an FPGA configuration file is generated;
[0048] In this embodiment, the parameters set for the serial transmitter using the EDA tool include: channel rate, encoding method, and equalization parameters. When the serial transmitter is configured using the EDA tool, it also includes: the EDA tool turns on the phase alignment function of the FPGA under test, and enables the built-in 8b / 10b encoding function inside the FPGA under test. Specifically, the serial data transmitter of the FPGA is configured using the EDA tool so that its operating rate is consistent with the serial data receiving rate of the high-speed board, the phase alignment function is turned on, and the 8b / 10b encoding and decoding function is turned on. When the serial data transmission rate of the high-speed serial transceiver embedded in the FPGA under test can be changed by the control port, a high-speed channel configuration that matches the serial data transmission rate of the high-speed serial transceiver embedded in the FPGA under test should be added. For example, when the data transmission rate of the embedded high-speed serial transceiver of the FPGA under test is constant at 5Gbps, only one configuration needs to be developed for the high-speed channel receiving end; when the data transmission rate of the embedded high-speed serial transceiver of the FPGA under test is in the range of 1Gbps to 10Gbps, at least two different configurations need to be developed for the high-speed channel receiving end according to the test requirements to meet the test requirements under 1Gbps and 10Gbps; in this embodiment, according to the test requirements, the data transmission end of the embedded high-speed serial transceiver of the FPGA under test needs to be tested in 1Gbps, 2.5Gbps, 5Gbps, 8Gbps and 10Gbps modes, so 5 different high-speed channel receiving end configurations need to be developed to meet the test requirements.
[0049] After the ATE machine powers on the serial transmitter of the high-speed interface transmitter embedded in the FPGA under test, it configures the FPGA configuration file and the FPGA under test, and then loads the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies the code pattern to the FPGA under test;
[0050] In this embodiment, the ATE machine applies a code pattern to the FPGA under test, further comprising: after the ATE machine configures the FPGA configuration file and the FPGA under test and then loads the configuration code stream of the FPGA configuration file into the FPGA under test, the ATE machine sends a clock to the serial transmission end of the FPGA under test and performs a reset operation, and sets the transmission rate of the FPGA under test; after the reset operation is completed, the ATE machine applies a code pattern to the parallel interface of the FPGA under test, and then the serial transmission end of the FPGA under test outputs data. Figure 3 , is a schematic diagram of applying code data by an ATE machine according to an embodiment of the present invention.
[0051] The ATE machine high-speed card channel performs channel sampling on the serial transmission end of the high-speed interface transmitter embedded in the tested FPGA to obtain sampled data, and performs verification after decoding and conversion of the sampled data and calculates the delay between channels. In this embodiment, decoding and converting the sampled data includes: using the embedded 8b / 10b decoding function of the ATE machine high-speed card channel to decode the sampled data, performing serial-to-parallel conversion according to the transmission rate after decoding to obtain converted data, and then verifying the converted data. Verifying the converted data includes: if the code type of the converted data conforms to the code type applied by the ATE machine to the tested FPGA, then it is considered that the converted data conforms to the verification.
[0052] In this embodiment, calculating the delay between channels based on the sampled data includes: when the ATE machine powers on the serial transmitter of the high-speed interface transmitter embedded in the FPGA under test, the ATE machine runs the ATE test program, and uses the eye diagram capture function of the high-speed board channel to calculate the delay of the main channel based on the sampled data; if the delay of the main channel is less than a set threshold, it is considered to meet the verification; the main channel is specified by the FPGA under test.
[0053] In general, the ATE machine is used to control the FPGA on the test board and the high-speed serial transmitter embedded in the FPGA under test. The machine applies the code pattern, and the high-speed serial transceiver embedded in the FPGA under test sends the serial data to the high-speed channel to perform functional and delay tests. Specifically, the test board is first powered on to complete the power-on initialization of the FPGA and the high-speed serial transmitter embedded in the FPGA under test; at the same time, the ATE configures the FPGA, and after the FPGA configuration is completed, the ATE resets the machine high-speed channel; after the reset is completed, the ATE sends the clock and parallel data to the high-speed interface transmitter under test, and the machine high-speed channel receives the serial data sent by the high-speed interface transmitter of the FPGA under test. The ATE machine high-speed channel is used to sample and read the transmission result of the FPGA high-speed interface transmitter in step 102, which is decoded by the 8b / 10b decoding module and converted into parallel data to determine whether the result is correct. If it is correct, the delay between channels is calculated. If it meets the requirements, the phase alignment function is normal. Specifically, run the ATE test program without powering off 102, use the eye diagram capture function of the high-speed channel to collect results and record delays, use the 8b / 10b module for decoding, use the built-in multi-phase acquisition module of the high-speed channel for serial-to-parallel conversion, and use the machine code verification function to judge the results. If correct, calculate the delay difference between channels for further judgment.
[0054] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.
[0055] A serial transmitting end phase alignment test system of an FPGA high-speed interface transmitter according to a second embodiment of the present invention comprises:
[0056] The device connection module is used to connect the serial transmission end of the high-speed interface transmitter embedded in the tested FPGA to the high-speed board channel of the ATE machine; connect the parallel data end of the high-speed interface transmitter embedded in the tested FPGA to the first digital channel of the ATE machine, connect the control port of the tested FPGA to the second digital channel of the ATE machine, and connect the configuration port of the tested FPGA to the third digital channel of the ATE machine;
[0057] The parameter setting module is used to set parameters and configure the serial transmitter using EDA tools; after the FPGA under test is configured, an FPGA configuration file is formed;
[0058] The code stream loading module is used to configure the FPGA configuration file and the FPGA under test after the serial transmitting end of the high-speed interface transmitter embedded in the FPGA under test is powered on by the ATE machine, and then load the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies the code pattern to the FPGA under test;
[0059] The sampling and verification module is used to use the high-speed board channel of the ATE machine to perform channel sampling on the serial transmitting end of the high-speed interface transmitter embedded in the tested FPGA to obtain sampling data, perform verification after decoding and conversion of the sampling data, and calculate the delay between channels.
[0060] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.
[0061] It should be noted that the serial transmitter phase alignment test system of the FPGA high-speed interface transmitter provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.
[0062] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the processor and stores a configured FPGA code stream, and the instructions are used to be executed by the processor to implement the above-mentioned serial transmitter phase alignment test method of the FPGA high-speed interface transmitter.
[0063] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned serial transmitter phase alignment test method of the FPGA high-speed interface transmitter.
[0064] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the electronic device and storage medium described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.
[0065] like Figure 4As shown, the hardware system of the present invention includes control and monitoring hardware and instrument and device hardware; the control and monitoring hardware includes a main control computer, on which test software is installed, and the outside of the main control computer has peripheral devices for auxiliary. The instrument and device hardware includes a signal excitation source, a test switch matrix, a signal collector, a test object adapter, and a test object; the instrument and hardware device is the channel part of ATE, the test object is FPGA, and the running program is the control and monitoring hardware (main control computer).
[0066] like Figure 5 As shown in the figure, the universal test software platform of the present invention includes: a graphical user interface GUI, a data management system, a test control database, a universal automatic test program, a test result database and a test object. The operating system software Windows, the test program language and development environment, the instrument driver and the VISA library act on the universal test software platform. Configuration, code transmission and verification are all realized by controlling the machine channel through software programming.
[0067] like Figure 6 As shown, the universal test system architecture of the present invention includes a main control computer, a bus instrument measurement and control combination, and a signal conditioning and switching device; the main control computer includes some operating systems, compilers and test execution programs; the bus instrument measurement and control combination includes modular test and measurement instruments, various control switches and communication buses; the signal conditioning and switching device includes switching and adaptation of various measurement and excitation control signals.
[0068] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.
[0069] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0070] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.
[0071] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.
[0072] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A serial transmitter phase alignment test method for an FPGA high-speed interface transmitter, characterized in that: The method comprises: Connect the serial transmission end of the high-speed interface transmitter embedded in the tested FPGA to the high-speed board channel of the ATE machine; connect the parallel data end of the high-speed interface transmitter embedded in the tested FPGA to the first digital channel of the ATE machine, connect the control port of the tested FPGA to the second digital channel of the ATE machine, and connect the configuration port of the tested FPGA to the third digital channel of the ATE machine; Use EDA tools to set parameters and configure the serial transmitter; after the FPGA under test is configured, an FPGA configuration file is generated; After the ATE machine powers on the serial transmitter of the high-speed interface transmitter embedded in the FPGA under test, it configures the FPGA configuration file and the FPGA under test, and then loads the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies the code pattern to the FPGA under test; The high-speed board channel of the ATE machine performs channel sampling on the serial transmitting end of the high-speed interface transmitter embedded in the tested FPGA to obtain sampling data, and performs verification and calculation of the delay between channels after decoding and converting the sampling data.
2. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 1, characterized in that: The parameters set for the serial transmitter using the EDA tool include: channel rate, encoding method, and equalization parameters.
3. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 2, characterized in that: The serial transmission end of the high-speed interface transmitter embedded in the FPGA under test is connected to the high-speed board channel of the ATE machine through AC coupling.
4. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 1, characterized in that: When using EDA tools to configure the serial transmitter, it also includes: The EDA tool turns on the phase alignment function of the FPGA under test and enables the built-in 8b / 10b encoding function inside the FPGA under test.
5. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 1, characterized in that: The ATE machine applies the code pattern to the FPGA under test and also includes: After the ATE machine configures the FPGA configuration file and the FPGA under test and then loads the configuration code stream of the FPGA configuration file into the FPGA under test, the ATE machine sends a clock to the serial transmitter of the FPGA under test and performs a reset operation, and at the same time sets the transmission rate of the FPGA under test; After the reset operation is completed, the ATE machine applies a code pattern to the parallel interface of the FPGA under test, and then the serial transmitter of the FPGA under test outputs data.
6. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 1, characterized in that: The decoding conversion of the sampled data includes: The sampled data is decoded using the built-in 8b / 10b decoding function of the high-speed card channel of the ATE machine. After decoding, the serial-to-parallel conversion is performed according to the transmission rate to obtain the converted data, and then the converted data is verified.
7. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 6, characterized in that: Verification of the converted data includes: If the code pattern of the converted data matches the code pattern applied by the ATE machine to the FPGA under test, the converted data is considered to meet the verification.
8. The serial transmitter phase alignment test method of the FPGA high-speed interface transmitter according to claim 7, characterized in that: Calculating the inter-channel delay based on sampled data includes: When the ATE machine powers on the serial transmitter of the high-speed interface transmitter embedded in the FPGA under test, the ATE machine runs the ATE test program and uses the eye diagram Capture function of the high-speed board channel to calculate the delay of the main channel based on the sampled data; if the delay of the main channel is less than the set threshold, it is considered to meet the verification; the main channel is the channel specified by the FPGA under test.
9. A serial transmitter phase alignment test system for an FPGA high-speed interface transmitter, characterized in that: The system comprises: The device connection module is used to connect the serial transmission end of the high-speed interface transmitter embedded in the tested FPGA to the high-speed board channel of the ATE machine; connect the parallel data end of the high-speed interface transmitter embedded in the tested FPGA to the first digital channel of the ATE machine, connect the control port of the tested FPGA to the second digital channel of the ATE machine, and connect the configuration port of the tested FPGA to the third digital channel of the ATE machine; The parameter setting module is used to set parameters and configure the serial transmitter using EDA tools; after the FPGA under test is configured, an FPGA configuration file is formed; The code stream loading module is used to configure the FPGA configuration file and the FPGA under test after the serial transmitting end of the high-speed interface transmitter embedded in the FPGA under test is powered on by the ATE machine, and then load the configuration code stream of the FPGA configuration file into the FPGA under test; then the ATE machine applies the code pattern to the FPGA under test; The sampling and verification module is used to use the high-speed board channel of the ATE machine to perform channel sampling on the serial transmitting end of the high-speed interface transmitter embedded in the tested FPGA to obtain sampling data, perform verification after decoding and conversion of the sampling data, and calculate the delay between channels.
10. An electronic device, characterized in that: include: at least one processor; And a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the serial transmitter phase alignment test method of the FPGA high-speed interface transmitter as described in any one of claims 1-8.