Write channel data transmission control method of AXI protocol, controller and program product

Abstract

The invention relates to the technical field of chip design, and provides a write channel data transmission control method of an AXI protocol, a controller and a computer program product. The method comprises the following steps: acquiring a to-be-transmitted write data channel signal and a to-be-transmitted write address channel signal; if a discontinuous mask appears in a write mask signal in the write data channel signal, splitting the discontinuous mask into a plurality of continuous masks, the plurality of continuous masks and the discontinuous mask corresponding to the same write data; writing data corresponding to the continuous masks are transmitted in a burst writing mode; and if a burst transmission type signal in the write address channel signal represents address incremental burst transmission, adjusting a write address signal and a write length signal in the write address channel signal. According to the method, the discontinuous masks in the mask writing signal are split into a plurality of continuous masks, so that data transmission of the writing channel conforms to PCIe rules, the problem of data transmission errors is avoided, and the compatibility and stability of a system are improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a write channel data transmission control method, a controller and a computer program product of an AXI protocol. Background Art

[0002] AXI (Advanced eXtensible Interface) is a high-performance, high-bandwidth bus protocol that is widely used to connect various devices such as processors, memory, and peripherals. In the design of SoC (System on Chip), the AXI protocol is usually used to implement communication between functional modules within the SoC system.

[0003] However, during the communication process between functional modules within the SoC system, the AXI Slave write channel of PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) may receive discontinuous write mask signals (i.e., wstrb signals) at any position. Although this situation is allowed in the AXI protocol, the First / Last DW Byte Enables rule of PCIe stipulates that discontinuous masks can only exist at the beginning and end of the write mask signal, and discontinuous masks at other positions will be forced to be regarded as continuous 1s. Therefore, this situation will cause data transmission errors and affect the compatibility and stability of the system. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a write channel data transmission control method, controller and computer program product of an AXI protocol. By splitting the discontinuous mask in the write mask signal into multiple continuous masks, the data transmission of the write channel complies with the rules of PCIe, thereby avoiding the problem of data transmission errors and improving the compatibility and stability of the system.

[0005] A first aspect of an embodiment of the present application provides a write channel data transmission control method of an AXI protocol, comprising:

[0006] Obtaining a write data channel signal and a write address channel signal to be transmitted;

[0007] If a discontinuous mask appears in the write mask signal in the write data channel signal, the discontinuous mask is split into a plurality of continuous masks, and the plurality of continuous masks and the discontinuous mask all correspond to the same write data;

[0008] The write data corresponding to each of the plurality of consecutive masks is transmitted through burst write;

[0009] If the burst transfer type signal in the write address channel signal indicates address incremental burst transfer, the write address signal and the write length signal in the write address channel signal are adjusted.

[0010] In the technical solution of the embodiment of the present application, the write data channel signal and the write address channel signal to be transmitted are obtained. If a discontinuous mask is detected in the write mask signal in the write data channel signal, the discontinuous mask is split into multiple continuous masks, and the multiple continuous masks and the discontinuous mask correspond to the same write data; then, the write data corresponding to each of the multiple continuous masks is transmitted in a burst write manner, which is equivalent to splitting the write data corresponding to the discontinuous mask into multiple write data corresponding to each of the multiple continuous masks for transmission, so that the transmitted write mask signal does not contain the discontinuous mask, so that the data transmission of the write channel complies with the rules of PCIe, thereby avoiding the problem of data transmission errors and improving the compatibility and stability of the system. In addition, considering that the write data of the AXI protocol is transmitted in a burst write manner, that is, a single burst write contains multiple write data, if the write data corresponding to the discontinuous mask is split into multiple write data corresponding to each of the multiple continuous masks for transmission, the number of write data contained in the single burst write may change, so it is necessary to adjust the write length signal in the write address channel signal accordingly. Moreover, when the burst transfer type selects address incremental burst transfer, the multiple write data corresponding to the multiple continuous masks will be written to different incremental addresses by default. However, these write data correspond to the same discontinuous mask and need to be written to the same address. Therefore, the write address signal in the write address channel signal also needs to be adjusted accordingly.

[0011] In one implementation of the embodiment of the present application, the write mask signal is 16 bits; whether any mask in the write mask signal is a discontinuous mask is determined by the following method:

[0012] If any of the four hexadecimal masks corresponding to the mask has one non-zero mask or two non-zero masks, it is determined that the mask is not a discontinuous mask;

[0013] If the 4 hexadecimal masks corresponding to any mask have 3 non-0 masks or 4 non-0 masks, and there is no 0 between any two 1s in the 16 bits of any mask, it is determined that any mask is not a discontinuous mask.

[0014] In an implementation of the embodiment of the present application, a discontinuous mask is split into multiple continuous masks, including:

[0015] The discontinuous mask is split into a first mask and a second mask; wherein the first half of the first mask is the first half of the discontinuous mask, and the second half of the first mask is 0; the second half of the second mask is the second half of the discontinuous mask, and the first half of the second mask is 0.

[0016] In an implementation of the embodiment of the present application, the write data corresponding to each of the plurality of consecutive masks is transmitted through burst write transmission, including:

[0017] If the masks obtained after combining multiple consecutive masks are continuous, the write data corresponding to each of the multiple consecutive masks are transmitted through the same burst write;

[0018] If the mask obtained by combining multiple continuous masks is not continuous, the write data corresponding to each of the multiple continuous masks are transmitted through different burst write transmissions.

[0019] In an implementation of the embodiment of the present application, obtaining a write data channel signal and a write address channel signal to be transmitted includes:

[0020] Buffering the write data channel signal into the first FIFO buffer; the write enable of the first FIFO buffer is controlled by the write data valid signal, and the read enable is controlled by the transmission of the write data;

[0021] The write address channel signal is buffered in the second FIFO buffer; the write enable of the second FIFO buffer is controlled by the write address valid signal, and the read enable is controlled by the burst write transmission.

[0022] In an implementation of the embodiment of the present application, adjusting the write address signal and the write length signal in the write address channel signal includes:

[0023] Setting and starting a first counter, wherein a count value of the first counter is increased by 1 when a write data is transmitted, and is reset after a burst write is transmitted;

[0024] Setting and starting a second counter, wherein a count value of the second counter is incremented by 1 when a burst write is transmitted, and is reset after a burst write is transmitted;

[0025] The write length signal is adjusted according to the difference between the count value of the first counter and the count value of the second counter.

[0026] In an implementation of the embodiment of the present application, adjusting the write address signal and the write length signal in the write address channel signal includes:

[0027] Setting and starting a third counter, wherein the count value of the third counter is increased by 2 when a write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted;

[0028] A fourth counter is set and started, wherein the count value of the fourth counter is increased by 2 when a target write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a target write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted; wherein the target write data refers to non-last write data in a burst write;

[0029] The write address signal is adjusted according to the difference between the count value of the third counter and the count value of the fourth counter.

[0030] In one implementation of the embodiment of the present application, the method further includes:

[0031] If the burst transfer type signal in the write address channel signal indicates a fixed-address burst transfer, the write length signal in the write address channel signal is adjusted.

[0032] A second aspect of an embodiment of the present application provides a write channel data transmission control device of an AXI protocol, comprising:

[0033] A signal acquisition module, used to acquire a write data channel signal and a write address channel signal to be transmitted;

[0034] A mask splitting module is used for splitting the discontinuous mask into multiple continuous masks if a discontinuous mask appears in the write mask signal in the write data channel signal, wherein the multiple continuous masks and the discontinuous mask all correspond to the same write data;

[0035] A data transmission module, used for transmitting the write data corresponding to each of the plurality of consecutive masks through burst write transmission;

[0036] The signal adjustment module is used to adjust the write address signal and the write length signal in the write address channel signal if the burst transfer type signal in the write address channel signal indicates address incremental burst transfer.

[0037] A third aspect of an embodiment of the present application provides a controller, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the write channel data transmission control method of the AXI protocol provided in the first aspect of the embodiment of the present application is implemented.

[0038] A fourth aspect of the embodiments of the present application provides a computer program product. When the computer program product runs on a controller, the controller executes the write channel data transmission control method of the AXI protocol provided in the first aspect of the embodiments of the present application.

[0039] The fifth aspect of the embodiments of the present application provides a computer-readable storage medium storing a computer program, which when executed by a processor, implements the method for controlling the data transmission of the write channel of the AXI protocol provided in the first aspect of the embodiments of the present application.

[0040] It can be understood that for the beneficial effects of the above second aspect to fifth aspect, reference can be made to the relevant descriptions in the first aspect above, which will not be elaborated here. Description of the Drawings

[0041] Figure 1 is a flowchart of a method for controlling the data transmission of the write channel of the AXI protocol provided by the embodiments of the present application;

[0042] Figure 2 is a schematic diagram of an operation principle of a method for controlling the data transmission of the write channel of the AXI protocol provided by the embodiments of the present application;

[0043] Figure 3 is a schematic structural diagram of a device for controlling the data transmission of the write channel of the AXI protocol provided by the embodiments of the present application;

[0044] Figure 4 is a schematic diagram of a controller provided by the embodiments of the present application. Detailed Embodiments

[0045] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application. In addition, in the description of the specification and the appended claims of the present application, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0046] The AXI protocol is a high-performance, high-bandwidth, and low-latency bus protocol that supports parallel read and write, out-of-order transmission, non-aligned operations, and burst transmission that only requires the first address to be specified. In the field of chip design technology, the AXI protocol is often used to implement communication between various functional modules within the chip system. However, when the AXI protocol is applied to the interface design of the PCIe standard, the AXI Slave write channel of PCIe may receive discontinuous write mask signals at any position, while the First / Last DW Byte Enables rule of PCIe stipulates that discontinuous masks can only exist at the beginning and end of the write mask signal, and discontinuous masks at other positions will be forced to be regarded as continuous 1s, which will cause errors in data transmission in the AXI write channel and reduce the compatibility and stability of the system.

[0047] In view of the above technical problems, the embodiments of the present application provide a write channel data transmission control method, controller and computer program product of the AXI protocol, which makes the data transmission of the write channel conform to the rules of PCIe by splitting the discontinuous mask in the write mask signal into multiple continuous masks, thereby avoiding the problem of data transmission errors and improving the compatibility and stability of the system. For more specific technical implementation details of the embodiments of the present application, please refer to the method embodiments described below.

[0048] See also Figure 1 , shows a write channel data transmission control method of an AXI protocol provided in an embodiment of the present application, comprising:

[0049] 101. Obtain a write data channel signal and a write address channel signal to be transmitted;

[0050] It should be understood that the executor of each method embodiment of the present application can be a controller connected between an AXI master device and an AXI slave device. The AXI master device and the AXI slave device communicate based on the AXI protocol. The controller can be used to split the discontinuous mask in the write mask signal output by the AXI master device into multiple continuous masks, and the write data corresponding to each of the multiple continuous masks can be transmitted to the AXI slave device through burst writing. This can meet the rules of PCIe and avoid the problem of data transmission errors. The specific working principle is explained below.

[0051] The AXI master device outputs write data channel signals and write address channel signals to the controller based on the AXI protocol. The write data channel signals are signals starting with w, which may include: wid signal, wdata signal, wstrb signal, wlast signal, walid signal, wready signal, and wuser signal, etc. The write address channel signals are signals starting with aw, which may include: awaddr signal, awlen signal, awsize signal, awid signal, awburst signal, awlock signal, awcache signal, awprot signal, awqos signal, awregion signal, awuser signal, awvalid signal, and awready signal, etc. For the specific definitions and descriptions of the above signals, please refer to the existing AXI protocol documents, which will not be repeated here.

[0052] After the controller obtains the write data channel signal and the write address channel signal output by the AXI master device, it can use various cache devices to cache these signals first, so as to perform subsequent operations such as discontinuous mask splitting, transmission of write data, and signal adjustment. In actual operation, cache devices such as SRAM (Static Random-Access Memory) or FIFO (First Input First Output) can be used to cache the write data channel signal and the write address channel signal respectively, that is, use one cache device to cache the write data channel signal, and use another cache device to cache the write address channel signal.

[0053] Considering that the working principle of the FIFO buffer is simple and efficient, can save the layout area and simplify the logic, the embodiment of the present application can select two FIFO buffer devices to cache the write data channel signal and the write address channel signal respectively. In an implementation of the embodiment of the present application, obtaining the write data channel signal and the write address channel signal to be transmitted includes:

[0054] (1) Buffering the write data channel signal into the first FIFO buffer; the write enable of the first FIFO buffer is controlled by the write data valid signal, and the read enable is controlled by the transmission of the write data;

[0055] (2) Buffering the write address channel signal into the second FIFO buffer; the write enable of the second FIFO buffer is controlled by the write address valid signal, and the read enable is controlled by the burst write transmission.

[0056] The first FIFO buffer is used to cache the write data channel signal, and its write enable is controlled by the write data valid signal (i.e., walid signal), that is, when the walid signal is 1, the write enable of the first FIFO buffer is valid, and the valid write data channel signal output by the AXI master device is written into the first FIFO buffer. The read enable of the first FIFO buffer is controlled by the transmission of the write data, that is, when each write data is transmitted through the wdata signal, the first FIFO buffer reads out the data once, which can avoid the problem of FIFO congestion.

[0057] The second FIFO buffer is used to cache the write address channel signal, and its write enable is controlled by the write address valid signal (i.e., awvalid signal), that is, when the awvalid signal is 1, the write enable of the second FIFO buffer is valid, and the valid write address channel signal output by the AXI master device is written into the second FIFO buffer. The transmission of the AXI protocol usually adopts the burst write (i.e., burst) method. Each burst write (i.e., each burst) only needs to specify a write head address, and multiple write data can be transmitted to the corresponding address according to the set burst transmission type. Therefore, the read enable of the second FIFO buffer is controlled by the burst write transmission, that is, each time a burst write (burst) is transmitted, the second FIFO buffer reads out data once to obtain the address data required for the next burst write, which not only meets the write data transmission requirements of the AXI protocol, but also avoids the problem of FIFO blockage.

[0058] 102. If a discontinuous mask appears in the write mask signal in the write data channel signal, the discontinuous mask is split into a plurality of continuous masks, and the plurality of continuous masks and the discontinuous mask all correspond to the same write data;

[0059] After acquiring the write data channel signal and the write address channel signal, the controller can monitor the write mask signal (i.e., wstrb signal) in the write data channel signal to determine whether a discontinuous mask appears in the wstrb signal. The wstrb signal is also called a write select signal, which can be used to indicate which bytes of data in the wdata signal are valid. Each bit of the wstrb signal corresponds to a byte in the wdata signal. Taking the AXI protocol with a 128-bit data width as an example, a 128-bit write data of the wdata signal corresponds to a 16-bit mask of the wstrb signal. A discontinuous mask means that a "0" appears between two "1"s in the mask, such as "101" or "1001". Taking the 16-bit wstrb signal as an example, a method for determining a discontinuous mask and a continuous mask is proposed below.

[0060] In one implementation of the embodiment of the present application, the write mask signal is 16 bits; whether any mask in the write mask signal is a discontinuous mask is determined by the following method:

[0061] (1) If any of the four hexadecimal masks corresponding to the mask has one non-zero mask or two non-zero masks, it is determined that the mask is not a discontinuous mask;

[0062] (2) If the four hexadecimal masks corresponding to any mask have three non-zero masks or four non-zero masks, and there is no 0 between any two 1s in the 16 bits of any mask, then it is determined that any mask is not a discontinuous mask.

[0063] Assume that any mask MASK in the 16-bit wstrb signal is currently obtained, the 16 bits of MASK can be divided into 4 hexadecimal masks. If there is 1 non-0 mask or 2 non-0 masks in the 4 hexadecimal masks, it can be determined that MASK is not a discontinuous mask, that is, MASK is a continuous mask. If there are 3 non-0 masks or 4 non-0 masks in the 4 hexadecimal masks, and there is no 0 between any two 1s in the 16 bits of MASK, it can also be determined that MASK is not a discontinuous mask, that is, MASK is a continuous mask. In special cases, if the 4 hexadecimal masks are all 0, it means invalid write data, and MASK can also be considered as a continuous mask. In addition to the above situation, MASK is determined to be a discontinuous mask. This judgment rule is shown in the following Table 1:

[0064] Table 1

[0065]

[0066] The mask that meets one of the conditions described in Table 1 is a continuous mask, otherwise it is a discontinuous mask. In Table 1, for the case of a hexadecimal mask with 1 non-0 and a hexadecimal mask with 2 non-0, A and B can be any non-0 hexadecimal numbers. Although "101" or "1001" may appear in the mask at this time, for 128-bit data, the mask corresponding to 64-bit or less bytes is allowed to have "101" or "1001", which is also in line with the PCIe rules. Therefore, it can be regarded as a continuous mask. For this reason, if the data bit width is 64 bits or less, the corresponding discontinuous mask does not need to be split. For the case of a hexadecimal mask with 3 non-0 and a hexadecimal mask with 4 non-0, it is required that there is no 0 between any two 1s in the 16 bits of the mask to be regarded as a continuous mask.

[0067] Each continuous mask appearing in the wstrb signal does not need to be processed, but each discontinuous mask appearing in the wstrb signal needs to be split into multiple continuous masks, and the multiple continuous masks and the discontinuous mask correspond to the same wid, wdata, wuser and other information.

[0068] Taking a 16-bit mask as an example, the splitting rule is to split a discontinuous mask into two masks. In one implementation of the embodiment of the present application, the discontinuous mask is split into multiple continuous masks, including:

[0069] The discontinuous mask is split into a first mask and a second mask; wherein the first half of the first mask is the first half of the discontinuous mask, and the second half of the first mask is 0; the second half of the second mask is the second half of the discontinuous mask, and the first half of the second mask is 0.

[0070] For a discontinuous mask, it is split into a first mask and a second mask, the first half of the first mask is the first half of the discontinuous mask, the second half of the first mask is 0, the second half of the second mask is the second half of the discontinuous mask, and the first half of the second mask is 0. For example, for a discontinuous mask of 0x4567, it is split into a first mask of 0x4500 and a second mask of 0x0067. Masks 0x4567, 0x4500, and 0x0067 all correspond to the same write data. The principle of mask splitting is to replace the write data corresponding to the discontinuous mask with the two write data corresponding to the two continuous masks for transmission to comply with the PCIe rules; that is, initially the write data is transmitted using mask 0x4567, but considering that the PCIe rules do not accept the discontinuous mask 0x4567, it is replaced by using mask 0x4500 to transmit the first half of the write data, and using mask 0x0067 to transmit the second half of the write data. In this way, the same data transmission result as transmitting the write data using mask 0x4567 can be obtained, and it complies with the PCIe rules.

[0071] In addition, if the data width is 256 bits, each discontinuous mask needs to be split twice, that is, it needs to be split into 4 masks. The specific splitting principle is consistent with the splitting principle of 128-bit data width. For 512-bit data width or 1024-bit data width, each discontinuous mask needs to be split into 8 masks or 16 masks, and so on. Moreover, a corresponding flag can be added to each mask obtained after splitting to distinguish between the unsplit mask and the split mask.

[0072] 103. Transmitting write data corresponding to each of the plurality of consecutive masks through burst write transmission;

[0073] After splitting the discontinuous mask into multiple continuous masks, the write data corresponding to each of the multiple continuous masks are transmitted in a burst write mode. Since the multiple continuous masks and the discontinuous mask correspond to the same write data, this is equivalent to splitting the write data corresponding to the discontinuous mask into multiple write data corresponding to each of the multiple continuous masks for transmission. The data transmission result will not change, but the transmitted wstrb signal can be made to contain no discontinuous mask, so that the data transmission of the write channel complies with the PCIe rules.

[0074] In an implementation of the embodiment of the present application, the write data corresponding to each of the plurality of consecutive masks is transmitted through burst write transmission, including:

[0075] (1) If the masks obtained by combining multiple consecutive masks are continuous, the write data corresponding to each of the multiple consecutive masks are transmitted through the same burst write transmission;

[0076] (2) If the mask obtained by combining multiple continuous masks is not continuous, the write data corresponding to each of the multiple continuous masks are transmitted through different burst write transmissions.

[0077] In order to effectively utilize the system bandwidth and improve data transmission efficiency, the write data corresponding to multiple continuous masks are preferably transmitted continuously through a burst. However, it is necessary to first determine whether the masks obtained after combining the multiple continuous masks are continuous. If the combined masks are continuous, they can be transmitted continuously through a burst. Otherwise, they can only be split into different bursts for transmission. For example, after splitting the discontinuous mask 0xABCD into mask 0xAB00 and mask 0x00CD, mask 0xAB00 and mask 0x00CD are combined to obtain mask 0xAB0000CD. If mask 0xAB0000CD is continuous, the write data corresponding to mask 0xAB00 and the write data corresponding to mask 0x00CD can be transmitted through one burst. At this time, the wlast signal remains 0, indicating that the last write data in a burst has not been reached; if mask 0xAB0000CD is discontinuous, the write data corresponding to mask 0xAB00 and the write data corresponding to mask 0x00CD need to be transmitted through different bursts. At this time, the wlast signal is pulled high to 1, indicating that the write data corresponding to mask 0xAB00 is the last write data in a burst, and the write data corresponding to mask 0x00CD will be transmitted in the next burst.

[0078] 104. If the burst transfer type signal in the write address channel signal indicates address incremental burst transfer, adjust the write address signal and the write length signal in the write address channel signal.

[0079] In the previous operation, the write data corresponding to the discontinuous mask is split into multiple write data corresponding to each of the continuous masks for transmission. This will not change the data transmission result, but can make the transmitted write mask signal contain no discontinuous mask, so that the data transmission of the write channel complies with the PCIe rules. However, the above operation may change the number of write data transmitted in a single burst, so it is necessary to adjust the write length signal in the write address channel signal, that is, the awlen signal accordingly. The number of write data transmitted in a single burst is controlled by the awlen signal. For example, when awlen=0, it means that a single burst transmits 1 write data, and when awlen=1, it means that a single burst transmits 2 write data... and so on. In addition, if the burst transmission type signal in the write address channel signal indicates an address incremental burst transmission, that is, the awburst signal is in incremental mode, the multiple write data corresponding to each of the multiple continuous masks will be written to different incremental addresses by default. However, these write data correspond to the same discontinuous mask and need to be written to the same address, so it is necessary to adjust the write address signal in the write address channel signal, that is, the awaddr signal, accordingly. After splitting and combining the discontinuous masks, the controller will readjust the write address signal and the write length signal to form a new AXI write request. The specific adjustment method of the write address signal and the write length signal is described below.

[0080] In an implementation of the embodiment of the present application, adjusting the write address signal and the write length signal in the write address channel signal includes:

[0081] (1) setting and starting a first counter, wherein a count value of the first counter is increased by 1 when a write data is transmitted, and is reset after a burst write is transmitted;

[0082] (2) setting and starting a second counter, wherein a count value of the second counter is incremented by 1 when a burst write is transmitted, and is reset after a burst write is transmitted;

[0083] (3) The write length signal is adjusted according to the difference between the count value of the first counter and the count value of the second counter.

[0084] For the adjustment process of the write length signal, the first counter CNT_A is set and started, and the count value of CNT_A is increased by 1 when a write data is transmitted, and is reset to 0 after a burst is transmitted; the second counter CNT_B is set and started, and the count value of CNT_B is increased by 1 when a burst is transmitted (that is, when the wlast signal is 1), and is reset to 0 after a burst is transmitted. Obviously, the count value of CNT_B can only be 0 or 1; then, the difference between the count value of CNT_A and the count value of CNT_B is calculated to obtain the value of the new awlen signal, and the adjustment can be completed by replacing the initial value of the awlen signal with the value of the new awlen signal. For example, suppose that after the mask splitting, there are three write data data1, data2 and data3 to be transmitted, of which data1 and data2 are transmitted through a burst1, and data3 is transmitted through another burst2; when transmitting burst1, CNT_A will count to 2, CNT_B will count to 1, and the difference between the two count values ​​is 1, that is, let the awlen signal be 1, when awlen is 1, it means that a single burst transmits 2 write data, which is accurate; after burst1 is transmitted, the wlast signal is pulled high to 1, and CNT_A and CNT_B are reset to 0; when transmitting burst2, CNT_A will count to 1, CNT_B will count to 1, and the difference between the two count values ​​is 0, that is, let the awlen signal be 0, when awlen is 0, it means that a single burst transmits 1 write data, which is also accurate. It can be seen that by setting the first counter CNT_A and the second counter CNT_B, the accurate awlen signal can be easily calculated for updating.

[0085] In an implementation of the embodiment of the present application, adjusting the write address signal and the write length signal in the write address channel signal includes:

[0086] (1) setting and starting a third counter, wherein a count value of the third counter is incremented by 2 when a write data corresponding to an unsplit mask is transmitted, and is incremented by 1 when a write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted;

[0087] (2) setting and starting a fourth counter, wherein the count value of the fourth counter is increased by 2 when a target write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a target write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted; wherein the target write data refers to non-last write data in a burst write;

[0088] (3) The write address signal is adjusted according to the difference between the count value of the third counter and the count value of the fourth counter.

[0089] For the adjustment process of the write address signal, the third counter CNT_C is set and started, and the count value of CNT_C is increased by 2 when the write data corresponding to an unsplit mask is transmitted, and is increased by 1 when the write data corresponding to a split mask is transmitted, and is reset to 0 after the last burst of an AXI write data request is transmitted. The unsplit mask and the split mask can be distinguished by the flag set when the mask is split; the fourth counter CNT_D is set and started, and the count value of CNT_D is increased by 2 when the target write data corresponding to an unsplit mask is transmitted, and is increased by 1 when the target write data corresponding to a split mask is transmitted, and is reset to 0 after the last burst of an AXI write data request is transmitted. The target write data here refers to the non-last write data in a burst, that is, the write data corresponding to the wlast signal being 0; thereafter, the difference between the count value of CNT_C and the count value of CNT_D is calculated, and the value of the new awaddr signal can be inferred, and the adjustment can be completed by replacing the value of the initial awaddr signal with the value of the new awaddr signal. For example, suppose that an AXI write data request currently being transmitted includes 4 bursts, namely burst1, burst2, burst3 and burst4. Due to mask splitting, burst1 is split into burst1A and burst1B, burst4 is split into burst4A and burst4B, while burst2 and burst3 are not split, and each burst transmits only 1 write data; when transmitting burst1A, burst1B, burst2, burst3, burst4A, and burst4B, the wlast signals are 1, 1, 0, 0, 1, and 1, respectively, and the count values ​​of CNT_C are 1, 2, 4, 6, 7, and 8, respectively, and CNT_ The count values ​​of D are 0, 0, 2, 4, 4, 4 in sequence. The difference between the count values ​​of CNT_C and CNT_D can be calculated to obtain the results of 1, 2, 3, and 4. Based on the result, the offset of burst compared to the initial write address can be inferred, thereby obtaining the updated awaddr signal; specifically, according to the AXI protocol, the following rules can be formulated: when the difference between the count values ​​of CNT_C and CNT_D is 1 or 2, the offset of burst compared to the initial write address is 0; when the difference between the count values ​​of CNT_C and CNT_D is 3 or 4, the offset of burst compared to the initial write address is 1, and so on; the offset is 1, indicating that the updated awaddr signal is the initial write address plus 0x20. It can be seen that by setting the third counter CNT_C and the fourth counter CNT_D, the accurate awaddr signal can be easily calculated for update.

[0090] In one implementation manner of the embodiment of the present application, the method further includes:

[0091] If the burst transfer type signal in the write address channel signal indicates an address-fixed burst transfer, adjust the write length signal in the write address channel signal.

[0092] If the burst transfer type signal in the write address channel signal indicates an address-fixed burst transfer, that is, the awburst signal is in the fixed mode, all write data will be written to the same fixed address. In this way, multiple write data corresponding to multiple consecutive masks and write data corresponding to discontinuous masks are all written to the same address. Therefore, there is no need to adjust the awaddr signal. At this time, only the awlen signal needs to be adjusted. The specific adjustment method of the awlen signal can refer to the description above.

[0093] Since the splitting of discontinuous masks does not affect other write data channel signals or write address channel signals such as the awsize signal, awid signal, awburst signal, awlock signal, awcache signal, awprot signal, awqos signal, awregion signal, awuser signal, wid signal, and wuser signal, the content of these signals can remain unchanged. After the controller completes the adjustment of the write address signal and the write length signal, it reads the updated write address channel signal, combines the data into a new AXI write data request, and sends it to the AXI slave device.

[0094] In one implementation manner of the embodiment of the present application, the controller can also set a switch for turning on or off the operations described in the above steps 101-104. Specifically, when the switch is turned on, the controller can execute the operations described in the above steps 101-104, that is, turn on the function of mask splitting transmission; when the switch is turned off, the controller directly transmits the write data channel signal and the write address channel signal output by the AXI master device to the AXI slave device without any processing in the middle. In this case, the input of the AXI slave device is the output of the AXI master device.

[0095] As an example, Figure 2 is a schematic diagram of an operation principle of the write channel data transmission control method of the AXI protocol provided by the embodiment of the present application. Figure 2A controller is added between the AXI master device and the AXI slave device. The controller has a function switch. When the switch is turned off, the write data channel signal and the write address channel signal output by the AXI master device are directly transmitted to the AXI slave device without any processing in between. When the switch is turned on, the write data channel signal output by the AXI master device will be transmitted to the write data channel signal cache module of the controller for caching, and the write address channel signal output by the AXI master device will be transmitted to the write address channel signal cache module of the controller for caching. The controller's discontinuous mask automatic identification and splitting module can detect the discontinuous mask of the write mask signal in the write data channel signal, and split the discontinuous mask into multiple continuous masks, so that the transmitted write mask signal does not contain a discontinuous mask, so that the data transmission of the write channel complies with the PCIe rules; in addition, during the mask splitting combination and write data transmission process, the controller's write address signal and write length signal recalculation module will recalculate the corresponding write address signal and write length signal, and read the updated write address channel signal through the write address channel signal cache module, combine the data into a new AXI write data request, and send it to the AXI slave device. Through this setting, the system can be used for AXI write data transmission in accordance with PCIe rules, and compatibility and stability are greatly improved.

[0096] In the technical solution of the embodiment of the present application, the write data channel signal and the write address channel signal to be transmitted are obtained. If a discontinuous mask is detected in the write mask signal in the write data channel signal, the discontinuous mask is split into multiple continuous masks, and the multiple continuous masks and the discontinuous mask correspond to the same write data; then, the write data corresponding to each of the multiple continuous masks is transmitted in a burst write manner, which is equivalent to splitting the write data corresponding to the discontinuous mask into multiple write data corresponding to each of the multiple continuous masks for transmission, so that the transmitted write mask signal does not contain the discontinuous mask, so that the data transmission of the write channel complies with the rules of PCIe, thereby avoiding the problem of data transmission errors and improving the compatibility and stability of the system. In addition, considering that the write data of the AXI protocol is transmitted in a burst write manner, that is, a single burst write contains multiple write data, if the write data corresponding to the discontinuous mask is split into multiple write data corresponding to each of the multiple continuous masks for transmission, the number of write data contained in the single burst write may change, so it is necessary to adjust the write length signal in the write address channel signal accordingly. Moreover, when the burst transfer type selects address incremental burst transfer, the multiple write data corresponding to the multiple continuous masks will be written to different incremental addresses by default. However, these write data correspond to the same discontinuous mask and need to be written to the same address. Therefore, the write address signal in the write address channel signal also needs to be adjusted accordingly.

[0097] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0098] The above mainly describes a write channel data transmission control method of the AXI protocol. The following will describe a write channel data transmission control device of the AXI protocol.

[0099] See also Figure 3 In the embodiment of the present application, an embodiment of a write channel data transmission control device of an AXI protocol includes:

[0100] The signal acquisition module 301 is used to acquire the write data channel signal and the write address channel signal to be transmitted;

[0101] The mask splitting module 302 is used for splitting the discontinuous mask into a plurality of continuous masks if a discontinuous mask appears in the write mask signal in the write data channel signal, wherein the plurality of continuous masks and the discontinuous mask all correspond to the same write data;

[0102] The data transmission module 303 is used to transmit the write data corresponding to each of the plurality of consecutive masks through burst write transmission;

[0103] The signal adjustment module 304 is configured to adjust the write address signal and the write length signal in the write address channel signal if the burst transfer type signal in the write address channel signal indicates address incremental burst transfer.

[0104] In one implementation of the embodiment of the present application, the write mask signal is 16 bits; the write channel data transmission control device of the AXI protocol further includes:

[0105] A first continuous mask judgment module, used for determining that any mask in the write mask signal is not a discontinuous mask if there is one non-zero mask or two non-zero masks among the four hexadecimal masks corresponding to the mask;

[0106] The second continuous mask judgment module is used to determine that any mask is not a discontinuous mask if there are 3 non-0 masks or 4 non-0 masks in the 4 hexadecimal masks corresponding to any mask, and there is no 0 between any two 1s in the 16 bits of any mask.

[0107] In one implementation of the embodiment of the present application, the mask splitting module includes:

[0108] The mask splitting unit is used to split the discontinuous mask into a first mask and a second mask; wherein the first half of the first mask is the first half of the discontinuous mask, and the second half of the first mask is 0; the second half of the second mask is the second half of the discontinuous mask, and the first half of the second mask is 0.

[0109] In one implementation of the embodiment of the present application, the data transmission module includes:

[0110] A first data transmission unit, configured to transmit write data corresponding to each of the plurality of continuous masks through the same burst write transmission if the masks obtained by combining the plurality of continuous masks are continuous;

[0111] The second data transmission unit is used for transmitting the write data corresponding to each of the plurality of continuous masks through different burst write transmissions if the mask obtained by combining the plurality of continuous masks is not continuous.

[0112] In one implementation of the embodiment of the present application, the signal acquisition module includes:

[0113] A write data signal buffer unit, used for buffering the write data channel signal into a first FIFO buffer; the write enable of the first FIFO buffer is controlled by the write data valid signal, and the read enable is controlled by the transmission of the write data;

[0114] The write address signal buffer unit is used to buffer the write address channel signal to the second FIFO buffer; the write enable of the second FIFO buffer is controlled by the write address valid signal, and the read enable is controlled by the burst write transmission.

[0115] In one implementation of the embodiment of the present application, the signal adjustment module includes:

[0116] A first counting unit, used to set and start a first counter, the count value of the first counter is increased by 1 when a write data is transmitted, and is reset after a burst write is transmitted;

[0117] A second counting unit, used to set and start a second counter, the count value of the second counter is increased by 1 when a burst write is transmitted, and is reset after a burst write is transmitted;

[0118] The write length signal adjustment unit is used to adjust the write length signal according to the difference between the count value of the first counter and the count value of the second counter.

[0119] In one implementation of the embodiment of the present application, the signal adjustment module includes:

[0120] a third counting unit, used to set and start a third counter, wherein the count value of the third counter is increased by 2 when a write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted;

[0121] a fourth counting unit, used to set and start a fourth counter, wherein the count value of the fourth counter is increased by 2 when a target write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a target write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted; wherein the target write data refers to non-last write data in a burst write;

[0122] The write address signal adjustment unit is used to adjust the write address signal according to the difference between the count value of the third counter and the count value of the fourth counter.

[0123] In one implementation of the embodiment of the present application, the write channel data transmission control device of the AXI protocol further includes:

[0124] The write length adjustment module is used to adjust the write length signal in the write address channel signal if the burst transfer type signal in the write address channel signal indicates a fixed address burst transfer.

[0125] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the write channel data transmission control method of the AXI protocol as represented by any of the above embodiments is implemented.

[0126] An embodiment of the present application further provides a computer program product. When the computer program product is run on a controller, the controller executes the write channel data transmission control method of the AXI protocol as represented by any of the above embodiments.

[0127] Figure 4 is a schematic diagram of a controller provided in an embodiment of the present application. Figure 4 As shown, the controller 4 of this embodiment includes: a processor 40, a memory 41, and a computer program 42 stored in the memory 41 and executable on the processor 40. When the processor 40 executes the computer program 42, the steps in the embodiments of the above-mentioned write channel data transmission control method of the AXI protocol are implemented, for example Figure 1 Alternatively, when the processor 40 executes the computer program 42, the functions of each module / unit in the above-mentioned device embodiments are realized, for example, Figure 3 Functions of modules 301 to 304 are shown.

[0128] The computer program 42 may be divided into one or more modules / units, which are stored in the memory 41 and executed by the processor 40 to complete the present application. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program 42 in the controller 4.

[0129] The processor 40 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0130] The memory 41 may be an internal storage unit of the controller 4, such as a hard disk or memory of the controller 4. The memory 41 may also be an external storage device of the controller 4, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the controller 4. Further, the memory 41 may also include both an internal storage unit of the controller 4 and an external storage device. The memory 41 is used to store the computer program and other programs and data required by the controller. The memory 41 may also be used to temporarily store data that has been output or is to be output.

[0131] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0132] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0133] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0134] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0135] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0136] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0137] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0138] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0139] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A write channel data transmission control method of AXI protocol, characterized in that: include: Obtaining a write data channel signal and a write address channel signal to be transmitted; If a discontinuous mask appears in the write mask signal in the write data channel signal, split the discontinuous mask into a plurality of continuous masks, wherein the plurality of continuous masks and the discontinuous mask correspond to the same write data; Transmitting the write data corresponding to each of the plurality of consecutive masks through burst write transmission; If the burst transfer type signal in the write address channel signal indicates address incremental burst transfer, the write address signal and the write length signal in the write address channel signal are adjusted.

2. The method according to claim 1, characterized in that The write mask signal is 16 bits; whether any mask in the write mask signal is a discontinuous mask is determined by: If the four hexadecimal masks corresponding to any of the masks have one non-zero mask or two non-zero masks, it is determined that any of the masks is not a discontinuous mask; If there are 3 non-0 masks or 4 non-0 masks among the 4 hexadecimal masks corresponding to any mask, and there is no 0 between any two 1s in the 16 bits of any mask, it is determined that any mask is not a discontinuous mask.

3. The method according to claim 2, characterized in that The step of splitting the discontinuous mask into a plurality of continuous masks comprises: The discontinuous mask is split into a first mask and a second mask; wherein the first half of the first mask is the first half of the discontinuous mask, and the second half of the first mask is 0; the second half of the second mask is the second half of the discontinuous mask, and the first half of the second mask is 0.

4. The method according to claim 1, characterized in that The step of transmitting the write data corresponding to each of the plurality of consecutive masks through burst write transmission includes: If the masks obtained by combining the multiple continuous masks are continuous, the write data corresponding to each of the multiple continuous masks are transmitted through the same burst write transmission; If the masks obtained by combining the multiple continuous masks are not continuous, the write data corresponding to each of the multiple continuous masks are transmitted through different burst write transmissions.

5. The method according to claim 1, characterized in that The step of obtaining a write data channel signal and a write address channel signal to be transmitted includes: Buffering the write data channel signal into a first FIFO buffer; the write enable of the first FIFO buffer is controlled by the write data valid signal, and the read enable is controlled by the transmission of the write data; The write address channel signal is cached in a second FIFO buffer; the write enable of the second FIFO buffer is controlled by a write address valid signal, and the read enable is controlled by a burst write transmission.

6. The method according to claim 1, characterized in that The step of adjusting the write address signal and the write length signal in the write address channel signal comprises: Setting and starting a first counter, wherein a count value of the first counter is increased by 1 when a write data is transmitted, and is reset after a burst write is transmitted; Setting and starting a second counter, wherein a count value of the second counter is incremented by 1 when a burst write is transmitted, and is reset after a burst write is transmitted; The write length signal is adjusted according to a difference between a count value of the first counter and a count value of the second counter.

7. The method according to claim 1, characterized in that The step of adjusting the write address signal and the write length signal in the write address channel signal comprises: Setting and starting a third counter, wherein the count value of the third counter is increased by 2 when a write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted; A fourth counter is set and started, wherein the count value of the fourth counter is increased by 2 when a target write data corresponding to an unsplit mask is transmitted, and is increased by 1 when a target write data corresponding to a split mask is transmitted, and is reset after the last burst write of a write data request is transmitted; wherein the target write data refers to non-last write data in a burst write; The write address signal is adjusted according to the difference between the count value of the third counter and the count value of the fourth counter.

8. The method according to any one of claims 1 to 7, characterized in that Also includes: If the burst transfer type signal in the write address channel signal indicates a fixed-address burst transfer, the write length signal in the write address channel signal is adjusted.

9. A controller comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the write channel data transmission control method of the AXI protocol according to any one of claims 1 to 8 is implemented.

10. A computer program product, characterized in that When the computer program product runs on a controller, the controller is enabled to execute the write channel data transmission control method of the AXI protocol according to any one of claims 1 to 8.

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