Multi-core system chip inter-core communication method and system

Abstract

The invention relates to a multi-core system chip inter-core communication method and system.The method comprises the steps that an inter-core communication module is divided into an A module and a B module, the A module and the B module are each provided with a bus interface, and the inter-core communication module is instantiated into a sub-module A and a sub-module B; and performing grouping management on hardware channels in the inter-core communication module by using a grouping control register, and setting the hardware channels contained in each group and access objects of the hardware channels through grouping logic. According to the invention, the number of inter-core communication modules can be significantly reduced, and the complexity of system integration is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent chips, and in particular relates to a multi-core system chip inter-core communication method and system. Background Art

[0002] As integrated circuit technology develops to the deep submicron stage, the research on processor architecture is moving towards multi-core and many-core. Whether it is to improve processor performance or consider the energy consumption factor of unit computing performance, multi-core and many-core architectures are currently hot research directions. There are a wide variety of organizational levels in on-chip communication design. For example, in a multi-core system based on shared cache, there are cross buses to connect the local cache and shared cache of each processing core, and there are also on-chip networks to connect; in a multi-core system based on a shared bus, the bus architecture can be divided into ordinary single bus, multi-level bus, ring bus, cross bus and on-chip network, etc. These enrich the design options of on-chip communication on the one hand, and also increase the freedom and complexity of on-chip communication design. One inter-core communication method is to have an inter-core communication module between the two cores, set up two sets of bus interfaces, and hang on the same or different buses. The inter-core communication module consists of two MUXs and multiple hardware channels. The hardware channel is used to receive write data from other cores, and the MUX is used to select which hardware channel to access. A single core can only access one hardware channel at a time. This method can realize mutual communication between two cores, but when the number of communicating cores increases, the number of corresponding inter-core communication modules must be increased. For example, if there is another core 2 on the system bus, the communication between core 0 and core 1 is completed by inter-core communication module 0, the communication between core 2 and core 1 is completed by inter-core communication module 1, and the communication between core 0 and core 2 is completed by inter-core communication module 2. If there are N cores in a multi-core system, a total of N*(N-1) / 2 inter-core communication modules are required, which is too complicated for system integration.

[0003] In addition, as the price of integrated circuits decreases, integrated circuit design begins to sink to the application layer. Currently, applications such as communications, machine vision, assisted driving, medical / bioimaging, avionics, big data analysis, and the Internet of Things require high-performance digital signal processing, intensive data computing capabilities, and strong graphics and image processing and display capabilities. In addition, the system and algorithm must be flexible and adaptive. After the product is manufactured, the chips in the system must be able to provide certain modification, optimization, and reconstruction capabilities to meet both hardware overhead requirements and application scenario requirements. In addition, the diversity of application scenarios also brings security issues. Malicious attackers may implant unauthorized software and code into bus devices through the debug port of the application CPU core, which will reduce the security of the bus devices.

[0004] As the number of cores continues to increase, the ways of building communication structures between cores vary greatly, and application scenarios become increasingly complex, how to meet the communication needs between cores without increasing or reducing hardware overhead is a technical problem to be solved. In fact, the communication needs between cores are largely related to system scenarios and application scenarios. A fixed communication mechanism is difficult to meet the communication needs between cores in a multi-core system, and it is also difficult to optimize the communication problem. Based on the above problems, the present invention starts from system scenarios and application scenarios, allocates and manages inter-core communication control resources according to the different needs of system scenarios and application scenarios, discovers scenario changes and characteristics under different scenarios to perform specific communication resource configuration; combines the underlying hardware resource configuration and scenarios to reduce the number of inter-core communication modules, reduce the complexity of system integration, and thereby reduce chip power consumption and area. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present invention proposes a multi-core system chip inter-core communication method and system, the system comprising: A system bus, two or more cores and an inter-core communication module; the inter-core communication module is used to control the communication between the two or more cores; the inter-core communication module is divided into two modules AB, the two modules AB are connected to the bus through a set of bus interfaces respectively, and each set of bus interfaces is used to connect one or more cores; each set of bus interfaces belongs to the same or different buses; the one or more cores communicate data on the chip through the bus interface; wherein: when the two sets of bus interfaces belong to different buses, the cores connected to different sets of bus interfaces communicate across the bus, and when the two sets of bus interfaces belong to the same bus, the cores can communicate across the cores based on the same bus; The AB modules each include a set of receiving ends and transmitting ends, and a MUX; the MUX is connected to the bus interface to communicate with the bus; the receiving end in the A module includes one or more channels, and the one or more channels are shared with the transmitting end corresponding to the B module, the receiving end in the A module is connected to the A module MUX to send data to the bus, and the transmitting end corresponding to the B module is connected to the B module MUX to receive data from the bus; the settings of the other set of receiving ends and transmitting ends are similar; The group control module is used to divide the channels in the AB module into one or more groups based on the communication relationship between the receiving core and the sending core, and perform group configuration, channel enable configuration and intra-group channel configuration to identify the correspondence between the groups and the cores based on the communication relationship, so that the sending core writes the sending data into the channel corresponding to the group after the channel is enabled, and generates a core interrupt for the receiving core with which the communication relationship occurs, so that the receiving core reads data through the corresponding channel after the interrupt occurs.

[0006] Furthermore, when the corresponding relationship between the sending core and the receiving core does not match the configuration information in the packet control module, an error is returned to the sending core to avoid possible communication anomalies.

[0007] Furthermore, the MUX is implemented using configurable logic.

[0008] Furthermore, the multi-core system chip is provided with two or more cores.

[0009] Furthermore, the system also includes a scenario configuration module, which is used to determine group configuration information, channel enable configuration information and intra-group channel configuration information according to application scenarios and / or system scenarios, and send the configuration information to the group control module; the group control module performs configuration or reconfiguration when the configuration conditions are met.

[0010] Further, the group control module includes a configuration module and a configuration lock module; the configuration module is used to perform group configuration, channel enable configuration and intra-group channel configuration based on configuration information; the group configuration is used to perform group configuration on the cores, indicating the cores included in each group; the channel enable configuration is used to indicate the channels included in each group; the intra-group channel configuration is used to indicate the correspondence between the channels in the group and the accessible cores; the configuration module uses the configuration register to save the above configuration information and perform configuration; The group control module performs core interruption based on the communication request and the channel identifier; specifically: when the A module performs a write operation, it writes into the corresponding channel in response to the write operation; the group control module and the B module generate an interruption for the receiving core for the corresponding group containing the channel, and send the interruption to the receiving core through the MUX; after the receiving core responds to the interruption, it reads data from the group and its channel corresponding to the B module and the receiving core; similarly, when the core to which the B module belongs wants to write data, it writes the data into the channel corresponding to the group in response to the write operation request of the core to which the B module belongs, and the group control module and the A module generate an interruption for the receiving core for the corresponding group in the channel, and send the interruption to the receiving core through the MUX; after the receiving core responds to the interruption, it obtains data from the A module channel.

[0011] Furthermore, the configuration condition is when the chip is initialized, the application scenario and / or the system scenario is initialized or changes.

[0012] A multi-core system chip inter-core communication control digital logic, the multi-core system chip inter-core communication control digital logic is used to implement the multi-core system chip inter-core communication system.

[0013] A multi-core system chip inter-core communication control chip, the multi-core system chip inter-core communication control chip is used to implement the multi-core system chip inter-core communication system mentioned above.

[0014] A multi-core system chip inter-core communication control circuit is characterized in that the multi-core system chip inter-core communication control circuit is used to implement the above-mentioned multi-core system chip inter-core communication system.

[0015] The beneficial effects of the present invention include: (1) Starting from the system scenario and application scenario, the inter-core communication control resources are allocated and managed according to the different requirements of the system scenario and application scenario, and the scene changes and characteristics of different scenarios are discovered to perform specific communication resource configuration; it can be compatible with system scenario adaptation and application scenario adaptation, and can combine the underlying hardware resource configuration and scenario to reduce the number of inter-core communication modules, reduce the complexity of system integration, and thus reduce chip power consumption and area.

[0016] (2) It can simultaneously serve cross-bus communication and cross-core communication based on the same bus. For both communication modes, it can significantly reduce the number of inter-core communication modules, thereby reducing the complexity of system integration. By managing the read and write access of the inter-core communication modules through group control, the read and write operation level can prevent the inter-core communication modules from being misoperated, thereby improving the security of inter-core communication in multi-core system chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application, but do not constitute an improper limitation of the present invention. In the drawings: Figure 1 This is a schematic diagram of the cross-bus communication control system of the multi-core system chip provided by the present invention.

[0018] Figure 2 A schematic diagram of a cross-core communication control system based on the same bus of a multi-core system chip provided by the present invention.

[0019] Figure 3 A control flow logic diagram of the multi-core system chip inter-core communication method provided by the present invention. DETAILED DESCRIPTION

[0020] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the illustrative embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0021] The present invention proposes a multi-core system chip inter-core communication system, as shown in the attached Figure 1As shown, the system includes: a system bus, two or more cores and an inter-core communication module; the inter-core communication module is used to control the communication between the two or more cores; the inter-core communication module is divided into two modules AB, and the two modules AB are respectively connected to the bus through a set of bus interfaces, and each set of bus interfaces is used to connect one or more cores; each set of bus interfaces belongs to the same or different buses; the one or more cores communicate data on the chip through the bus interface; wherein: when the two sets of bus interfaces belong to different buses, the cores connected to different sets of bus interfaces communicate across the bus, and when the two sets of bus interfaces belong to the same bus, the cores can communicate across the cores based on the same bus; The AB modules each include a group of receiving ends and transmitting ends, and a MUX; the MUX is connected to the bus interface to communicate with the bus; the receiving end in the A module includes one or more channels, the one or more channels are shared with the transmitting end corresponding to the B module, the receiving end in the A module is connected to the A module MUX to send data to the bus, and the transmitting end corresponding to the B module is connected to the B module MUX to receive data from the bus; the settings of another group of receiving ends and transmitting ends are similar, the receiving end in the B module includes one or more channels, the one or more channels are shared with the transmitting end corresponding to the A module, the receiving end in the B module is connected to the B module MUX to send data to the bus, and the transmitting end corresponding to the A module is connected to the A module MUX to receive data from the bus; that is, the channel allocated to the group is shared by the transmitting end and the receiving end group, and the channel allocated to the core is shared by the sending core and the receiving core based on the communication relationship; The group control module is used to divide the channels in the AB module into one or more groups based on the communication relationship between the receiving core and the sending core, and perform group configuration, channel enable configuration and intra-group channel configuration to identify the corresponding relationship between the group and the core based on the communication relationship, so that the sending core writes the sending data into the channel corresponding to the group after the channel is enabled, and generates a core interrupt for the receiving core in the communication relationship, so that the receiving core reads the data through the corresponding channel after the interrupt occurs; when the corresponding relationship indicated by the configuration information in the group control module is not consistent with the sending core and the receiving core, an error will be returned to the sending core to avoid possible communication abnormalities; The group control module includes a configuration module and a configuration lock module; the configuration module is used to perform group configuration, channel enable configuration and intra-group channel configuration based on configuration information; the group configuration is used to group the cores and indicate the cores included in each group; the channel enable configuration is used to indicate the channels included in each group; the intra-group channel configuration is used to indicate the correspondence between the channels in the group and the accessible cores; the configuration module uses the configuration register to save the above configuration information and perform configuration; Further: when performing configuration, the configuration module configures the MUX of the A module and the MUX of the B module based on the intra-group channel configuration information to establish communication links between the channels and cores in the A module and the B module respectively; Preferably, the MUX is implemented using configurable logic, such as FPGA; The configuration lock module is used to lock the configuration information stored in the configuration register after the configuration is completed to prevent subsequent accidental modification; As attached Figure 1 As shown, there are 4 cores on the chip, cores 0 to 3; cores 0 to 2 are set in module A, and core 3 is set in module B. The 3 cores on module A need to communicate with 1 core on module B through the inter-core communication module; 6 pairs of channels are set on the inter-core communication module; among them: the channels of module A are divided into 3 groups through the intra-group channel configuration information, and each group is allocated 2 channels to be accessed by the specified core; the channels of module B can be ungrouped or divided into 1 group, and accessed by core 3; Figure 1 The A module channels are divided into 3 groups, specifically: channels 0-1 in the A and B modules establish data communication between cores 0 and 3; channels 2-3 in the A and B modules establish data communication between cores 1 and 3; channels 4-5 in the A and B modules establish data communication between cores 2 and 3; when cores 0, 1, and 2 want to communicate with core 3, for core 0, it is indicated that it belongs to group 0 based on the group configuration information, and further indicates channels 0 and 1 contained in group 0 based on the channel enable configuration information. Therefore, the data communication between core 0 and core 3 will be carried out through channels 0 and 1. Core 0 can only access B when it needs to send data. The module's channel 0 / 1, that is, the A module's transmitting end channel 0 / 1, is mapped to the B module's receiving end channel 0 / 1, and the two are set in association; similarly, core 1 can only access channels 2 / 3 when it needs to send data, and core 2 can only access channels 4 / 5 when it needs to send data. The interrupt control of the core to which the A module belongs is performed based on the grouping information, and the write operation data is written to the corresponding channel; when the receiving core reads data, the grouping control module generates 3 group interrupts, which are sent to cores 0, 1, and 2 respectively, and the B module interrupt is given to core 3; it can be understood that the receiving end of the A module and the sending end of the B module appear in pairs and share channels; The group control module performs core interruption based on the communication request and channel identification; specifically: when module A performs a write operation, it writes into the corresponding channel in response to the write operation; the group control module and module B generate an interruption for the receiving core for the corresponding group containing the channel, and send the interruption to the receiving core through MUX; after the receiving core responds to the interruption, it reads data from the group and its channel corresponding to module B and the receiving core; similarly, when the core to which module B belongs wants to write data, it writes the data into the channel corresponding to the group in response to the write operation request of the core to which module B belongs, and the group control module and module A generate an interruption for the receiving core for the corresponding group in the channel, and send the interruption to the receiving core through MUX; after the receiving core responds to the interruption, it takes data from the channel of module A; then for the attached Figure 1 For example, when core 3 wants to communicate with cores 0, 1, and 2, it can freely access all channels of module B, because all channels are divided into group 1; writing data in module B will generate a receive interrupt in module A. After core 0 responds to the interrupt, it fetches data from channels 0 and 1 of module A. After core 1 responds to the interrupt, it fetches data from channels 2 and 3 of module A. After core 2 responds to the interrupt, it fetches data from channels 4 and 5 of module A. Preferably: when performing bus-based cross-core communication, a group control module is deployed for module A and module B respectively; Preferably: when performing bus-based cross-core communication, deploy the same group control module for module A and module B, and control is performed by different parts of the group control module; Preferably: the system further comprises a scenario configuration module, the scenario configuration module is used to determine group configuration information, channel enable configuration information and intra-group channel configuration information according to the application scenario and / or system scenario, and send the configuration information to the group control module; the group control module performs configuration or reconfiguration when the configuration conditions are met; further: the scenario configuration module first determines the AB module channel configuration information, which is used to indicate the number of channels to which the AB module belongs; accordingly, the configuration module first divides the channels into A modules or B modules based on the AB module channel configuration information; The scene configuration module first determines the AB module channel configuration information; specifically: Step SA1: Determine the number of cores and their bus access status based on system scenario information; Specifically: When performing cross-bus communication, determine based on system scenario information Each core is connected to bus 0. Each core is connected to the first bus; the two modules AB of the inter-core communication module serve the 0th bus and the 1st bus respectively; when performing cross-core communication based on the same bus, the system scenario information is used to determine The cores access the 0th bus, where: CA cores use the 0th interface to access the bus, and Each core uses the first interface to access the bus; the two modules AB of the inter-core communication module serve the same bus through the 0th interface and the 1st interface respectively; Step SA2: Analyze the communication data between cores in the application scenario based on the application scenario data to obtain communication relationship data and , Used to indicate the core to which module A belongs Send data to the core to which module B belongs The amount of data (or data frequency, number of accesses, etc.); Used to indicate the core to which module B belongs Send data to the core to which module A belongs The amount of data (or data frequency, number of accesses, etc.); Preferably: the application scenario data is obtained based on historical monitoring data or real-time monitoring data; Preferably: a monitoring module is set in the operating system to obtain the historical monitoring data or the real-time monitoring data; Obviously: when communicating across the bus, the core and nuclear are different; when performing cross-core communication based on the same bus, the core and nuclear are the same or different; they need to be divided into module A or module B in advance; for any core ,like and = 0, then only the core Divided into the cores to which module A belongs; for any core ,like and = 0, then only the core The cores are divided into the cores belonging to the B module; the remaining cores are set as the cores belonging to the A module and the cores belonging to the B module; where: is the set of all kernels; is the communication relationship data threshold; for example, it is set to 0 or a smaller value; Step SA3: Normalize the communication relationship data and set the communication relationship data ; ; Step SA4: Divide the channels of modules A and B, and set the number of channels of module A to , let the number of channels of module B be N-NA; wherein: N is the total number of channels in the inter-core communication module; the channels belonging to the AB module are divided based on the number of channels of the A module and the number of channels of the B module, and the division information is used as the determined AB module channel configuration information; Preferably: dividing the channel into module A or module B based on the channel identification; The scenario configuration module is used to determine group configuration information, channel enable configuration information and intra-group channel configuration information according to application scenarios and system scenarios, and specifically includes the following steps: Step SB1: Determine the communication relationship data based on the application scenario, and assign the A module to the channels and B modules belong to The channels are allocated to different cores in module A and module B. Specifically, the number of channels of core a in module A is calculated using the following formulas (1) and (2): ; Calculate the number of channels of core b in module B based on the following formulas (3) and (4): ; Allocation based on channel number and channel ID; where: and They are the core sets of module A and module B respectively; (1); (2); (3); (4); Step SB2: Determine the group configuration information, channel enable configuration information and intra-group channel configuration information; specifically: for each receiving core in module A Assign a group and set the group ID ; and the communication relationship data between module B and the receiving core is greater than 0 ( )'s sending core is also assigned to this group , the above group allocation information is used as group configuration information; for each receiving core in module A For example, each group Contains the core of module A All the channels that belong to it; Preferably: when the sending core in module B whose communication relationship data with the receiving core is greater than 0 is allocated multiple groups When multiple groups are connected, they are grouped together or the multiple groups are retained; this is related to the management method of configuration information and does not affect the interrupt mode; For the sending core in module B whose communication relationship data with the receiving core is greater than 0 Further determine the channel enable configuration information; based on The channel allocated to the receiving core a in module A is allocated to the sending core in module B whose communication relationship data with the receiving core a is greater than 0 in proportion to the value. , and use the channel reassignment information as channel enable configuration information so that the sending core Towards the core When writing data, you can group The assigned channel is enabled; at the same time, the sending core The identifier is associated and saved as the channel configuration information within the group; the configuration information includes group configuration information, channel enable configuration information and channel configuration information within the group, which is expressed as (core identifier of module A, group identifier, channel identifier) ​​(core identifier of module B, group identifier, channel identifier); for example: the configuration information is (0,0,0 / 1 / 2 / 3) (1,0,0 / 1), indicating that core 0 to which module A belongs is divided into group 0 as the receiving end and has channels 0 / 1 / 2 / 3. At this time, core 1 to which module B belongs is the sending end, and the group identifier is 0. When it initiates writing data, it can enable channels 0 / 1; and when core 2 to which module B belongs wants to write data to channel 0 / 1, an error message will be returned to core 2 to which module B belongs; when core 1 to which module B belongs wants to write data to channel 0 / 1, it will not; at this point, the construction of the sending end and the receiving end of sending data from module A to module B is completed; all groups of module A constitute the sending end of module A, and all groups of module B constitute the receiving end of module B; The determination of the grouping configuration information, channel enabling configuration information and intra-group channel configuration information of the cores in module B, as well as the determination of the relevant configuration information of the cross-core communication mode based on the same bus, is also similar and will not be repeated here; through the grouping setting, when performing data communication, the use of channels and communication timing can be controlled for the sending core and the receiving core based on the group number, and the core interrupt control can be performed; Preferably: when there is a core whose number of channels is 0 or less than the channel number threshold, group merging is performed, and the core and the core with the second smallest number of channels are grouped into the same group, so that the two merged cores can share the channel. At this time, it is necessary to add identification logic in the group control module to identify the sending core or the receiving core, or to set the receiving identification logic in the communication module of the sending core or the receiving core to identify whether the communication data is received correctly; Preferably: the configuration condition is when the chip is initialized, the application scenario and / or the system scenario is initialized or changes; for example: when the number of cores connected to the system bus changes, the system scenario will change accordingly, and the grouping of module A or module B needs to be reconfigured based on the bus to which it is connected; for example: if the number of cores connected to the bus belonging to module B increases, the number of module B groups needs to be increased, and channels 0, 2, and 4 can be divided into group 0 for access by core 3, and channels 1, 3, and 5 can be divided into group 1 for access by core 4; when the application scenario changes, the grouping can be re-divided according to the read and write characteristics in the application scenario, so that the corresponding relationship between the group and the core changes; Preferably: in the inter-core communication module, the grouping strategies of module A and module B are the same or different; The working logic of cross-bus communication and cross-core communication based on the same bus is similar. The difference is that when cross-bus communication is performed, the cores of the two modules AB are connected to different buses and use different sets of bus interfaces to communicate respectively; when cross-core communication is performed based on the same bus, the cores of the two modules AB are connected to the same bus and use different sets of bus interfaces to communicate respectively; in addition, the logic of the scenario configuration module will be more complicated. The scenario configuration module needs to additionally group the cores according to the application scenario, so that the cores belong to module A or module B respectively, and determine the configuration information based on the correspondence between module A and module B and the core; as shown in the attached figure. Figure 2 As shown in the figure, there are 3 cores on the chip, cores 0~2; cores 0~1 are set in module A, and cores 1 and 2 are set in module B. The 2 cores on module A need to communicate with the 2 cores on module B through the inter-core communication module; 6 pairs of channels are set on the inter-core communication module; among them: the A module channels are divided into 2 groups through group configuration information, group 0 is allocated 4 channels to be accessed by core 0, and group 1 is allocated 2 channels to be accessed by core 1; the B module channels are divided into 2 groups, group 0 is allocated 2 channels to be accessed by core 1, and group 1 is allocated 4 channels to be accessed by core 2; Appendix Figure 2 The B module channels are divided into 2 groups, specifically: data communication is established between core 0 and core 1-2 for channels 0-3 in modules A and B respectively; data communication is established between core 1 and core 2 for channels 4-5 in modules A and B; the group control module generates 2 group interrupts for module A, which are sent to cores 0 and 1 respectively; the group control module generates 2 group interrupts for module B, which are sent to cores 1 and 2 respectively; Preferably: in cross-core communication based on the same bus, the same core can belong to module A or module B; The present invention provides a multi-core system chip inter-core communication method and system, wherein the control flow logic of the method comprises the following steps: Step S0: The scenario configuration module is used to determine configuration information including group configuration information, channel enable configuration information and intra-group channel configuration information according to the application scenario and the system scenario; Preferably: the scene configuration module writes the configuration information into a memory of the configuration module, and the memory is used to store the configuration information; Step S1: The configuration module in the grouping control module divides all available channels based on the above configuration information; Step S2: Determine whether communication has started; specifically: determine whether a sending core has initiated a communication request; if yes, determine that communication has started; Preferably: the communication request is sent to the inter-core communication module, and the grouping control module of the inter-core communication module performs core interruption based on the grouping; further: the interruption is an interruption to the sending core and / or the receiving core; Step S3: If the communication starts, the sending core queries the channel status, and writes the data to the sending end when the corresponding channel is idle; specifically, the sending core queries the channel status through the packet control logic; here, the packet control logic queries the channel status of the channel that is corresponding to the sending core and accessible; when the corresponding channel is idle, writing the data to the sending end is actually writing the data to the channel corresponding to the receiving core in the corresponding receiving end; Step S4: Determine whether the packets match; if not, report an error and return to step S2; if they match, proceed to the next step; during the writing process, determine whether the packet written by the sending core is correct, that is, whether the written channel is correct. If correct, writing is allowed, otherwise an error is reported; Step S5: the data is written to the receiving end corresponding to the inter-core communication module, the channel state becomes non-idle, the receiving end flag is set, and a receiving interrupt is generated to the receiving core; writing to the corresponding receiving end here indicates that the writing is completed and the channel state is changed. The management of the channel state can be performed by the channel itself, or a separate channel management module is set by the inter-core communication module to manage it; Preferably: a receiving flag is set to indicate that the receiving core can receive data; Step S6: Determine whether the interrupt is responded to, if so, proceed to the next step; initiate an interrupt to notify the receiving core to enter the interrupt state to read the data in the channel, and the receiving core responds to the packet control if it can be received; Step S7: reading data from the corresponding hardware channel; Preferably: clear the corresponding receiving flag after reading is completed; Step S8: Communication ends; Preferably: the AB modules can use different grouping strategies; The present invention proposes a multi-core system chip inter-core communication method and system, as shown in the attached Figure 3 As shown, the method comprises the following steps: Step S1: first divide the inter-core communication module into two modules AB, each of which has a set of bus interfaces, and instantiate the inter-core communication module into two sub-modules A and sub-module B. Sub-module A and sub-module B are combined together to form a complete inter-core communication module; Step S2: Use the group control register to manage the hardware channels inside the inter-core communication module in groups, and use the group logic to set the hardware channels and access objects contained in each group.

[0022] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of a programming language, including an assembled or interpreted language, a declarative or procedural language, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0023] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0024] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0025] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0026] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A multi-core system chip inter-core communication system, characterized in that: The system comprises: a system bus, two or more cores and an inter-core communication module; the inter-core communication module is used to control the communication between the two or more cores; the inter-core communication module is divided into two modules AB, the two modules AB are connected to the bus through a set of bus interfaces respectively, and each set of bus interfaces is used to connect one or more cores; each set of bus interfaces belongs to the same or different buses; the one or more cores communicate data on the chip through the bus interface; wherein: when the two sets of bus interfaces belong to different buses, the cores connected to different sets of bus interfaces communicate across the bus, and when the two sets of bus interfaces belong to the same bus, the cores can communicate across the cores based on the same bus; The AB modules each include a set of receiving ends and transmitting ends, and a MUX; the MUX is connected to the bus interface to communicate with the bus; the receiving end in the A module includes one or more channels, and the one or more channels are shared with the transmitting end corresponding to the B module, the receiving end in the A module is connected to the A module MUX to send data to the bus, and the transmitting end corresponding to the B module is connected to the B module MUX to receive data from the bus; the settings of the other set of receiving ends and transmitting ends are similar; The group control module is used to divide the channels in the AB module into one or more groups based on the communication relationship between the receiving core and the sending core, and perform group configuration, channel enable configuration and intra-group channel configuration to identify the correspondence between the groups and the cores based on the communication relationship, so that the sending core writes the sending data into the channel corresponding to the group after the channel is enabled, and generates a core interrupt for the receiving core with which the communication relationship occurs, so that the receiving core reads data through the corresponding channel after the interrupt occurs.

2. The multi-core system chip inter-core communication system according to claim 1, characterized in that: When the corresponding relationship between the sending core and the receiving core does not match the configuration information in the packet control module, an error is returned to the sending core to avoid possible communication anomalies.

3. The multi-core system chip inter-core communication system according to claim 2, characterized in that: The MUX is implemented using configurable logic.

4. The multi-core system chip inter-core communication system according to claim 3, characterized in that: The multi-core system chip is provided with two or more cores.

5. The multi-core system chip inter-core communication system according to claim 4, characterized in that: The system also includes a scenario configuration module, which is used to determine group configuration information, channel enable configuration information and intra-group channel configuration information according to application scenarios and / or system scenarios, and send the configuration information to the group control module; the group control module performs configuration or reconfiguration when the configuration conditions are met.

6. The multi-core system chip inter-core communication system according to claim 5, characterized in that: The group control module includes a configuration module and a configuration lock module; the configuration module is used to perform group configuration, channel enable configuration and intra-group channel configuration based on configuration information; the group configuration is used to group the cores and indicate the cores included in each group; the channel enable configuration is used to indicate the channels included in each group; the intra-group channel configuration is used to indicate the correspondence between the channels in the group and the accessible cores; the configuration module uses the configuration register to save the above configuration information and perform configuration; The group control module performs core interruption based on the communication request and the channel identifier; specifically: when the A module performs a write operation, it writes into the corresponding channel in response to the write operation; the group control module and the B module generate an interruption for the receiving core for the corresponding group containing the channel, and send the interruption to the receiving core through the MUX; after the receiving core responds to the interruption, it reads data from the group and its channel corresponding to the B module and the receiving core; similarly, when the core to which the B module belongs wants to write data, it writes the data into the channel corresponding to the group in response to the write operation request of the core to which the B module belongs, and the group control module and the A module generate an interruption for the receiving core for the corresponding group in the channel, and send the interruption to the receiving core through the MUX; after the receiving core responds to the interruption, it obtains data from the A module channel.

7. The multi-core system chip inter-core communication system according to claim 6, characterized in that: The configuration conditions are when the chip is initialized, the application scenario and / or the system scenario is initialized or changes occur.

8. A multi-core system chip inter-core communication method, characterized in that: The multi-core system chip inter-core communication method is used to implement the multi-core system chip inter-core communication system described in any one of claims 1-7.

9. A multi-core system chip inter-core communication control chip, characterized in that: The multi-core system chip inter-core communication control chip is used to implement the multi-core system chip inter-core communication system described in any one of claims 1-7.

10. A multi-core system chip inter-core communication control circuit, characterized in that: The multi-core system chip inter-core communication module is used to implement the multi-core system chip inter-core communication system described in any one of claims 1-7.

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