Circuit Structure and Application Method of a Low-Order Bio-Neural Network Based on Memristors

Abstract

The present invention discloses a circuit structure and an application method of a low-order biological neural network based on memristors. The circuit structure includes: an encoding module that expands a 4-bit binary input vector into a 16-bit sample expansion vector; a sample memory module that maps the sample expansion vector into a first set of memory pulse signals, inputs the first set of memory pulse signals to a first memristor array to adjust corresponding resistance values, and stores the samples in the first memristor array; a label memory module that maps a predefined operation result between the sample expansion vector and a predefined sample label vector into a second set of memory pulse signals, inputs the second set of memory pulse signals to a second memristor array to adjust corresponding resistance values, and stores the mapping relationship between the samples and the labels in the second memristor array; a prediction module that reads corresponding prediction voltages from the first memristor array and the second memristor array, and processes the prediction voltages through a preset algebraic operation to obtain a prediction probability.

Description

Technical Field

[0001] The present invention relates to the field of artificial neural network hardware, and particularly to a circuit structure and application method of a low-order biological neural network based on memristors. Background Art

[0002] With the rapid development of artificial intelligence technology, the computing requirements of neural networks are increasing day by day. However, in the traditional von Neumann architecture, the computing unit (processor) and the storage unit (memory) are independent of each other, and data needs to be frequently transferred between the two, resulting in problems such as the Memory Wall and Bandwidth Bottleneck. This architecture limits the computing efficiency, and at the same time brings high energy consumption and latency, becoming a bottleneck for the performance improvement of neural networks.

[0003] Memristors, with their non-volatile, analog conductance characteristics, and unique advantage of integrating storage and computing, provide new possibilities for the hardware implementation of neural networks. In particular, memristor crossbar arrays can efficiently perform matrix operations and support large-scale parallel computing, thus significantly improving the computing performance. In addition, the network structure of low-order biological neural networks highly matches the storage-computing integrated characteristics of memristors, opening up an innovative path to break through the limitations of traditional computing architectures.

[0004] Therefore, developing an efficient computing hardware based on memristors to support the operation of low-order biological neural networks has become an important technical challenge that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a circuit structure and application method of a low-order biological neural network based on memristors to solve the above problems existing in the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A circuit structure of a low-order biological neural network based on memristors, comprising:

[0008] An encoding module, configured to expand and process a 4-bit binary input vector into a 16-bit sample expansion vector;

[0009] A sample memory module, configured to map the sample expansion vector into a first group of memory pulse signals, input the first group of memory pulse signals to a first memristor array to adjust the corresponding resistance values, and implement storing the sample into the first memristor array;

[0010] A label memory module, configured to map the result of a predefined operation between a sample extended vector and a predefined sample label vector to a second set of memory pulse signals, and input the second set of memory pulse signals into a second memristor array to adjust corresponding resistance values, so as to store the mapping relationship between samples and labels into the second memristor array;

[0011] A prediction module, configured to read corresponding prediction voltages from the first memristor array and the second memristor array, and process the prediction voltages through a preset algebraic operation to obtain a prediction probability.

[0012] Among them, the extension processing steps in the encoding module include:

[0013] Receiving a binary input vector of length 4 , where each element takes values in {0, 1};

[0014] Setting the first bit of the extended vector to 0;

[0015] Directly copying the elements of the input vector X to the 2nd to 5th bits, i.e., ;

[0016] Calculating all binary exclusive OR results of the 6th to 11th bits , i.e., ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ;

[0017] Calculating all ternary exclusive OR results of the 12th to 15th bits , i.e., ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ;

[0018] Calculating the quaternary exclusive OR result of the 16th bit ⊕ ⊕ ⊕ ;

[0019] Replace each element 0 in the obtained 16-bit vector with -1 to obtain a sample extended vector.

[0020] Among them, both the first memristor array and the second memristor array are composed of 16 1T1R structural units. Each 1T1R structural unit contains a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

[0021] Among them, the memory pulse signal mapping relationship in the sample memory module is: -1 in the sample extended vector corresponds to , 1 corresponds to , where is a preset memory voltage value for adjusting the resistance state of the memristor array;

[0022] The memory pulse signal mapping relationship in the label memory module is: -1 in the predefined operation result corresponds to , 1 corresponds to .

[0023] Among them, the update method of the memristor resistance values in the sample memory module and the label memory module is: by applying positive and negative pulses with the same amplitude to the top electrode of the memristor and applying pulses with different amplitudes to the transistor gate, the dynamic adjustment of the memristor resistance value is realized;

[0024] Among them, the memristor resistance value decreases when a positive pulse is applied, and the memristor resistance value increases when a negative pulse is applied.

[0025] Among them, a linear relationship ΔR∝N is satisfied between the resistance value change ΔR and the number of pulses N.

[0026] Among them, a parallel computing method is adopted to update the resistance values of the memristor units in the same row simultaneously.

[0027] Among them, the predefined operation in the label memory module is the matrix multiplication of the sample extended vector and the sample label, where the sample label takes values in {-1, 1}.

[0028] Among them, the prediction module includes a preset memristor, a read memristor, a fixed-value resistor, and an operational amplifier;

[0029] By applying a preset current and a prediction current to the top electrodes of the preset memristor and the read memristor respectively, a differential voltage signal is generated; this differential voltage signal is processed by a differential amplifier circuit to generate an amplified prediction voltage; a preset algebraic operation is performed using this prediction voltage to generate a processed output signal; a prediction probability is obtained through this output signal;

[0030] Among them, the differential amplifier circuit is composed of four fixed-value resistors and an operational amplifier, and the output voltage equivalently represents the difference between the resistance values of the preset memristor and the read memristor;

[0031] Among them, the prediction probability is calculated by the following formula:

[0032]

[0033] Among them, the sample prediction voltage represents: in the memristor array of the sample memory module, when the memristor selected according to the predetermined condition is used as the read memristor, the voltage obtained through the prediction module; the label prediction voltage represents: in the memristor array of the label memory module, when the memristor selected according to the predetermined condition is used as the read memristor, the voltage obtained through the prediction module.

[0034] An application method for the circuit structure of a low-order biological neural network based on memristors, including:

[0035] S1: Expand the 4-bit binary input vector into a 16-bit sample expansion vector;

[0036] S2: Map the sample expansion vector into a first group of memory pulse signals, and input the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance values, so as to store the sample into the first memristor array;

[0037] S3: Map the predefined operation result between the sample expansion vector and the predefined sample label vector into a second group of memory pulse signals, and input the second group of memory pulse signals into the second memristor array to adjust the corresponding resistance values, so as to store the mapping relationship between the sample and the label into the second memristor array;

[0038] S4: Read the corresponding prediction voltages from the first memristor array and the second memristor array, and process the prediction voltages through a preset algebraic operation to obtain the prediction probability.

[0039] Compared with the prior art, the present invention has the following advantages: The input vector encoding method of the present invention is unique. By using the method of extended vectors, the encoded vectors have memory and discriminability. By constructing extended vectors that contain all possible binary and higher-order exclusive-or combinations, the similarities and differences between different input samples can be effectively expressed in the vector space, thereby enhancing the classification and recognition capabilities of the neural network and improving the calculation accuracy and generalization ability. In terms of updating the resistance value of the memristor, the present invention adopts a dynamic pulse regulation strategy. By applying positive and negative pulses with a fixed amplitude to the top electrode of the memristor and applying pulses with different amplitudes to the gate of the transistor simultaneously, precise weight adjustment is achieved. Compared with the traditional fixed-pulse programming method, the dynamic pulse control strategy of the present invention can effectively improve the weight writing accuracy, reduce the drift error of the memristor, and improve the stability and trainability of the neural network.

[0040] Other features and advantages of the present invention will be described in the subsequent specification, and part of them will become obvious from the specification or be understood by implementing the present invention.

[0041] The technical solution of the present invention will be further described in detail below through the drawings and embodiments. Description of the Drawings

[0042] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0043] Figure 1 is a schematic circuit diagram of a low-order biological neural network based on a memristor in an embodiment of the present invention;

[0044] Figure 2 is a schematic circuit diagram of an encoding module in an embodiment of the present invention;

[0045] Figure 3 is a schematic circuit diagram of a sample memory module in an embodiment of the present invention;

[0046] Figure 4 is a schematic circuit diagram of a label memory module in an embodiment of the present invention;

[0047] Figure 5 is a schematic circuit diagram of a prediction module in an embodiment of the present invention;

[0048] Figure 6 is a graph of the resistance value change in an embodiment of the present invention. Detailed Embodiments

[0049] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for illustrating and explaining the present invention, and are not used to limit the present invention.

[0050] An embodiment of the present invention provides a circuit structure of a low-order biological neural network based on a memristor, including:

[0051] An encoding module, configured to expand and process a 4-bit binary input vector into a 16-bit sample expansion vector;

[0052] A sample memory module, configured to map the sample expansion vector into a first group of memory pulse signals, input the first group of memory pulse signals to a first memristor array to adjust corresponding resistance values, and implement storing the sample into the first memristor array;

[0053] A label memory module, configured to map a predefined operation result between the sample expansion vector and a predefined sample label vector into a second group of memory pulse signals, and input the second group of memory pulse signals to a second memristor array to adjust corresponding resistance values, and implement storing the mapping relationship between the sample and the label into the second memristor array;

[0054] A prediction module, configured to read corresponding prediction voltages from the first memristor array and the second memristor array, and process the prediction voltages through a preset algebraic operation to obtain a prediction probability.

[0055] The working principle of the above technical solution is as follows: The encoding module expands the input 4-bit binary vector (a 4-bit data composed of 0 and 1) into a 16-bit sample expansion vector. Among them, the encoding module receives the 4-bit binary input vector and converts it into a 16-bit vector through specific expansion processing operations. This process increases the dimension of the data, making it more suitable for subsequent storage and calculation in the memristor array. The expanded 16-bit sample expansion vector provides a richer information expression ability for the neural network.

[0056] The sample memory module maps the 16-bit sample expansion vector into a first group of memory pulse signals, and inputs these signals into the first memristor array, and realizes the storage of sample data by adjusting the resistance values. Among them, the sample memory module converts the 16-bit sample expansion vector output by the encoding module into a series of pulse signals (referred to as the first group of memory pulse signals). These pulse signals are applied to the first memristor array, and the sample information is "recorded" by changing the resistance values of the memristors. The resistance state of the memristor can reflect the characteristics of the input sample, thereby completing the storage of sample data.

[0057] The label memory module maps the operation result between the sample extended vector and the predefined sample label vector into a second set of memory pulse signals, and inputs these signals into the second memristor array to store the mapping relationship between the sample and the label by adjusting the resistance value. The label memory module first performs a predefined operation (such as matrix multiplication) on the sample extended vector and the sample label vector to obtain a result representing the association between the sample and the label. This result is then converted into a second set of memory pulse signals and input into the second memristor array. The resistance values of the memristor array are adjusted according to these pulse signals, thereby storing the mapping relationship between the sample and the label.

[0058] The prediction module reads the prediction voltages from the first memristor array and the second memristor array, and processes these voltages through a preset algebraic operation to obtain the prediction probability. In the prediction stage, the prediction module applies current signals to the two memristor arrays to read out the corresponding prediction voltages. These voltage values reflect the previously stored sample information and its mapping relationship with the label. Subsequently, through algebraic operations (such as addition, multiplication, etc.) on these voltage values, the prediction probability of the input sample is calculated to complete the classification or prediction task.

[0059] As Figure 1 shown, by inputting a 4-bit binary input vector into the encoding module, an extended processing operation is performed to obtain a 16-bit sample extended vector. The memory voltage signal corresponding to the sample extended vector is input into the sample memory module to achieve sample storage; at the same time, the memory voltage signal corresponding to the matrix multiplication result of the sample extended vector and the sample label is input into the label memory module to achieve sample and label storage. Finally, the prediction voltages are obtained by reading the memory information stored in the sample memory module and the label memory module respectively through the prediction current signal, and then the prediction probability is obtained through algebraic operations.

[0060] Explanation: The memory voltage signal and the memory pulse signal are equivalent technical features, both referring to the signals used to adjust the resistance value of the memristor. The sample memory module and the label memory module are respectively implemented through the first memristor array and the second memristor array. The memory voltage signal corresponding to the sample extended vector is obtained by mapping the sample extended vector. The predefined operations include but are not limited to matrix multiplication operations.

[0061] The beneficial effects of the above technical solution are: Through the collaborative work of the encoding module, the sample memory module, the label memory module, and the prediction module, this circuit structure constructs a low-order biological neural network based on memristors, which can efficiently store and process sample data and its mapping relationship with labels, thereby improving the classification and recognition capabilities of the neural network.

[0062] In another embodiment, the extended processing step in the encoding module includes:

[0063] Receive a binary input vector of length 4 , where each element takes values in {0, 1};

[0064] Set the first bit of the extended vector to 0;

[0065] Copy the elements of the input vector X directly to the 2nd to 5th bits, i.e., ;

[0066] Calculate the binary XOR results of all bits from the 6th to 11th, i.e., , i.e., ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ;

[0067] Calculate the ternary XOR results of all bits from the 12th to 15th , i.e., ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ;

[0068] Calculate the quaternary XOR result of the 16th bit ⊕ ⊕ ⊕ ;

[0069] Replace each element 0 in the obtained 16-bit vector with -1 to obtain the sample extended vector.

[0070] The working principle of the above technical solution is as follows: As Figure 2 shown in the schematic diagram of the circuit structure of the encoding module, it includes: extending the 4-bit binary input vector , where each element takes values in , and performing an extension operation to expand it into a 16-bit sample extended vector. The encoding module consists of 17 binary memristors and 4 fixed resistors, where the high-resistance state resistance of the memristor is , the low-resistance state resistance of the memristor is , and the resistance value of the fixed resistor , the high resistance state of the memristor represents logic 0, and the low resistance state represents logic 1. In the embodiments of the present invention, the set voltage of the memristor is set , the reset voltage , the parameter voltage needs to satisfy ;

[0071] The specific encoding steps are as follows:

[0072] Step S1: Initialize 17 memristors to the high resistance state;

[0073] Step S2: According to the logic change the states of the memristors and , according to the logic change the state of the memristor , and set the memristor to the state corresponding to logic 0;

[0074] Step S3: and Store the XOR result of the two bits into the memristor ;

[0075] Step S3 includes: The state of the memristor represents , and the set voltage represents , where , , ;

[0076] When , , if , at this time, the voltage division of the memristor is , and store logic 0; if , at this time, the voltage division of the memristor is , and store logic 1;

[0077] When , , if , at this time, the voltage division of the memristor is , and store logic 1; if , at this time, the voltage division of the memristor is , and store logic 0;

[0078] Step S4, perform the following XOR operations in parallel according to the operations in Step S3. To avoid repetition, the description of the same details is omitted while describing the operation steps below:

[0079] Memristor The state represents , by setting the voltage represents , calculate and The XOR result of two bits is stored in the memristor ;

[0080] Memristor The state represents , by setting the voltage represents , calculate and The XOR result of two bits is stored in the memristor ;

[0081] Memristor The state represents 0, by setting the voltage represents , calculate 0 and The XOR result of two bits is stored in the memristor ;

[0082] Memristor The state represents , by setting the voltage represents , calculate and The XOR result of two bits is stored in the memristor ;

[0083] Step S5, perform the following XOR operations in parallel according to the operations in Step S3. To avoid repetition, the same detailed descriptions are omitted while describing the operation steps below:

[0084] Memristor The state represents , by setting the voltage represents , calculate and The XOR result of two bits is stored in the memristor ;

[0085] Memristor The state represents , by setting the voltage represents , calculate and The XOR result of two bits is stored in the memristor ;

[0086] Memristor The state of represents 0. By setting the voltage represents , calculate 0 and the XOR result of two bits is stored in the memristor ;

[0087] The memristor the state of represents , by setting the voltage represents , calculate and the XOR result of two bits is stored in the memristor ;

[0088] Step S6, perform the following XOR operations in parallel according to the operations in Step S3. To avoid repetition, the same detailed descriptions are omitted while describing the operation steps below:

[0089] The memristor the state of represents , by setting the voltage represents , calculate and the XOR result of two bits is stored in the memristor ;

[0090] The memristor the state of represents , by setting the voltage represents , calculate and the XOR result of two bits is stored in the memristor ;

[0091] The memristor the state of represents , by setting the voltage represents , calculate and the XOR result of two bits is stored in the memristor ;

[0092] The memristor the state of represents , by setting the voltage represents , calculate and the XOR result of two bits is stored in the memristor ;

[0093] Step S7, sequentially read the memristor , , , , , , , , , , , , , , , The state of obtains a 16-bit sample expansion vector.

[0094] The beneficial effects of the above technical solution are as follows: The encoding module expands the 4-bit binary input vector into a 16-bit sample expansion vector. By constructing an expansion vector containing binary and high-order XOR combinations, the expression ability of the input data is enhanced, the similarity and difference between samples can be effectively distinguished, and the calculation accuracy and generalization ability of the neural network are improved.

[0095] In another embodiment, both the first memristor array and the second memristor array are composed of 16 1T1R structural units. Each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

[0096] The working principle of the above technical solution is as follows: As Figure 3 shown, the circuit structure schematic diagram of the sample memory module includes: a memristor array composed of 16 1T1R structural units. Each 1T1R structural unit includes a transistor and a memristor. The bottom electrode of the memristor is connected to the drain of the transistor, and the source of the transistor in the memristor array is grounded. The high-resistance state resistance value of the selected memristor is 16 kΩ, and the low-resistance state resistance value is 100 Ω. The 16 memristors are initialized to 7 kΩ. Among them, the transistor used in this embodiment is a field-effect transistor (such as MOSFET), or other devices with the same switching characteristics. In addition, in this embodiment, the source and drain of the transistor used are symmetric in structure. Therefore, in practical applications, the two can be interchanged without strict distinction.

[0097] As Figure 4 shown, the circuit structure schematic diagram of the label memory module includes: The storage process is the same as that of the sample memory module shown in Figure 3 shown, but the stored object is the matrix multiplication result of the sample expansion vector and the sample label. Therefore, in order to avoid repetition, the description of the same details is omitted while describing the operation steps of the training method below. Specifically, the label memory module is composed of a memristor array composed of 16 1T1R structural units. Each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor, and the sources of all transistors are grounded.

[0098] The beneficial effects of the above technical solution are as follows: The first memristor array and the second memristor array are composed of 16 1T1R structural units, which can efficiently store and read sample data and their label mapping relationships, improving the storage density and read / write speed of the circuit.

[0099] In another embodiment, the mapping relationship of the memory pulse signal in the sample memory module is: -1 in the sample expansion vector corresponds to , 1 corresponds to , where is a preset memory voltage value for adjusting the resistance state of the memristor array;

[0100] The mapping relationship of the memory pulse signal in the label memory module is: -1 in the predefined operation result corresponds to , 1 corresponds to .

[0101] The working principle of the above technical solution is as follows: To store the first sample, the memory pulse signal corresponding to the 16-bit sample expansion vector is input to the top electrode of the memristor to adjust the resistance value of the memristor. When the i-th bit of the sample expansion vector is -1, , the corresponding pulse signal is applied; when the i-th bit of the sample expansion vector is 1, , the corresponding pulse signal is applied, where , the corresponding rules are as follows:

[0102] When the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0103] To store the second and subsequent samples, the memory pulse signal corresponding to the 16-bit sample expansion vector is input to the top electrode of the memristor to adjust the resistance value of the memristor. When the i-th bit of the sample expansion vector is -1, , the corresponding pulse signal is applied; when the i-th bit of the sample expansion vector is 1, , the corresponding pulse signal is applied, where , the corresponding rules are as follows:

[0104] For the case where the value represented by the current memristor resistance is -1, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0105] For the case where the value represented by the current memristor resistance is 1, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0106] For the case where the value represented by the current memristor resistance is -2, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0107] For the case where the value represented by the current memristor resistance is 2, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0108] For the case where the value represented by the current memristor resistance is -3, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0109] For the case where the value represented by the current memristor resistance is 3, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0110] For the case where the value represented by the current memristor resistance is -4, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0111] For the case where the value represented by the current memristor resistance is 4, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0112] For the case where the value represented by the current memristor resistance is -5, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0113] For the case where the value represented by the current memristor resistance is 5, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ;

[0114] For the case where the value represented by the current memristor resistance is -6, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0115] For the case where the value represented by the current memristor resistance is 6, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0116] For the case where the value represented by the current memristor resistance is -7, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0117] For the case where the value represented by the current memristor resistance is 7, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0118] For the case where the value represented by the current memristor resistance is -8, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0119] For the case where the value represented by the current memristor resistance is 8, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0120] For the case where the value represented by the current memristor resistance is -9, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0121] For the case where the value represented by the current memristor resistance is 9, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample expansion vector is 1, ;

[0122] Implement storing the sample into the memristor array.

[0123] The beneficial effects of the above technical solution are: The sample memory module and the label memory module accurately map the sample expansion vector and the predefined operation result to pulse signals through a reasonable memory pulse signal mapping relationship, realizing precise adjustment of the memristor resistance value.

[0124] In another embodiment, the method for updating the resistance values of the memristors in the sample memory module and the tag memory module is as follows: by applying positive and negative pulses with the same amplitude to the top electrode of the memristor and applying pulses with different amplitudes to the transistor gate, the dynamic adjustment of the resistance value of the memristor is achieved;

[0125] Among them, when a positive pulse is applied, the resistance value of the memristor decreases, and when a negative pulse is applied, the resistance value of the memristor increases.

[0126] The working principle of the above technical solution is as follows: in the sample memory module and the tag memory module, the resistance value of the memristor is updated by applying positive and negative pulses with different amplitudes to the top electrode of the memristor and applying pulses with different amplitudes to the transistor gate to achieve the dynamic adjustment of the resistance value of the memristor.

[0127] The specific operation process includes: when a positive pulse is applied: the resistance value of the memristor will decrease because the positive pulse can trigger the redistribution of charges inside the memristor, thereby reducing its resistance value, representing the update of the state of the memristor. When a negative pulse is applied: the resistance value of the memristor will increase. The application of the negative pulse will cause the rearrangement of charges inside the memristor, thereby increasing its resistance value, indicating the change of the state of the memristor. The role of different pulse amplitudes on the transistor gate: At the same time, by applying pulses with different amplitudes to the transistor gate, the adjustment of the resistance value of the memristor can be further controlled. The control signal of the transistor gate and the pulse signal of the memristor act together to ensure the precise adjustment of the resistance value of the memristor under different operating conditions.

[0128] The beneficial effect of the above technical solution is that the sample memory module and the tag memory module adopt a dynamic pulse adjustment strategy to update the resistance value of the memristor. By applying a combination of positive and negative pulses and pulses with different amplitudes, the dynamic and precise adjustment of the resistance value is achieved, improving the weight writing accuracy, reducing the drift error, and enhancing the stability and trainability of the neural network.

[0129] In another embodiment, there is a linear relationship ΔR∝N between the resistance value change ΔR and the number of pulses N.

[0130] The working principle of the above technical solution is that there is a linear relationship ΔR∝N between the resistance value change ΔR and the number of pulses N. Among them, the predicted voltage obtained through the differential amplifier circuit equivalently represents the difference in the resistance value of the memristor. Because the resistance value of the memristor is linearly related, the predicted voltage represents the sample memory information.

[0131] The beneficial effect of the above technical solution is that the change in the resistance value of the memristor is linearly related to the number of pulses, simplifying the resistance value adjustment process and improving the control accuracy and response speed of the circuit structure.

[0132] In another embodiment, a parallel computing method is adopted to update the resistance values of the memristor cells in the same row simultaneously.

[0133] The working principle of the above technical solution is as follows: By adopting the parallel computing method, the resistance values of the memristor cells in the same row can be updated efficiently and simultaneously. This method utilizes the parallel access capabilities of the array structure and the control circuit, combines data parallelism and synchronization mechanisms, and significantly improves the update speed and efficiency. This feature is particularly important in scenarios that require processing large-scale data, such as neural network training and real-time computing tasks.

[0134] Perform the following exclusive OR operation in parallel according to the operation in step S3. To avoid repetition, the description of the same details is omitted while describing the operation steps below:

[0135] Memristor The state represents , by setting the voltage represents , calculate and The two-bit exclusive OR result is stored in the memristor ;

[0136] Memristor The state represents , by setting the voltage represents , calculate and The two-bit exclusive OR result is stored in the memristor ;

[0137] Memristor The state represents , by setting the voltage represents , calculate and The two-bit exclusive OR result is stored in the memristor ;

[0138] Memristor The state represents , by setting the voltage represents , calculate and The two-bit exclusive OR result is stored in the memristor ;

[0139] The beneficial effect of the above technical solution is that by updating the resistance values of the memristor cells in the same row simultaneously through the parallel computing method, the computing efficiency of the circuit is improved, and the time required for training and prediction is shortened.

[0140] In another embodiment, the predefined operation in the label memory module is the matrix multiplication of the sample expansion vector and the sample label, where the sample label takes values of {-1, 1}.

[0141] The working principle of the above technical solution is: the matrix multiplication of the sample expansion vector and the sample label, characterized in that the label corresponding to each sample takes values of {-1, 1}, so as to calculate the result of the matrix multiplication and realize storing the sample and the label into the memristor array.

[0142] The beneficial effect of the above technical solution is: the label memory module uses the matrix multiplication of the sample expansion vector and the sample label as the predefined operation, effectively expressing the mapping relationship between the sample and the label, and improving the classification accuracy of the neural network.

[0143] In another embodiment, the prediction module includes a preset memristor, a read memristor, a fixed resistor, and an operational amplifier;

[0144] By applying a preset current and a prediction current to the top electrodes of the preset memristor and the read memristor respectively, a differential voltage signal is generated; the differential voltage signal is processed by a differential amplification circuit to generate an amplified prediction voltage; a preset algebraic operation is performed using the prediction voltage to generate a processed output signal; a prediction probability is obtained through the output signal;

[0145] Among them, the differential amplification circuit is composed of four fixed resistors and an operational amplifier, and the output voltage equivalently represents the difference in resistance values between the preset memristor and the read memristor;

[0146] The prediction probability is calculated by the following formula:

[0147]

[0148] Among them, the sample prediction voltage represents: in the memristor array of the sample memory module, when the memristor selected according to the predetermined condition is used as the read memristor, the voltage obtained through the prediction module; the label prediction voltage represents: in the memristor array of the label memory module, when the memristor selected according to the predetermined condition is used as the read memristor, the voltage obtained through the prediction module.

[0149] The working principle of the above technical solution is: as Figure 5 shown, the circuit structure schematic diagram of the prediction memory module provided by the embodiment of the present invention includes:

[0150] Composed of a memristor, a fixed resistor, and an operational amplifier, by applying a preset current to the top electrode of the preset memristor and the read memristor and the predicted current , the predicted voltage is obtained through a differential amplifier circuit.

[0151] Specifically, the prediction operation steps are as follows:

[0152] Step S8: Initialize the memristor to 7 kΩ, and read the memristor sequentially one by one from the 16 memristors in the sample memory module;

[0153] Step S9: Set and ;

[0154] Input the sample to be predicted into the encoding module to obtain a 16-bit sample extended vector. When the i-th bit of the sample extended vector is -1, ; when the i-th bit of the sample extended vector is 1, ;

[0155] Step S10: Input and to the top electrodes of the preset memristor and the read memristor respectively to obtain the inputs and of the differential amplifier circuit;

[0156] The differential amplifier circuit is composed of four fixed-value resistors and an operational amplifier. In the embodiment of the present invention, their relationship is ;

[0157] The operational amplifier is in a negative feedback working state, so the voltages at the in-phase input terminal and the anti-phase input terminal are equal, that is: ;

[0158] and form a voltage dividing circuit, so ;

[0159] and form a voltage dividing circuit, so ;

[0160] According to the virtual short characteristic of the operational amplifier, it can be deduced that ;

[0161] According to the virtual open characteristic of the operational amplifier, it can be deduced that , that is ;

[0162] Substitute and after arrangement, we get ;

[0163] In an embodiment of the present invention under the conditions, the predicted voltage is obtained ;

[0164] The predicted voltage obtained through the differential amplifier circuit equivalently represents the difference in the resistance values of the memristors. Since the resistance values of the memristors are linearly related, the predicted voltage represents the sample memory information.

[0165] Step S11: Repeat step S8, but the memristor to be read is one of the 16 memristors in the tag memory module;

[0166] Step S12: Repeat step S9, but perform matrix multiplication on the sample extension vector corresponding to the sample to be predicted and the sample tag, and set according to the rules of step S2 through the result of the matrix multiplication and ;

[0167] Step S13: Repeat step S10, and the predicted voltage represents the tag memory information.

[0168] The predicted voltage obtains the predicted probability through algebraic operations, and the process of the predicted probability operation can be represented by the following formula:

[0169]

[0170] In the formula, the sample predicted voltage is the voltage obtained by using the memristor included in the memristor array in the sample memory module as the memristor to be read, which represents the number of times the sample to be predicted is memorized in the sample memory module; the tag predicted voltage is the voltage obtained by using the memristor included in the memristor array in the tag memory module as the memristor to be read, which represents the number of times the tag corresponding to the sample to be predicted is 1 in the tag memory module.

[0171] As Figure 6 shown, the resistance value change curve graph provided by the embodiment of the present invention includes:

[0172] The pulse duration applied to the transistor gate each time is 0.1 s;

[0173] The resistance value of the memristor can vary between 2 kΩ and 12 kΩ, and the adjustment amplitude each time is ±0.5 kΩ. Thus, starting from the initial state of 7 kΩ, the memristor can be adjusted up and down by 10 levels;

[0174] In addition, since the samples have the characteristic that the first bit of their extension vectors is -1, it means that at most 10 samples can be stored.

[0175] The bit width of the input vector can be between 2 and 4 bits to adapt to different computing requirements. In different application scenarios, the precision requirements of the input vector may vary. For example, in some low-power or resource-constrained environments, a 2-bit input vector may be sufficient to meet the computing needs and reduce storage and computing overhead. In scenarios with higher requirements for computing precision, using a 3-bit or 4-bit input vector can provide a more fine-grained information representation, thereby improving the system's recognition ability and classification accuracy. By supporting input vectors of 2 to 4 bits, the system can balance between computing precision and resource utilization, flexibly adjust the input format according to specific application requirements, and optimize the overall performance.

[0176] The label vector can contain multiple elements, not limited to a single label. In some application scenarios, a sample may belong to multiple categories or have multiple relevant features simultaneously. Therefore, the label vector can take the form of multiple elements, not limited to a single label. To support this multi-label storage and matching mechanism, the number of rows in the memristor array in the label memory module needs to match the number of elements in a label vector. This means that when the dimension of the label vector increases, the number of rows in the memristor array also increases accordingly to ensure that each label element can be correctly stored and retrieved. This design helps enhance the flexibility of the system, enabling it to handle more complex classification tasks and support advanced functions such as multi-label learning.

[0177] The beneficial effects of the above technical solution are as follows: The prediction module uses a preset memristor, a read memristor, a fixed-value resistor, and an operational amplifier to form a differential amplifier circuit, accurately reads and processes the prediction voltage, and improves the reliability and accuracy of the prediction result. The prediction probability is calculated by comprehensively considering the sample prediction voltage and the label prediction voltage through a reasonably designed formula, accurately reflecting the prediction result of the sample, and further improving the prediction performance of the neural network.

[0178] In another embodiment, an application method for a circuit structure of a low-order bio-neural network based on memristors includes:

[0179] S1: Expand and process a 4-bit binary input vector into a 16-bit sample expansion vector;

[0180] S2: Map the sample expansion vector into a first set of memory pulse signals, and input the first set of memory pulse signals into the first memristor array to adjust the corresponding resistance values, so as to store the sample into the first memristor array;

[0181] S3: Map the predefined operation result between the sample expansion vector and the predefined sample label vector into a second set of memory pulse signals, and input the second set of memory pulse signals into the second memristor array to adjust the corresponding resistance values, so as to store the mapping relationship between the sample and the label into the second memristor array;

[0182] S4: Read the corresponding predicted voltages from the first memristor array and the second memristor array, and process the predicted voltages through a preset algebraic operation to obtain a predicted probability.

[0183] The working principle of the above technical solution is as follows: The expansion process in step S1 includes:

[0184] Receiving a binary input vector of length 4 , where each element takes values in {0, 1};

[0185] Set the first bit of the expansion vector to 0;

[0186] Directly copy the elements of the input vector X to the 2nd to 5th bits, i.e., ;

[0187] Calculate all the binary XOR results of the 6th to 11th bits , i.e., ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ;

[0188] Calculate all the ternary XOR results of the 12th to 15th bits , i.e., ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ;

[0189] Calculate the quaternary XOR result of the 16th bit ⊕ ⊕ ⊕ ;

[0190] Replace each element 0 in the obtained 16-bit vector with -1 to obtain a sample expansion vector.

[0191] Both the first memristor array and the second memristor array used in the method are composed of 16 1T1R structural units. Each 1T1R structural unit contains a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

[0192] The memory pulse signal mapping relationship in step S2 is: -1 in the sample expansion vector corresponds to , 1 corresponds to , where is a preset memory voltage value used to adjust the resistance state of the memristor array;

[0193] The memory pulse signal mapping relationship in step S3 is: -1 in the predefined operation result corresponds to , 1 corresponds to .

[0194] The method for updating the resistance value of the memristor in steps S2 and S3 is: by applying positive and negative pulses with the same amplitude to the top electrode of the memristor and applying pulses with different amplitudes to the gate of the transistor, the dynamic adjustment of the resistance value of the memristor is realized; among them, the resistance value of the memristor decreases when a positive pulse is applied, and the resistance value of the memristor increases when a negative pulse is applied.

[0195] The relationship between the change in resistance value ΔR and the number of pulses N satisfies a linear relationship ΔR∝N.

[0196] Adopt a parallel computing method to update the resistance values of the memristor units in the same row simultaneously.

[0197] The predefined operation in step S3 is the matrix multiplication of the sample expansion vector and the sample label, where the sample label takes values of {-1, 1}.

[0198] Step S4 includes: by applying a preset current and a predicted current to the top electrodes of the preset memristor and the memristor to be read respectively, a differential voltage signal is generated; the differential voltage signal is processed by a differential amplifier circuit to generate an amplified predicted voltage; using the predicted voltage for a preset algebraic operation to generate a processed output signal; obtaining a predicted probability through the output signal;

[0199] Among them, the differential amplifier circuit consists of four fixed-value resistors and an operational amplifier, and the output voltage equivalently represents the difference in resistance values between the preset memristor and the memristor to be read;

[0200] The predicted probability is calculated by the following formula:

[0201]

[0202] Among them, the sample prediction voltage means: in the memristor array used in step S2, when the memristor selected according to a predetermined condition is used as the read memristor, the voltage obtained through the prediction process; the label prediction voltage means: in the memristor array used in step S3, when the memristor selected according to a predetermined condition is used as the read memristor, the voltage obtained through the prediction process.

[0203] The beneficial effects of the above technical solution are as follows: By expanding the input vector, the memory and distinguishability between samples are enhanced, effectively improving the classification and recognition capabilities of the neural network. The dynamic pulse regulation strategy realizes accurate update of the memristor resistance, improves the weight writing accuracy, and reduces the drift error. Compared with the traditional method, this solution improves the stability and trainability of the neural network.

[0204] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the equivalent technology of the present invention, the present invention is also intended to include these changes and modifications.

Claims

1. A circuit structure of a low-order biological neural network based on a memristor, characterized in that: include: The encoding module is used for expanding the 4-bit binary input vector into a 16-bit sample expansion vector; A sample memory module, used for mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; A label memory module, used for mapping a predefined operation result between a sample extension vector and a predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into a second memristor array to adjust corresponding resistance values, so as to store a mapping relationship between samples and labels in the second memristor array; The prediction module is used to read the corresponding predicted voltages from the first memristor array and the second memristor array, and process the predicted voltages through a preset algebraic operation to obtain a predicted probability.

2. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The extended processing steps in the encoding module include: Accepts a binary input vector of length 4 , where each element The value is {0,1}; The first bit of the extended vector is set to 0; Copy bits 2 to 5 directly from the elements of the input vector X, that is ; Calculate the binary XOR results of all bits from 6 to 11 ,Right now ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ; Calculate the ternary XOR results of all bits 12 to 15 ,Right now ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ; Calculate the 16th bit of the quaternary XOR result ⊕ ⊕ ⊕ ; Replace each element 0 in the resulting 16-bit vector with -1 to obtain a sample extension vector.

3. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The first memristor array and the second memristor array are both composed of 16 1T1R structural units, wherein each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

4. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The mapping relationship of the memory pulse signal in the sample memory module is: -1 in the sample extension vector corresponds to , 1 corresponds to ,in is a preset memory voltage value, used to adjust the resistance state of the memristor array; The mapping relationship of the memory pulse signal in the tag memory module is: -1 in the predefined operation result corresponds to , 1 corresponds to .

5. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The resistance value of the memristor in the sample memory module and the label memory module is updated in the following way: by applying positive and negative pulses of the same amplitude to the top electrode of the memristor and applying pulses of different amplitudes to the gate of the transistor, the resistance value of the memristor is dynamically adjusted; wherein, when a positive pulse is applied, the resistance value of the memristor decreases, and when a negative pulse is applied, the resistance value of the memristor increases.

6. The circuit structure of the low-order biological neural network based on memristor according to claim 5, characterized in that: The change in resistance value ΔR and the number of pulses N satisfy the linear relationship ΔR∝N.

7. The circuit structure of the low-order biological neural network based on memristor according to claim 5, characterized in that: The resistance values ​​of the memristor units in the same row are updated simultaneously by using parallel computing.

8. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The predefined operation in the label memory module is the matrix multiplication of the sample extension vector and the sample label, where the sample label takes the value of {-1,1}.

9. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The prediction module includes a preset memristor, a read memristor, a fixed resistor and an operational amplifier; By applying a preset current to the top electrodes of the preset memristor and the read memristor, and predicted current , generating a differential voltage signal; the differential voltage signal is processed by a differential amplifier circuit to generate an amplified predicted voltage; a preset algebraic operation is performed using the predicted voltage to generate a processed output signal; and a predicted probability is obtained through the output signal; The differential amplifier circuit is composed of four fixed resistors and an operational amplifier, and the output voltage is equivalent to the difference between the resistance of the preset memristor and the resistance of the read memristor; The predicted probability is calculated by the following formula: ； Among them, the sample prediction voltage represents: in the memristor array of the sample memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module; the tag prediction voltage represents: in the memristor array of the tag memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module.

10. An application method of a circuit structure of a low-order biological neural network based on a memristor, characterized in that: include: S1: Expand the 4-bit binary input vector into a 16-bit sample expansion vector; S2: Mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; S3: mapping a predefined operation result between the sample extension vector and the predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into the second memristor array to adjust the corresponding resistance value, so as to store the mapping relationship between the sample and the label in the second memristor array; S4: Reading corresponding predicted voltages from the first memristor array and the second memristor array, and processing the predicted voltages through a preset algebraic operation to obtain predicted probabilities.

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