Driving circuit, driving method and display device

Abstract

The invention provides a driving circuit, a driving method and a display device. The driving circuit comprises an output circuit, a first node control circuit, a second node control circuit, a third node control circuit and a first energy storage circuit. The second node control circuit controls the communication between the second node and the first clock signal end under the control of the potential of the third node; the first end of the first energy storage circuit is electrically connected with the input end, the second end of the first energy storage circuit is electrically connected with the third node, and the first energy storage circuit is used for storing electric energy; the third node control circuit is used for controlling the potential of the third node. The driving signal output is normal, the screen display is normal, the product image quality is ensured, the power consumption is reduced, and the terminal power consumption and image quality requirements are met.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device. Background Art

[0002] In the related art, end users have high demands for the standby time of wearable products, and they require the power consumption of wearable items to be reduced to improve the standby time of wearable products. In order to reduce the power consumption in AOD (always on) mode, the clock signal in the Frame Skip interval can be changed from the Toogle (trigger) state to the high state. During the reliability test, due to the offset of the TFT (thin film transistor) characteristics, the gate is electrically connected to the third node to control the transistor leakage of the potential of the second node, thereby affecting the working state of the transistor whose gate is electrically connected to the second node included in the output circuit, causing abnormal output of the drive signal, resulting in abnormal display of the screen after the reliability test. Summary of the invention

[0003] The present invention provides a driving circuit, a driving method and a display device, which solve the problem that the driving signal output of the existing driving circuit is abnormal during the frame skipping stage, resulting in abnormal display failure of the screen after the reliability is reduced.

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, including an output circuit, a first node control circuit, a second node control circuit, a third node control circuit, and a first energy storage circuit;

[0005] The output circuit is electrically connected to the first node, the second node and the driving output terminal respectively, and is used to control the output of the driving signal through the driving output terminal under the control of the potential of the first node and the potential of the second node;

[0006] The first node control circuit is used to control the potential of the first node;

[0007] The second node control circuit is electrically connected to the third node, the first clock signal terminal and the second node respectively, and is used to control the second node to be connected to the first clock signal terminal under the control of the potential of the third node;

[0008] The first end of the first energy storage circuit is electrically connected to the input end, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electric energy;

[0009] The third node control circuit is used to control the potential of the third node.

[0010] Optionally, the first node and the third node are the same node; or,

[0011] The first node control circuit is electrically connected to the first voltage terminal, the third node and the first node respectively, and is used to control the connection between the third node and the first node under the control of a first voltage signal provided by the first voltage terminal.

[0012] Optionally, the third node control circuit is electrically connected to the third node, the first clock signal terminal, the input terminal, the second node, the second voltage terminal and the second clock signal terminal, respectively, and is used to control the connection between the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third node and the second voltage terminal under the control of the potential of the second node and the second clock signal provided by the second clock signal terminal.

[0013] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a second energy storage circuit and a third energy storage circuit;

[0014] A first end of the second energy storage circuit is electrically connected to the first node, a second end of the second energy storage circuit is electrically connected to the driving output end, and the second energy storage circuit is used to store electric energy;

[0015] The third energy storage circuit is electrically connected to the second node and is used to maintain the potential of the second node.

[0016] Optionally, the second node control circuit is also electrically connected to a third voltage terminal, and is used to control the connection between the second node and the third voltage terminal under the control of a first clock signal provided by the first clock signal terminal.

[0017] Optionally, the output circuit includes a first output subcircuit and a second output subcircuit;

[0018] The first output subcircuit is electrically connected to the first node, the driving output terminal and the second clock signal terminal respectively, and is used to control the connection between the driving output terminal and the second clock signal terminal under the control of the potential of the first node;

[0019] The second output subcircuit is electrically connected to the second node, the driving output terminal and the second voltage terminal respectively, and is used to control the connection between the driving output terminal and the second voltage terminal under the control of the potential of the second node.

[0020] Optionally, the first energy storage circuit includes a first capacitor;

[0021] A first end of the first capacitor is electrically connected to the input end, and a second end of the first capacitor is electrically connected to the third node.

[0022] Optionally, the second node control circuit includes a first transistor;

[0023] A gate of the first transistor is electrically connected to the third node, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the second node.

[0024] Optionally, the second node control circuit further includes a second transistor;

[0025] A gate of the second transistor is electrically connected to the first clock signal terminal, a first electrode of the second transistor is electrically connected to the third voltage terminal, and a second electrode of the second transistor is electrically connected to the second node.

[0026] Optionally, the first node control circuit includes a third transistor;

[0027] A gate of the third transistor is electrically connected to the first voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the first node.

[0028] Optionally, the third node control circuit includes a fourth transistor, a fifth transistor and a sixth transistor;

[0029] The gate of the fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourth transistor is electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0030] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor;

[0031] A gate of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

[0032] Optionally, the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor;

[0033] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the driving output end;

[0034] A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to a DC voltage end.

[0035] Optionally, the first output sub-circuit includes a seventh transistor, and the second output sub-circuit includes an eighth transistor;

[0036] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the driving output terminal, and the second electrode of the seventh transistor is electrically connected to the second clock signal terminal;

[0037] A gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second voltage terminal, and a second electrode of the eighth transistor is electrically connected to the driving output terminal.

[0038] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:

[0039] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node;

[0040] A first node control circuit controls the potential of the first node;

[0041] The second node control circuit controls the connection between the second node and the first clock signal terminal under the control of the potential of the third node;

[0042] The first energy storage circuit controls the potential of the third node according to an input signal provided by the input terminal;

[0043] The third node control circuit controls the potential of the third node.

[0044] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned pixel circuit.

[0045] The driving circuit, driving method and display device described in the present invention enable the potential of the third node to maintain an effective voltage state for a long time in the Frame Skip interval after the electrical position of the clock signal is high. Under reliability conditions, at the potential of the third node, the transistor that controls the potential of the second node can still be closed, without affecting the working state of the transistor whose gate is electrically connected to the second node included in the output circuit, so that the driving signal is output normally and the screen is displayed normally, thereby ensuring product image quality and reducing power consumption, meeting terminal power consumption and image quality requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0047] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0048] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0049] Figure 4 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0050] Figure 5 yes Figure 4 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0051] Fig. 6A yes Figure 4 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the input stage;

[0052] Figure 6B yes Figure 4 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the output stage;

[0053] Figure 6C yes Figure 4 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the output reset phase;

[0054] Fig.6D yes Figure 4 A schematic diagram of the working state of at least one embodiment of the driving circuit shown in the output cut-off stage;

[0055] Fig. 6E yes Figure 4 The diagram shows a working state diagram of at least one embodiment of a driving circuit in a frame skipping stage. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0058] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0059] The driving circuit described in the embodiment of the present invention includes an output circuit, a first node control circuit, a second node control circuit, a third node control circuit and a first energy storage circuit;

[0060] The output circuit is electrically connected to the first node, the second node and the driving output terminal respectively, and is used to control the output of the driving signal through the driving output terminal under the control of the potential of the first node and the potential of the second node;

[0061] The first node control circuit is used to control the potential of the first node;

[0062] The second node control circuit is electrically connected to the third node, the first clock signal terminal and the second node respectively, and is used to control the second node to be connected to the first clock signal terminal under the control of the potential of the third node;

[0063] The first end of the first energy storage circuit is electrically connected to the input end, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electric energy;

[0064] The third node control circuit is used to control the potential of the third node.

[0065] The driving circuit described in the embodiment of the present invention is additionally provided with a first energy storage circuit, and the first energy storage circuit is electrically connected to the input end and the third node respectively, so that in the Frame Skip interval, after the electrical position of the clock signal is high, the potential of the third node can maintain an effective voltage state for a long time, and under reliability conditions, at the potential of the third node, the transistor controlling the potential of the second node can still be closed, and does not affect the working state of the transistor whose gate is electrically connected to the second node included in the output circuit, so that the driving signal is output normally and the screen is displayed normally, thereby ensuring the product image quality and reducing power consumption, and meeting the terminal power consumption and image quality requirements.

[0066] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0067] In at least one embodiment of the present invention, the first node and the third node are the same node; or, the first node control circuit is electrically connected to the first voltage terminal, the third node and the first node, respectively, and is used to control the connection between the third node and the first node under the control of the first voltage signal provided by the first voltage terminal.

[0068] In a specific implementation, the first node may be the same node as the third node, or the first node control circuit may control the third node to be connected to the first node under the control of a first voltage signal.

[0069] like Figure 1As shown, the driving circuit according to at least one embodiment of the present invention includes an output circuit 10, a first energy storage circuit 11, a first node control circuit 12, a second node control circuit 13 and a third node control circuit 14;

[0070] The output circuit 10 is electrically connected to the first node N1, the second node N2 and the driving output terminal OUT respectively, and is used to control the output of the driving signal through the driving output terminal OUT under the control of the potential of the first node N1 and the potential of the second node N2;

[0071] A first end of the first energy storage circuit 11 is electrically connected to the input end STV, a second end of the first energy storage circuit 11 is electrically connected to the third node N3, and the first energy storage circuit 11 is used to store electric energy;

[0072] The first node control circuit 12 is electrically connected to the first node N1, the third node N3 and the first voltage terminal V1 respectively, and is used to control the third node N3 to be connected to the first node N1 under the control of the first voltage signal provided by the first voltage terminal V1;

[0073] The second node control circuit 13 is electrically connected to the third node N3, the first clock signal terminal CK and the second node N2 respectively, and is used to control the connection between the second node N2 and the first clock signal terminal CK under the control of the potential of the third node N3;

[0074] The third node control circuit 14 is electrically connected to the third node N3 and is used to control the potential of the third node N3.

[0075] The present invention Figure 1 When at least one embodiment of the driving circuit shown is working, in the Frame Skip interval, when the potential of the first clock signal provided by the first clock signal terminal CK is high, the potential of the third node can be kept at a high level for a long time through the first energy storage circuit. Under reliability conditions, the transistor whose gate is electrically connected to the second node included in the output circuit can still be closed without affecting the working state of the transistor, so that the driving circuit can output normally.

[0076] In at least one embodiment of the present invention, the output circuit includes a first output subcircuit and a second output subcircuit;

[0077] The first output subcircuit is electrically connected to the first node, the driving output terminal and the second clock signal terminal respectively, and is used to control the connection between the driving output terminal and the second clock signal terminal under the control of the potential of the first node;

[0078] The second output subcircuit is electrically connected to the second node, the driving output terminal and the second voltage terminal respectively, and is used to control the connection between the driving output terminal and the second voltage terminal under the control of the potential of the second node.

[0079] In a specific implementation, the output circuit may include a first output sub-circuit and a second output sub-circuit, wherein the first output sub-circuit controls the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node; and the second output sub-circuit controls the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0080] Optionally, the second voltage terminal may be a high voltage terminal, but is not limited thereto.

[0081] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the output circuit includes a first output sub-circuit 101 and a second output sub-circuit 102;

[0082] The first output sub-circuit 101 is electrically connected to the first node N1, the driving output terminal OUT and the second clock signal terminal CB respectively, and is used to control the connection between the driving output terminal OUT and the second clock signal terminal CB under the control of the potential of the first node N1;

[0083] The second output sub-circuit 102 is electrically connected to the second node N2, the driving output terminal OUT and the second voltage terminal V2 respectively, and is used to control the connection between the driving output terminal OUT and the second voltage terminal V2 under the control of the potential of the second node.

[0084] In at least one embodiment of the present invention, the third node control circuit is electrically connected to the third node, the first clock signal terminal, the input terminal, the second node, the second voltage terminal and the second clock signal terminal, respectively, and is used to control the connection between the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third node and the second voltage terminal under the control of the potential of the second node and the second clock signal provided by the second clock signal terminal.

[0085] In a specific implementation, the third node control circuit can control the connection between the third node and the input terminal under the control of the first clock signal, and control the connection between the third node and the second voltage terminal under the control of the potential of the second node and the second clock signal.

[0086] The driving circuit described in at least one embodiment of the present invention further includes a second energy storage circuit and a third energy storage circuit;

[0087] The first end of the second energy storage circuit is electrically connected to the first node, the second end of the second energy storage circuit is electrically connected to the drive output end, and the second energy storage circuit is used for storing electrical energy;

[0088] The third energy storage circuit is electrically connected to the second node and is used for maintaining the potential of the second node.

[0089] In a specific implementation, the drive circuit may further include a second energy storage circuit and a third energy storage circuit. The second energy storage circuit is electrically connected to the first node and the drive output end respectively, the third energy storage circuit is electrically connected to the second node, the second energy storage circuit is used for controlling the potential of the first node, and the third energy storage circuit is used for maintaining the potential of the second node.

[0090] In at least one embodiment of the present invention, the second node control circuit is further electrically connected to the first clock signal terminal and the third voltage terminal respectively, and is used for controlling the connection between the second node and the third voltage terminal under the control of the first clock signal provided by the first clock signal terminal.

[0091] In a specific implementation, the second node control circuit may control the connection between the second node and the third voltage terminal under the control of the first clock signal.

[0092] Optionally, the third voltage terminal may be a low voltage terminal.

[0093] Such as Figure 3 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 2 shown,

[0094] The third node control circuit 14 is electrically connected to the third node N3, the first clock signal terminal CK, the input terminal STV, the second node N2, the second voltage terminal V2 and the second clock signal terminal CB respectively, and is used for controlling the connection between the third node N3 and the input terminal STV under the control of the first clock signal provided by the first clock signal terminal CK, and controlling the connection between the third node N3 and the second voltage terminal V2 under the control of the potential of the second node N2 and the second clock signal provided by the second clock signal terminal CB;

[0095] The drive circuit according to at least one embodiment of the present invention further includes a second energy storage circuit 32 and a third energy storage circuit 33;

[0096] The first end of the second energy storage circuit 32 is electrically connected to the first node N1, the second end of the second energy storage circuit 32 is electrically connected to the drive output end OUT, and the second energy storage circuit 32 is used for storing electrical energy;

[0097] The third energy storage circuit 33 is electrically connected to the second node N2, and is used to maintain the potential of the second node N2;

[0098] The second node control circuit 13 is also electrically connected to the third voltage terminal V3, and is used to control the connection between the second node N2 and the third voltage terminal V3 under the control of the first clock signal provided by the first clock signal terminal CK.

[0099] Optionally, the first energy storage circuit includes a first capacitor;

[0100] A first end of the first capacitor is electrically connected to the input end, and a second end of the first capacitor is electrically connected to the third node.

[0101] Optionally, the second node control circuit includes a first transistor;

[0102] A gate of the first transistor is electrically connected to the third node, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the second node.

[0103] Optionally, the second node control circuit further includes a second transistor;

[0104] A gate of the second transistor is electrically connected to the first clock signal terminal, a first electrode of the second transistor is electrically connected to the third voltage terminal, and a second electrode of the second transistor is electrically connected to the second node.

[0105] Optionally, the first node control circuit includes a third transistor;

[0106] A gate of the third transistor is electrically connected to the first voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the first node.

[0107] Optionally, the third node control circuit includes a fourth transistor, a fifth transistor and a sixth transistor;

[0108] The gate of the fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourth transistor is electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0109] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor;

[0110] A gate of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

[0111] Optionally, the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor;

[0112] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the driving output end;

[0113] A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to a DC voltage end.

[0114] Optionally, the DC voltage terminal may be a high voltage terminal, but is not limited thereto.

[0115] Optionally, the first output sub-circuit includes a seventh transistor, and the second output sub-circuit includes an eighth transistor;

[0116] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the driving output terminal, and the second electrode of the seventh transistor is electrically connected to the second clock signal terminal;

[0117] A gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second voltage terminal, and a second electrode of the eighth transistor is electrically connected to the driving output terminal.

[0118] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown,

[0119] The first energy storage circuit includes a first capacitor C1;

[0120] A first end of the first capacitor C1 is electrically connected to the input terminal STV, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0121] The second node control circuit includes a first transistor T1;

[0122] The gate of the first transistor T1 is electrically connected to the third node N3, the source of the first transistor T1 is electrically connected to the first clock signal terminal CK, and the drain of the first transistor T1 is electrically connected to the second node N2;

[0123] The second node control circuit further includes a second transistor T2;

[0124] The gate of the second transistor T2 is electrically connected to the first clock signal terminal CK, the source of the second transistor T2 is electrically connected to the low voltage terminal VGL, and the drain of the second transistor T2 is electrically connected to the second node N2;

[0125] The first node control circuit includes a third transistor T3;

[0126] The gate of the third transistor T3 is electrically connected to the low voltage terminal VGL, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the first node N1;

[0127] The third node control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6;

[0128] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK, the source of the fourth transistor T4 is electrically connected to the input terminal STV, and the drain of the fourth transistor T4 is electrically connected to the third node N3;

[0129] The gate of the fifth transistor T5 is electrically connected to the second node N2, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the source of the sixth transistor T6;

[0130] The gate of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the drain of the sixth transistor T6 is electrically connected to the third node N3;

[0131] The second energy storage circuit includes a second capacitor C2, and the third energy storage circuit includes a third capacitor C3;

[0132] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the driving output terminal OUT;

[0133] A first end of the third capacitor C3 is electrically connected to the second node N2, and a second end of the third capacitor is electrically connected to the high voltage terminal VGH;

[0134] The first output subcircuit includes a seventh transistor, and the second output subcircuit includes an eighth transistor;

[0135] The gate of the seventh transistor T7 is electrically connected to the first node N1, the source of the seventh transistor T7 is electrically connected to the driving output terminal OUT, and the drain of the seventh transistor T7 is electrically connected to the second clock signal terminal CB;

[0136] A gate of the eighth transistor T8 is electrically connected to the second node N2 , a source of the eighth transistor T8 is electrically connected to the high voltage terminal VGH, and a drain of the eighth transistor T8 is electrically connected to the driving output terminal OUT.

[0137] exist Figure 4 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0138] like Figure 5 As shown, the present invention Figure 4 In at least one embodiment of the driving circuit shown in the figure, when working, the display cycle includes an input stage S1, an output stage S2, an output reset stage S3 and an output cut-off stage S4 which are arranged in sequence; after the display cycle, it enters the Frame Skip interval, and both CK and CB output high voltage signals; Figure 5 Among them, the one labeled SF is the frame skipping stage;

[0139] In the input stage S1, STV provides a low voltage signal, CK provides a low voltage signal, and CB provides a high voltage signal, such as Fig. 6A As shown, T4 and T2 are turned on, T1, T5 and T8 are turned on, T6 is turned off, T7 is turned on, and OUT outputs a high voltage signal;

[0140] In the output stage S2, STV provides a high voltage signal, CK provides a high voltage signal, and CB provides a low voltage signal, such as Figure 6B As shown, T4 and T2 are turned off. Due to the bootstrap effect of C1, the potential of N3 is pulled up, T1 switches from the on state to the off state, T8 changes from the on state to the off state, T5 is turned off, T7 is turned on, and OUT outputs a low voltage signal;

[0141] In the output reset phase S3, STV provides a high voltage signal, CK provides a low voltage signal, and CB provides a high voltage signal, such as Figure 6C As shown, T4 and T2 are turned on, T1 is turned off, T8 is turned on, T5 is turned on, T7 is turned off, and OUT outputs a high voltage signal;

[0142] In the output cut-off stage S4, STV provides a high voltage signal, CK provides a high voltage signal, and CB provides a low voltage signal, such as Fig.6D As shown, T4, T1 and T2 are turned off, T5 and T6 are turned on, T7 is turned off, T8 is turned on, and OUT outputs a high voltage signal;

[0143] In the frame skipping stage SF, STV, CK and CB all provide high voltage signals, such as Fig. 6EAs shown, T4, T1 and T2 are turned off, T5 is turned on, T7 is turned off, T6 is turned off, T8 is turned on, and OUT outputs a high voltage signal; due to the existence of C1, the potential of N3 is maintained at a high voltage, T1 remains in the off state, T8 is normally open, and OUT continuously outputs a high voltage signal.

[0144] The present invention Figure 4 When at least one embodiment of the driving circuit shown is working, in the frame skipping stage SF, due to the existence of C1, the gate potential of T2 remains in a high level state for a long time. Under the reliability condition, T1 can still be closed without affecting the working state of T8. OUT normally outputs a high voltage signal, and the display screen displays normally, ensuring the product image quality and reducing power consumption, thereby meeting the terminal power consumption and image quality requirements.

[0145] The driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:

[0146] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node;

[0147] A first node control circuit controls the potential of the first node;

[0148] The second node control circuit controls the connection between the second node and the first clock signal terminal under the control of the potential of the third node;

[0149] The first energy storage circuit controls the potential of the third node according to an input signal provided by the input terminal;

[0150] The third node control circuit controls the potential of the third node.

[0151] The display device described in the embodiment of the present invention includes the above-mentioned pixel circuit.

[0152] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, It is characterized in that It includes an output circuit, a first node control circuit, a second node control circuit, a third node control circuit and a first energy storage circuit; The output circuit is electrically connected to the first node, the second node and the driving output terminal respectively, and is used to control the output of the driving signal through the driving output terminal under the control of the potential of the first node and the potential of the second node; The first node control circuit is used to control the potential of the first node; The second node control circuit is electrically connected to the third node, the first clock signal terminal and the second node respectively, and is used to control the second node to be connected to the first clock signal terminal under the control of the potential of the third node; The first end of the first energy storage circuit is electrically connected to the input end, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electric energy; The third node control circuit is used to control the potential of the third node.

2. The driving circuit according to claim 1, It is characterized in that The first node and the third node are the same node; or, The first node control circuit is electrically connected to the first voltage terminal, the third node and the first node respectively, and is used to control the connection between the third node and the first node under the control of a first voltage signal provided by the first voltage terminal.

3. The driving circuit according to claim 1, It is characterized in that The third node control circuit is electrically connected to the third node, the first clock signal terminal, the input terminal, the second node, the second voltage terminal and the second clock signal terminal, respectively, and is used to control the connection between the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third node and the second voltage terminal under the control of the potential of the second node and the second clock signal provided by the second clock signal terminal.

4. The driving circuit according to claim 1, It is characterized in that Also comprising a second energy storage circuit and a third energy storage circuit; A first end of the second energy storage circuit is electrically connected to the first node, a second end of the second energy storage circuit is electrically connected to the driving output end, and the second energy storage circuit is used to store electric energy; The third energy storage circuit is electrically connected to the second node and is used to maintain the potential of the second node.

5. The driving circuit according to claim 1, It is characterized in that The second node control circuit is also electrically connected to the third voltage terminal, and is used to control the connection between the second node and the third voltage terminal under the control of the first clock signal provided by the first clock signal terminal.

6. The driving circuit according to claim 1, It is characterized in that The output circuit includes a first output subcircuit and a second output subcircuit; The first output subcircuit is electrically connected to the first node, the driving output terminal and the second clock signal terminal respectively, and is used to control the connection between the driving output terminal and the second clock signal terminal under the control of the potential of the first node; The second output subcircuit is electrically connected to the second node, the driving output terminal and the second voltage terminal respectively, and is used to control the connection between the driving output terminal and the second voltage terminal under the control of the potential of the second node.

7. The driving circuit according to claim 1, It is characterized in that The first energy storage circuit includes a first capacitor; A first end of the first capacitor is electrically connected to the input end, and a second end of the first capacitor is electrically connected to the third node.

8. The driving circuit according to claim 1, It is characterized in that The second node control circuit includes a first transistor; A gate of the first transistor is electrically connected to the third node, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the second node.

9. The driving circuit according to claim 5, It is characterized in that The second node control circuit further includes a second transistor; A gate of the second transistor is electrically connected to the first clock signal terminal, a first electrode of the second transistor is electrically connected to the third voltage terminal, and a second electrode of the second transistor is electrically connected to the second node.

10. The driving circuit according to claim 2, It is characterized in that The first node control circuit includes a third transistor; A gate of the third transistor is electrically connected to the first voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the first node.

11. The driving circuit according to claim 3, It is characterized in that The third node control circuit includes a fourth transistor, a fifth transistor and a sixth transistor; The gate of the fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourth transistor is electrically connected to the input terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; A gate of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

12. The driving circuit according to claim 4, It is characterized in that The second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the driving output end; A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to a DC voltage end.

13. The driving circuit according to claim 6, It is characterized in that The first output subcircuit includes a seventh transistor, and the second output subcircuit includes an eighth transistor; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the driving output terminal, and the second electrode of the seventh transistor is electrically connected to the second clock signal terminal; A gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second voltage terminal, and a second electrode of the eighth transistor is electrically connected to the driving output terminal.

14. A driving method, applied to the driving circuit according to any one of claims 1 to 13, It is characterized in that The driving method comprises: The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node; A first node control circuit controls the potential of the first node; The second node control circuit controls the connection between the second node and the first clock signal terminal under the control of the potential of the third node; The first energy storage circuit controls the potential of the third node according to an input signal provided by the input terminal; The third node control circuit controls the potential of the third node.

15. A display device, It is characterized in that The method comprises a pixel circuit as claimed in any one of claims 1 to 13.

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