Pixel circuit, driving method and display device

Abstract

The invention provides a pixel circuit, a driving method and a display device. The pixel circuit comprises a driving circuit, a compensation control circuit, a setting circuit, a data write-in circuit, a first energy storage circuit and a second energy storage circuit, the setting circuit writes a setting voltage into the third node under the control of a first scanning signal; the first end of the first energy storage circuit is electrically connected with the energy storage node, and the second end of the first energy storage circuit is electrically connected with the third node; the first end of the second energy storage circuit is electrically connected with the fourth node, and the second end of the second energy storage circuit is electrically connected with the first node; the data write-in circuit provides the data voltage to the fourth node under the control of the second scanning signal. According to the invention, the writing time of the data voltage can be ensured, the pixel circuit can be fully charged through the data voltage on the premise of ensuring the display uniformity, and the display effect is ensured.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device. Background Art

[0002] The related pixel circuit cannot guarantee the data voltage writing time during high-frequency display, and cannot fully charge the pixel circuit through the data voltage under the premise of ensuring display uniformity. Summary of the invention

[0003] The main purpose of the present invention is to provide a pixel circuit, a driving method and a display device to solve the problem that the existing pixel circuit cannot guarantee the data voltage writing time during high-frequency display and cannot fully charge the pixel circuit through the data voltage under the premise of ensuring display uniformity.

[0004] In one aspect, an embodiment of the present invention provides a pixel circuit, including a driving circuit, a compensation control circuit, a setting circuit, a data writing circuit, a first energy storage circuit and a second energy storage circuit;

[0005] The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the third node, and the driving circuit is used to generate a driving current under the control of the potential of the first node;

[0006] The compensation control circuit is electrically connected to the first scanning end, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the first scanning signal provided by the first scanning end;

[0007] The set circuit is electrically connected to the first scan terminal, the set voltage terminal and the third node respectively, and is used to write the set voltage provided by the set voltage terminal into the third node under the control of the first scan signal;

[0008] The first end of the first energy storage circuit is electrically connected to the energy storage node, and the second end of the first energy storage circuit is electrically connected to the third node;

[0009] The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the first node;

[0010] The data writing circuit is electrically connected to the second scanning end, the data line and the fourth node respectively, and is used to provide the data voltage provided by the data line to the fourth node under the control of the second scanning signal provided by the second scanning end.

[0011] Optionally, the energy storage node is the first node or the fourth node.

[0012] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit and a second initialization circuit;

[0013] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the fourth node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal;

[0014] The second initialization circuit is electrically connected to the third scanning terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the third scanning signal provided by the third scanning terminal;

[0015] The first initial control end is the first scanning end or the third scanning end.

[0016] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a third initialization circuit and a fourth initialization circuit;

[0017] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0018] The second light emitting control circuit is electrically connected to the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal;

[0019] The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal;

[0020] The fourth initialization circuit is electrically connected to the third scan terminal, the fourth initial voltage terminal and the second node respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the second node under the control of the third scan signal provided by the third scan terminal;

[0021] The second electrode of the light emitting element is electrically connected to the low level end;

[0022] The third initial control end is the first scanning end, the second scanning end or the third scanning end.

[0023] Optionally, the driving circuit includes a driving transistor, the setting circuit includes a first transistor, the data writing circuit includes a second transistor, the compensation control circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0024] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0025] The gate of the first transistor is electrically connected to the first scanning terminal, the first electrode of the first transistor is electrically connected to the set voltage terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0026] The gate of the second transistor is electrically connected to the second scanning end, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;

[0027] The gate of the third transistor is electrically connected to the first scanning end, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the fourth node;

[0028] The first end of the first capacitor is electrically connected to the energy storage node, and the second end of the first capacitor is electrically connected to the third node;

[0029] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the first node.

[0030] Optionally, the first initialization circuit includes a fourth transistor, and the second initialization circuit includes a fifth transistor;

[0031] The gate of the fourth transistor is electrically connected to the first initial control terminal, the first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node;

[0032] A gate of the fifth transistor is electrically connected to the third scanning terminal, a first electrode of the fifth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first node.

[0033] Optionally, the first light emitting control circuit includes a sixth transistor, the second light emitting control circuit includes a seventh transistor, the third initialization circuit includes an eighth transistor, and the fourth initialization circuit includes a ninth transistor;

[0034] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the first electrode of the sixth transistor is electrically connected to the second node;

[0035] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the first electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element;

[0036] The gate of the eighth transistor is electrically connected to the third initial control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the first electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element;

[0037] A gate of the ninth transistor is electrically connected to the third scanning terminal, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second node.

[0038] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned pixel circuit, wherein a display period includes a compensation phase, a data writing phase and a light emitting phase which are arranged in sequence; the driving method includes:

[0039] In the compensation stage, the setting circuit writes the setting voltage into the third node under the control of the first scanning signal, and the compensation control circuit controls the connection between the first node and the second node under the control of the first scanning signal;

[0040] At the beginning of the compensation phase, the driving circuit controls the connection between the second node and the third node under the control of the potential of the first node, and changes the potential of the first node until the driving circuit is turned off;

[0041] In the data writing phase, the data writing circuit provides a data voltage to the fourth node under the control of the second scanning signal;

[0042] During the light-emitting phase, the driving circuit generates a driving current.

[0043] Optionally, the pixel circuit further includes a second initialization circuit and a fourth initialization circuit; the display cycle further includes an initialization phase; the initialization phase is arranged before the compensation phase; the driving method further includes:

[0044] In the initialization stage, the second initialization circuit writes a second initial voltage to the first node under the control of the third scanning signal, so that when the compensation stage starts, the driving circuit can control the connection between the second node and the third node under the control of the potential of the first node, and the fourth initialization circuit writes a fourth initial voltage to the second node under the control of the third scanning signal.

[0045] Optionally, when the display refresh frequency is lower than the first frequency, the compensation phase lasts longer than the first time;

[0046] When the display refresh frequency is greater than or equal to the first frequency, the duration of the compensation phase is less than or equal to the second time;

[0047] The first time is greater than or equal to the second time.

[0048] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned pixel circuit.

[0049] Optionally, the pixel circuit is electrically connected to at least one control signal terminal; the display device further comprises at least one GOA module; the at least one control signal terminal comprises at least one of a first scanning terminal, a second scanning terminal, a third scanning terminal, and a light emitting control terminal;

[0050] The GOA module includes a multi-stage GOA circuit; the GOA circuit includes a generation circuit and a control circuit;

[0051] The generating circuit is used to generate a first driving control signal, a second driving control signal and a third driving control signal, and provides the first driving control signal through the first driving control terminal, provides the second driving control signal through the second driving control terminal, and provides the third driving control signal through the third driving control terminal;

[0052] The control circuit includes an output circuit and an output reset circuit;

[0053] The output circuit is electrically connected to the control signal terminal, the first drive control terminal, the second drive control terminal, the first output clock signal terminal, and the second output clock signal terminal, respectively, and is used to control the connection or disconnection between the control signal terminal and the first output clock signal terminal under the control of the first drive control signal, and to control the connection or disconnection between the control signal terminal and the second output clock signal terminal under the control of the second drive control signal;

[0054] The output reset circuit is electrically connected to the control signal terminal, the third drive control terminal, the output node, the first voltage control terminal, the second voltage control terminal, the first voltage terminal and the second voltage terminal, respectively, and is used to write the first voltage signal provided by the first voltage terminal into the output node under the control of the first voltage control signal provided by the first voltage control terminal, write the second voltage signal provided by the second voltage terminal into the output node under the control of the second voltage control signal provided by the second voltage control terminal, and control the connection or disconnection between the output node and the control signal terminal under the control of the third drive control signal.

[0055] Optionally, the output circuit is used to control the connection between the control signal terminal and the first output clock signal terminal under the control of the first drive control signal when the frequency is refreshed at a high frequency, and to control the connection between the control signal terminal and the second output clock signal terminal under the control of the second drive control signal when the frequency is refreshed at a low frequency;

[0056] The output reset circuit is used to write the first voltage signal to the output node under the control of the first voltage control signal when displaying at low brightness, and to write the second voltage signal to the output node under the control of the second voltage control signal when displaying at high brightness;

[0057] The frequency of the first output clock signal provided by the first output clock signal terminal is greater than the frequency of the second output clock signal provided by the second output clock signal terminal;

[0058] The transistor controlled by the control signal end is an n-type transistor, and the voltage value of the first voltage signal is less than the voltage value of the second voltage signal; or, the transistor controlled by the control signal end is a p-type transistor, and the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal.

[0059] Optionally, a rising time of the first output clock signal is shorter than a rising time of the second output clock signal, and a falling time of the first output clock signal is shorter than a falling time of the second output clock signal.

[0060] Optionally, the output circuit includes a first transistor and a second transistor, and the output reset circuit includes a third transistor, a fourth transistor and a fifth transistor;

[0061] The gate of the first transistor is electrically connected to the first driving control terminal, the first electrode of the first transistor is electrically connected to the first output clock signal terminal, and the second electrode of the first transistor is electrically connected to the control signal terminal;

[0062] The gate of the second transistor is electrically connected to the second driving control terminal, the first electrode of the second transistor is electrically connected to the second output clock signal terminal, and the second electrode of the second transistor is electrically connected to the control signal terminal;

[0063] The gate of the third transistor is electrically connected to the first voltage control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output node;

[0064] The gate of the fourth transistor is electrically connected to the second voltage control terminal, the first electrode of the fourth transistor is electrically connected to the second voltage terminal, and the second electrode of the fourth transistor is electrically connected to the output node;

[0065] A gate of the fifth transistor is electrically connected to the third driving control terminal, a first electrode of the fifth transistor is electrically connected to the output node, and a second electrode of the fifth transistor is electrically connected to the control signal terminal.

[0066] The pixel circuit, driving method and display device described in the embodiments of the present invention design data voltage writing and threshold voltage compensation separately, and the required scanning time for one line is relatively short, so that the data voltage writing time can be guaranteed during high-frequency display. Under the premise of ensuring display uniformity, the pixel circuit can be fully charged by the data voltage to ensure the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0068] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0069] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0070] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0071] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0072] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0073] Figure 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0074] Figure 8 yes Figure 7 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0075] Fig. 9 is a circuit diagram of at least one embodiment of a pixel circuit and a GOA (Gate On Array, a gate driving circuit disposed on an array substrate) circuit included in a display device according to at least one embodiment of the present invention;

[0076] Fig.10 yes Figure 7 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0077] Fig.11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0078] Fig.12 is a structural diagram of at least one embodiment of a GOA circuit in a display device according to the present invention. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0080] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0081] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0082] The pixel circuit described in the embodiment of the present invention includes a driving circuit, a compensation control circuit, a setting circuit, a data writing circuit, a first energy storage circuit and a second energy storage circuit;

[0083] The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the third node, and the driving circuit is used to generate a driving current under the control of the potential of the first node;

[0084] The compensation control circuit is electrically connected to the first scanning end, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the first scanning signal provided by the first scanning end;

[0085] The set circuit is electrically connected to the first scan terminal, the set voltage terminal and the third node respectively, and is used to write the set voltage provided by the set voltage terminal into the third node under the control of the first scan signal;

[0086] The first end of the first energy storage circuit is electrically connected to the energy storage node, and the second end of the first energy storage circuit is electrically connected to the third node;

[0087] The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the first node;

[0088] The data writing circuit is electrically connected to the second scanning end, the data line and the fourth node respectively, and is used to provide the data voltage provided by the data line to the fourth node under the control of the second scanning signal provided by the second scanning end.

[0089] When the pixel circuit described in the embodiment of the present invention is working, the data voltage writing and the threshold voltage compensation are designed separately, and the required scanning time for one line is short, so that the data voltage writing time can be guaranteed during high-frequency display. Under the premise of ensuring display uniformity, the pixel circuit can be fully charged by the data voltage to ensure the display effect.

[0090] Optionally, the energy storage node may be the first node or the fourth node.

[0091] like Figure 1 As shown, the pixel circuit according to the embodiment of the present invention includes a driving circuit 10, a compensation control circuit 11, a setting circuit 12, a data writing circuit 13, a first energy storage circuit 14 and a second energy storage circuit 15;

[0092] The control end of the driving circuit 10 is electrically connected to the first node N1, the first end of the driving circuit 10 is electrically connected to the second node N2, the second end of the driving circuit 10 is electrically connected to the third node N3, and the driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1;

[0093] The compensation control circuit 11 is electrically connected to the first scanning terminal S1, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the second node N2 under the control of the first scanning signal provided by the first scanning terminal S1;

[0094] The setting circuit 12 is electrically connected to the first scanning terminal S1, the setting voltage terminal VS and the third node N3 respectively, and is used to write the setting voltage Vs provided by the setting voltage terminal VS into the third node N3 under the control of the first scanning signal;

[0095] The first end of the first energy storage circuit 14 is electrically connected to the first node N1, and the second end of the first energy storage circuit 14 is electrically connected to the third node N3;

[0096] The first end of the second energy storage circuit 15 is electrically connected to the fourth node N4, and the second end of the second energy storage circuit 15 is electrically connected to the first node N1;

[0097] The data writing circuit 13 is electrically connected to the second scanning terminal S2, the data line DL and the fourth node N4 respectively, and is used to provide the data voltage Vdata provided by the data line DL to the fourth node N4 under the control of the second scanning signal provided by the second scanning terminal S2.

[0098] The present invention Figure 1 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a compensation phase, a data writing phase and a light emitting phase which are arranged in sequence; and the driving method includes:

[0099] In the compensation stage, the setting circuit 12 writes the setting voltage Vs into the third node N3 under the control of the first scanning signal, and the compensation control circuit 11 controls the connection between the first node N1 and the second node N2 under the control of the first scanning signal;

[0100] At the beginning of the compensation phase, the driving circuit 10 controls the second node N2 and the third node N3 to be connected under the control of the potential of the first node N1, so as to charge the second energy storage circuit 15 through the set voltage Vs, so as to change the potential of the first node N1, until the driving circuit 10 is turned off;

[0101] In the data writing phase, the data writing circuit 13 provides the data voltage Vdata to the fourth node N4 under the control of the second scanning signal;

[0102] In the light emitting stage, the driving circuit 10 generates a driving current.

[0103] The present invention Figure 1 At least one embodiment of the pixel circuit shown in the figure separately designs the data voltage writing and the threshold voltage compensation when working, and the required scanning time for one row is shorter, so that the data voltage writing time can be guaranteed during high-frequency display. Under the premise of ensuring display uniformity, the pixel circuit can be fully charged by the data voltage to ensure the display effect.

[0104] like Figure 2 As shown, the pixel circuit according to the embodiment of the present invention includes a driving circuit 10, a compensation control circuit 11, a setting circuit 12, a data writing circuit 13, a first energy storage circuit 14 and a second energy storage circuit 15;

[0105] The control end of the driving circuit 10 is electrically connected to the first node N1, the first end of the driving circuit 10 is electrically connected to the second node N2, the second end of the driving circuit 10 is electrically connected to the third node N3, and the driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1;

[0106] The compensation control circuit 11 is electrically connected to the first scanning terminal S1, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the second node N2 under the control of the first scanning signal provided by the first scanning terminal S1;

[0107] The setting circuit 12 is electrically connected to the first scanning terminal S1, the setting voltage terminal VS and the third node N3 respectively, and is used to write the setting voltage Vs provided by the setting voltage terminal VS into the third node N3 under the control of the first scanning signal;

[0108] The first end of the first energy storage circuit 14 is electrically connected to the fourth node N4, and the second end of the first energy storage circuit 14 is electrically connected to the third node N3;

[0109] The first end of the second energy storage circuit 15 is electrically connected to the fourth node N4, and the second end of the second energy storage circuit 15 is electrically connected to the first node N1;

[0110] The data writing circuit 13 is electrically connected to the second scanning terminal S2, the data line DL and the fourth node N4 respectively, and is used to provide the data voltage Vdata provided by the data line DL to the fourth node N4 under the control of the second scanning signal provided by the second scanning terminal S2.

[0111] The present invention Figure 2 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a compensation phase, a data writing phase and a light emitting phase which are arranged in sequence; and the driving method includes:

[0112] In the compensation stage, the setting circuit 12 writes the setting voltage Vs into the third node N3 under the control of the first scanning signal, and the compensation control circuit 11 controls the connection between the first node N1 and the second node N2 under the control of the first scanning signal;

[0113] At the beginning of the compensation phase, the driving circuit 10 controls the second node N2 and the third node N3 to be connected under the control of the potential of the first node N1, so as to charge the second energy storage circuit 15 through the set voltage Vs, so as to change the potential of the first node N1, until the driving circuit 10 is turned off;

[0114] In the data writing phase, the data writing circuit 13 provides the data voltage Vdata to the fourth node N4 under the control of the second scanning signal;

[0115] In the light emitting stage, the driving circuit 10 generates a driving current.

[0116] The present invention Figure 2At least one embodiment of the pixel circuit shown in the figure separately designs the data voltage writing and the threshold voltage compensation when working, and the required scanning time for one row is shorter, so that the data voltage writing time can be guaranteed during high-frequency display. Under the premise of ensuring display uniformity, the pixel circuit can be fully charged by the data voltage to ensure the display effect.

[0117] The pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit and a second initialization circuit;

[0118] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the fourth node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal;

[0119] The second initialization circuit is electrically connected to the third scanning terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the third scanning signal provided by the third scanning terminal;

[0120] The first initial control end is the first scanning end or the third scanning end.

[0121] In a specific implementation, the pixel circuit may further include a first initialization circuit and a second initialization circuit; the first initialization circuit, under the control of a first initial control signal, writes a first initial voltage into the fourth node to reset the potential of the fourth node; the second initialization circuit, under the control of the third scanning signal, writes the second initial voltage into the first node to reset the potential of the first node.

[0122] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 31 and a second initialization circuit 32;

[0123] The first initialization circuit 31 is electrically connected to the third scan terminal S3, the first initial voltage terminal I1 and the fourth node N4 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the third scan signal provided by the third scan terminal S3;

[0124] The second initialization circuit 32 is electrically connected to the third scan terminal S3, the second initial voltage terminal I2 and the first node N1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the third scan signal provided by the third scan terminal S3, so that at the beginning of the compensation phase, the driving transistor included in the driving circuit 10 can be turned on.

[0125] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 31 and a second initialization circuit 32;

[0126] The first initialization circuit 31 is electrically connected to the third scan terminal S3, the first initial voltage terminal I1 and the fourth node N4 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the third scan signal provided by the third scan terminal S3;

[0127] The second initialization circuit 32 is electrically connected to the third scan terminal S3, the second initial voltage terminal I2 and the first node N1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the third scan signal provided by the third scan terminal S3, so that at the beginning of the compensation phase, the driving transistor included in the driving circuit 10 can be turned on.

[0128] The pixel circuit described in at least one embodiment of the present invention further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a third initialization circuit and a fourth initialization circuit;

[0129] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0130] The second light emitting control circuit is electrically connected to the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal;

[0131] The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal;

[0132] The fourth initialization circuit is electrically connected to the third scan terminal, the fourth initial voltage terminal and the second node respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the second node under the control of the third scan signal provided by the third scan terminal;

[0133] The second electrode of the light emitting element is electrically connected to the low level end;

[0134] The third initial control end is the first scanning end, the second scanning end or the third scanning end.

[0135] In a specific implementation, the pixel circuit may further include a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a third initialization circuit and a fourth initialization circuit; the first light-emitting control circuit and the second light-emitting control circuit are used for light-emitting control, and the third initialization circuit, under the control of a third initial control signal, writes a third initial voltage into the first electrode of the light-emitting element to clear the residual charge at the first electrode of the light-emitting element; the fourth initialization circuit, under the control of a third scanning signal, writes the fourth initial voltage into the second node to effectively improve the hysteresis effect caused by the grayscale difference between adjacent pixels under low brightness, and improve the ghosting phenomenon.

[0136] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present invention further includes a light emitting element E1, a first light emitting control circuit 51, a second light emitting control circuit 52, a third initialization circuit 53 and a fourth initialization circuit 54;

[0137] The first light emitting control circuit 51 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0138] The second light emitting control circuit 52 is electrically connected to the light emitting control terminal EM, the third node N3 and the first electrode of the light emitting element E1 respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0139] The third initialization circuit 53 is electrically connected to the third scanning terminal S3, the third initial voltage terminal I3 and the first electrode of the light emitting element E1 respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light emitting element E1 under the control of the third initial control signal provided by the third scanning terminal S3;

[0140] The fourth initialization circuit 54 is electrically connected to the third scan terminal S3, the fourth initial voltage terminal I4 and the second node N2 respectively, and is used to write the fourth initial voltage Vinit4 provided by the fourth initial voltage terminal I4 into the second node N2 under the control of the third scan signal provided by the third scan terminal S3;

[0141] The second electrode of the light emitting element E1 is electrically connected to the low level end ELVSS.

[0142] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present invention further includes a light emitting element E1, a first light emitting control circuit 51, a second light emitting control circuit 52, a third initialization circuit 53 and a fourth initialization circuit 54;

[0143] The first light emitting control circuit 51 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0144] The second light emitting control circuit 52 is electrically connected to the light emitting control terminal EM, the third node N3 and the first electrode of the light emitting element E1 respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0145] The third initialization circuit 53 is electrically connected to the third scanning terminal S3, the third initial voltage terminal I3 and the first electrode of the light emitting element E1 respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light emitting element E1 under the control of the third initial control signal provided by the third scanning terminal S3;

[0146] The fourth initialization circuit 54 is electrically connected to the third scan terminal S3, the fourth initial voltage terminal I4 and the second node N2 respectively, and is used to write the fourth initial voltage Vinit4 provided by the fourth initial voltage terminal I4 into the second node N2 under the control of the third scan signal provided by the third scan terminal S3;

[0147] The second electrode of the light emitting element E1 is electrically connected to the low level end ELVSS.

[0148] In at least one embodiment of the present invention, the transistor included in the pixel circuit may be a top-gate structure TFT (thin film transistor);

[0149] In a top-gate structure TFT, the overlapping area between the orthographic projection of the gate on the substrate and the orthographic projection of the source on the substrate is small, and the overlapping area between the orthographic projection of the gate on the substrate and the orthographic projection of the drain on the substrate is small, which can reduce the existence of parasitic capacitance; at the same time, the top-gate structure TFT has the advantage of reducing the circuit capacitive load and the gate line RC (resistance-capacitance) load.

[0150] Optionally, the driving circuit includes a driving transistor, the setting circuit includes a first transistor, the data writing circuit includes a second transistor, the compensation control circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0151] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0152] The gate of the first transistor is electrically connected to the first scanning terminal, the first electrode of the first transistor is electrically connected to the set voltage terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0153] The gate of the second transistor is electrically connected to the second scanning end, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;

[0154] The gate of the third transistor is electrically connected to the first scanning end, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the fourth node;

[0155] The first end of the first capacitor is electrically connected to the first node or the fourth node, and the second end of the first capacitor is electrically connected to the third node;

[0156] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the first node.

[0157] Optionally, the first initialization circuit includes a fourth transistor, and the second initialization circuit includes a fifth transistor;

[0158] The gate of the fourth transistor is electrically connected to the first initial control terminal, the first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node;

[0159] A gate of the fifth transistor is electrically connected to the third scanning terminal, a first electrode of the fifth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first node.

[0160] Optionally, the first light emitting control circuit includes a sixth transistor, the second light emitting control circuit includes a seventh transistor, the third initialization circuit includes an eighth transistor, and the fourth initialization circuit includes a ninth transistor;

[0161] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the first electrode of the sixth transistor is electrically connected to the second node;

[0162] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the first electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element;

[0163] The gate of the eighth transistor is electrically connected to the third initial control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the first electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element;

[0164] A gate of the ninth transistor is electrically connected to the third scanning terminal, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second node.

[0165] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor DT, the setting circuit includes a first transistor T1, the data writing circuit includes a second transistor T2, the compensation control circuit includes a third transistor T3, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2; the light emitting element is an organic light emitting diode O1;

[0166] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;

[0167] The gate of the first transistor T1 is electrically connected to the first scanning terminal S1, the source of the first transistor T1 is electrically connected to the set voltage terminal VS, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0168] The gate of the second transistor T2 is electrically connected to the second scanning terminal S2, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the first transistor T2 is electrically connected to the second node N2;

[0169] The gate of the third transistor T3 is electrically connected to the first scanning terminal S1, the source of the third transistor T3 is electrically connected to the data line DL, and the drain of the third transistor T3 is electrically connected to the fourth node N4;

[0170] The first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3;

[0171] A first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the first node N1;

[0172] The first initialization circuit includes a fourth transistor T4, and the second initialization circuit includes a fifth transistor T5;

[0173] The gate of the fourth transistor T4 is electrically connected to the third scanning terminal S3, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4;

[0174] The gate of the fifth transistor T5 is electrically connected to the third scanning terminal S3, the source of the fifth transistor T5 is electrically connected to the second initial voltage terminal I2, and the drain of the fifth transistor T5 is electrically connected to the first node N1;

[0175] The first light emitting control circuit includes a sixth transistor T6, the second light emitting control circuit includes a seventh transistor T7, the third initialization circuit includes an eighth transistor T8, and the fourth initialization circuit includes a ninth transistor T9;

[0176] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal ELVDD, and the source of the sixth transistor T6 is electrically connected to the second node N2;

[0177] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, the drain of the seventh transistor T7 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;

[0178] The gate of the eighth transistor T8 is electrically connected to the third scanning terminal S3, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of O1;

[0179] A gate electrode of the ninth transistor T9 is electrically connected to the third scanning terminal S3, a first electrode of the ninth transistor T9 is electrically connected to the fourth initial voltage terminal I4, and a drain electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0180] exist Figure 7 In at least one embodiment of the pixel circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto. In a specific implementation, at least one of T1-T9 can be replaced by a p-type transistor.

[0181] like Figure 8 As shown, the present invention Figure 7 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include an initialization phase J1, a compensation phase J2, a data writing phase J3 and a light emitting phase J4 which are arranged successively;

[0182] In the initialization phase J1, EM provides a low voltage signal, S3 provides a high voltage signal, S1 and S2 both provide low voltage signals, T4, T5, T8 and T9 are all turned on, I1 provides a first initial voltage Vinit1 to N4, I2 provides a second initial voltage Vinit2 to N1, I3 provides a third initial voltage Vinit3 to the anode of O1, and I4 provides a fourth initial voltage Vinit4 to N2, and the potential of N1 and the potential of N4 are initialized, so that at the beginning of the compensation phase J2, DT can be turned on, and the residual charge of the anode of O1 can be cleared, and the hysteresis effect can be improved;

[0183] In the compensation phase J2, EM provides a low voltage signal, S3 provides a low voltage signal, S1 provides a high voltage signal, S2 provides a low voltage signal, VS provides a set voltage Vs to N3, and T3 is turned on;

[0184] At the beginning of the compensation phase J2, DT is turned on, and the potential of N1 is reduced by discharge. When the potential of N1 becomes Vs+Vth, DT is turned off, and the threshold voltage compensation is completed; wherein Vth is the threshold voltage of DT;

[0185] In the data writing phase J3, EM provides a low voltage signal, S3 provides a low voltage signal, S1 provides a low voltage signal, S2 provides a high voltage signal, T3 is turned on, DL provides a data voltage Vdata to N4, and the potential of N1 is changed accordingly, and the potential of N1 becomes Vs+Vth+Vdata-Vinit1;

[0186] In the light-emitting stage J4, EM provides a high voltage signal, S1, S2 and S3 all provide low voltage signals, T6 and T7 are turned on, and DT drives O1 to emit light. At this time, the gate-source voltage Vgs of DT is equal to Vdata-Vinit1; the light-emitting current of O1 is independent of Vth and Vdd, which can effectively avoid the crosstalk problem caused by the coupling of Vdata and Vdd; Vdd is the voltage value of the power supply voltage provided by ELVDD.

[0187] like Fig. 9 As shown, the display device described in at least one embodiment of the present invention may include at least one embodiment of a GOA (Gate On Array, a gate driving circuit disposed on an array substrate) circuit and Figure 7 At least one embodiment of the pixel circuit shown;

[0188] At least one embodiment of the GOA circuit may include a generating circuit 91 and a control circuit;

[0189] The generating circuit 91 is used to generate a first driving control signal, a second driving control signal and a third driving control signal, and provides the first driving control signal through the first driving control terminal DT1, provides the second driving control signal through the second driving control terminal DT2, and provides the second driving control signal through the third driving control terminal DT3;

[0190] The control circuit includes an output circuit and an output reset circuit;

[0191] The output circuit includes a first transistor M1 and a second transistor M2, and the output reset circuit includes a third transistor M3, a fourth transistor M4 and a fifth transistor M5;

[0192] The gate of the first transistor M1 is electrically connected to the first driving control terminal DT1, the source of the first transistor M1 is electrically connected to the first output clock signal terminal CK1, and the drain of the first transistor M1 is electrically connected to the third scanning terminal S3;

[0193] The gate of the second transistor M2 is electrically connected to the second driving control terminal DT2, the source of the second transistor M2 is electrically connected to the second output clock signal terminal CK2, and the drain of the second transistor M2 is electrically connected to the third scanning terminal S3;

[0194] The gate of the third transistor M3 is electrically connected to the first voltage control terminal VC1, the source of the third transistor M3 is electrically connected to the first low voltage terminal VGL1, and the drain of the third transistor M3 is electrically connected to the output node NS;

[0195] The gate of the fourth transistor M4 is electrically connected to the second voltage control terminal VC2, the source of the fourth transistor M4 is electrically connected to the second low voltage terminal VGL2, and the drain of the fourth transistor M4 is electrically connected to the output node NS;

[0196] A gate of the fifth transistor M5 is electrically connected to the third driving control terminal DT3 , a source of the fifth transistor M5 is electrically connected to the output node NS, and a drain of the fifth transistor M5 is electrically connected to the third scanning terminal S3 .

[0197] exist Fig. 9 In at least one embodiment shown, M1 - M5 are n-type transistors, but the present invention is not limited thereto.

[0198] The present invention Fig. 9 At least one embodiment of the pixel circuit shown in FIG. 1 is in operation.

[0199] When performing high-frequency refresh, when it is necessary to provide a valid third scan signal to the third scan terminal S3 (when the transistor controlled by the third scan terminal is an n-type transistor, the valid third scan signal can be a high voltage signal), DT1 provides a high voltage signal, DT2 and DT3 provide low voltage signals, M1 is turned on, M2 and M5 are turned off, and CK1 is connected to S3;

[0200] During low-frequency refresh, when a valid third scan signal needs to be provided to the third scan terminal S3, DT1 and DT3 provide low voltage signals, DT2 provides high voltage signals, M2 is turned on, M1 and M5 are turned off, and CK2 is connected to S3;

[0201] The frequency of the first output clock signal provided by CK1 is greater than the frequency of the second output clock signal provided by CK2; and the rise time of the first output clock signal is less than the rise time of the second output clock signal, and the fall time of the first output clock signal is less than the fall time of the second output clock signal. The first output clock signal has a higher driving capability than the second output clock signal, which effectively improves the ability of the third scanning signal to turn on the transistor, and can increase the level climbing speed of the third scanning signal when refreshing at a high frequency; when refreshing at a low frequency, CK2 provides the third scanning terminal with a third scanning signal, which can reduce power consumption at a low refresh rate; at the same time, using M1 and M2 as the output circuits of CK1 and CK2 can effectively improve the tolerance of the output circuit, thereby increasing the lifespan;

[0202] When it is necessary to provide an invalid third scan signal to the third scan terminal S3 (when the transistor controlled by the third scan terminal is an n-type transistor, the invalid third scan signal may be a low voltage signal),

[0203] When displaying at low brightness, DT1 and DT2 provide low voltage signals, DT3 provides high voltage signals; M1 and M2 are turned off, M5 is turned on, VC1 provides high voltage signals, VC2 provides low voltage signals; M3 is turned on, M4 is turned off, and NS is connected to VGL1;

[0204] When displaying at high brightness, DT1 and DT2 provide low voltage signals, DT3 provides high voltage signals; M1 and M2 are turned off, M5 is turned on, VC1 provides low voltage signals, VC2 provides high voltage signals; M3 is turned off, M4 is turned on, and NS is connected to VGL2;

[0205] T5, T8 and T4 are n-type transistors, and the voltage value of the first low voltage signal provided by VGL1 is less than the voltage value of the second low voltage signal provided by VGL2, so that when displaying at low brightness, T5, T8 and T4 can be closed more tightly, reducing the proportion of low-brightness leakage current, improving display uniformity, and saving power consumption when displaying at high brightness; using two transistors as the output reset unit of VGL1 and VGL2 can effectively improve the tolerance of the output reset unit, thereby increasing its service life.

[0206] Figure 7 At least one embodiment of the pixel circuit shown can directly skip the initialization phase and the compensation phase when working, for example, in high refresh rate situations, which is beneficial to improving the charging quality of the data voltage and thus improving the picture quality.

[0207] like Fig.10 As shown, Figure 7 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a data writing phase J3 and a light emitting phase J4 which are arranged successively;

[0208] In the data writing phase J3, S2 provides a high voltage signal, S1 and S2 provide a low voltage signal, EM provides a low voltage signal, T3 is turned on, and DL provides a data voltage Vdata to N4;

[0209] In the light-emitting stage J4, EM provides a high voltage signal, S1, S2 and S3 all provide low voltage signals, T6 and T7 are turned on, and DT drives O1 to emit light.

[0210] Fig.11 At least one embodiment of the pixel circuit shown is Figure 7 The difference of at least one embodiment of the pixel circuit shown is as follows: the first end of C1 is electrically connected to the fourth node N4.

[0211] When the pixel circuit described in at least one embodiment of the present invention is in operation,

[0212] In the case of low-frequency refresh, the display is unstable and the duration of the corresponding compensation phase needs to be increased;

[0213] In the case of high-frequency refresh, the display is stable and the duration of the corresponding compensation phase can be reduced.

[0214] The driving method described in the embodiment of the present invention is applied to the above-mentioned pixel circuit, and the display cycle includes a compensation phase, a data writing phase and a light emitting phase which are arranged in sequence; the driving method includes:

[0215] In the compensation stage, the setting circuit writes the setting voltage into the third node under the control of the first scanning signal, and the compensation control circuit controls the connection between the first node and the second node under the control of the first scanning signal;

[0216] At the beginning of the compensation phase, the driving circuit controls the connection between the second node and the third node under the control of the potential of the first node, and changes the potential of the first node until the driving circuit is turned off;

[0217] In the data writing phase, the data writing circuit provides a data voltage to the fourth node under the control of the second scanning signal;

[0218] During the light-emitting phase, the driving circuit generates a driving current.

[0219] In at least one embodiment of the present invention, the pixel circuit further includes a second initialization circuit and a fourth initialization circuit; the display cycle further includes an initialization phase; the initialization phase is arranged before the compensation phase; the driving method further includes:

[0220] In the initialization stage, the second initialization circuit writes a second initial voltage to the first node under the control of the third scanning signal, so that when the compensation stage starts, the driving circuit can control the connection between the second node and the third node under the control of the potential of the first node, and the fourth initialization circuit writes a fourth initial voltage to the second node under the control of the third scanning signal.

[0221] Optionally, when the display refresh frequency is lower than the first frequency, the compensation phase lasts longer than the first time;

[0222] When the display refresh frequency is greater than or equal to the first frequency, the duration of the compensation phase is less than or equal to the second time;

[0223] The first time is greater than or equal to the second time.

[0224] In at least one embodiment of the present invention, the first frequency may be greater than or equal to 20 Hz and less than or equal to 40 Hz. For example, the first frequency may be 20 Hz, 30 Hz or 40 Hz, but is not limited thereto.

[0225] The display device described in the embodiment of the present invention includes the above-mentioned pixel circuit.

[0226] In at least one embodiment of the present invention, the pixel circuit is electrically connected to at least one control signal terminal; the display device further includes at least one GOA module; the at least one control signal terminal includes at least one of a first scanning terminal, a second scanning terminal, a third scanning terminal, and a light emitting control terminal;

[0227] The GOA module includes a multi-stage GOA circuit; the GOA circuit includes a generation circuit and a control circuit;

[0228] The generating circuit is used to generate a first driving control signal, a second driving control signal and a third driving control signal, and provides the first driving control signal through the first driving control terminal, provides the second driving control signal through the second driving control terminal, and provides the third driving control signal through the third driving control terminal;

[0229] The control circuit includes an output circuit and an output reset circuit;

[0230] The output circuit is electrically connected to the control signal terminal, the first drive control terminal, the second drive control terminal, the first output clock signal terminal, and the second output clock signal terminal, respectively, and is used to control the connection or disconnection between the control signal terminal and the first output clock signal terminal under the control of the first drive control signal, and to control the connection or disconnection between the control signal terminal and the second output clock signal terminal under the control of the second drive control signal;

[0231] The output reset circuit is electrically connected to the control signal terminal, the third drive control terminal, the output node, the first voltage control terminal, the second voltage control terminal, the first voltage terminal and the second voltage terminal, respectively, and is used to write the first voltage signal provided by the first voltage terminal into the output node under the control of the first voltage control signal provided by the first voltage control terminal, write the second voltage signal provided by the second voltage terminal into the output node under the control of the second voltage control signal provided by the second voltage control terminal, and control the connection or disconnection between the output node and the control signal terminal under the control of the third drive control signal.

[0232] In at least one embodiment of the present invention, the output circuit is used to control the connection between the control signal terminal and the first output clock signal terminal under the control of the first drive control signal during high-frequency refreshing, and to control the connection between the control signal terminal and the second output clock signal terminal under the control of the second drive control signal during low-frequency refreshing;

[0233] The output reset circuit is used to write the first voltage signal to the output node under the control of the first voltage control signal when displaying at low brightness, and to write the second voltage signal to the output node under the control of the second voltage control signal when displaying at high brightness;

[0234] The frequency of the first output clock signal provided by the first output clock signal terminal is greater than the frequency of the second output clock signal provided by the second output clock signal terminal;

[0235] The transistor controlled by the control signal end is an n-type transistor, and the voltage value of the first voltage signal is less than the voltage value of the second voltage signal; or, the transistor controlled by the control signal end is a p-type transistor, and the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal.

[0236] In a specific implementation, when the transistor controlled by the control signal terminal is an n-type transistor, the first voltage signal may be a first low voltage signal, and the second voltage signal may be a second low voltage signal, and the voltage value of the first low voltage signal is less than the voltage value of the second voltage signal, so that when displaying at low brightness, the transistor controlled by the control signal terminal can be closed more tightly, reducing the proportion of low brightness leakage current, improving display uniformity, and saving power consumption when displaying at high brightness;

[0237] When the transistor controlled by the control signal end is a p-type transistor, the first voltage signal may be a first high voltage signal, the second voltage signal may be a second high voltage signal, and the voltage value of the first high voltage signal may be greater than the voltage value of the second high voltage signal, so that when displaying at low brightness, the transistor controlled by the control signal end can be closed tighter, reducing the proportion of low-brightness leakage current, improving display uniformity, and saving power consumption when displaying at high brightness.

[0238] In at least one embodiment of the present invention, a rising time of the first output clock signal is shorter than a rising time of the second output clock signal, and a falling time of the first output clock signal is shorter than a falling time of the second output clock signal.

[0239] In a specific implementation, the driving capability of the first output clock signal is stronger than that of the second output clock signal. The first output clock signal has a higher driving capability than the second output clock signal, which effectively improves the ability of the control signal provided by the control signal end to turn on the transistor, and can increase the level rising speed of the control signal during high-frequency refresh.

[0240] like Fig.12 As shown, at least one embodiment of the GOA circuit may include a generating circuit 111 and a control circuit;

[0241] The generating circuit 111 is used to generate a first driving control signal, a second driving control signal and a third driving control signal, and provides the first driving control signal through the first driving control terminal DT1, provides the second driving control signal through the second driving control terminal DT2, and provides the third driving control signal through the third driving control terminal DT3;

[0242] The control circuit includes an output circuit 121 and an output reset circuit 122;

[0243] The output circuit 121 is electrically connected to the control signal terminal SC, the first drive control terminal DT1, the second drive control terminal DT2, the first output clock signal terminal CK1 and the second output clock signal terminal CK2 respectively, and is used to control the connection or disconnection between the control signal terminal SC and the first output clock signal terminal CK1 under the control of the first drive control signal, and control the connection or disconnection between the control signal terminal SC and the second output clock signal terminal CK2 under the control of the second drive control signal;

[0244] The output reset circuit 122 is electrically connected to the control signal terminal SC, the third drive control terminal DT3, the output node NS, the first voltage control terminal VC1, the second voltage control terminal VC2, the first voltage terminal V1 and the second voltage terminal V2, respectively, and is used for writing the first voltage signal provided by the first voltage terminal V1 into the output node NS under the control of the first voltage control signal provided by the first voltage control terminal VC1, and writing the second voltage signal provided by the second voltage terminal V2 into the output node NS under the control of the second voltage control signal provided by the second voltage control terminal VC2, and controlling the connection or disconnection between the output node NS and the control signal terminal SC under the control of the third drive control signal.

[0245] In a specific implementation, the control signal terminal SC may be a first scanning terminal, a second scanning terminal, a third scanning terminal or a light emitting control terminal.

[0246] exist Fig.12In at least one embodiment shown, the output circuit 121 is used to control the connection between the control signal terminal SC and the first output clock signal terminal CK1 under the control of the first drive control signal when the frequency is refreshed at a high frequency, and to control the connection between the control signal terminal SC and the second output clock signal terminal CK2 under the control of the second drive control signal when the frequency is refreshed at a low frequency;

[0247] The output reset circuit 122 is used to write the first voltage signal into the output node NS under the control of the first voltage control signal when displaying at low brightness, and to write the second voltage signal into the output node NS under the control of the second voltage control signal when displaying at high brightness;

[0248] The frequency of the first output clock signal provided by the first output clock signal terminal CK1 is greater than the frequency of the second output clock signal provided by the second output clock signal terminal CK2;

[0249] When the transistor controlled by the control signal terminal is an n-type transistor, the voltage value of the first voltage signal is less than the voltage value of the second voltage signal;

[0250] When the transistor controlled by the control signal terminal is a p-type transistor, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal;

[0251] The rising time of the first output clock signal is shorter than the rising time of the second output clock signal, the falling time of the first output clock signal is shorter than the falling time of the second output clock signal, and the driving capability of the first output clock signal is stronger.

[0252] Fig.12 At least one embodiment shown in FIG. 1 is in operation.

[0253] When high-frequency refreshing is performed, when it is necessary to provide a valid control signal to the control signal terminal SC (when the transistor controlled by the control signal terminal is an n-type transistor, the valid control signal can be a high voltage signal; when the transistor controlled by the control signal terminal is a p-type transistor, the valid control signal can be a low voltage signal), the output circuit 121 controls the control signal terminal SC to be connected with the first output clock signal terminal CK1 under the control of the first drive control signal, the output circuit 121 controls the control signal terminal SC to be disconnected from the second output clock signal terminal CK2 under the control of the second drive control signal, and the output reset circuit 112 controls the output node NS to be disconnected from the control signal terminal SC under the control of the third drive control signal; CK1 is connected to SC;

[0254] When low-frequency refreshing is performed, when a valid control signal needs to be provided to the control signal terminal SC, the output circuit 121 controls the control signal terminal SC to be connected to the second output clock signal terminal CK2 under the control of the second drive control signal, the output circuit 121 controls the control signal terminal SC to be disconnected from the first output clock signal terminal CK1 under the control of the first drive control signal, and the output reset circuit 112 controls the output node NS to be disconnected from the control signal terminal SC under the control of the third drive control signal; CK2 is connected to SC;

[0255] The frequency of the first output clock signal provided by CK1 is greater than the frequency of the second output clock signal provided by CK2; and the rise time of the first output clock signal is less than the rise time of the second output clock signal, and the fall time of the first output clock signal is less than the fall time of the second output clock signal. The first output clock signal has a higher driving capability than the second output clock signal, which effectively improves the ability of the third scanning signal to turn on the transistor, and can increase the level climbing speed of the control signal during high-frequency refresh; during low-frequency refresh, CK2 provides a control signal to the control signal terminal, which can reduce power consumption during low refresh;

[0256] When it is necessary to provide an invalid control signal to the third scanning terminal S3 (when the transistor controlled by the control signal terminal is an n-type transistor, the invalid control signal may be a low voltage signal; when the transistor controlled by the control signal terminal is a p-type transistor, the invalid control signal may be a high voltage signal),

[0257] When displaying at low brightness, the output circuit 121 controls the control signal terminal SC to be disconnected from the first output clock signal terminal CK1 under the control of the first drive control signal, and the output circuit 121 controls the control signal terminal SC to be disconnected from the second output clock signal terminal CK2 under the control of the second drive control signal. The output reset circuit 112 controls the output node NS to be connected to the control signal terminal SC under the control of the third drive control signal; the output reset circuit 112 writes the first voltage signal provided by the first voltage terminal V1 to the output node NS under the control of the first voltage control signal provided by the first voltage control terminal VC1; SC is connected to V1;

[0258] When displaying at high brightness, the output circuit 121 controls the control signal terminal SC to be disconnected from the first output clock signal terminal CK1 under the control of the first drive control signal, and controls the control signal terminal SC to be disconnected from the second output clock signal terminal CK2 under the control of the second drive control signal. The output reset circuit 112 controls the output node NS to be connected to the control signal terminal SC under the control of the third drive control signal; the output reset circuit 112 writes the second voltage signal provided by the second voltage terminal V2 into the output node NS under the control of the second voltage control signal provided by the second voltage control terminal VC2; SC is connected to V2;

[0259] When the transistor controlled by the control signal terminal is an n-type transistor, the voltage value of the first voltage signal is less than the voltage value of the second voltage signal, so that when displaying at low brightness, the transistor controlled by the control signal terminal can be closed more tightly, reducing the proportion of low-brightness leakage current, improving display uniformity, and saving power consumption when displaying at high brightness;

[0260] When the transistor controlled by the control signal end is a p-type transistor, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, so that when displaying at low brightness, the transistor controlled by the control signal end can be closed tighter, reducing the proportion of low-brightness leakage current, improving display uniformity, and saving power consumption when displaying at high brightness.

[0261] Optionally, the output circuit includes a first transistor and a second transistor, and the output reset circuit includes a third transistor, a fourth transistor and a fifth transistor;

[0262] The gate of the first transistor is electrically connected to the first driving control terminal, the first electrode of the first transistor is electrically connected to the first output clock signal terminal, and the second electrode of the first transistor is electrically connected to the control signal terminal;

[0263] The gate of the second transistor is electrically connected to the second driving control terminal, the first electrode of the second transistor is electrically connected to the second output clock signal terminal, and the second electrode of the second transistor is electrically connected to the control signal terminal;

[0264] The gate of the third transistor is electrically connected to the first voltage control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output node;

[0265] The gate of the fourth transistor is electrically connected to the second voltage control terminal, the first electrode of the fourth transistor is electrically connected to the second voltage terminal, and the second electrode of the fourth transistor is electrically connected to the output node;

[0266] A gate of the fifth transistor is electrically connected to the third driving control terminal, a first electrode of the fifth transistor is electrically connected to the output node, and a second electrode of the fifth transistor is electrically connected to the control signal terminal.

[0267] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a driving circuit, a compensation control circuit, a setting circuit, a data writing circuit, a first energy storage circuit and a second energy storage circuit; The control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the third node, and the driving circuit is used to generate a driving current under the control of the potential of the first node; The compensation control circuit is electrically connected to the first scanning end, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the first scanning signal provided by the first scanning end; The set circuit is electrically connected to the first scan terminal, the set voltage terminal and the third node respectively, and is used to write the set voltage provided by the set voltage terminal into the third node under the control of the first scan signal; The first end of the first energy storage circuit is electrically connected to the energy storage node, and the second end of the first energy storage circuit is electrically connected to the third node; The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the first node; The data writing circuit is electrically connected to the second scanning end, the data line and the fourth node respectively, and is used to provide the data voltage provided by the data line to the fourth node under the control of the second scanning signal provided by the second scanning end.

2. The pixel circuit according to claim 1, wherein: The energy storage node is the first node or the fourth node.

3. The pixel circuit according to claim 1 or 2, characterized in that: Also includes a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the fourth node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal; The second initialization circuit is electrically connected to the third scanning terminal, the second initial voltage terminal and the first node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the third scanning signal provided by the third scanning terminal; The first initial control end is the first scanning end or the third scanning end.

4. The pixel circuit according to claim 3, characterized in that: Also includes a light emitting element, a first light emitting control circuit, a second light emitting control circuit, a third initialization circuit and a fourth initialization circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal; The fourth initialization circuit is electrically connected to the third scan terminal, the fourth initial voltage terminal and the second node respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the second node under the control of the third scan signal provided by the third scan terminal; The second electrode of the light emitting element is electrically connected to the low level end; The third initial control end is the first scanning end, the second scanning end or the third scanning end.

5. The pixel circuit according to claim 1 or 2, characterized in that: The driving circuit includes a driving transistor, the setting circuit includes a first transistor, the data writing circuit includes a second transistor, the compensation control circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The gate of the first transistor is electrically connected to the first scanning terminal, the first electrode of the first transistor is electrically connected to the set voltage terminal, and the second electrode of the first transistor is electrically connected to the third node; The gate of the second transistor is electrically connected to the second scanning end, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node; The gate of the third transistor is electrically connected to the first scanning end, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the fourth node; The first end of the first capacitor is electrically connected to the energy storage node, and the second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the first node.

6. The pixel circuit according to claim 3, characterized in that: The first initialization circuit includes a fourth transistor, and the second initialization circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the first initial control terminal, the first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node; A gate of the fifth transistor is electrically connected to the third scanning terminal, a first electrode of the fifth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first node.

7. The pixel circuit according to claim 4, characterized in that: The first light emitting control circuit includes a sixth transistor, the second light emitting control circuit includes a seventh transistor, the third initialization circuit includes an eighth transistor, and the fourth initialization circuit includes a ninth transistor; The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the first electrode of the sixth transistor is electrically connected to the second node; The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the first electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element; The gate of the eighth transistor is electrically connected to the third initial control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the first electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element; A gate of the ninth transistor is electrically connected to the third scanning terminal, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second node.

8. A driving method, applied to the pixel circuit according to any one of claims 1 to 7, characterized in that: The display cycle includes a compensation phase, a data writing phase and a light emitting phase which are arranged successively; the driving method includes: In the compensation stage, the setting circuit writes the setting voltage into the third node under the control of the first scanning signal, and the compensation control circuit controls the connection between the first node and the second node under the control of the first scanning signal; At the beginning of the compensation phase, the driving circuit controls the connection between the second node and the third node under the control of the potential of the first node, and changes the potential of the first node until the driving circuit is turned off; In the data writing phase, the data writing circuit provides a data voltage to the fourth node under the control of the second scanning signal; During the light-emitting phase, the driving circuit generates a driving current.

9. The driving method according to claim 8, characterized in that: The pixel circuit further includes a second initialization circuit and a fourth initialization circuit; the display cycle further includes an initialization phase; the initialization phase is arranged before the compensation phase; the driving method further includes: In the initialization stage, the second initialization circuit writes a second initial voltage to the first node under the control of the third scanning signal, so that when the compensation stage starts, the driving circuit can control the connection between the second node and the third node under the control of the potential of the first node, and the fourth initialization circuit writes a fourth initial voltage to the second node under the control of the third scanning signal.

10. The driving method according to claim 8 or 9, characterized in that: When the display refresh frequency is less than the first frequency, the compensation phase lasts longer than the first time; When the display refresh frequency is greater than or equal to the first frequency, the duration of the compensation phase is less than or equal to the second time; The first time is greater than or equal to the second time.

11. A display device, characterized in that: The method comprises a pixel circuit as claimed in any one of claims 1 to 7.

12. The display device according to claim 11, wherein: The pixel circuit is electrically connected to at least one control signal terminal; the display device further comprises at least one GOA module; the at least one control signal terminal comprises at least one of a first scanning terminal, a second scanning terminal, a third scanning terminal, and a light emitting control terminal; The GOA module includes a multi-stage GOA circuit; the GOA circuit includes a generation circuit and a control circuit; The generating circuit is used to generate a first driving control signal, a second driving control signal and a third driving control signal, and provides the first driving control signal through the first driving control terminal, provides the second driving control signal through the second driving control terminal, and provides the third driving control signal through the third driving control terminal; The control circuit includes an output circuit and an output reset circuit; The output circuit is electrically connected to the control signal terminal, the first drive control terminal, the second drive control terminal, the first output clock signal terminal, and the second output clock signal terminal, respectively, and is used to control the connection or disconnection between the control signal terminal and the first output clock signal terminal under the control of the first drive control signal, and to control the connection or disconnection between the control signal terminal and the second output clock signal terminal under the control of the second drive control signal; The output reset circuit is electrically connected to the control signal terminal, the third drive control terminal, the output node, the first voltage control terminal, the second voltage control terminal, the first voltage terminal and the second voltage terminal, respectively, and is used to write the first voltage signal provided by the first voltage terminal into the output node under the control of the first voltage control signal provided by the first voltage control terminal, write the second voltage signal provided by the second voltage terminal into the output node under the control of the second voltage control signal provided by the second voltage control terminal, and control the connection or disconnection between the output node and the control signal terminal under the control of the third drive control signal.

13. The display device according to claim 12, wherein: The output circuit is used to control the connection between the control signal terminal and the first output clock signal terminal under the control of the first drive control signal when the frequency is refreshed at a high frequency, and to control the connection between the control signal terminal and the second output clock signal terminal under the control of the second drive control signal when the frequency is refreshed at a low frequency; The output reset circuit is used to write the first voltage signal to the output node under the control of the first voltage control signal when displaying at low brightness, and to write the second voltage signal to the output node under the control of the second voltage control signal when displaying at high brightness; The frequency of the first output clock signal provided by the first output clock signal terminal is greater than the frequency of the second output clock signal provided by the second output clock signal terminal; The transistor controlled by the control signal terminal is an n-type transistor, and the voltage value of the first voltage signal is smaller than the voltage value of the second voltage signal; Alternatively, the transistor controlled by the control signal terminal is a p-type transistor, and the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal.

14. The display device according to claim 13, wherein: A rising time of the first output clock signal is shorter than a rising time of the second output clock signal, and a falling time of the first output clock signal is shorter than a falling time of the second output clock signal.

15. The display device according to any one of claims 12 to 14, characterized in that: The output circuit includes a first transistor and a second transistor, and the output reset circuit includes a third transistor, a fourth transistor and a fifth transistor; The gate of the first transistor is electrically connected to the first driving control terminal, the first electrode of the first transistor is electrically connected to the first output clock signal terminal, and the second electrode of the first transistor is electrically connected to the control signal terminal; The gate of the second transistor is electrically connected to the second driving control terminal, the first electrode of the second transistor is electrically connected to the second output clock signal terminal, and the second electrode of the second transistor is electrically connected to the control signal terminal; The gate of the third transistor is electrically connected to the first voltage control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output node; The gate of the fourth transistor is electrically connected to the second voltage control terminal, the first electrode of the fourth transistor is electrically connected to the second voltage terminal, and the second electrode of the fourth transistor is electrically connected to the output node; A gate of the fifth transistor is electrically connected to the third driving control terminal, a first electrode of the fifth transistor is electrically connected to the output node, and a second electrode of the fifth transistor is electrically connected to the control signal terminal.

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