Driver and display device

Abstract

The invention relates to a driver and a display device. The driver includes a plurality of stages. At least one stage of the plurality of stages includes: an input circuit transmitting an input signal to a third node in response to a clock signal; an inverter circuit that inverts the voltage of the third node and generates a voltage of a fourth node; a first node control circuit controlling the voltage of the first node based on the voltage of the fourth node and the voltage of the second node; a second node control circuit controlling a voltage of the second node based on a voltage of the third node and a voltage of the first node; and an output circuit generating an output signal based on the voltages of the first node and the second node. At least one of the inverter circuit, the first node control circuit, and the second node control circuit includes transistors of different types.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a display device, and more particularly, to a driver and a display device including the same. Background Art

[0002] The driver (e.g., gate driver and / or emission driver) of the display device can sequentially provide signals (e.g., gate signals and / or emission signals) to the pixels of the display panel row by row. In order to sequentially provide signals row by row, the driver can be implemented in the form of a shift register including multiple stages.

[0003] Typically, each stage of the driver may include only a single type of transistor, such as a P-type metal oxide semiconductor ("PMOS") transistor. Summary of the invention

[0004] Some embodiments provide a driver in which each stage includes a different type of transistor.

[0005] Some embodiments provide a display device including a driver in which each stage includes transistors of a different type.

[0006] In an embodiment of the present disclosure, a driver is provided, the driver comprising a plurality of stages. At least one of the plurality of stages comprises: an input circuit transmitting an input signal to a third node in response to a clock signal; an inverter circuit inverting a voltage of the third node and generating a voltage of a fourth node; a first node control circuit controlling a voltage of the first node based on a voltage of the fourth node and a voltage of the second node; a second node control circuit controlling a voltage of the second node based on a voltage of the third node and a voltage of the first node; and an output circuit generating an output signal based on a voltage of the first node and a voltage of the second node. At least one of the inverter circuit, the first node control circuit, and the second node control circuit comprises transistors of different types.

[0007] In an embodiment, the output signal may have a first low gate voltage as a low voltage, the fourth node may have a second low gate voltage as a low voltage, the first node may have a third low gate voltage as a low voltage, and at least two of the first low gate voltage, the second low gate voltage, and the third low gate voltage may have different voltage levels.

[0008] In an embodiment, the second low gate voltage may be higher than the first low gate voltage, and the third low gate voltage may be lower than or equal to the first low gate voltage.

[0009] In an embodiment, the low gate voltage of the clock signal may be different from the first low gate voltage, the second low gate voltage, and the third low gate voltage.

[0010] In an embodiment, the input signal, the clock signal, the output signal, the first node, the second node, the third node, and the fourth node may have the same high gate voltage as a high voltage.

[0011] In an embodiment, the output circuit may include: a first P-type metal oxide semiconductor ("PMOS") transistor, which outputs a high gate voltage as an output signal in response to a voltage at a second node; and a second PMOS transistor, which outputs a first low gate voltage as an output signal in response to a voltage at the first node.

[0012] In an embodiment, the input circuit may include: a third PMOS transistor transmitting the input signal to a third node in response to the clock signal.

[0013] In an embodiment, the input circuit may further include: a fourth N-type metal oxide semiconductor ("NMOS") transistor transmitting the input signal to the third node in response to the inverted clock signal.

[0014] In an embodiment, the inverter circuit may include: a fourth PMOS transistor providing a high gate voltage to a fourth node in response to a voltage of the third node; and a first NMOS transistor providing a second low gate voltage to the fourth node in response to the voltage of the third node.

[0015] In an embodiment, the first node control circuit may include: a fifth PMOS transistor providing a high gate voltage to the first node in response to a voltage of the fourth node; and a second NMOS transistor providing a third low gate voltage to the first node in response to a voltage of the second node.

[0016] In an embodiment, the second node control circuit may include: a sixth PMOS transistor providing a high gate voltage to the second node in response to a voltage of the third node; and a third NMOS transistor providing a third low gate voltage to the second node in response to a voltage of the first node.

[0017] In an embodiment, at least one stage may further include: a capacitor connected between the third node and the second low gate voltage line.

[0018] In an embodiment, at least one stage may further include: a capacitor connected between the third node and the first node.

[0019] In an embodiment, at least one stage may further include: a seventh PMOS transistor including a gate receiving a third low gate voltage, and the seventh PMOS transistor is set at the first node to divide the first node into a fifth node and a sixth node; and a capacitor connected between the output node outputting the output signal and the sixth node.

[0020] In an embodiment, the first node control circuit may include a second NMOS transistor that provides a third low gate voltage to the first node, the second node control circuit may include a third NMOS transistor that provides a third low gate voltage to the second node, and each of the second NMOS transistor and the third NMOS transistor may include a bottom gate that receives a fourth low gate voltage lower than the third low gate voltage.

[0021] In an embodiment, the first node control circuit may include a second NMOS transistor providing a third low gate voltage to the first node, and the second NMOS transistor may include a first bottom gate. The second node control circuit may include a third NMOS transistor providing a third low gate voltage to the second node, and the third NMOS transistor may include a second bottom gate. At least one stage may also include: a first coupling capacitor connected between the second node and the first bottom gate; an eighth PMOS transistor including a gate connected to a third low gate voltage line transmitting a third low gate voltage, a first terminal connected to the first bottom gate, and a second terminal connected to the third low gate voltage line; a second coupling capacitor connected between the first node and the second bottom gate; and a ninth PMOS transistor including a gate connected to the third low gate voltage line, a first terminal connected to the second bottom gate, and a second terminal connected to the third low gate voltage line.

[0022] In an embodiment, at least one stage may further include: a carry circuit that generates a carry signal based on the voltage of the fourth node. The carry circuit may include: a tenth PMOS transistor that outputs a high gate voltage as the carry signal in response to the voltage of the fourth node; and a fifth NMOS transistor that outputs a second low gate voltage as the carry signal in response to the voltage of the fourth node.

[0023] In an embodiment, the second low gate voltage may be higher than the first low gate voltage as the low voltage of the output signal, and the low gate voltage of the clock signal may be higher than the first low gate voltage and lower than the second low gate voltage.

[0024] According to an embodiment, a driver is provided, which includes a plurality of stages. At least one of the plurality of stages includes: a first PMOS transistor including a gate connected to a second node, a first terminal connected to a high gate voltage line, and a second terminal connected to an output node; a second PMOS transistor including a gate connected to a first node, a first terminal connected to an output node, and a second terminal connected to a first low gate voltage line; a third PMOS transistor including a gate for receiving a clock signal, a first terminal for receiving an input signal, and a second terminal connected to a third node; a fourth PMOS transistor including a gate connected to a third node, a first terminal connected to a high gate voltage line, and a second terminal connected to a fourth node; a first NMOS transistor including a gate connected to a third node, a first terminal connected to a fourth node, and a second terminal connected to a high gate voltage line. a first terminal connected to the high gate voltage line and a second terminal connected to the second low gate voltage line; a fifth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the high gate voltage line and a second terminal connected to the first node; a second NMOS transistor including a gate connected to the second node, a first terminal connected to the first node and a second terminal connected to the third low gate voltage line; a sixth PMOS transistor including a gate connected to the third node, a first terminal connected to the high gate voltage line and a second terminal connected to the second node; a third NMOS transistor including a gate connected to the first node, a first terminal connected to the second node and a second terminal connected to the third low gate voltage line; and a capacitor connected between the third node and the second low gate voltage line.

[0025] In an embodiment of the present disclosure, a display device is provided, the display device comprising: a display panel including a plurality of pixels; a data driver providing a data signal to the plurality of pixels; a gate driver providing a gate signal to the plurality of pixels; an emission driver providing an emission signal to the plurality of pixels; and a controller controlling the data driver, the gate driver, and the emission driver. At least one of the gate driver and the emission driver comprises a plurality of stages. At least one of the plurality of stages comprises: an input circuit transmitting an input signal to a third node in response to a clock signal; an inverter circuit inverting a voltage of the third node and generating a voltage of a fourth node; a first node control circuit controlling a voltage of the first node based on a voltage of the fourth node and a voltage of the second node; a second node control circuit controlling a voltage of the second node based on a voltage of the third node and a voltage of the first node; and an output circuit generating an output signal based on a voltage of the first node and a voltage of the second node. At least one of the inverter circuit, the first node control circuit, and the second node control circuit comprises transistors of different types.

[0026] As described above, in the driver and the display device of the embodiment, at least one stage may include an input circuit, an inverter circuit, a first node control circuit, a second node control circuit, and an output circuit, and at least one of the inverter circuit, the first node control circuit, and the second node control circuit may include transistors of different types. In addition, the swing width of the clock signal applied to the input circuit may be smaller than the swing width of the output signal output from the output circuit. Accordingly, the driver can operate stably while reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating an embodiment of a driver.

[0029] Figure 2 Is used to describe Figure 1 Timing diagram of the operation of the driver.

[0030] Figure 3 is a block diagram illustrating an embodiment of a stage of a driver.

[0031] Figure 4 is a diagram for describing an embodiment of voltages for a driver.

[0032] Figure 5 is a circuit diagram showing an embodiment of a stage of a driver.

[0033] Figure 6 Is used to describe Figure 5 A timing diagram of an embodiment of the operation of the stage.

[0034] Figure 7 Is used to describe Figure 5 A circuit diagram of an embodiment of the operation of a stage in a first time period.

[0035] Figure 8 Is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the second time period.

[0036] Fig. 9 is a circuit diagram showing an embodiment of a stage of a driver.

[0037] Fig.10 Is used to describe Fig. 9 A timing diagram of an embodiment of the operation of the stage.

[0038] Fig.11 is a circuit diagram showing an embodiment of a stage of a driver.

[0039] Fig.12is a circuit diagram showing an embodiment of a stage of a driver.

[0040] Fig.13 is a circuit diagram showing an embodiment of a stage of a driver.

[0041] Fig.14 is a block diagram illustrating an embodiment of a driver.

[0042] Fig.15 is a circuit diagram showing an embodiment of a stage of a driver.

[0043] Fig.16 is a diagram for describing an embodiment of voltages for a driver.

[0044] Fig.17 is a block diagram illustrating an embodiment of a display device.

[0045] Fig.18 is a block diagram illustrating an embodiment of an electronic device including a display device. DETAILED DESCRIPTION

[0046] These embodiments are described more fully hereinafter with reference to the accompanying drawings.The same or similar reference numerals refer to the same or similar elements throughout.

[0047] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0048] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this article, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as "second element", "second component", "second region", "second layer" or "second part".

[0049] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the content explicitly indicates otherwise, the singular forms "one", "a kind of" and "the" are intended to include plural forms, including "at least one (kind)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms "include" and / or "comprise" or "contain" and / or "have" illustrate the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0050] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device is turned over in one drawing, the element described as being on the "lower" side of the other elements will subsequently be positioned as the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one drawing, the element described as being "below" or "below" the other elements will subsequently be positioned as "above" the other elements. Therefore, the exemplary terms "below..." or "below..." can cover both upper and lower orientations.

[0051] As used herein, "about" or "approximately" includes the stated value and means within the range of acceptable deviations for the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). Terms such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formalized sense.

[0053] Figure 1 is a block diagram illustrating an embodiment of a driver, and Figure 2 Is used to describe Figure 1Timing diagram of the operation of the driver.

[0054] Reference Figure 1 , the driver 100 in the embodiment may include a plurality of stages STG1, STG2, STG3, STG4, etc. The driver 100 may be implemented in the form of a shift register, wherein the plurality of stages STG1, STG2, STG3, STG4, etc. sequentially output output signals OUT1, OUT2, OUT3, OUT4, etc. In some embodiments, the driver 100 may be included in a display device and may be formed in a display panel of the display device. In an embodiment, for example, the driver 100 may be integrated or formed in / on a substrate of a display panel.

[0055] Based on the start signal FLM, the clock signal CLK and the inverted clock signal CLKB, a plurality of stages STG1, STG2, STG3, STG4, etc. may sequentially output output signals OUT1, OUT2, OUT3, OUT4, etc. In addition, the first stage STG1 may receive the start signal FLM as an input signal, and each of the subsequent stages STG2, STG3, STG4, etc. may receive the output signal of the previous stage as an input signal. For example, in an embodiment, the second stage STG2 may receive the first output signal OUT1 of the first stage STG1 as an input signal, the third stage STG3 may receive the second output signal OUT2 of the second stage STG2 as an input signal, and the fourth stage STG4 may receive the third output signal OUT3 of the third stage STG3 as an input signal.

[0056] In some embodiments, when the clock signal CLK has a relatively low level (e.g., a logic low level), each odd-numbered stage STG1, STG3, etc. may start outputting output signals OUT1, OUT3, etc., and when the inverted clock signal CLKB has a relatively low level, each even-numbered stage STG2, STG4, etc. may start outputting output signals OUT2, OUT4, etc. In an embodiment, as Figure 1 and Figure 2As shown in, for example, when the clock signal CLK becomes a relatively low level after the start signal FLM becomes a relatively high level (e.g., a logic high level), the first stage STG1 may start outputting the first output signal OUT1 having a relatively high level. In addition, when the clock signal CLK becomes a relatively low level after the start signal FLM becomes a relatively low level, the first stage STG1 may start outputting the first output signal OUT1 having a relatively low level. When the inverted clock signal CLKB becomes a relatively low level after the first output signal OUT1 becomes a relatively high level, the second stage STG2 may start outputting the second output signal OUT2 having a relatively high level. In addition, when the inverted clock signal CLKB becomes a relatively low level after the first output signal OUT1 becomes a relatively low level, the second stage STG2 may start outputting the second output signal OUT2 having a relatively low level. When the clock signal CLK becomes a relatively low level after the second output signal OUT2 becomes a relatively high level, the third stage STG3 may start outputting the third output signal OUT3 having a relatively high level. In addition, when the clock signal CLK becomes a relatively low level after the second output signal OUT2 becomes a relatively low level, the third stage STG3 can start outputting the third output signal OUT3 having a relatively low level. When the inverted clock signal CLKB becomes a relatively low level after the third output signal OUT3 becomes a relatively high level, the fourth stage STG4 can start outputting the fourth output signal OUT4 having a relatively high level. In addition, when the inverted clock signal CLKB becomes a relatively low level after the third output signal OUT3 becomes a relatively low level, the fourth stage STG4 can start outputting the fourth output signal OUT4 having a relatively low level. In this way, a plurality of stages STG1, STG2, STG3, STG4, etc. can sequentially output output signals OUT1, OUT2, OUT3, OUT4, etc. by delaying or shifting the output signals OUT1, OUT2, OUT3, OUT4, etc. by half a cycle of the clock signal CLK.

[0057] although Figure 2 An example is shown in which each of the clock signal CLK and the inverted clock signal CLKB has a clock duty ratio of about 50%, but the clock signal CLK and the inverted clock signal CLKB provided for the driver 100 according to the present disclosure are not limited to Figure 2 In an embodiment, for example, to ensure that the low period of the clock signal CLK and the low period of the inverted clock signal CLKB do not overlap with each other, each of the clock signal CLK and the inverted clock signal CLKB may have a low period shorter than a high period, and the low period of the clock signal CLK and the low period of the inverted clock signal CLKB may have a substantially constant time interval.

[0058] Figure 3 is a block diagram showing an embodiment of a stage of a driver, and Figure 4 is a diagram for describing an embodiment of voltages for a driver.

[0059] Reference Figure 3 , each stage 200 of the driver in the embodiment may include: an input circuit 210 that receives an input signal SIN; a level shifter circuit 220 that performs a level shift operation so that the first node Q and / or the second node QB have a voltage (e.g., a third low gate voltage VGL3) different from the voltage of the input signal SIN (e.g., the first low gate voltage VGL1); and an output circuit 230 that generates an output signal OUT based on the voltage of the first node Q and the voltage of the second node QB. In some embodiments, the level shifter circuit 220 may include an inverter circuit 240, a first node control circuit 250, and a second node control circuit 260.

[0060] The input circuit 210 can transmit the input signal SIN to the third node FQ in response to the clock signal CLK. Figure 1 and Figure 2 As shown in , the input circuit 210 of the first stage of the driver can receive the start signal FLM as the input signal SIN, and each of the subsequent stages can receive the output signal POUT of the previous stage as the input signal SIN. In addition, in some embodiments, as Figure 1 and Figure 2 As shown in , the input circuit 210 of the odd-numbered stages may transmit the input signal SIN to the third node FQ thereof in response to the clock signal CLK, and the input circuit 210 of the even-numbered stages may transmit the input signal SIN to the third node FQ thereof in response to the inverted clock signal CLKB.

[0061] In some embodiments, the input signal SIN and the clock signal CLK have substantially the same high gate voltage VGH as a high voltage, but the low gate voltage VGL as a low voltage of the clock signal CLK may be higher than the first low gate voltage VGL1 as a low voltage of the input signal SIN (e.g., the output signal POUT of the previous stage). Figure 4As shown in , the output signal OUT and the clock signal CLK have substantially the same high gate voltage VGH as a high voltage, but the low gate voltage VGL of the clock signal CLK may be higher than the first low gate voltage VGL1 of the output signal OUT. In an embodiment, for example, the high gate voltage VGH may be (but not limited to) about 7.7 volts (V), the first low gate voltage VGL1 may be (but not limited to) about -8.5V, and the low gate voltage VGL of the clock signal CLK may be (but not limited to) about -6.3V. That is, the clock signal CLK may have a swing width from the high gate voltage VGH to the low gate voltage VGL, which is smaller than the swing width of the output signal OUT from the high gate voltage VGH to the first low gate voltage VGL1. Accordingly, since the clock signal CLK has a relatively small swing width, the power consumption of the driver in the embodiment can be reduced.

[0062] The inverter circuit 240 may invert the voltage of the third node FQ to generate a voltage of the fourth node FQB. In an embodiment, for example, when the voltage of the third node FQ has a relatively high level, the inverter circuit 240 may make the voltage of the fourth node FQB have a relatively low level, and when the voltage of the third node FQ has a relatively low level, the voltage of the fourth node FQB may have a relatively high level. In some embodiments, the inverter circuit 240 may receive a high gate voltage VGH and a second low gate voltage VGL2, and may control the voltage of the fourth node FQB based on the high gate voltage VGH and the second low gate voltage VGL2. Accordingly, as Figure 4 As shown in , the fourth node FQB may have a high gate voltage VGH as a high voltage and a second low gate voltage VGL2 as a low voltage. In some embodiments, the second low gate voltage VGL2 may be higher than the first low gate voltage VGL1. In an embodiment, for example, the first low gate voltage VGL1 may be (but not limited to) about -8.5V, and the second low gate voltage VGL2 may be (but not limited to) about 0.7V.

[0063] The first node control circuit 250 may control the voltage of the first node Q based on the voltage of the fourth node FQB and the voltage of the second node QB, and the second node control circuit 260 may control the voltage of the second node QB based on the voltage of the third node FQ and the voltage of the first node Q. In some embodiments, the first node control circuit 250 and the second node control circuit 260 may receive the high gate voltage VGH and the third low gate voltage VGL3, and may control the voltages of the first node Q and the second node QB based on the high gate voltage VGH and the third low gate voltage VGL3. Therefore, as Figure 4As shown in , the first node Q and / or the second node QB may have a high gate voltage VGH as a high voltage and a third low gate voltage VGL3 as a low voltage. In some embodiments, the third low gate voltage VGL3 may be lower than or equal to the first low gate voltage VGL1. In an embodiment, for example, the first low gate voltage VGL1 may be (but not limited to) about -8.5V, and the third low gate voltage VGL3 may be (but not limited to) about -8.5V to about -15V.

[0064] The output circuit 230 may generate an output signal OUT based on the voltage of the first node Q and the voltage of the second node QB. In some embodiments, the output circuit 230 may receive the high gate voltage VGH and the first low gate voltage VGL1, and may generate an output signal OUT having the high gate voltage VGH as a high voltage and the first low gate voltage VGL1 as a low voltage. In addition, since the first node Q and / or the second node QB have a third low gate voltage VGL3 as a low voltage lower than the first low gate voltage VGL1 of the output signal OUT, and the output circuit 230 operates based on the third low gate voltage VGL3 of the first node Q and / or the second node QB, the output circuit 230 may operate stably without performing a bootstrap operation to reduce the low voltage of the first node Q and / or the second node QB. In addition, even when the threshold voltage of the transistor included in the stage 200 is shifted, the stage 200 may operate stably based on the third low gate voltage VGL3 lower than the first low gate voltage VGL1.

[0065] In the stage 200 in the embodiment, at least one of the inverter circuit 240, the first node control circuit 250, and the second node control circuit 260 may include transistors of different types. That is, at least one of the inverter circuit 240, the first node control circuit 250, and the second node control circuit 260 may include a P-type transistor (e.g., a P-type metal oxide semiconductor ("PMOS") transistor) and an N-type transistor (e.g., an N-type metal oxide semiconductor ("NMOS") transistor). In some embodiments, the active region of the PMOS transistor and the active region of the NMOS transistor may include materials different from each other. In an embodiment, the active region of the PMOS transistor may include polycrystalline silicon (e.g., low temperature polycrystalline silicon ("LTPS")) or be composed of polycrystalline silicon (e.g., LTPS), but is not limited thereto. In addition, the active region of the NMOS transistor may include an oxide semiconductor, an organic semiconductor, or an amorphous silicon or be composed of an oxide semiconductor, an organic semiconductor, or an amorphous silicon, but is not limited thereto. Furthermore, in some embodiments, an active region of a PMOS transistor and an active region of an NMOS transistor may be formed in different layers disposed at different heights from a substrate of a display panel, but is not limited thereto.

[0066] Furthermore, in the stage 200 of the embodiment, as Figure 3 and Figure 4 As shown in , the input signal SIN, the clock signal CLK, the output signal OUT, the first node Q, the second node QB, the third node FQ, and the fourth node FQB may have substantially the same high gate voltage VGH as a high voltage. However, the second low gate voltage VGL2 of the fourth node FQB may be higher than the first low gate voltage VGL1 of the output signal OUT, and the third low gate voltage VGL3 of the first node Q and the second node QB may be lower than or equal to the first low gate voltage VGL1. In addition, as Figure 4 As shown in , the clock signal CLK provided to the stage 200 may have a low gate voltage VGL different from the first low gate voltage VGL1, the second low gate voltage VGL2, and the third low gate voltage VGL3 as a low voltage. In some embodiments, as described above, the low gate voltage VGL of the clock signal CLK may be higher than the first low gate voltage VGL1 of the output signal OUT, and the swing width of the clock signal CLK may be smaller than the swing width of the output signal OUT. Accordingly, the driver including the stage 200 in the embodiment can operate stably while reducing power consumption.

[0067] Figure 5 is a circuit diagram showing an embodiment of a stage of a driver.

[0068] Reference Figure 5 The stage 200a of the driver in the embodiment may include an input circuit 210, an output circuit 230, an inverter circuit 240, a first node control circuit 250, a second node control circuit 260 and a capacitor CFQ (hereinafter also referred to as a first capacitor CFQ).

[0069] The output circuit 230 may generate an output signal OUT based on the voltage of the first node Q and the voltage of the second node QB. In some embodiments, the output circuit 230 may include: a first PMOS transistor PT1 that outputs a high gate voltage VGH as the output signal OUT in response to the voltage of the second node QB; and a second PMOS transistor PT2 that outputs a first low gate voltage VGL1 as the output signal OUT in response to the voltage of the first node Q. In an embodiment, for example, the first PMOS transistor PT1 may include a gate connected to the second node QB, a first terminal connected to a high gate voltage line transmitting the high gate voltage VGH, and a second terminal connected to an output node NO outputting the output signal OUT, and the second PMOS transistor PT2 may include a gate connected to the first node Q, a first terminal connected to the output node NO, and a second terminal connected to a first low gate voltage line transmitting the first low gate voltage VGL1.

[0070] The input circuit 210 may transmit the input signal SIN to the third node FQ in response to the clock signal CLK. In some embodiments, the input circuit 210 may include a third PMOS transistor PT3 that transmits the input signal SIN to the third node FQ in response to the clock signal CLK. In an embodiment, for example, the third PMOS transistor PT3 may include a gate that receives the clock signal CLK, a first terminal that receives the input signal SIN, and a second terminal connected to the third node FQ.

[0071] The capacitor CFQ can maintain the voltage of the third node FQ when the third PMOS transistor PT3 is turned off. In some embodiments, the capacitor CFQ can be connected between the third node FQ and the second low gate voltage line transmitting the second low gate voltage VGL2. In an embodiment, for example, the capacitor CFQ can include a first electrode connected to the third node FQ and a second electrode connected to the second low gate voltage line.

[0072] The inverter circuit 240 may invert the voltage of the third node FQ to generate the voltage of the fourth node FQB. In some embodiments, the inverter circuit 240 may include a fourth PMOS transistor PT4 that provides a high gate voltage VGH to the fourth node FQB in response to the voltage of the third node FQ and a first NMOS transistor NT1 that provides a second low gate voltage VGL2 to the fourth node FQB in response to the voltage of the third node FQ. In an embodiment, for example, the fourth PMOS transistor PT4 may include a gate connected to the third node FQ, a first terminal connected to a high gate voltage line, and a second terminal connected to the fourth node FQB, and the first NMOS transistor NT1 may include a gate connected to the third node FQ, a first terminal connected to the fourth node FQB, and a second terminal connected to the second low gate voltage line.

[0073] The first node control circuit 250 may control the voltage of the first node Q based on the voltage of the fourth node FQB and the voltage of the second node QB. In some embodiments, the first node control circuit 250 may include a fifth PMOS transistor PT5 that provides a high gate voltage VGH to the first node Q in response to the voltage of the fourth node FQB and a second NMOS transistor NT2 that provides a third low gate voltage VGL3 to the first node Q in response to the voltage of the second node QB. In an embodiment, for example, the fifth PMOS transistor PT5 may include a gate connected to the fourth node FQB, a first terminal connected to a high gate voltage line, and a second terminal connected to the first node Q, and the second NMOS transistor NT2 may include a gate connected to the second node QB, a first terminal connected to the first node Q, and a second terminal connected to a third low gate voltage line transmitting the third low gate voltage VGL3.

[0074] The second node control circuit 260 may control the voltage of the second node QB based on the voltage of the third node FQ and the voltage of the first node Q. In some embodiments, the second node control circuit 260 may include a sixth PMOS transistor PT6 that provides a high gate voltage VGH to the second node QB in response to the voltage of the third node FQ and a third NMOS transistor NT3 that provides a third low gate voltage VGL3 to the second node QB in response to the voltage of the first node Q. In an embodiment, for example, the sixth PMOS transistor PT6 may include a gate connected to the third node FQ, a first terminal connected to a high gate voltage line, and a second terminal connected to the second node QB, and the third NMOS transistor NT3 may include a gate connected to the first node Q, a first terminal connected to the second node QB, and a second terminal connected to the third low gate voltage line.

[0075] In the following, reference is made to Figures 5 to 8 An embodiment of the operation of stage 200a is described.

[0076] Figure 6 Is used to describe Figure 5 A timing diagram of an example of the operation of the stage, Figure 7 Is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in a first time period, and Figure 8 Is used to describe Figure 5 A circuit diagram of an embodiment of the operation of the stage in the second time period.

[0077] Reference Figure 5 and Figure 6 , when the clock signal CLK becomes the low gate voltage VGL after the input signal SIN has the high gate voltage VGH, the stage 200a can start to output the output signal OUT having the high gate voltage VGH, and when the clock signal CLK becomes the low gate voltage VGL after the input signal SIN has the first low gate voltage VGL1, the stage 200a can start to output the output signal OUT having the first low gate voltage VGL1.

[0078] In the first time period TP1 when the input signal SIN has the high gate voltage VGH and the clock signal CLK has the low gate voltage VGL, the stage 200a may output the output signal OUT having the high gate voltage VGH. To do this, Figure 7 As shown in , the third PMOS transistor PT3 may be turned on in response to the clock signal CLK having the low gate voltage VGL, and may transmit the input signal SIN having the high gate voltage VGH to the third node FQ. Therefore, the third node FQ may have the high gate voltage VGH.

[0079] The first NMOS transistor NT1 may be turned on in response to the high gate voltage VGH of the third node FQ, and may provide the second low gate voltage VGL2 to the fourth node FQB. The fifth PMOS transistor PT5 may be turned on in response to the second low gate voltage VGL2 of the fourth node FQB, and may provide the high gate voltage VGH to the first node Q. In some embodiments, the second low gate voltage VGL2 may be lower than the voltage obtained by subtracting the absolute value of the threshold voltage of the first NMOS transistor NT1 from the high gate voltage VGH to ensure that the first NMOS transistor NT1 is turned on, and may be lower than the voltage obtained by subtracting the absolute value of the threshold voltage of the fifth PMOS transistor PT5 from the high gate voltage VGH to ensure that the fifth PMOS transistor PT5 is turned on. That is, the second low gate voltage VGL2 may be higher than the first low gate voltage VGL1, but lower than the high gate voltage VGH by the absolute value of the threshold voltage of the first NMOS transistor NT1 or the fifth PMOS transistor PT5.

[0080] The third NMOS transistor NT3 may be turned on in response to the high gate voltage VGH of the first node Q, and may provide the third low gate voltage VGL3 to the second node QB. In addition, the fourth PMOS transistor PT4 and the sixth PMOS transistor PT6 may be turned off in response to the high gate voltage VGH of the third node FQ, and the second NMOS transistor NT2 may be turned off in response to the third low gate voltage VGL3 of the second node QB.

[0081] The first PMOS transistor PT1 may be turned on in response to the third low gate voltage VGL3 of the second node QB, and the second PMOS transistor PT2 may be turned off in response to the high gate voltage VGH of the first node Q. Therefore, the first PMOS transistor PT1 may provide the high gate voltage VGH to the output node NO, and the stage 200a may output the output signal OUT having the high gate voltage VGH at the output node NO.

[0082] In addition, in the second period TP2 when the input signal SIN has the first low gate voltage VGL1 and the clock signal CLK has the low gate voltage VGL, the stage 200a may output the output signal OUT having the first low gate voltage VGL1. To do this, Figure 8As shown in , the third PMOS transistor PT3 can be turned on in response to the clock signal CLK having a low gate voltage VGL, and the input signal SIN having a first low gate voltage VGL1 can be transmitted to the third node FQ. In some embodiments, to reduce power consumption, the low gate voltage VGL of the clock signal CLK can be higher than the first low gate voltage VGL1 of the input signal SIN. In this case, the third node FQ may not be reduced to the first low gate voltage VGL1, and the voltage of the third node FQ may be higher than each of the low gate voltage VGL and the first low gate voltage VGL1. That is, the third PMOS transistor PT3 can be turned on until the voltage of the third node FQ becomes the sum VGL+|VTH| of the low gate voltage VGL of the clock signal CLK and the absolute value |VTH| of the threshold voltage of the third PMOS transistor PT3. Therefore, the voltage of the third node FQ can become the sum VGL+|VTH| of the low gate voltage VGL and the absolute value |VTH| of the threshold voltage.

[0083] The fourth PMOS transistor PT4 and the sixth PMOS transistor PT6 may be turned on in response to the voltage VGL+|VTH| of the third node FQ. In order to ensure that the fourth PMOS transistor PT4 and the sixth PMOS transistor PT6 are turned on, the voltage VGL+|VTH| of the third node FQ should be lower than the high gate voltage VGH by the absolute value of the threshold voltage |VTH| of each of the fourth PMOS transistor PT4 and the sixth PMOS transistor PT6. Therefore, in some embodiments, the low gate voltage VGL of the clock signal CLK may be higher than the first low gate voltage VGL1 to reduce power consumption, but may be lower than the voltage obtained by subtracting twice the absolute value of the threshold voltage |VTH| from the high gate voltage VGH (i.e., "VGH-2×|VTH|") to ensure that the fourth PMOS transistor PT4 and the sixth PMOS transistor PT6 are turned on. The fourth PMOS transistor PT4 may provide the high gate voltage VGH to the fourth node FQB, and the sixth PMOS transistor PT6 may provide the high gate voltage VGH to the second node QB.

[0084] The first NMOS transistor NT1 can be turned off in response to the voltage VGL+|VTH| of the third node FQ. In order to reduce the leakage current through the first NMOS transistor NT1, the second low gate voltage VGL2 at the second terminal (or source) of the first NMOS transistor NT1 can be higher than or equal to the voltage VGL+|VTH| of the third node FQ. Therefore, in some embodiments, the second low gate voltage VGL2 can not only be higher than the first low gate voltage VGL1, but also higher than or equal to the sum VGL+|VTH| of the low gate voltage VGL and the absolute value of the threshold voltage |VTH|. In addition, the fifth PMOS transistor PT5 can be turned off in response to the high gate voltage VGH of the fourth node FQB.

[0085] The second NMOS transistor NT2 may be turned on in response to the high gate voltage VGH of the second node QB, and may provide the third low gate voltage VGL3 to the first node Q. Also, the third NMOS transistor NT3 may be turned off in response to the third low gate voltage VGL3 of the first node Q.

[0086] The first PMOS transistor PT1 may be turned off in response to the high gate voltage VGH of the second node QB, and the second PMOS transistor PT2 may be turned on in response to the third low gate voltage VGL3 of the first node Q. In some embodiments, the third low gate voltage VGL3 may be lower than or equal to the first low gate voltage VGL1. Therefore, even when the bootstrap operation of reducing the voltage of the first node Q is not performed, the second PMOS transistor PT2 may be turned on (e.g., fully turned on). Accordingly, the second PMOS transistor PT2 may provide the first low gate voltage VGL1 to the output node NO, and the stage 200a may output an output signal OUT having the first low gate voltage VGL1 at the output node NO.

[0087] Fig. 9 is a circuit diagram showing an embodiment of a stage of a driver, and Fig.10 Is used to describe Fig. 9 A timing diagram of an embodiment of the operation of the stage.

[0088] Reference Fig. 9 The stage 200b of the driver in the embodiment may include an input circuit 210, an output circuit 230, an inverter circuit 240, a first node control circuit 250, a second node control circuit 260, a first capacitor CFQ, a seventh PMOS transistor PT7, and a second capacitor CQ. In addition to the seventh PMOS transistor PT7 and the second capacitor CQ, the stage 200b may also include: Fig. 9 The stage 200b may have Figure 5 The stage 200a has substantially the same configuration and substantially the same operation.

[0089] The seventh PMOS transistor PT7 may be disposed at the first node Q to divide the first node Q into a fifth node Q1 and a sixth node Q2. In addition, the gate of the seventh PMOS transistor PT7 may receive a third low gate voltage VGL3. Therefore, since the seventh PMOS transistor PT7 receives the third low gate voltage VGL3 as a low voltage for turning on the seventh PMOS transistor PT7, the seventh PMOS transistor PT7 may also be referred to as an always-on transistor ("AOT"). In an embodiment, for example, the seventh PMOS transistor PT7 may include a gate connected to a third low gate voltage line transmitting the third low gate voltage VGL3, a first terminal connected to the fifth node Q1, and a second terminal connected to the sixth node Q2.

[0090] The second capacitor CQ may be connected between the output node NO outputting the output signal OUT and the sixth node Q2. In an embodiment, for example, the second capacitor CQ may include a first electrode connected to the output node NO and a second electrode connected to the sixth node Q2.

[0091] The bootstrap operation of lowering the voltage of the sixth node Q2 may be performed by the second PMOS transistor PT2, the seventh PMOS transistor PT7, and the second capacitor CQ. In an embodiment, for example, when the third low gate voltage VGL3 is provided to the fifth node Q1 through the second NMOS transistor NT2, the third low gate voltage VGL3 of the fifth node Q1 may be provided to the sixth node Q2 through the seventh PMOS transistor PT7. The second PMOS transistor PT2 may be turned on in response to the third low gate voltage VGL3 of the sixth node Q2, and may provide the first low gate voltage VGL1 to the output node NO having the high gate voltage VGH. When the voltage of the output node NO connected to the first electrode of the second capacitor CQ is reduced from the high gate voltage VGH to the first low gate voltage VGL1, the voltage of the sixth node Q2 connected to the second electrode of the second capacitor CQ may also be reduced from the third low gate voltage VGL3 to the boosted low gate voltage BVGL3, as shown in FIG. Fig.10 As shown in. In the case where the voltage of the sixth node Q2 is reduced to the boosted low gate voltage BVGL3 lower than the third low gate voltage VGL3 applied to the gate of the seventh PMOS transistor PT7, the seventh PMOS transistor PT7 may not transmit the boosted low gate voltage BVGL3 from the sixth node Q2 to the fifth node Q1. As described above, when the voltage of the sixth node Q2 is reduced to the boosted low gate voltage BVGL3 by the bootstrap operation, the driving capability (or conduction degree) of the second PMOS transistor PT2 can be improved, and the falling speed of the output signal OUT from the high gate voltage VGH to the first low gate voltage VGL1 can be improved.

[0092] Fig.11 is a circuit diagram showing an embodiment of a stage of a driver.

[0093] Reference Fig.11 The driver stage 200c in the embodiment may include an input circuit 210, an output circuit 230, an inverter circuit 240', a first node control circuit 250', a second node control circuit 260', a first capacitor CFQ, a seventh PMOS transistor PT7, and a second capacitor CQ. In addition to the first NMOS transistor NT1', the second NMOS transistor NT2', and the third NMOS transistor NT3' each including a bottom gate, Fig.11 The level 200c can have Fig. 9 The configuration and operation of stage 200b are substantially the same as those of stage 200b. Fig. 9 Compared with the embodiment, Fig.11 An embodiment in which each NMOS transistor includes a bottom gate is shown, but those skilled in the art will readily appreciate that Fig.11 This feature shown in can be combined with any embodiment. That is, Fig.11 Additions or changes to the embodiments may be applied to Fig. 9 In the embodiments, for example, Figure 5 In an embodiment, each NMOS transistor may include a bottom gate.

[0094] The first NMOS transistor NT1' may include a gate connected to the third node FQ, a first terminal connected to the fourth node FQB, a second terminal connected to the second low gate voltage line transmitting the second low gate voltage VGL2, and a bottom gate connected to the first low gate voltage line transmitting the first low gate voltage VGL1. Since the bottom gate of the first NMOS transistor NT1' receives the first low gate voltage VGL1 lower than the second low gate voltage VGL2 applied to the second terminal (e.g., source) of the first NMOS transistor NT1', the threshold voltage of the first NMOS transistor NT1' may be increased (or shifted in a positive direction), and the leakage current through the first NMOS transistor NT1' may be reduced.

[0095] The second NMOS transistor NT2' may include a gate connected to the second node QB, a first terminal connected to the fifth node Q1, a second terminal connected to the third low gate voltage line transmitting the third low gate voltage VGL3, and a bottom gate connected to the fourth low gate voltage line transmitting the fourth low gate voltage VGL4, and the third NMOS transistor NT3' may include a gate connected to the fifth node Q1, a first terminal connected to the second node QB, a second terminal connected to the third low gate voltage line, and a bottom gate connected to the fourth low gate voltage line. In some embodiments, the fourth low gate voltage VGL4 may be lower than the third low gate voltage VGL3. Therefore, since the bottom gate of each of the second NMOS transistor NT2' and the third NMOS transistor NT3' receives a fourth low gate voltage lower than the third low gate voltage VGL3 applied to its source, the threshold voltage of each of the second NMOS transistor NT2' and the third NMOS transistor NT3' may be increased, and the leakage current through each of the second NMOS transistor NT2' and the third NMOS transistor NT3' may be reduced.

[0096] Fig.12 is a circuit diagram showing an embodiment of a stage of a driver.

[0097] Reference Fig.12 The stage 200d of the driver in the embodiment may include an input circuit 210, an output circuit 230, an inverter circuit 240', a first node control circuit 250', a second node control circuit 260', a first capacitor CFQ, a seventh PMOS transistor PT7, a second capacitor CQ, a first coupling capacitor CC1, an eighth PMOS transistor PT8, a second coupling capacitor CC2 and a ninth PMOS transistor PT9. In addition, the stage 200d may not receive the fourth low gate voltage VGL4 (refer to Fig.11 ) and may further include a first coupling capacitor CC1 and a second coupling capacitor CC2 and an eighth PMOS transistor PT8 and a ninth PMOS transistor PT9, Fig.12 The level 200d can have Fig.11 Stage 200c has substantially the same configuration and substantially the same operation.

[0098] The first coupling capacitor CC1 may be connected between the second node QB and the bottom gate of the second NMOS transistor NT2'. The eighth PMOS transistor PT8 may include a gate connected to the third low gate voltage line transmitting the third low gate voltage VGL3, a first terminal connected to the bottom gate of the second NMOS transistor NT2', and a second terminal connected to the third low gate voltage line. That is, the eighth PMOS transistor PT8 may have a diode connection structure in which the current flows only in the direction from the bottom gate of the second NMOS transistor NT2' to the third low gate voltage line. In addition, the second coupling capacitor CC2 may be connected between the fifth node Q1 (or the first node Q) and the bottom gate of the third NMOS transistor NT3'. The ninth PMOS transistor PT9 may include a gate connected to the third low gate voltage line, a first terminal connected to the bottom gate of the third NMOS transistor NT3', and a second terminal connected to the third low gate voltage line. That is, the ninth PMOS transistor PT9 may have a diode connection structure in which the current flows only in the direction from the bottom gate of the third NMOS transistor NT3' to the third low gate voltage line.

[0099] When the second NMOS transistor NT2' is turned off, the first coupling capacitor CC1 and the eighth PMOS transistor PT8 can provide a voltage lower than the third low gate voltage VGL3 to the bottom gate of the second NMOS transistor NT2'. In an embodiment, for example, when the voltage of the second node QB increases from the third low gate voltage VGL3 to the high gate voltage VGH, the second NMOS transistor NT2' can be turned on. In addition, when the voltage of the second node QB increases, the voltage of the bottom gate of the second NMOS transistor NT2' can also be increased by the first coupling capacitor CC1. However, by the eighth PMOS transistor PT8 having a diode connection structure, the voltage of the bottom gate of the second NMOS transistor NT2' can be reduced to the third low gate voltage VGL3 (or reduced to the sum of the absolute value of the third low gate voltage VGL3 and the threshold voltage of the eighth PMOS transistor PT8). In an alternative embodiment, when the voltage of the second node QB decreases from the high gate voltage VGH to the third low gate voltage VGL3, the second NMOS transistor NT2' can be turned off. In addition, when the voltage of the second node QB is reduced, the voltage of the bottom gate of the second NMOS transistor NT2' can also be reduced by the first coupling capacitor CC1. Therefore, when the second NMOS transistor NT2' is turned off, a voltage lower than the third low gate voltage VGL3 can be applied to the bottom gate of the second NMOS transistor NT2', and the leakage current through the second NMOS transistor NT2' can be reduced.

[0100] In addition, when the third NMOS transistor NT3' is turned off, the second coupling capacitor CC2 and the ninth PMOS transistor PT9 can provide a voltage lower than the third low gate voltage VGL3 to the bottom gate of the third NMOS transistor NT3'. In an embodiment, when the voltage of the fifth node Q1 increases from the third low gate voltage VGL3 to the high gate voltage VGH, the third NMOS transistor NT3' can be turned on. In addition, for example, when the voltage of the fifth node Q1 increases, the voltage of the bottom gate of the third NMOS transistor NT3' can also be increased by the second coupling capacitor CC2. However, by the ninth PMOS transistor PT9 having a diode connection structure, the voltage of the bottom gate of the third NMOS transistor NT3' can be reduced to the third low gate voltage VGL3 (or reduced to the sum of the absolute value of the third low gate voltage VGL3 and the threshold voltage of the ninth PMOS transistor PT9). In an alternative embodiment, when the voltage of the fifth node Q1 decreases from the high gate voltage VGH to the third low gate voltage VGL3, the third NMOS transistor NT3' can be turned off. In addition, when the voltage of the fifth node Q1 decreases, the voltage of the bottom gate of the third NMOS transistor NT3' can also be reduced through the second coupling capacitor CC2. Therefore, when the third NMOS transistor NT3' is turned off, a voltage lower than the third low gate voltage VGL3 can be applied to the bottom gate of the third NMOS transistor NT3', and the leakage current through the third NMOS transistor NT3' can be reduced.

[0101] Fig.13 is a circuit diagram showing an embodiment of a stage of a driver.

[0102] Reference Fig.13 , the stage 200e of the driver in the embodiment may include an input circuit 210, an output circuit 230, an inverter circuit 240, a first node control circuit 250', a second node control circuit 260', a first capacitor CFQ', a seventh PMOS transistor PT7, and a second capacitor CQ. Except that the first NMOS transistor NT1 may not have a bottom gate, and the first capacitor CFQ' may be connected to the fifth node Q1 (or the first node Q) instead of the second low gate voltage line transmitting the second low gate voltage VGL2, Fig.13 The Level 200e can have Fig.11 Stage 200c has substantially the same configuration and substantially the same operation.

[0103] The first capacitor CFQ' may be connected between the third node FQ and the fifth node Q1 (or the first node Q). When the third node FQ becomes a low voltage, the fifth node Q1 (or the first node Q) may also be reduced from the high gate voltage VGH to the third low gate voltage VGL3. In addition, the low voltage of the third node FQ may be further reduced by the first capacitor CFQ'. Accordingly, the reduced low voltage of the third node FQ may be applied to the gate of the first NMOS transistor NT1, and thus the leakage current through the first NMOS transistor NT1 may be reduced.

[0104] although Fig.13 Shows from Fig.11 The first capacitor CFQ' is connected to the fifth node Q1 (or the first node Q) in the embodiment of the embodiment modified by the embodiment, but those skilled in the art will easily understand that Fig.13 Additions or changes to the embodiments may be applied to Fig.11 Embodiments of different embodiments.

[0105] Fig.14 is a block diagram illustrating an embodiment of a driver.

[0106] Reference Fig.14 , the driver 1000 in the embodiment may include a plurality of stages STG1 ′, STG2 ′, STG3 ′, STG4 ′, etc.

[0107] exist Fig.14 The drive 1000, with Figure 1 Each stage in the driver 100 receives an output signal of the previous stage as an input signal, and each stage (e.g., the second stage STG2') can receive a carry signal (e.g., a first carry signal CR1) of the previous stage (e.g., the first stage STG1') as an input signal. In an embodiment, for example, the second stage STG2' can receive the first carry signal CR1 of the first stage STG1' as an input signal, the third stage STG3' can receive the second carry signal CR2 of the second stage STG2' as an input signal, and the fourth stage STG4' can receive the third carry signal CR3 of the third stage STG3' as an input signal.

[0108] In addition, in some embodiments, when the clock signal CLK has a relatively low level and the inverted clock signal CLKB has a relatively high level, the individual odd stages STG1', STG3', etc. can start outputting carry signals CR1, CR3, etc. and output signals OUT1, OUT3, etc., and when the clock signal CLK has a relatively high level and the inverted clock signal CLKB has a relatively low level, the individual even stages STG2', STG4', etc. can start outputting carry signals CR2, CR4, etc. and output signals OUT2, OUT4, etc.

[0109] Fig.15 is a circuit diagram showing an embodiment of a stage of a driver, and Fig.16 is a diagram for describing an embodiment of voltages for a driver.

[0110] Reference Fig.15 The stage 1200 of the driver in the embodiment may include an input circuit 210', an output circuit 230, an inverter circuit 240, a first node control circuit 250, a second node control circuit 260, a first capacitor CFQ, a seventh PMOS transistor PT7, a second capacitor CQ and a carry circuit 270. In addition to the stage 1200 receiving a carry signal PCR of a previous stage instead of an output signal of the previous stage as an input signal SIN, the input circuit 210' may further include a fourth NMOS transistor NT4, and the stage 1200 may further include a carry circuit 270, Fig.15 The level 1200 can have Fig. 9 The stage 200b has substantially the same configuration and substantially the same operation. Fig.15 Shown with Fig. 9 Compared with the embodiment of the embodiment further including the fourth NMOS transistor NT4 and the carry circuit 270, any one of the above embodiments may further include the fourth NMOS transistor NT4 and the carry circuit 270.

[0111] The input circuit 210' may include not only a third PMOS transistor PT3 that transmits the input signal SIN to the third node FQ in response to the clock signal CLK, but also a fourth NMOS transistor NT4 that transmits the input signal SIN in response to the inverted clock signal CLKB. Therefore, when the input signal SIN has a second low gate voltage VGL2' and the inverted clock signal CLKB has a high gate voltage VGH, the fourth NMOS transistor NT4 may be turned on and the second low gate voltage VGL2 of the input signal SIN may be transmitted to the third node FQ. That is, when the input signal SIN has a second low gate voltage VGL2', the fourth NMOS transistor NT4 may transmit the input signal SIN to the third node FQ, and thus the voltage of the third node FQ may become substantially equal to the second low gate voltage VGL2' of the input signal SIN. In some embodiments, in order to prevent leakage current from passing through the fourth NMOS transistor NT4 when the inverted clock signal CLKB has a low gate voltage VGL', the low gate voltage VGL' of the clock signal CLK and the inverted clock signal CLKB may be lower than the second low gate voltage VGL2' of the input signal SIN and the carry signal CR. That is, the low gate voltage VGL′ of the clock signal CLK and the inverted clock signal CLKB may be higher than the first low gate voltage VGL1 of the output signal OUT and lower than the second low gate voltage VGL2 ′.

[0112] The carry circuit 270 may include a tenth PMOS transistor PT10 that outputs a high gate voltage VGH as a carry signal CR in response to the voltage of the fourth node FQB, and a fifth NMOS transistor NT5 that outputs a second low gate voltage VGL2' as a carry signal CR in response to the voltage of the fourth node FQB. In an embodiment, for example, the tenth PMOS transistor PT10 may include a gate connected to the fourth node FQB, a first terminal connected to a high gate voltage line transmitting the high gate voltage VGH, and a second terminal connected to a carry node outputting the carry signal CR, and the fifth NMOS transistor NT5 may include a gate connected to the fourth node FQB, a first terminal connected to the carry node, and a second terminal connected to a second low gate voltage line transmitting the second low gate voltage VGL2'. In some embodiments, the second low gate voltage VGL2' may be higher than the first low gate voltage VGL1 of the output signal OUT.

[0113] and Figure 5 Level 200a, Fig. 9 Level 200b, Fig.11 Level 200c, Fig.12 The 200d and Fig.13Different from the stage 200e, since the input circuit 210' of the stage 1200 further includes a fourth NMOS transistor NT4 and receives the carry signal PCR of the previous stage instead of the output signal of the previous stage as the input signal SIN, Figure 5 Level 200a, Fig. 9 Level 200b, Fig.11 Level 200c, Fig.12 The 200d and Fig.13 In the stage 200e, the second low gate voltage VGL2' of the input signal SIN and the carry signal CR can be set to be higher than the first low gate voltage VGL1 of the output signal OUT, and the low gate voltage VGL' of the clock signal CLK and the inverted clock signal CLKB can also be set to be higher than the low gate voltage VGL. In an embodiment, as Fig.16 As shown in , for example, the second low gate voltage VGL2' may be (but not limited to) about -3.7 V, and the low gate voltage VGL' may be (but not limited to) about -4.7 V. Accordingly, compared with the swing width of the output signal OUT, the swing widths of the clock signal CLK and the inverted clock signal CLKB may be further reduced, and thus the power consumption of the driver including the stage 1200 may be further reduced.

[0114] Fig.17 is a block diagram illustrating an embodiment of a display device.

[0115] Reference Fig.17 The display device 2000 in the embodiment may include: a display panel 2010, including a plurality of pixels PX; a data driver 2030, providing a data signal DS to the plurality of pixels PX; a gate driver 2050, providing a gate signal GS to the plurality of pixels PX; an emission driver 2070, providing an emission signal EM to the plurality of pixels PX; and a controller 2090, controlling the data driver 2030, the gate driver 2050 and the emission driver 2070.

[0116] The display panel 2010 may include data lines, gate lines, emission lines, and a plurality of pixels PX connected to the data lines, gate lines, and emission lines. In some embodiments, each pixel PX may include a light-emitting element, and the display panel 2010 may be a light-emitting display panel. In some embodiments, the light-emitting element may be an organic light-emitting diode ("OLED"). In other embodiments, the light-emitting element may be a nano light-emitting diode ("NED"), a quantum dot ("QD") light-emitting diode, a micro light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In other embodiments, the display panel 2010 may be a liquid crystal display ("LCD") panel or any other suitable display panel.

[0117] The data driver 2030 may generate a data signal DS based on a data control signal DCTRL and output image data ODAT received from the controller 2090, and may provide the data signal DS to a plurality of pixels PX through a data line. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 2030 and the controller 2090 may be implemented as a single integrated circuit, and the single integrated circuit may also be referred to as a timing controller embedded data driver ("TED") integrated circuit. In other embodiments, the data driver 2030 and the controller 2090 may be implemented as separate integrated circuits.

[0118] The gate driver 2050 may generate a gate signal GS based on a gate control signal GCTRL received from the controller 2090, and may sequentially provide the gate signal GS to a plurality of pixels PX through gate lines row by row. In some embodiments, the gate control signal GCTRL may include, but is not limited to, a gate start signal and a gate clock signal. In some embodiments, the gate driver 2050 may include Figure 5 Level 200a, Fig. 9 Level 200b, Fig.11 Level 200c, Fig.12 Level 200d or Fig.13 Class 200e Figure 1 The driver 100 may include Fig.15 Level 1200 Fig.14 Driver 1000. In addition, in some embodiments, Fig.17 As shown in , the gate driver 2050 may be integrated or formed in the display panel 2010. In other embodiments, the gate driver 2050 may be implemented as one or more integrated circuits.

[0119] The emission driver 2070 may generate an emission signal EM based on an emission control signal ECTRL received from the controller 2090, and may sequentially provide the emission signal EM to a plurality of pixels PX through the emission lines row by row. In some embodiments, the emission control signal ECTRL may include, but is not limited to, an emission start signal and an emission clock signal. In some embodiments, the emission driver 2070 may include Figure 5 Level 200a, Fig. 9 Level 200b, Fig.11 Level 200c, Fig.12 Level 200d or Fig.13 Class 200e Figure 1 The driver 100 may include Fig.15 Level 1200 Fig.14Driver 1000. In addition, in some embodiments, Fig.17 As shown in , the emission driver 2070 may be integrated or formed in the display panel 2010. In other embodiments, the emission driver 2070 may be implemented as one or more integrated circuits.

[0120] The controller 2090 (e.g., a timing controller ("TCON")) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit ("GPU"), an application processor ("AP"), or a graphics card). In some embodiments, the input image data IDAT may be red, green, and blue ("RGB") image data including red image data, green image data, and blue image data. In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 2090 may generate output image data ODAT, a data control signal DCTRL, a gate control signal GCTRL, and an emission control signal ECTRL based on the input image data IDAT and the control signal CTRL. The controller 2090 may control the operation of the data driver 2030 by providing the output image data ODAT and the data control signal DCTRL to the data driver 2030 , may control the operation of the gate driver 2050 by providing the gate control signal GCTRL to the gate driver 2050 , and may control the operation of the emission driver 2070 by providing the emission control signal ECTRL to the emission driver 2070 .

[0121] In the display device 2000 in the embodiment, at least one of the gate driver 2050 and the emission driver 2070 may be implemented as Figure 1 Drive 100 or Fig.14 The driver 1000 is a device for driving a clock signal input circuit. At least one stage of the driver may include an input circuit, an inverter circuit, a first node control circuit, a second node control circuit, and an output circuit, and at least one of the inverter circuit, the first node control circuit, and the second node control circuit may include transistors of different types. In addition, the swing width of the clock signal applied to the input circuit may be smaller than the swing width of the output signal output from the output circuit. Accordingly, the driver can operate stably while reducing power consumption.

[0122] Fig.18 is a block diagram illustrating an embodiment of an electronic device including a display device.

[0123] Reference Fig.18, the electronic device 2100 may include a processor 2110, a memory device 2120, a storage device 2130, an input / output ("I / O") device 2140, a power supply 2150, and a display device 2160. The electronic device 2100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electronic devices, and the like.

[0124] The processor 2110 may perform various computing functions or tasks. The processor 2110 may be an application processor ("AP"), a microprocessor, a central processing unit ("CPU"), etc. The processor 2110 may be connected to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 2110 may also be connected to an expansion bus, such as a peripheral component interconnect ("PCI") bus.

[0125] The memory device 2120 may store data used for the operation of the electronic device 2100. In an embodiment, for example, the memory device 2120 may include at least one non-volatile memory device such as an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, a ferroelectric random access memory ("FRAM") device, etc. and / or at least one volatile memory device such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a mobile dynamic random access memory ("mobile DRAM") device, etc.

[0126] The storage device 2130 may be a solid state drive ("SSD") device, a hard disk drive ("HDD") device, a compact disk read only memory ("CD-ROM") device, etc. The I / O device 2140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 2150 may provide power for the operation of the electronic device 2100. The display device 2160 may be connected to other components via a bus or other communication link.

[0127] In the display device 2160, at least one stage may include an input circuit, an inverter circuit, a first node control circuit, a second node control circuit, and an output circuit, and at least one of the inverter circuit, the first node control circuit, and the second node control circuit may include transistors of different types. In addition, the swing width of the clock signal applied to the input circuit may be smaller than the swing width of the output signal output from the output circuit. Accordingly, the driver can operate stably while reducing power consumption.

[0128] The inventive concept may be applied to any display device 2160 and any electronic device 2100 including the display device 2160. In an embodiment, for example, the inventive concept may be applied to a smart phone, a wearable electronic device, a mobile phone, a television ("TV") (e.g., a digital TV, a three-dimensional ("3D") TV, etc.), a personal computer ("PC") (such as a tablet computer or a laptop computer), a home appliance, a personal digital assistant ("PDA"), a portable multimedia player ("PMP"), a digital camera, a music player, a portable game console, a navigation device, etc.

[0129] The foregoing is an illustration of the embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made to the embodiments without departing substantially from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the disclosed illustrative embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A drive, wherein: The driver comprises: A plurality of stages, at least one of the plurality of stages comprising: an input circuit that transmits an input signal to a third node in response to a clock signal; an inverter circuit, inverting the voltage of the third node and generating a voltage of a fourth node; a first node control circuit, controlling a voltage of a first node based on the voltage of the fourth node and a voltage of a second node; a second node control circuit that controls the voltage of the second node based on the voltage of the third node and the voltage of the first node; and an output circuit that generates an output signal based on the voltage of the first node and the voltage of the second node, Wherein, at least one of the inverter circuit, the first node control circuit, and the second node control circuit includes transistors of different types.

2. The driver according to claim 1, wherein: the output signal has a first low gate voltage as a low voltage, the fourth node has a second low gate voltage as a low voltage, The first node has a third low gate voltage as a low voltage, and At least two of the first low gate voltage, the second low gate voltage, and the third low gate voltage have different voltage levels from each other.

3. The driver according to claim 2, wherein: The second low gate voltage is higher than the first low gate voltage, and The third low gate voltage is lower than or equal to the first low gate voltage.

4. The driver according to claim 2, wherein: The low gate voltage of the clock signal is different from the first low gate voltage, the second low gate voltage, and the third low gate voltage.

5. The driver according to claim 1, wherein: The input signal, the clock signal, the output signal, the first node, the second node, the third node, and the fourth node have the same high gate voltage as a high voltage.

6. The driver according to claim 1, wherein: The output circuit comprises: a first P-type metal oxide semiconductor transistor that outputs a high gate voltage as the output signal in response to the voltage of the second node; and The second P-type metal oxide semiconductor transistor outputs a first low gate voltage as the output signal in response to the voltage of the first node.

7. The driver according to claim 1, wherein: The input circuit comprises: The third P-type metal oxide semiconductor transistor transmits the input signal to the third node in response to the clock signal.

8. The driver according to claim 7, wherein: The input circuit further comprises: The fourth N-type metal oxide semiconductor transistor transmits the input signal to the third node in response to an inverted clock signal.

9. The driver according to claim 1, wherein: The inverter circuit comprises: a fourth P-type metal oxide semiconductor transistor providing a high gate voltage to the fourth node in response to the voltage of the third node; and The first N-type metal oxide semiconductor transistor provides a second low gate voltage to the fourth node in response to the voltage of the third node.

10. The driver according to claim 1, wherein: The first node control circuit comprises: a fifth P-type metal oxide semiconductor transistor providing a high gate voltage to the first node in response to the voltage of the fourth node; and The second NMOS transistor provides a third low gate voltage to the first node in response to the voltage of the second node.

11. The driver according to claim 1, wherein: The second node control circuit comprises: a sixth P-type metal oxide semiconductor transistor that provides a high gate voltage to the second node in response to the voltage of the third node; and The third N-type metal oxide semiconductor transistor provides a third low gate voltage to the second node in response to the voltage of the first node.

12. The driver according to claim 1, wherein: The at least one stage further comprises: A capacitor is connected between the third node and the second low gate voltage line.

13. The driver according to claim 1, wherein: The at least one stage further comprises: A capacitor is connected between the third node and the first node.

14. The driver according to claim 1, wherein: The at least one stage further comprises: a seventh P-type metal oxide semiconductor transistor including a gate receiving a third low gate voltage, and the seventh P-type metal oxide semiconductor transistor is disposed at the first node to divide the first node into a fifth node and a sixth node; and A capacitor is connected between an output node outputting the output signal and the sixth node.

15. The driver according to claim 1, wherein: The first node control circuit includes a second N-type metal oxide semiconductor transistor that provides a third low gate voltage to the first node, The second node control circuit includes a third N-type metal oxide semiconductor transistor for providing the third low gate voltage to the second node, and Each of the second N-type metal oxide semiconductor transistor and the third N-type metal oxide semiconductor transistor includes a bottom gate receiving a fourth low gate voltage lower than the third low gate voltage.

16. The driver according to claim 1, wherein: The first node control circuit includes a second N-type metal oxide semiconductor transistor that provides a third low gate voltage to the first node, and the second N-type metal oxide semiconductor transistor includes a first bottom gate, wherein the second node control circuit comprises a third N-type metal oxide semiconductor transistor providing the third low gate voltage to the second node, and the third N-type metal oxide semiconductor transistor comprises a second bottom gate, and Wherein, the at least one stage further comprises: a first coupling capacitor connected between the second node and the first bottom gate; an eighth P-type metal oxide semiconductor transistor, comprising a gate connected to a third low gate voltage line transmitting the third low gate voltage, a first terminal connected to the first bottom gate, and a second terminal connected to the third low gate voltage line; a second coupling capacitor connected between the first node and the second bottom gate; and A ninth P-type metal oxide semiconductor transistor includes a gate connected to the third low gate voltage line, a first terminal connected to the second bottom gate, and a second terminal connected to the third low gate voltage line.

17. The driver according to claim 1, wherein: The at least one stage further comprises: a carry circuit that generates a carry signal based on the voltage of the fourth node, and Wherein, the carry circuit comprises: a tenth P-type metal oxide semiconductor transistor, outputting a high gate voltage as the carry signal in response to the voltage of the fourth node; and The fifth N-type metal oxide semiconductor transistor outputs a second low gate voltage as the carry signal in response to the voltage of the fourth node.

18. The driver according to claim 17, wherein: The second low gate voltage is higher than the first low gate voltage which is the low voltage of the output signal, and The low gate voltage of the clock signal is higher than the first low gate voltage and lower than the second low gate voltage.

19. A drive, wherein: The driver comprises a plurality of stages, at least one of the plurality of stages comprising: a first P-type metal oxide semiconductor transistor including a gate connected to the second node, a first terminal connected to the high gate voltage line, and a second terminal connected to the output node; a second P-type metal oxide semiconductor transistor including a gate connected to the first node, a first terminal connected to the output node, and a second terminal connected to the first low gate voltage line; a third P-type metal oxide semiconductor transistor including a gate receiving a clock signal, a first terminal receiving an input signal, and a second terminal connected to a third node; a fourth P-type metal oxide semiconductor transistor including a gate connected to the third node, a first terminal connected to the high gate voltage line, and a second terminal connected to a fourth node; a first N-type metal oxide semiconductor transistor including a gate connected to the third node, a first terminal connected to the fourth node, and a second terminal connected to a second low gate voltage line; a fifth P-type metal oxide semiconductor transistor including a gate connected to the fourth node, a first terminal connected to the high gate voltage line, and a second terminal connected to the first node; a second N-type metal oxide semiconductor transistor including a gate connected to the second node, a first terminal connected to the first node, and a second terminal connected to a third low gate voltage line; a sixth P-type metal oxide semiconductor transistor including a gate connected to the third node, a first terminal connected to the high gate voltage line, and a second terminal connected to the second node; a third N-type metal oxide semiconductor transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third low gate voltage line; and A capacitor is connected between the third node and the second low gate voltage line.

20. A display device, wherein: The display device comprises: A display panel including a plurality of pixels; a data driver for providing data signals to the plurality of pixels; A gate driver, providing gate signals to the plurality of pixels; an emission driver that provides emission signals to the plurality of pixels; and A controller controls the data driver, the gate driver and the emission driver, at least one of the gate driver and the emission driver comprising: A plurality of stages, at least one of the plurality of stages comprising: an input circuit that transmits an input signal to a third node in response to a clock signal; an inverter circuit, inverting the voltage of the third node and generating a voltage of a fourth node; a first node control circuit, controlling a voltage of a first node based on the voltage of the fourth node and a voltage of a second node; a second node control circuit that controls the voltage of the second node based on the voltage of the third node and the voltage of the first node; and an output circuit that generates an output signal based on the voltage of the first node and the voltage of the second node, Wherein, at least one of the inverter circuit, the first node control circuit, and the second node control circuit includes transistors of different types.

Images