Configuration method of phase change nonvolatile memory

Abstract

The present specification relates to a configuration method of a phase change non-volatile memory, comprising partitioning the memory into a first set of one or more regions having a first maximum write cycle number, and a second set of one or more other regions having a second maximum write cycle number greater than the first maximum write cycle number, the first maximum write cycle number and the second maximum write cycle number are associated with different physical write parameters.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATION(S)

[0002] This application claims the benefit of priority to French patent application No. FR2312769, filed on November 21, 2023, entitled “Procédé de configuration d'une mémoire non volatile à changement de phase”. Technical Field

[0003] The present specification generally relates to configuration methods of phase-change non-volatile memory and microcontrollers implementing these methods. Background Art

[0004] Phase change non-volatile memory integrated in a microcontroller is potentially sensitive to high temperatures, such as those used during the soldering step. This may produce changes to the data written to the memory prior to the soldering step. It is even more difficult to predict at which point in the life of the microcontroller the soldering step will occur. Summary of the invention

[0005] A method for configuring a phase-change non-volatile memory of a microcontroller is provided to address the situation where the microcontroller is soldered before or after data is written to the memory, while maintaining a satisfactory maximum number of write cycles.

[0006] The embodiments overcome all or part of the disadvantages of the known methods.

[0007] An embodiment provides a configuration method for a phase-change non-volatile memory, comprising partitioning the memory into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, wherein the first maximum number of write cycles and the second maximum number of write cycles are associated with different physical write parameters.

[0008] An embodiment provides a microcontroller provided with a phase change non-volatile memory, which is configured to implement partitioning of the memory into a first set of one or more areas having a first maximum number of write cycles and a second set of one or more other areas having a second maximum number of write cycles greater than the first maximum number of write cycles, wherein the first maximum number of write cycles and the second maximum number of write cycles are associated with different physical write parameters.

[0009] According to an embodiment, the first maximum number of write cycles corresponds to the use of a first write mode and the second maximum number of write cycles corresponds to the use of a second write mode.

[0010] According to an embodiment, the partitioning and the use of the first writing mode and the use of the second writing mode are implemented by a memory interface.

[0011] According to an embodiment, when using the first write mode, data elements written before the soldering step of the microcontroller remain stable during said soldering step.

[0012] According to an embodiment, when the second writing mode is used, the values ​​written before the soldering step of the microcontroller do not remain stable during said soldering step.

[0013] According to an embodiment, the second maximum number of write cycles is at least five times greater than the first maximum number of write cycles.

[0014] According to an embodiment, after writing, the crystallinity of the memory sectors in the regions of the first set and the second set differs depending on the use of the first writing mode or the use of the second writing mode.

[0015] According to an embodiment, use of the first writing mode or use of the second writing mode is defined for each zone of each set by one or more option bytes.

[0016] According to an embodiment, the definition of the use of the first writing mode or the definition of the use of the second writing mode is implemented by a bitmap register associated to the option byte(s).

[0017] According to an embodiment, when the use of a first write mode has been defined for one or more zones of one of the sets, and this or these zones correspond to an application requiring a number of write cycles Nappli greater than a first maximum number of write cycles, then the (one or more) zones are divided into N memory sectors into which the data of the application are written successively; N is greater than or equal to the ratio of Nappli to the first maximum number of write cycles.

[0018] According to an embodiment, N memory sectors have their respective addresses with indices, and when one of the data elements of the application is written to the memory sector indexed N, the next data element is then written to the sector with the lowest index.

[0019] According to an embodiment, after writing in an area by using the second writing pattern, it is possible to re-write in the area by using the first writing pattern.

[0020] According to an embodiment, after writing into an area by using a first writing mode, it is not possible to re-write into the area by using a second writing mode.

[0021] According to an embodiment, the first writing mode comprises applying a first voltage, current or power level; and the second writing mode comprises applying a second voltage, current or power level different from the first voltage, current or power level.

[0022] According to an embodiment, the first voltage, current or power level is higher than the second voltage, current or power level. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above-mentioned features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0024] Figure 1 An example of a microcontroller of the type to which the described embodiments are applicable is shown very schematically and in block diagram form;

[0025] Figure 2 A block diagram is shown according to an embodiment Figure 1 The configuration method of the box;

[0026] Figure 3 A block diagram is shown according to another embodiment Figure 1 The configuration method of the box;

[0027] Figure 4 An example of a block of a microcontroller according to one embodiment is shown very schematically;

[0028] Figure 5 The block diagram shows Figure 4 The configuration method of the box;

[0029] Figure 6 Very schematically shown Figure 4 An example of a box;

[0030] Figure 7 The block diagram shows Figure 6 The configuration method of the box and write to Figure 6 The method in the box; and

[0031] Figure 8 The block diagram shows Figure 6 Another way to configure the box and another way to write to Figure 6 The method in the box. DETAILED DESCRIPTION

[0032] Similar features in the various figures have been denoted by similar reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may be deployed with the same structure, dimensions and material properties.

[0033] For clarity, only those steps and elements that are helpful for understanding the embodiments are shown and described in detail.

[0034] Unless otherwise stated: when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0035] In the following description, when absolute position qualifiers such as "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as "top", "bottom", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc. are mentioned, unless otherwise specified, they refer to the orientation of the drawing.

[0036] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0037] Figure 1 An example of a microcontroller 100 of the type to which the described embodiments are applicable is shown very schematically and in block diagram form. The microcontroller 100 is, for example, a microcontroller.

[0038] The microcontroller 100 comprises a non-volatile memory 104 (NVM), for example of the phase change type, which is able to communicate via a communication bus 114 with a non-volatile memory interface 106 (NVM interface), which is configured to write data to the non-volatile memory 104 or read data from the non-volatile memory 104.

[0039] The microcontroller 100 further includes, for example, a processing unit 110 (CPU) including one or more processors under the control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is, for example, a volatile random access memory (RAM). The processing unit 110 and the memory 112 communicate, for example, via a system (data, address and control) bus 140. The memory 104 is coupled to the system bus 140 via a non-volatile memory interface 106 and via a bus 114. The device 100 also includes an input / output interface 108 (I / O interface) coupled to the system bus 140 for communication with the outside.

[0040] The microcontroller 100 may integrate other circuits (e.g., one or more volatile and / or non-volatile memories, or other processing units) for implementing other functions. Figure 11 is symbolized by box 116 (FCT). Among these other circuits, microcontroller 100 includes, for example, a read-only or static memory 118 (ROM).

[0041] For example, the memory 104 is partitioned into different areas including one or more memory sectors. In the phase change memory 104, these sectors can be directly rewritten without a prior erase operation. Writing into these sectors is performed by changing their resistance, for example by applying a physical write parameter such as a voltage or current when writing.

[0042] Recently, a variety of write modes have been developed to write data into the memory sectors of phase change memory. Some write modes allow a high maximum number of write cycles, for example, about 10,000 cycles, while other write modes allow a lower maximum number of write cycles, for example, about 1,000 cycles, but with higher temperature resistance. The performance of the cycles of different write modes is, for example, associated with the change of the crystallinity of the memory sectors according to the selected write mode. The term crystallinity similarly represents atomic arrangement, for example, the orientation, lattice parameters or amorphous, polycrystalline or single crystal properties of the atomic plane. However, the sectors written in the write mode that allows a high maximum number of write cycles (for example, 10,000 cycles) are more sensitive to high temperatures (such as the high temperatures reached by the microcontroller 100 when being welded). Therefore, the data written in the write mode that allows high cycles may be damaged or erased when the microcontroller is being welded, in other words, not robust.

[0043] For example, different applications implemented by the microcontroller 100 use different areas of the memory 104. Each type of application may require a different maximum number of cycles. Some applications may also be implemented by the microcontroller manufacturer in the factory, and other applications may be loaded by external service providers who will solder the microcontroller in the product before or after writing the data. It is therefore difficult to predict when the microcontroller will be soldered.

[0044] On the other hand, conventional non-volatile memory (ie, not phase change memory) allows high write cycles, yet is not overly sensitive to temperature. Therefore, customers or service providers should be allowed to use phase change memory in a manner close to that of conventional non-volatile memory.

[0045] The described embodiments provide for partitioning a memory 104 into a first set of one or more zones having a first maximum number of write cycles and a second set of one or more other zones having a second maximum number of write cycles greater than the first maximum number of write cycles, wherein the first maximum number of write cycles and the second maximum number of write cycles are associated with different physical write parameters.

[0046] This makes it possible to exploit the advantages of phase change memory, such as not having to erase before rewriting, while providing flexibility in choosing the write mode for various customers or service providers using the microcontroller 100. Thus, for example, a solder-resistant write mode can be chosen for a given area of ​​the memory, and another write mode can be chosen for another area, which is not robust to the soldering step but is anyway implemented after soldering.

[0047] Embodiments also enable obtaining the same maximum number of write cycles as conventional non-volatile memory while ensuring that data written prior to welding will remain robust.

[0048] Figure 2 It shows that according to the embodiment Figure 1 More specifically, Figure 2 A configuration method of the memory 104 is illustrated.

[0049] During a first step 202 (start), a method for configuring memory 104 is started and carried out, for example, by means of memory interface 106 .

[0050] During the second step 204 (Partitioning NVM PCM Memory in Different Regions, Each Region Having At Least Two Possible Write Modes with Different Maximum Write Cycle Counts), the memory 104 is divided into one or more regions (e.g., by using the memory interface 106), each region having multiple possible write modes. The (one or more) regions each include one or more memory sectors. In other words, the memory 104 is partitioned into multiple regions, each region having multiple possible write modes, each write mode allowing a maximum memory sector write cycle count and data temperature tolerance specific thereto.

[0051] In the example, the first write mode (power mode) enables data elements in a memory sector of one of the areas in the memory 104, which were written to before the welding step of the microcontroller 100, to remain stable during the welding step of the microcontroller 100. The first write mode is obtained, for example, by applying a first voltage level, a first current level or a first electrical power level. These first voltage, current or power levels may also include voltage, current or power variations.

[0052] In the example of the second write mode (user mode), the data elements written into the memory sector before the welding step of the microcontroller do not remain stable during the welding step. This difference in temperature resistance between the first mode and the second mode is, for example, due to the fact that one or more voltages, currents or powers achieved by the first mode (power mode) are higher than those achieved for the second mode (user mode). The second write mode is obtained, for example, by applying a second voltage level, a second current level or a second electrical power level that is different from the first voltage, current or power level (for example, lower than the first voltage, current or power level). These second voltage, current or power levels may also include voltage, current or power variations. In the example, the resistivity of the memory sector in the area obtained using the second write mode is different from the resistivity obtained using the first write mode.

[0053] In an example, the second write mode (user mode) allows a higher maximum number of write cycles than the first write mode (power mode), for example more than five times higher. The second write mode (user mode) allows a maximum number of write cycles of, for example, about 10,000 cycles, while the first write mode (power mode) allows a maximum number of write cycles of, for example, about 1,000 cycles, but the temperature resistance of the written data is higher.

[0054] The difference between the maximum number of write cycles achievable by the first write mode and the second write mode is due, for example, to the difference between the first and second voltage modes or current modes.

[0055] Figure 3 A block diagram is shown according to another embodiment Figure 1 The configuration method of the box. Figure 3 The method is similar to Figure 2 The method is the same as that of FIG. 2 , but an additional step 306 is implemented after step 204 (for different areas, defining a writing mode among possible writing modes).

[0056] At step 306 , among possible write modes, a write mode, such as a first mode or a second mode, is defined (in other words, selected) for each area in the memory 104 . The definition is implemented, for example, by the memory interface 106 .

[0057] The term designation means that each area is assigned a write mode selected from among, for example, the first or second write mode. The selection of the write mode is performed, for example, by changing an option byte.

[0058] After writing into memory sectors in an area defined with a first write mode (power mode), these sectors cannot be rewritten when the area is subsequently defined with a second write mode (user mode), in case the first write mode permanently modifies the crystallinity of the memory sectors.

[0059] In contrast, after writing to memory sectors in an area defined to have the second write mode (user mode), in a case where the second write mode (user mode) does not permanently modify the crystallinity of the memory sectors, these sectors can be rewritten if the area is subsequently defined to have the first write mode (power mode).

[0060] Figure 3 The method offers the possibility of specifying or allocating, for example, a first writing mode or a second writing mode for each zone, allowing several successive service providers or customers to use the microcontroller at the same time.

[0061] Figure 4 An example of a block of a microcontroller 100 according to one embodiment is shown very schematically.

[0062] More specifically, Figure 4 An example of partitioning memory 104 into regions 402 (user memory), 404 (system memory), 406 (HCD), 408 (OBK1 / 2 / 3), 410 (OBK0), 412 (OTP), 414 (RO), 416 (user OB), and 418 (Engi Ob) is shown. Figure 4 The write mode defined for each zone in the example zones depends on the usage of the zone (eg, usage of the zone by different applications).

[0063] Area 402 includes, for example, a plurality of sub-sectors, each of which is defined to have one of the write modes. In an example, each sub-sector corresponds to a group of a plurality of sectors, such as four sectors. In order to define the write mode of each sub-sector, a bitmap register is used, for example, in association with (one or more) option bytes. In an example, setting an option bit or byte of the bitmap register to 0 or to 1 corresponds to defining the write mode selected for the sub-sector corresponding to the bit or byte. In an example, the bitmap register is referred to as NVM_WRMyR. In this example, the first sub-sector is recorded as NVM_WRMyR[0], the second sub-sector is recorded as NVM_WRMyR[1], and the third sub-sector is recorded as NVM_WRMyR[2], and so on. The bitmap register associates a bit or byte representing a first or second write mode (e.g., 0 represents the first mode and 1 represents the second mode) with each sub-sector in the sub-sectors of area 402.

[0064] For example, area 404 is used by an application that has its data written by the manufacturer of microcontroller 100. Furthermore, since area 404 is not intended to be rewritten, it only requires a small write cycle capacity. The welding step will probably be implemented later in the life of the microcontroller. Therefore, area 404 is defined with, for example, a first write mode so that data can be retained during the welding step.

[0065] For example, area 406 is used by applications that require a large number of write cycles. Therefore, area 406 is defined to have a second write mode. In an example, the definition of the write mode is hard-coded from the beginning of the microcontroller manufacturing so that it cannot be modified by the program.

[0066] For example, region 412 corresponds to one-time programmable data. Therefore, the required low cycling level enables the use of the first write mode (power mode) for this region.

[0067] For example, the area 414 corresponds to data that can only be read (read-only data). Therefore, the required low write cycle level enables the use of the first write mode (power mode) for this area 414.

[0068] For example, zone 416 corresponds to data written by the manufacturer of the microcontroller, but which can be updated, for example, by an external service provider during the service life of the microcontroller. In other words, the microcontroller may be soldered after the manufacturer writes the data. Therefore, the write mode defined for this zone must be the first write mode (power mode). However, it may be necessary to maintain data updates in this zone throughout the service life of the microcontroller 100. For example, some applications need to achieve a larger number of write cycles Nappli, such as 10,000 times.

[0069] Figure 6 and Figure 7 The embodiments described in make it possible to solve this problem.

[0070] For example, zone 418 is programmed by the manufacturer with data corresponding, for example, to manufacturing or commissioning data issued by the manufacturer.The number of write cycles in the life of the microcontroller is reduced and therefore zone 418 is defined with a first write mode (power mode) to withstand the soldering step.

[0071] Area 420 includes, for example, five sub-sectors OBK0, OBK1, OBK2, OBK3NS, and OBK3S, which include, for example, option byte keys corresponding to security keys of different service providers. These option byte keys can be programmed by different service providers outside the manufacturer, for example. For example, the four sub-sectors OBK1, OBK2, OBK3NS, and OBK3S can be defined with programmable write modes after manufacturing, which enables flexibility in use.

[0072] For example, sub-sector OBK0 is programmed by the manufacturer with data that must remain robust throughout the service life of the microcontroller 100. Therefore, sub-sector OBK0 is defined to have a first write mode (power mode). In the example, such definition of the write mode is hard-coded from the beginning of the microcontroller manufacturing so as not to be modified by the program.

[0073] In an example not shown, all sub-sectors OBK1, OBK2, OBK3NS and OBK3S belong to two sectors, namely the current sector containing the valid values ​​of all security keys of sub-sectors OBK1, OBK2, OBK3NS and OBK3S, and the alternative sector used to update these keys. In order to update the key in one of the sub-sectors, the alternative sector is selected (for example by implementing a dedicated register), after which the new key is written to the alternative sector (for example by software means), and the valid keys of the other sub-sectors are copied in the alternative sector (for example by a state machine associated with a command (for example, called OBKSWAP)). The command OBKSWAP is implemented, for example, via the memory interface 106 to exchange the effect of two sectors. Therefore, the alternative sector becomes the current sector in which the data elements of the new key are valid. Since sub-sectors OBK1, OBK2, OBK3NS and OBK3S can be defined with different write modes and used with different numbers of write cycles, it is not recommended to update all sub-sectors every time the key of a single sub-sector in the sub-sectors must be updated. For example, if sub-sectors OBK0 and OBK1 are programmed with a first write mode (power mode) and other sub-sectors are programmed with a second mode (user mode), then if the user updates the key in OBK2 thousands of times, sub-sectors OBK0 and OBK1 also cycle thousands of times, which become easily damaged in the first write mode.

[0074] Therefore, it is necessary to provide different methods for writing into the sub-sectors of zone 420, which methods are compatible with the fact that multiple writing modes can be defined for the different sub-sectors OBKO, OBK1, OBK2, OBK3NS and OBK3S.

[0075] Figure 5 A block diagram is shown according to an embodiment Figure 4 More specifically, Figure 5 A method of writing into sub-sectors OBK1, OBK2, OBK3NS, and OBK3S of area 420 is illustrated.

[0076] Figure 5 The method is that, for data updating, each sub-sector OBK0, OBK1, OBK2, OBK3NS and OBK3S is managed independently, with two sectors being specific to each of the sub-sectors.

[0077] Because in Figure 5 In the example shown in , sub-sectors OBK1, OBK2, OBK3NS and OBK3S are treated independently, so Figure 5 A method is shown in which a new key is written to a single sub-sector among the sub-sectors (ie, the sub-sector concerned by the update of one of the keys), while the other sub-sectors remain unchanged.

[0078] At step 502 (OBKSWAP request), the current sector is referred to as S1 and the replacement sector is referred to as S2. In this step, a command referred to as OBKSWAP is implemented (eg, using a state machine).

[0079] At step 504 (address index=0) following step 502, the index of the address read from the current sector starts from zero.

[0080] At step 506 (Is the data in S2 original?) after step 504, check whether the address corresponding to the current index is blank. If so (branch Y), then execute step 508 (copy data from S1 to S2). If not, then execute step 510 (end of sector?).

[0081] At step 508 , the data from the current sector S1 and the updated key are copied to the replacement sector S2 , and then step 510 is performed.

[0082] At step 510 , if the address index corresponds to the sector end address (branch Y), then step 512 is performed (erase current sector: S1 ). If the index does not correspond to the sector end address (branch N), then the index is incremented and the method returns to step 506 .

[0083] At step 512, the current sector S1 is erased.

[0084] Step 512 is followed by step 514 (Swap Current / Alternate Sectors), where the current sector S1 becomes the alternate sector and the alternate sector S2 becomes the current sector.

[0085] Figure 6 Very schematically shown Figure 4 Example of a box. Figure 6More specifically, an example implementation of zone 416 is shown, in which zone 416 is divided into ten sectors or sector groups 602 (User OB1), 604 (User OB2), 606 (User OB3), 608 (User OB4), 610 (User OB5), 612 (User OB6), 614 (User OB7), 616 (User OB8), 618 (User OB9), and 620 (User OB10). Each sector in zone 416 is defined to have a first write mode.

[0086] This example of an embodiment associated with the write method described in the next figure enables applications using area 416 to benefit from the robustness of data written in the first write mode (power mode) while benefiting from a maximum number of write cycles that is greater than the maximum number of write cycles available for the first write mode (power mode).

[0087] Figure 7 The block diagram shows Figure 6 More specifically, Figure 7 shows how to configure and write to Figure 6 The method in zone 416.

[0088] Figure 7 The methods include Figure 3 The example is similar to steps 202, 204 and 306.

[0089] In an additional step 708 (dividing the area into N groups of sectors, N being greater than or equal to the ratio of the maximum number of write cycles required to the maximum number of write cycles of the first mode) performed after step 306, if the maximum number of write cycles Nappli required by the application using the area 416 is greater than the maximum number of write cycles of the first writing mode (power mode), then the area is divided into N memory sectors into which the data of the application are written. N is, for example, greater than or equal to the ratio of Nappli to the maximum number of write cycles in the first writing mode (power mode).

[0090] At step 710 following step 708 (write data in one sector in a sector group, then change sector when threshold is reached), a counter counts the number of write cycles that occur in each of the N memory sectors.

[0091] In an example, when the counter reaches a given threshold for a sector, data is then written to another sector. In an example, when the counter reaches the threshold, the sector with less written data becomes the sector into which the new data of the application is written.

[0092] Steps 708 and 710 are performed, for example, by means of memory interface 106 .

[0093] Each sector in zone 416 has a capacity of 1000 write cycles, for example, due to the use of the first write mode (power mode). By switching from one sector to another, a maximum number of write cycles of 10000 (10*1000) can be achieved for zone 416 as a whole. This maximum number of write cycles is much higher than the maximum number of write cycles of the first write mode (power mode) while maintaining the robustness of the written data associated with the welding step.

[0094] Figure 8 A block diagram shows another configuration method and another way to write to Figure 6 In particular, Figure 8 shows how to configure and write to Figure 6 The method in zone 416.

[0095] Figure 8 The methods include Figure 3 The example is similar to steps 202, 204 and 306.

[0096] In an additional step 808 (Write First Valid Data in First Sector with First Index) performed after step 306, a valid data element is written in a first write mode to a first sector or first group of sectors in area 416 (whose address has a first index). For example, the data element corresponds to a security key, such as an option byte key.

[0097] At step 809 (Have all sectors reached the maximum number of data write cycles?) after step 808, if the number of N sectors or groups of sectors of zone 416 that have been written is equal to the maximum possible number of write cycles of the first write mode (branch Y), the method stops at step 811 (Stop). In the opposite case (branch N), step 810 (update sector index and write data in the sector corresponding to the updated index) is implemented.

[0098] At step 810, the data elements previously written to the first sector are no longer valid. In this step, the address index relative to the sector or group of sectors in zone 416 is incremented unless the index is equal to Figure 7 The index is then reset to 0, e.g., as in a circular permutation. New valid data elements are then written to the sectors or groups of sectors in area 416 (whose addresses correspond to the updated index) in the first write mode (power mode). Thus, each of the N sectors is filled in turn until each of the sectors has reached the maximum number of write cycles associated with using the first write mode.

[0099] Then step 809 is implemented again.

[0100] Steps 808 , 809 and 810 are implemented, for example, by means of memory interface 106 .

[0101] In the example where the maximum number of write cycles in the first mode is 1000 cycles, the maximum number of write cycles for zone 416 as a whole can therefore reach 10000 (10*1000) cycles, which is much higher than the maximum number of write cycles in the first write mode (power mode) while maintaining the robustness of the written data associated with the welding step.

[0102] A variety of embodiments and variants have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variants may be combined, and those skilled in the art will recognize other variants. In particular, the use of bitmap registers may be generalized to all regions of memory 104.

[0103] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, although the method is described in the context of a microcontroller, a person skilled in the art can implement their knowledge to apply the method to other types of electronic circuits, such as a system on a chip (SOC).

[0104] A configuration method for a non-volatile phase change memory (104) may include partitioning the memory (104) into a first set of one or more zones (402, 404, 406, 408, 410, 412, 414, 416, 418) having a first maximum number of write cycles and a second set of one or more other zones (402, 404, 406, 408, 410, 412, 414, 416, 418) having a second maximum number of write cycles greater than the first maximum number of write cycles, the first maximum number of write cycles and the second maximum number of write cycles being associated with different physical write parameters.

[0105] A microcontroller (100) may be provided with a phase-change non-volatile memory (104) configured to implement partitioning of the memory (104) into a first set of one or more zones (402, 404, 406, 408, 410, 412, 414, 416, 418) having a first maximum number of write cycles and a second set of one or more other zones (402, 404, 406, 408, 410, 412, 414, 416, 418) having a second maximum number of write cycles greater than the first maximum number of write cycles, the first maximum number of write cycles and the second maximum number of write cycles being associated with different physical write parameters.

[0106] The first maximum number of write cycles may correspond to the use of a first write mode (power mode), and the second maximum number of write cycles may correspond to the use of a second write mode (user mode).

[0107] Partitioning and use of the first write mode and use of the second write mode may be accomplished via a memory interface (106).

[0108] When the first write mode (power mode) is used, data elements written prior to the soldering step of the microcontroller (100) can remain stable during the soldering step.

[0109] When the second writing mode (user mode) is used, the values ​​written before the soldering step of the microcontroller (100) cannot remain stable during the soldering step.

[0110] The second maximum number of write cycles may be at least five times greater than the first maximum number of write cycles.

[0111] After writing, the crystallinity of the memory sectors in the regions of the first set and the second set may be different depending on the use of the first writing pattern or the use of the second writing pattern.

[0112] Use of the first writing mode or use of the second writing mode may be defined for each zone in each set by one or more option bytes.

[0113] The limitation of the use of the first writing mode or the limitation of the use of the second writing mode may be implemented using a bitmap register associated to the option byte(s).

[0114] When the use of a first write mode (power mode) has been defined for one or more zones of one of the sets, and this zone or zones correspond to an application requiring a number of write cycles Nappli greater than a first maximum number of write cycles, then the (one or more) zones can be divided into N memory sectors (502, 504, 506, 508, 510, 512, 514, 516, 518, 520) into which the data of the application are written successively; N is greater than or equal to the ratio of Nappli to the first maximum number of write cycles.

[0115] N memory sectors may have their own address with an index, and when one of the data elements of the application is written to the memory sector indexed N, the next data element may then be written to the sector with the lowest index.

[0116] After writing into the area by using the second writing mode (user mode), it is possible to re-write into the area by using the first writing mode (power mode).

[0117] After writing in an area by using the first writing mode (power mode), it is not possible to re-write in the area by using the second writing mode (user mode).

[0118] The first write mode (power mode) may include applying a first voltage, current, or power level; and the second write mode (user mode) may include applying a second voltage, current, or power level that is different from the first voltage, current, or power level.

[0119] The first voltage, current, or power level may be higher than the second voltage, current, or power level.

[0120] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications cited in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If necessary, the concepts of various patents, applications, and publications are adopted to provide further embodiments, and various aspects of the embodiments can be modified.

[0121] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalent forms to which these claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A configuration method for a non-volatile phase change memory, comprising: partitioning the nonvolatile phase-change memory into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, The first maximum number of write cycles and the second maximum number of write cycles are associated with different physical write parameters.

2. A microcontroller provided with a phase change non-volatile memory, configured to: implementing partitioning the phase-change non-volatile memory into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, The first maximum number of write cycles and the second maximum number of write cycles are associated with different physical write parameters.

3. The method of claim 1, wherein the first maximum number of write cycles corresponds to the use of a first write mode (power mode), and the second maximum number of write cycles corresponds to the use of a second write mode (user mode). The method of claim 3 , wherein the partitioning and the use of the first write mode and the use of the second write mode are implemented via a memory interface.

5. The method according to claim 3, wherein: When the first write mode (power mode) is used, data elements written before the soldering step of the microcontroller remain stable during the soldering step.

6. The method according to claim 3, wherein: When the second writing mode (user mode) is used, the values ​​written before the soldering step of the microcontroller do not remain stable during the soldering step. 7 . The method of claim 1 , wherein the second maximum number of write cycles is at least five times greater than the first maximum number of write cycles.

8. The method according to claim 3, wherein: After writing, the crystallinity of the memory sectors in the regions of the first set and the second set differs depending on the use of the first writing pattern or the use of the second writing pattern.

9. The method of claim 3, wherein use of the first writing mode or use of the second writing mode is defined for each zone in each set by one or more of the option bytes.

10. The method of claim 9, wherein the limiting of the use of the first writing mode or the limiting of the use of the second writing mode is implemented by a bitmap register associated to the one or more option bytes.

11. The method according to claim 3, wherein when the use of a first write mode (power mode) has been defined for one or more zones of one of the first set and the second set, and the one or more zones of one of the first set and the second set correspond to an application requiring a number of write cycles Nappli greater than a first maximum number of write cycles, then the one or more zones of one of the first set and the second set are divided into N memory sectors into which data of the application is successively written, N is greater than or equal to a ratio of Nappli to the first maximum number of write cycles.

12. The method of claim 11, wherein the N memory sectors have their respective addresses with indices, and when one of the data elements of the application is written to a memory sector indexed N, the next data element is then written to the sector with the lowest index.

13. The method according to claim 3, wherein: After writing into the area by using the second writing mode (user mode), it is possible to re-write into the area by using the first writing mode (power mode).

14. The method according to claim 3, wherein: After writing in an area by using the first writing mode (power mode), it is not possible to re-write in the area by using the second writing mode (user mode).

15. The method of claim 3, wherein the first write mode (power mode) comprises applying at least one of a first voltage, current, or power level; and The second write mode (user mode) includes applying at least one of a second voltage, current, or power level that is different from the at least one of the first voltage, current, or power level.

16. The method of claim 15, wherein at least one of the first voltage, current, or power level is higher than the at least one of the second voltage, current, or power level.

17. The microcontroller of claim 2, wherein the first maximum number of write cycles corresponds to use of a first write mode, and the second maximum number of write cycles corresponds to use of a second write mode.

18. The microcontroller according to claim 17, wherein use of the first writing mode or use of the second writing mode is defined for each zone in each set by one or more option bytes.

19. The microcontroller according to claim 17, wherein: When the use of the first write mode has been defined for one or more zones of one of the first set and the second set, and the one or more zones of one of the first set and the second set correspond to an application requiring a number of write cycles Nappli greater than a first maximum number of write cycles, then the one or more zones of one of the first set and the second set are divided into N memory sectors into which data of the application are successively written, N is greater than or equal to a ratio of Nappli to the first maximum number of write cycles.

20. The microcontroller of claim 17, wherein the first write mode comprises applying at least one of a first voltage, current, or power level, and The second write mode includes applying at least one of a second voltage, current, or power level that is different from the at least one of the first voltage, current, or power level.

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