Memory device, control method thereof, and memory system

Abstract

Embodiments of the present disclosure disclose a memory device, a control method thereof, and a memory system, the memory device including: a memory array including a plurality of memory rows, each of the memory rows including a plurality of memory cells coupled on one word line, and a peripheral circuit coupled with the memory array; the peripheral circuit is configured to: in response to a read command, determine whether address information identical to first address information of a first storage line corresponding to the read command exists in a refresh table; a plurality of pieces of address information are stored in the refresh table, and each piece of address information corresponds to one storage row in the plurality of storage rows; and in response to the situation that the address information which is the same as the first address information exists in the refresh table, deleting the address information which is the same as the first address information from the refresh table.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, for example, to a memory device and a control method thereof, and a memory system. Background Art

[0002] A memory device is a storage device used to store information in modern information technology, such as a dynamic random access memory (DRAM), which may include a storage array and peripheral circuits. The peripheral circuits may control the storage array and operate the storage array to perform read, write or refresh operations. Summary of the invention

[0003] According to some aspects of the embodiments of the present disclosure, a memory device is provided, comprising: a memory array and a peripheral circuit coupled to the memory array, the memory array comprising a plurality of memory rows, each of the memory rows comprising a plurality of memory cells coupled to a word line; the peripheral circuit being configured to: in response to a read command, determine whether there is address information in a refresh table that is identical to first address information of a first memory row corresponding to the read command; the refresh table storing a plurality of address information, each of which corresponds to one of the plurality of memory rows; in response to the presence of address information in the refresh table that is identical to the first address information, delete the address information that is identical to the first address information from the refresh table.

[0004] In some embodiments, the multiple address information are sorted according to priority; the peripheral circuit is also configured to: perform a refresh operation on the corresponding storage row according to the highest priority address information in the refresh table, and delete the refreshed highest priority address information from the refresh table.

[0005] In some embodiments, the peripheral circuit is further configured to: determine whether there is address information of a storage row adjacent to the first storage row in the refresh table; in response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, insert the address information of a storage row adjacent to the first storage row into the refresh table; in response to the presence of address information of a storage row adjacent to the first storage row in the refresh table, adjust the priority of the address information of the storage row adjacent to the first storage row in the refresh table.

[0006] In some embodiments, the refresh table includes a first sub-table and a second sub-table; the priority of the address information in the first sub-table is higher than the priority of the address information in the second sub-table.

[0007] In some embodiments, the peripheral circuit is further configured to: in response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, insert the address information of the storage row adjacent to the first storage row into the second sub-table, and the address information of the storage row adjacent to the first storage row has the highest priority in the second sub-table.

[0008] In some embodiments, the storage rows adjacent to the first storage row include a second storage row and a third storage row, and the peripheral circuit is further configured to: in response to the absence of address information identical to the second address information corresponding to the second storage row and address information identical to the third address information corresponding to the third storage row in the refresh table, insert the second address information and the third address information into the second sub-table; wherein the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority; or, the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority.

[0009] In some embodiments, the peripheral circuit is further configured to: in response to address information of a storage row adjacent to the first storage row existing in the first sub-table, adjust the priority of address information of a storage row adjacent to the first storage row to the highest priority in the first sub-table.

[0010] In some embodiments, the peripheral circuit is further configured to: in response to address information of a storage row adjacent to the first storage row existing in the second sub-table, adjust address information of a storage row adjacent to the first storage row into the first sub-table.

[0011] In some embodiments, the priority of the address information of the storage row adjacent to the first storage row in the first sub-table is the lowest priority.

[0012] In some embodiments, the peripheral circuit is further configured to: when the amount of address information stored in the second sub-table is greater than a set threshold, delete at least one address information in the second sub-table.

[0013] In some embodiments, the peripheral circuit is configured to: delete the address information in the second sub-table in order of priority; wherein, the address information with a lower priority is deleted first.

[0014] In some embodiments, the peripheral circuit is further configured to: in response to deleting the highest priority address information after refresh from the refresh table, increase the priority levels corresponding to the remaining address information in the refresh table by one level, and insert the fourth address information corresponding to the fourth storage row into the refresh table, wherein the priority level of the fourth address information in the refresh table is the lowest priority level.

[0015] In some embodiments, the priority of each of the plurality of address information is determined according to the probability that the storage row corresponding to the address information is attacked by a row hammer.

[0016] In some embodiments, the peripheral circuit includes: control logic, and a comparison unit coupled thereto; wherein the comparison unit is configured to: in response to the read command, obtain each address information in the refresh table, and compare the first address information with each address information one by one to generate a comparison result; send the comparison result to the control logic; the control logic is configured to: determine whether there is address information identical to the first address information in the refresh table based on the comparison result; and in response to the existence of address information identical to the first address information in the refresh table, delete the first address information from the refresh table.

[0017] According to some aspects of the embodiments of the present disclosure, a memory system is provided, comprising the memory device of the above embodiments, and a memory controller, wherein the memory controller is coupled to the memory and controls the memory device.

[0018] According to some aspects of the embodiments of the present disclosure, a control method for a memory device is provided, comprising: in response to a read command, determining whether there is address information in a refresh table that is identical to first address information of a first storage row corresponding to the read command; wherein the refresh table stores a plurality of address information, each address information corresponding to one storage row of the plurality of storage rows; each of the storage rows comprises a plurality of storage cells coupled to a word line; in response to the presence of address information in the refresh table that is identical to the first address information, deleting the address information that is identical to the first address information from the refresh table.

[0019] In some embodiments, the multiple address information are sorted according to priority, and the control method further includes: performing a refresh operation on the corresponding storage row according to the highest priority address information in the refresh table, and deleting the refreshed highest priority address information from the refresh table.

[0020] In some embodiments, the control method includes: determining whether there is address information of a storage row adjacent to the first storage row in the refresh table; in response to the absence of address information of an adjacent storage row of the first storage row in the refresh table, inserting the address information of an adjacent storage row of the first storage row into the refresh table; in response to the presence of address information of an adjacent storage row of the first storage row in the refresh table, adjusting the priority of the address information of an adjacent storage row of the first storage row in the refresh table.

[0021] In some embodiments, the refresh table includes a first sub-table and a second sub-table; the priority of the address information in the first sub-table is higher than the priority of the address information in the second sub-table.

[0022] In some embodiments, the control method includes: in response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, inserting the address information of the storage row adjacent to the first storage row into the second sub-table, and the address information of the storage row adjacent to the first storage row has the highest priority in the second sub-table.

[0023] In some embodiments, the storage rows adjacent to the first storage row include a second storage row and a third storage row, and the control method includes: in response to the absence of address information identical to the second address information corresponding to the second storage row and the third address information identical to the third storage row in the refresh table, inserting the second address information and the third address information into the second sub-table; wherein the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority; or, the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority.

[0024] In some embodiments, the control method includes: in response to address information of a storage row adjacent to the first storage row existing in the first sub-table, adjusting the priority of address information of a storage row adjacent to the first storage row to the highest priority in the first sub-table.

[0025] In some embodiments, the control method includes: in response to address information of a storage row adjacent to the first storage row existing in the second sub-table, adjusting address information of a storage row adjacent to the first storage row to the first sub-table.

[0026] In some embodiments, the priority of the address information of the storage row adjacent to the first storage row in the first sub-table is the lowest priority.

[0027] In some embodiments, the control method further includes: when the amount of address information stored in the second sub-table is greater than a set threshold, deleting at least one address information in the second sub-table.

[0028] In some embodiments, the control method includes: deleting the address information in the second sub-table in order of priority; wherein, the address information with a lower priority is deleted first.

[0029] In some embodiments, the control method includes: in response to deleting the refreshed highest priority address information from the refresh table, raising the priority levels of the remaining address information in the refresh table by one level, and inserting the fourth address information corresponding to the fourth storage row into the refresh table, wherein the priority level of the fourth address information in the refresh table is the lowest priority level.

[0030] In some embodiments, the priority of each of the plurality of address information is determined according to the probability that the storage row corresponding to the address information is attacked by a row hammer.

[0031] In a memory device provided by an embodiment of the present disclosure, a peripheral circuit is configured to judge, in response to a read command, whether there is address information in a refresh table that is identical to first address information of a first storage row corresponding to the read command, wherein a plurality of address information are stored in the refresh table, and each address information corresponds to one storage row in the plurality of storage rows; whether data stored in a storage unit on the first storage row is erroneous can be judged by a read operation, and in response to the presence of address information identical to the first address information in the refresh table, the address information identical to the first address information is deleted from the refresh table, thereby avoiding repeated refreshing of the first storage row whose data is known to be erroneous, thereby improving the operating efficiency of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of a system including a memory system according to an embodiment of the present disclosure;

[0033] Figure 2 is a schematic diagram of a system including a memory device according to an embodiment of the present disclosure;

[0034] Figure 3 is a schematic diagram of a storage array and peripheral circuits according to an embodiment of the present disclosure;

[0035] Figure 4 is a schematic diagram of a memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0036] Figures 5 to 10 is a schematic diagram of an operation on a refresh table according to an embodiment of the present disclosure;

[0037] Fig.11 It is a flowchart of a control method of a memory device according to an embodiment of the present disclosure.

[0038] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0039] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0041] In the drawings, like reference numerals refer to like elements throughout.

[0042] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] It should be understood that "some embodiments" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0045] The methods disclosed in the several method embodiments provided in the embodiments of the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The memory device in the embodiments of the present disclosure can be a DRAM, or at least a part of the device in the DRAM, and can be applicable to a double data rate synchronous dynamic random access memory using DDR4 memory specifications, DDR5 memory specifications, and a low power double data rate synchronous dynamic random access memory using LPDDR5 memory specifications. It should be noted that the embodiments of the present disclosure are not limited to DRAM, but in the subsequent introduction, for the sake of clarity, only DRAM is used as an example for explanation.

[0046] Reference Figure 1 As shown, the embodiment of the present disclosure provides a system 100 including a host 108. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0047] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104 to perform reading, writing or refreshing. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. The memory device 104 includes a DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure. The memory system 102 can be used as a memory of the host 108 in the system 100 or a cache of the system 100. In some specific examples, the memory system 102 can be used as an auxiliary in a solid-state drive, which can bring improvements in reading and writing to the solid-state drive. At present, high-end solid-state drive products mostly choose to embed DRAM to improve the performance of the product and improve the random read and write speed. For example, when writing files, especially small files, the small files are processed by DRAM and then stored in the flash memory (Flash), so that the solid-state drive storage efficiency is higher and the speed is faster. Flash includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory.

[0048] In some other embodiments, referring to Figure 2 As shown, the system 100 may only include a host 108 and a memory device 104 coupled thereto, and a controller for controlling the memory device 104 may be located inside the host 108, such as a memory controller integrated in a central processing unit (CPU), or a south bridge or north bridge chip integrated in a motherboard of the system 100. The memory device 104 may include, but is not limited to: a double data rate synchronous dynamic random access memory of a DDR4 memory specification, a DDR5 memory specification, and a low power double data rate synchronous dynamic random access memory of a LPDDR5 memory specification.

[0049] In some embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are directly coupled or indirectly coupled to each other.

[0050] Figure 3 3 is a schematic diagram showing a storage array 301 and a peripheral circuit 302 according to an exemplary embodiment of the present disclosure. Figure 3 As shown, in a DRAM, a memory array 301 may be arranged in rows and columns, so that a memory cell 305 may be addressed by specifying its row and column of the array, and a peripheral circuit 302 is coupled to and controls the reading, writing or refreshing of the memory array 301. The memory array 301 includes a plurality of word lines, such as Figure 3 The memory array 301 also includes a plurality of bit lines, such as WLn, WLn+1, WLn-1 and WLn-2 shown in FIG. Figure 3 As shown in BLn, BLn+1, BLn-1 and BLn-2, ​​the word line and the bit line intersect, and the memory cell 305 at the intersection of the selected word line and the selected bit line is selected to perform a read, write or refresh operation. A plurality of memory cells 305 coupled on a word line constitute a memory row. Figure 3 A memory cell 305 shown in the figure may include a capacitor and a transistor, and a memory cell 305 may include a transistor and a capacitor. The gate of the transistor is coupled to the word line, a controlled terminal (source) of the transistor is coupled to an electrode (first electrode) of the capacitor, the other controlled terminal (drain) of the transistor is coupled to the bit line, and the other electrode (second electrode) of the capacitor may be grounded or applied with other voltages (such as vdd / 2). Figure 3 As shown, the storage array 301 is arranged in an array of x rows and y columns. The rows and columns may be vertical or non-vertical. The extension direction of the word line may be parallel to the x direction or have an angle with the x direction. The extension direction of the bit line may be parallel to the y direction or have an angle with the y direction. The orthographic projection of the word line on the xoy plane is perpendicular to the orthographic projection of the bit line on the xoy plane, or is not perpendicular but has a certain angle. The embodiments of the present disclosure do not limit this. When performing a read or write operation, the corresponding word line can be selected using a word line selection signal, and the corresponding bit line can be selected according to a column selection signal. The word line and the bit line are selected at the same time to locate the selected storage unit 305 for read and write operations. In some embodiments, Figure 3 The capacitor can be replaced with other storage structures, including but not limited to: phase change storage structure, resistive storage structure or magnetic storage structure.

[0051] In some embodiments, the capacitor represents logical 1 and 0 by the amount of charge stored therein, or the high and low voltage difference across the capacitor. The voltage signal on the word line is applied to the gate to control the conduction or shutdown of the transistor, so as to select and deselect the capacitor, and then read the data information stored in the capacitor through the bit line, or write the data into the capacitor through the bit line for storage. When reading the storage unit 305, the sense amplifier circuit (SA) in the peripheral circuit 302 is coupled to the bit line, and the sense amplifier circuit is used to capture the weak voltage fluctuation on the bit line, and the capacitor voltage of the storage unit 305 is restored locally according to the voltage fluctuation. The sense amplifier circuit may include a latch, which can latch the restored capacitor voltage value, so that the information stored in the storage unit 305 is transferred from the capacitor to the sense amplifier circuit. The sense amplifier circuit may include a differential sense amplifier circuit, which is coupled to two bit lines and works with a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference on a pair of bit lines.

[0052] The peripheral circuit 302 may also include control logic (such as Figure 4 The control logic 304 shown in the figure), row decoding circuit, column decoding circuit, voltage generator and other devices. The control logic 304 is used to exchange signals with the host 108, the memory controller or the memory controller 106. The control logic 304 is used to control the row decoding circuit (row decoder), column decoding circuit (column decoder), voltage generator and other devices in the peripheral circuit 302 to perform read, write or refresh operations on the storage cells 305 in the storage array 301. The row decoding circuit is coupled to the word line and is configured to perform row address decoding or row addressing, and apply the corresponding operation voltage to the word line that needs to be operated. The column decoding circuit is coupled to the bit line and is configured to perform column decoding address decoding or column addressing.

[0053] Exemplarily, when the memory device 104 receives an access request from the host 108 or the memory controller 106, it receives an address signal, and performs a read, write, or refresh operation on the storage unit 305 corresponding to the address signal. The address signal may include a row address signal and a column address signal. The peripheral circuit 302 performs an address decoding or addressing operation, and may input the row address signal into a row address buffer, decode it through a row decoding circuit, and output a row selection signal. The row selection signal indicates to activate the word line where the storage unit 305 that needs to perform the operation is located. The column address signal is input into a column address buffer, decoded through a column decoding circuit, and output a column selection signal. The column selection signal indicates to activate the bit line where the storage unit 305 that needs to perform the operation is located. The storage unit 305 at the intersection of the activated bit line and the activated word line, or the storage unit 305 that is coupled to both the activated bit line and the activated word line at the same time is the storage unit 305 that needs to perform the operation.

[0054] For DRAM, there is a security vulnerability of row-hammer attack, that is, when the number of accesses to the storage cells 305 on a certain storage row in the storage array 301 is large, for example, a storage row (for example, the first storage row 307) is read millions of times per second, the charge in the storage cells 305 on the accessed (or hammered) storage row will leak to the storage cells 305 of the adjacent storage row, causing the bits of the storage cells 305 on the adjacent storage row to flip, resulting in data errors. The storage row that is attacked and accessed by the row hammer attack is the attacked row, and its adjacent storage row is the victim row. As the storage density of the storage array 301 continues to increase, the spacing between adjacent storage rows is getting smaller and smaller, the spacing between word lines is getting smaller and smaller, the mutual interference between adjacent storage rows and the risk of charge leakage are getting higher and higher, and the risk of storage row data flipping caused by the row hammer attack is also getting higher and higher.

[0055] In some exemplary embodiments of the present disclosure, the capacitors storing data in DRAM may leak charge. Generally, the storage unit 305 is refreshed periodically to maintain the charge in the capacitor to prevent data loss. This refresh operation can globally refresh the storage array 301 and refresh all storage rows row by row until all storage rows are refreshed. Generally, the global refresh operation in this embodiment is performed after a read / write cycle. The storage array 301 is read or written during the read / write cycle. After the cycle ends, the refresh cycle is entered. After the refresh cycle ends, the read / write cycle is entered again. This cycle is repeated to reduce the risk of data loss due to leakage of the storage unit 305 and maintain the good stability of the memory device 104.

[0056] In some specific examples, the row hammer attack is random, and before the storage row bit flips, it is not known which storage row is attacked and which storage row has data errors, so the frequency of global refresh operations can be increased to prevent row hammer attacks, but high-risk storage rows and low-risk storage rows will be refreshed indiscriminately, and there will be repeated refreshes. Increasing the refresh frequency may occupy more than 30% to 40% of the system bandwidth, reducing the read and write bandwidth, and reducing the operating performance of the memory device 104. In some specific examples, the refresh operation on the storage cell 305 in a storage row can be to read the storage cell 305 to determine whether the information stored in the storage cell 305 is correct. If it is not correct, the storage cell 305 will be charged, and the charging process can be equivalent to a re-writing process to restore the data originally stored in the storage cell 305.

[0057] In view of this, the embodiments of the present disclosure provide a memory device 104 and an operation control method thereof to reduce the risk of storage row data errors caused by row hammer attacks.

[0058] According to some aspects of the embodiments of the present disclosure, referring to Figure 3 As shown, a memory device is provided, including: a memory array 301 and a peripheral circuit 302 coupled to the memory array 301, the memory array 301 includes multiple memory rows, each memory row includes multiple memory cells 305 coupled to a word line; the peripheral circuit 302 is configured to: in response to a read command, determine whether there is address information in a refresh table that is the same as the first address information of a first memory row 307 corresponding to the read command; the refresh table stores multiple address information, each address information corresponds to one memory row in the multiple memory rows; in response to the existence of address information in the refresh table that is the same as the first address information, delete the address information that is the same as the first address information from the refresh table.

[0059] In some embodiments, reference Figure 4 As shown, the peripheral circuit 302 includes: a control logic 304, and a comparison unit 306 coupled thereto; wherein the comparison unit 306 is configured to: in response to a read command ACT, obtain each address information in the refresh table, and compare the first address information with each address information one by one to generate a comparison result; send the comparison result to the control logic 304; the control logic 304 is configured to: determine whether there is address information identical to the first address information in the refresh table according to the comparison result; and in response to the existence of address information identical to the first address information in the refresh table, delete the first address information from the refresh table. The read command may be generated by the host 108 or the memory controller 106 and sent to the memory device 104, and the read command may include the first address information to be read; or the first address information is generated along with the read command and sent to the memory device 104 together with the read command, or the first address information is sent to the memory device 104 after the read command. In response to the read command, the control logic 304 can control devices such as the row decoding circuit and the column decoding circuit to perform a read operation on the first storage row 307; the control logic 304 can perform a refresh operation on the corresponding storage row according to the address information stored in the refresh table.

[0060] Reference Figure 3 As shown, the storage rows in the memory device 104 correspond to word lines, and one storage row may include storage cells 305 coupled to one word line. The first storage row 307 may be a storage row corresponding to any word line in the memory array 301, for example, a storage row corresponding to the word line WLn. The first address information may correspond to the address information of one, a plurality of, or all storage cells 305 in the first storage row 307.

[0061] In some embodiments, the refresh table can be applied to the global refresh of all storage rows of the storage array 301. Here, the refresh table can store the address information corresponding to all storage rows of the storage array 301 as a global refresh table. When used as a global refresh table, the peripheral circuit 302 responds to the refresh command, and the peripheral circuit 302 can access the refresh table, obtain the address information in the refresh table in sequence according to the preset refresh rules, and perform a refresh operation on the storage row. The peripheral circuit 302 can start from any address information in the refresh table and refresh the storage rows in sequence until all storage rows corresponding to the address information in the refresh table are refreshed. The refresh table in the embodiment of the present disclosure has a large amount of data when used as a global refresh table, and the global refresh table can be split into multiple sub-refresh tables.

[0062] Different from the global refresh table in some embodiments, the refresh table in some other embodiments of the present disclosure can be applied to refresh to prevent row hammer attacks, and the peripheral circuit 302 can be configured to access the refresh table in response to a read command or a write command, obtain the address information stored in the refresh table, and perform a refresh operation on the storage row. If the data in the refresh table is bit flipped, the peripheral circuit 302 can perform an error correction operation on it and rewrite the correct data. It can be understood that the row hammer attack is random, and the first storage row 307 can be an attacked row that suffers from a row hammer attack, and its adjacent storage row is a high-risk victim row with a great risk of bit flipping, or the first storage row 307 can be a victim row of bit flipping, and it is impossible to know whether the first storage row 307 is bit flipped before reading or refreshing the first storage row 307. When the first storage row 307 is read, if its data is bit-flipped, the peripheral circuit 302 can also perform an error correction operation to restore its data. If the refresh table still has the first address information at this time, the peripheral circuit 302 will refresh the first storage row 307 after reading the first storage row 307. The refresh operation at this time is redundant. When the first storage row 307 is read, its data is not bit-flipped, and its adjacent storage row is a high-risk victim row, which may cause bit flipping due to interference or charge leakage of the first storage row 307. The refresh table stores the address information of the adjacent storage row of the first storage row 307, or inserts the address information corresponding to the adjacent storage row of the first storage row 307 into the refresh table for the peripheral circuit 302 to retrieve and refresh, thereby reducing the risk of row hammer attacks.

[0063] In response to a read command, the embodiment of the present disclosure performs a read operation on the first storage row 307 corresponding to the first address information. Whether the storage data of the first storage row 307 is erroneous can be determined through the read operation. The address information identical to the first address information in the refresh table is deleted to avoid repeated refresh of the first storage row 307, thereby improving the operating efficiency of the memory device 104.

[0064] In some embodiments, multiple address information are sorted according to priority; the peripheral circuit 302 is also configured to: perform a refresh operation on the corresponding storage row according to the address information with the highest priority in the refresh table, and delete the refreshed address information with the highest priority from the refresh table.

[0065] In some embodiments, the priority of each of the multiple address information is determined according to the probability that the storage row corresponding to the address information is attacked by a row hammer. The greater the probability that the storage row is attacked by a row hammer, the higher the priority, and the earlier it is refreshed. It can be understood that after the highest priority address information in the refresh table of the embodiment of the present disclosure is refreshed and deleted, the address information at the remaining priorities will all be upgraded by one level, and the address information originally at the second highest priority will be updated to the highest priority and can be refreshed in the next operation; the refresh table also introduces new storage rows and stores them as the lowest priority.

[0066] A row hammer attack is a random event, and the attacked storage row is also random. The probability of a storage row being attacked by a row hammer attack can be recorded based on the history of row hammer attacks on some memory devices 104, and the greater the number of historical attacks, the greater the probability; or the probability of a storage row being attacked by a hammer attack can be determined based on the number of times the storage row is read, and the greater the number of times it is read, the greater the probability; or a probability algorithm can be combined to assign each storage row a probability of being attacked by a row hammer, and only a certain amount of address information with a high probability of row hammer attacks is stored in the refresh table, and the address information of all storage rows is not stored, so as to reduce the data volume of the refresh table; and when a certain address information in the refresh table is deleted and the address information of other storage rows needs to be inserted, the inserted address information is also determined according to the probability algorithm to insert the address information with a higher risk, and the address information with a higher risk here is determined in real time by the built-in probability algorithm, and the address information stored in the refresh table changes in real time with the refresh operation, and has higher security than the refresh table with fixed address information.

[0067] In some embodiments, the peripheral circuit 302 is further configured to: determine whether there is address information of a storage row adjacent to the first storage row 307 in the refresh table; in response to the absence of address information of a storage row adjacent to the first storage row 307 in the refresh table, insert the address information of the storage row adjacent to the first storage row 307 into the refresh table; in response to the presence of address information of the storage row adjacent to the first storage row 307 in the refresh table, adjust the priority of the address information of the storage row adjacent to the first storage row 307 in the refresh table.

[0068] Based on the bit flip model caused by the row hammer attack, when the first storage row 307 is read, its adjacent storage row has a higher bit flip risk. The peripheral circuit 302 needs to determine whether there is address information of the storage row adjacent to the first storage row 307 in the existing refresh table. If not, the address information of the storage row adjacent to the first storage row 307 is inserted into the refresh table to avoid high-risk storage rows from being missed for refresh. The inserted address information may be located at a non-highest priority in the refresh table. The address information with the highest priority in the refresh table before insertion has the highest risk. If the address information of the storage row adjacent to the first storage row 307 is recorded in the refresh table, it means that the default risk level of the address information is very high. At present, there is a risk of being interfered by the first storage row 307. At this time, the priority of the address information in the refresh table needs to be increased.

[0069] Specifically, refer to Figure 4 As shown, the comparison unit 306 responds to the read command ACT, accesses the refresh table and compares the first address information with the address information stored in the refresh table one by one, and sends the comparison result and the address to be compared to the control logic 304. The control logic 304 determines whether the first address information exists in the refresh table according to the comparison result, and deletes the first address information if it exists; the control logic 304 determines whether the address information of the adjacent storage row of the first storage row 307 does not exist in the refresh table according to the comparison result, and inserts the address information of the adjacent storage row of the first storage row 307 into the refresh table; the control logic 304 determines whether the address information of the adjacent storage row of the first storage row 307 does not exist in the refresh table according to the comparison result, and adjusts the priority of the address information of the adjacent storage row of the first storage row 307 in the refresh table; the control logic 304 accesses the refresh table to obtain the address information with the highest priority in the refresh table, sends the refresh command and the address information with the highest priority to the storage array 301, controls the storage array 301 to refresh the storage row corresponding to the address information with the highest priority, and deletes the refreshed address information with the highest priority in the refresh table.

[0070] In some embodiments, storage rows adjacent to the first storage row 307 include a second storage row and / or a third storage row; the peripheral circuit 302 is also configured to: determine whether there is address information in the refresh table that is identical to the second address information corresponding to the second storage row; and / or determine whether there is address information in the refresh table that is identical to the third address information corresponding to the third storage row; in response to the second address information not existing in the refresh table, insert the second address information into the refresh table; and / or, in response to the third address information not existing in the refresh table, insert the third address information into the refresh table; in response to the second address information and / or the third address information existing in the refresh table, adjust the priority of the second address information and / or the third address information in the refresh table.

[0071] Combination Figure 3As shown, when the first storage row 307 is the storage row at the edge of the storage array 301, for example, it can be the storage row corresponding to the first word line WL0 or the last word line WLn+n, there is only one storage row adjacent to the first storage row 307, which can be recorded as the second storage row or the third storage row, corresponding to the second address information and the third address information respectively. Taking the second storage row as an example, when the refresh table does not have the second address information, the second address information is inserted into the refresh table, and when the refresh table has the second address information, the priority of the second address information in the refresh table is adjusted.

[0072] When the first storage row 307 is a storage row between the most edge storage rows in the storage array 301, for example, the first storage row 307 may be a storage row corresponding to the word line WLn, and the storage rows adjacent to the first storage row 307 include two storage rows, namely the second storage row and the third storage row. When the second address information and the third address information are not in the refresh table, both address information are inserted into the refresh table. When one of the second address information and the third address information is in the refresh table and the other address information is not in the refresh table, such as the second address information is in the refresh table and the third address information is not in the refresh table, the second address information is inserted into the refresh table and the priority of the third address information in the refresh table is adjusted. When the second address information and the third address information are all in the refresh table, the priorities of the second address information and the third address information in the refresh table are adjusted, and the relative priorities of the two address information may remain unchanged before and after the adjustment, or may be swapped; for example, before adjusting the refresh table, the priority of the second address information is higher than that of the third address information, and the priority of the second address information may be adjusted to be higher than that of the third address information, or the priority of the third address information may be adjusted to be higher than that of the second address information.

[0073] In some embodiments, after one or two address information are inserted into the refresh table, the address information of the number of inserted address information needs to be deleted to keep the number of address information stored in the refresh table in real time unchanged, that is, to keep the queue depth corresponding to the refresh table unchanged. The refresh table can be refreshed through operations such as address information insertion, deletion, or priority adjustment. In one refresh operation, only the address information with the highest priority in the refresh table is refreshed.

[0074] In some embodiments, reference Figure 5 As shown, the refresh table includes a first sub-table and a second sub-table; the priority of the address information in the first sub-table is higher than the priority of the address information in the second sub-table. The first sub-table can be recorded as a hot table, including address information with a higher risk or probability of a row hammer attack; the second sub-table can be recorded as a cold table, including address information with a lower risk or probability of a row hammer attack; the address information with the highest priority in the first sub-table is refreshed.

[0075] The address information with the highest priority in the first sub-table is the address information currently being refreshed. After being refreshed, the address information with the highest priority will be deleted from the refresh table. The address information with other priorities will be upgraded one level at a time, and a new address information will be added to the lowest priority of the refresh table, keeping the number of address information stored in the refresh table unchanged. Figure 5 For example, the refresh table has 7 entries (7 grids), the first sub-table includes 3 entries, storing 3 address information; the second sub-table includes 4 entries, storing 4 address information; the priority of the refresh table decreases with the arrows, the address information in the highest priority entry is refreshed, the number of entries (or queue depth) of the refresh table remains unchanged, but the address information corresponding to each entry is constantly changing with the insertion and refresh of address information, the address information on the highest priority entry may be temporarily vacant after being deleted due to refresh, but it will be immediately filled in due to the adjustment and update of the priority for the next refresh. In a refresh operation, only the address information with the highest priority in the refresh table is refreshed.

[0076] In some embodiments, the peripheral circuit 302 is further configured to: in response to the absence of address information of a storage row adjacent to the first storage row 307 in the refresh table, insert the address information of the storage row adjacent to the first storage row 307 into the second sub-table, and the address information of the storage row adjacent to the first storage row 307 has the highest priority in the second sub-table.

[0077] In some embodiments, when the first storage row 307 has only one adjacent storage row, there is only one address information adjacent to the first address information, such as the second address information. When the second address information does not exist in both the first subtable and the second subtable, the second address information is inserted into the second subtable and is at the highest priority. The address information with the lowest priority of the second subtable can be deleted, or not deleted. In some embodiments, when the second address information is stored in the first subtable, the priority of the second address information of the first subtable is raised to the highest priority. If the second address information is originally at the highest priority of the first subtable, no adjustment is required. The second address information with the highest priority will be refreshed, and the refreshed second address information will be deleted from the first subtable. In some embodiments, when the second address information is stored in the second subtable, the second address information is moved to the first subtable and is at the lowest priority of the first subtable. Subsequent embodiments will explain examples of the operations of refreshing the table to insert address information, delete address information, and adjust priority when the first address information has adjacent second address information and third address information.

[0078] In some embodiments, the storage rows adjacent to the first storage row 307 include a second storage row and a third storage row, and the peripheral circuit 302 is further configured as follows:

[0079] In response to the non - existence of address information identical to the second address information corresponding to the second storage row and address information identical to the third address information corresponding to the third storage row in the refresh table, insert the second address information and the third address information into the second sub - table; wherein, the priority of the second address information in the second sub - table is the highest priority, and the priority of the third address information in the second sub - table is the second - highest priority; or, the priority of the second address information in the second sub - table is the highest priority, and the priority of the third address information in the second sub - table is the second - highest priority.

[0080] In some embodiments, when there are two adjacent storage rows in the first storage row 307, the peripheral circuit 302 is further configured to: in response to the non - existence of the second address information or the third address information in the refresh table, insert the second address information or the third address information into the second sub - table, and make the priority of the second address information or the third address information in the second sub - table the highest priority; in response to the non - existence of the second address information and the third address information in the refresh table, insert the second address information and the third address information into the second sub - table; wherein, make the priority of the second address information in the second sub - table the highest priority and the priority of the third address information in the second sub - table the second - highest priority, or make the priority of the second address information in the second sub - table the highest priority and the priority of the third address information in the second sub - table the second - highest priority.

[0081] Refer to Figure 5 As shown, before responding to the read command, the address information corresponding to multiple storage rows stored in the refresh table is 0x0005, 0x0010, 0x0057, 0x0013, 0x00ad, 0x00fa, 0x0049, and the priorities decrease in turn. For the read command ACT 0x0010 corresponding to the first address information 0x0010, the address information of the adjacent storage rows of the first address information 0x0010 includes the second address information 0x0011 and the third address information 0x0012. Neither of the two address information is in the first sub - table nor in the second sub - table. Insert 0x0011 into the second sub - table and make it at the highest priority of the second sub - table, insert 0x0012 into the second sub - table and make it at the second - highest priority of the second sub - table; or insert 0x0012 into the second sub - table and make it at the highest priority of the second sub - table, insert 0x0011 into the second sub - table and make it at the second - highest priority of the second sub - table. After inserting the two address information into the second sub - table, the second sub - table will increase two address information. It is possible to delete the two address information with the lowest priority and the second - lowest priority in the second sub - table, or not to delete. Figure 5After 0x0011 and 0x0012 are inserted into the second subtable, 0x00fa and 0x0049 are deleted. The highest priority address information 0x0005 in the first subtable is refreshed and deleted from the first subtable. The highest priority entry in the first subtable is temporarily vacant. Subsequently, 0x0010, 0x0057, 0x0011, 0x0012, 0x0013, and 0x00ad are increased in priority one by one. 0x0010 will become the new highest priority, and the fourth address information corresponding to the fourth storage row is inserted into the lowest priority of the second subtable. The fourth address information can be obtained according to the probability algorithm, and the fourth address information can include 0x00nn. It should be pointed out that Figure 5 Before inserting 0x0011 and 0x0012, the first address information 0x0010 exists in the refresh table (the first sub-table), and the first address information 0x0010 is not deleted from the refresh table even if it is read.

[0082] Reference Figure 6 As shown, in response to reading the first address information 0x0010, the first address information 0x0010 exists in the refresh table, and the first address information 0x0010 is deleted from the refresh table, similarly Figure 5 After the second address information 0x0011 and the third address information 0x0012 are inserted into the second sub-table, since the first address information 0x0010 is previously deleted, only one address information of the second sub-table needs to be deleted, such as deleting the lowest priority 0x0049 of the second sub-table. Figure 5 The illustrated embodiment retains one more high-risk address information 0x00fa, further reducing the probability of a row hammer attack.

[0083] It should be noted that in some other embodiments, for the refresh table without the second address information and the third address information inserted, the address information of 0x0005, 0x0010, 0x0057, 0x0013, 0x00ad, 0x00fa, and 0x0049 may be refreshed in sequence according to the priority.

[0084] In some embodiments, the peripheral circuit 302 is further configured to: in response to the address information of the storage row adjacent to the first storage row 307 existing in the first sub-table, adjust the priority of the address information of the storage row adjacent to the first storage row 307 to the highest priority in the first sub-table.

[0085] In some embodiments, the peripheral circuit 302 is further configured to: in response to the address information of the storage row adjacent to the first storage row 307 existing in the second sub-table, adjust the address information of the storage row adjacent to the first storage row 307 to the first sub-table. In some embodiments, the priority of the address information of the storage row adjacent to the first storage row 307 in the first sub-table is the lowest priority.

[0086] When the first storage row 307 has only one adjacent storage row, there is only one address information adjacent to the first address information, such as the second address information. In some examples, when the second address information exists in the first sub-table, the priority of the second address information in the first sub-table is adjusted to the highest priority. In other examples, when the second address information exists in the second sub-table, the second address information is moved to the first sub-table, and the priority of the second address information in the first sub-table can be adjusted to the lowest priority or the second lowest priority.

[0087] In some embodiments, the peripheral circuit 302 is also configured to: in response to the second address information or the third address information being present in the first sub-table, adjust the priority of the second address information or the third address information to the highest priority in the first sub-table; or, in response to the second address information and the third address information being present in the first sub-table, adjust the priority of the second address information and the third address information to the highest priority and the second highest priority in the first sub-table.

[0088] In some embodiments, the peripheral circuit 302 is further configured to: in response to the second address information and / or the third address information being present in the second sub-table, move the second address information and / or the third address information to the first sub-table.

[0089] In some embodiments, the peripheral circuit 302 is also configured to: in response to the second address information or the third address information existing in the second sub-table, move the second address information or the third address information to the first sub-table, so that the priority of the second address information or the third address information in the first sub-table is the lowest priority; or, in response to the second address information and the third address information existing in the second sub-table, move the second address information and the third address information to the first sub-table, wherein the priority of the second address information in the first sub-table is the lowest priority and the priority of the third address information in the first sub-table is the second lowest priority, or, the priority of the second address information in the first sub-table is the second lowest priority and the priority of the third address information in the first sub-table is the lowest priority.

[0090] Reference Figure 7As shown, before responding to the read command, the address information stored in the refresh table is 0x0005, 0x0010, 0x0057, 0x0013, 0x00ad, 0x00fa, and 0x0049; among which, 0x0005, 0x0010, and 0x0057 belong to the first sub-table, and 0x0013, 0x00ad, 0x00fa, and 0x0049 belong to the second sub-table. In response to the read command ACT0x0011 of the first address information 0x0011, the two adjacent address information 0x0010 and 0x0012 are originally required to be inserted into the second sub-table and at the highest priority and the second highest priority, but 0x0010 is stored in the first sub-table, and only the priority of 0x0010 is adjusted to the highest priority of the first sub-table, 0x0012 is not recorded in the first sub-table and the second sub-table, 0x0012 is inserted into the second sub-table and at the highest priority, and the address information 0x0049 with the lowest priority of the second sub-table is deleted. 0x0010 will be refreshed and deleted from the first sub-table after the refresh.

[0091] Reference Figure 8 As shown, before responding to the read command, the address information stored in the refresh table is 0x0010, 0x0005, 0x0057, 0x0012, 0x0013, 0x00ad, 0x00fa; among them, 0x0010, 0x0005, 0x0057 belong to the first sub-table, and 0x0012, 0x0013, 0x00ad, 0x00fa belong to the second sub-table. In response to the read command ACT0x0013 of the first address information 0x0013, it is originally necessary to insert the two adjacent address information 0x0012 and 0x0014 into the second sub-table, and they are at the highest priority and the second highest priority, but 0x0012 is stored in the second sub-table, 0x0012 is moved to the first sub-table and is at the lowest priority, 0x0014 is not recorded in the first sub-table and the second sub-table, 0x0014 is inserted into the second sub-table and is at the highest priority. After the adjustment operation, the highest priority address information of the first sub-table is still 0x0010, and 0x0010 will be refreshed and deleted from the first sub-table after refreshing. An address information 0x00ad of the second sub-table is deleted, and 0x00ad is not the lowest priority of the second sub-table. The first address information 0x0013 is stored in the second sub-table and is not deleted from the refresh table after being read.

[0092] Reference Fig. 9As shown, before responding to the read command, the address information stored in the refresh table is 0x0010, 0x0005, 0x0057, 0x0012, 0x0013, 0x00ad, and 0x00fa; among them, 0x0010, 0x0005, and 0x0057 belong to the first sub-table, and 0x0012, 0x0013, 0x00ad, and 0x00fa belong to the second sub-table. In response to the read command ACT0x0013 of the first address information 0x0013, 0x0012 in the second sub-table is moved to the first sub-table and is at the lowest priority, 0x0014 is inserted into the second sub-table and is at the highest priority, and 0x0013 in the second sub-table is deleted. After the adjustment operation, the highest priority address information of the first sub-table is still 0x0010, and 0x0010 will be refreshed and deleted from the first sub-table after the refresh. Compared to Figure 8 , Fig. 9 Because the first address information 0x0013 is deleted, while keeping the number of address information in the refresh table unchanged, one less address information can be deleted in the second subtable, that is, one more risky address information is retained, reducing the risk of row hammer attack, for example Fig. 9 0x00ad is reserved.

[0093] In some embodiments, the operation sequence of DRAM can be divided into a read / write cycle and a refresh cycle. In a read / write cycle, the memory device 104 can receive multiple read commands, and the peripheral circuit 302 responds to each read command and updates the refresh table in real time by inserting address information, adjusting priority, or deleting address information according to the read address information, but is not limited to performing a refresh operation in response to each read command. For example Fig.10As shown, two read commands ACT 0x0011 and ACT 0x0013 are executed successively: before responding to the first read command, the address information stored in the refresh table is 0x0005, 0x0010, 0x0057, 0x0013, 0x00ad, 0x00fa, 0x0049; among them, 0x0005, 0x0010, 0x0057 belong to the first sub-table, and 0x0013, 0x00ad, 0x00fa, 0x0049 belong to the second sub-table. In response to the read command ACT0x0011, 0x0010 is stored in the first sub-table, the priority of 0x0010 is moved to the first sub-table and is at the highest priority, 0x0012 is not recorded in the first sub-table and the second sub-table, 0x0012 is inserted into the second sub-table and is at the highest priority, the address information 0x0049 of the lowest priority of the second sub-table is deleted, and the highest priority 0x0010 is not refreshed. In response to the read command ACT 0x0013, 0x0012 is stored in the second sub-table, 0x0012 is moved to the first sub-table and is at the lowest priority, 0x0014 is not recorded in the first sub-table and the second sub-table, 0x0014 is inserted into the second sub-table and is at the highest priority, the read 0x0013 is recorded in the second sub-table and deleted from the second sub-table, and the highest priority 0x0010 is refreshed and deleted from the first sub-table.

[0094] In some embodiments, reference Fig.10 As shown, the refresh table can be used for additional refresh operations in addition to the global refresh operation (or automatic refresh operation) in the memory device 104. The highest priority 0x0010 in the refresh table can be refreshed once on the basis of the global refresh operation. The additional refresh operation can be performed in the refresh cycle, and 0x0010 may be refreshed twice in the refresh cycle. When the refresh cycle is after the timing of the read command ACT 0x0013, the peripheral circuit 302 performs a refresh operation according to the current latest refresh table in the refresh cycle, and refreshes the storage row corresponding to the highest priority 0x0010; and the read command ACT 0x0011 in the read / write cycle timing will trigger the update of the refresh table, but will not perform a refresh operation, that is, the storage row corresponding to the highest priority 0x0010 will not be refreshed at present.

[0095] In some embodiments, the peripheral circuit 302 is further configured to: when the number of address information stored in the second sub-table is greater than a set threshold, delete at least one address information in the second sub-table. For the second sub-table, one address information adjacent to the first storage row 307 may be inserted, or two address information adjacent to the first storage row 307 may be inserted. When the number of address information stored in the second sub-table is greater than the set storage number, the address information with a lower priority in the second sub-table may be deleted, and the lower the priority, the first to be deleted.

[0096] In some embodiments, the peripheral circuit 302 is further configured to: in response to the second address information and / or the third address information being inserted into the second sub-table so that the amount of address information stored in the second sub-table is greater than a set threshold, delete at least one address information in the second sub-table.

[0097] In some embodiments, the peripheral circuit 302 is configured to: delete the address information in the second sub-table in order of priority; wherein, the address information with a lower priority is deleted first.

[0098] The address information stored in the refresh table of the disclosed embodiment is a certain value, and the address information stored in the first sub-table and the second sub-table is a certain value. In response to the read command corresponding to different address information, the address information content and priority of the refresh table will be updated in real time, but the number of address information in the refresh table remains unchanged to keep the data volume of the refresh table small. Figure 5 As shown, the second address information 0x0011 and the third address information 0x0012 are inserted into the second sub-table, the number of address information in the second sub-table increases by two relative to the set threshold value 4, and the lowest priority 0x0049 and the second lowest priority 0x00fa in the second sub-table are deleted to maintain the set threshold value 4 of the second sub-table. Figure 7 As shown, an address information 0x0012 is inserted into the second sub-table, and 0x0049 with the lowest priority is deleted.

[0099] When deleting address information from the second subtable, the address information with the lowest priority can be deleted in order of priority, or it can be deleted randomly, but the newly inserted address information will not be deleted. Figure 8 As shown, an address information 0x0014 is inserted into the second sub-table, and the non-lowest priority 0x00ad is deleted. Thus, the security of the refresh table update algorithm can be increased, the performance of the memory device 104 in dealing with row hammer attacks can be improved, and the security performance of the memory device 104 can be improved.

[0100] In some embodiments, the peripheral circuit 302 is further configured to: in response to deleting the highest priority address information after refresh from the refresh table, increase the priority levels of the remaining address information in the refresh table by one level, and insert the fourth address information corresponding to the fourth storage row into the refresh table, wherein the priority level of the fourth address information in the refresh table is the lowest priority level.

[0101] Reference Figure 5As shown, the highest priority 0x0005 is deleted from the refresh table after being refreshed, and the highest priority entry in the refresh table will be temporarily vacant. Subsequently, 0x0010, 0x0057, 0x0011, 0x0012, 0x0013, and 0x00ad will be increased in priority one by one, and 0x0010 will become the new highest priority. The fourth address information corresponding to the fourth storage row is inserted into the lowest priority of the second sub-table. The fourth address information can be obtained according to a probability algorithm, and the fourth address information can include 0x00nn.

[0102] In some other embodiments, after 0x0005 is refreshed and deleted, the remaining 0x0010 and 0x0057 in the first sub-table can be increased in priority one by one, 0x0010 is at the highest priority, the lowest priority is vacant, and the fourth address information is inserted into the first sub-table and is at the lowest priority.

[0103] According to some aspects of the embodiments of the present disclosure, Figure 1 A memory system is provided, including a memory device 104 and a memory controller 106, wherein the memory controller 106 is coupled to the memory and controls the memory device 104. The memory device 104 may include a DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure. The memory device 104 may include, but is not limited to: a double data rate synchronous dynamic random access memory of a DDR4 memory specification, a DDR5 memory specification, and a low power double data rate synchronous dynamic random access memory of a LPDDR5 memory specification.

[0104] In some embodiments, reference Figure 2 As shown, the controller for controlling the memory device 104 may be located inside the host 108 , such as a memory controller integrated into a central processing unit (CPU), or a south bridge or north bridge chip integrated into a motherboard of the system 100 .

[0105] According to some aspects of the embodiments of the present disclosure, Fig.11 A control method for a memory device is provided, comprising: in response to a read command, determining whether there is address information in a refresh table that is identical to first address information of a first storage row corresponding to the read command; wherein the refresh table stores a plurality of address information, each of which corresponds to one of the plurality of storage rows; each of the storage rows comprises a plurality of storage cells coupled to a word line; and in response to the presence of address information in the refresh table that is identical to the first address information, deleting the address information that is identical to the first address information from the refresh table.

[0106] In some embodiments, the multiple address information are sorted according to priority, and the control method further includes: performing a refresh operation on the corresponding storage row according to the highest priority address information in the refresh table, and deleting the refreshed highest priority address information from the refresh table.

[0107] In some embodiments, the control method includes: determining whether there is address information of a storage row adjacent to the first storage row 307 in the refresh table; in response to the absence of address information of an adjacent storage row of the first storage row 307 in the refresh table, inserting the address information of an adjacent storage row of the first storage row 307 into the refresh table; in response to the presence of address information of an adjacent storage row of the first storage row 307 in the refresh table, adjusting the priority of the address information of an adjacent storage row of the first storage row 307 in the refresh table.

[0108] In some embodiments, the control method includes: determining whether there is address information in the refresh table that is identical to the second address information corresponding to the second storage row; and / or determining whether there is address information in the refresh table that is identical to the third address information corresponding to the third storage row; wherein the storage rows adjacent to the first storage row 307 include the second storage row and / or the third storage row; in response to the second address information not existing in the refresh table, inserting the second address information into the refresh table; and / or, in response to the third address information not existing in the refresh table, inserting the third address information into the refresh table; in response to the second address information and / or the third address information existing in the refresh table, adjusting the priority of the second address information and / or the third address information in the refresh table.

[0109] In some embodiments, the refresh table includes a first sub-table and a second sub-table; the priority of the address information in the first sub-table is higher than the priority of the address information in the second sub-table.

[0110] In some embodiments, the control method includes: in response to the absence of address information of a storage row adjacent to the first storage row 307 in the refresh table, inserting the address information of the storage row adjacent to the first storage row 307 into the second sub-table, and the address information of the storage row adjacent to the first storage row 307 has the highest priority in the second sub-table.

[0111] In some embodiments, the storage rows adjacent to the first storage row 307 include a second storage row and a third storage row, and the control method includes: in response to the absence of address information identical to the second address information corresponding to the second storage row and address information identical to the third address information corresponding to the third storage row in the refresh table, inserting the second address information and the third address information into the second sub-table; wherein the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority; or, the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority.

[0112] In some embodiments, the control method includes: in response to the address information of the storage row adjacent to the first storage row 307 existing in the first sub-table, adjusting the priority of the address information of the storage row adjacent to the first storage row 307 to the highest priority in the first sub-table.

[0113] In some embodiments, the control method includes: in response to address information of a storage row adjacent to the first storage row 307 existing in the second sub-table, adjusting address information of a storage row adjacent to the first storage row 307 to the first sub-table.

[0114] In some embodiments, the priority of the address information of the storage row adjacent to the first storage row 307 in the first sub-table is the lowest priority.

[0115] In some embodiments, the control method includes: in response to the absence of the second address information or the third address information in the refresh table, inserting the second address information or the third address information into the second sub-table, so that the priority of the second address information or the third address information in the second sub-table is the highest priority; in response to the absence of the second address information and the third address information in the refresh table, inserting the second address information and the third address information into the second sub-table; wherein, the priority of the second address information in the second sub-table is the highest priority and the priority of the third address information in the second sub-table is the second highest priority, or the priority of the second address information in the second sub-table is the highest priority and the priority of the third address information in the second sub-table is the second highest priority.

[0116] In some embodiments, the control method includes: in response to the second address information or the third address information existing in the first sub-table, adjusting the priority of the second address information or the third address information to the highest priority in the first sub-table; or, in response to the second address information and the third address information existing in the first sub-table, adjusting the priority of the second address information and the third address information to the highest priority and the second highest priority in the first sub-table.

[0117] In some embodiments, the control method includes: in response to the second address information and / or the third address information being present in the second sub-table, moving the second address information and / or the third address information to the first sub-table.

[0118] In some embodiments, the control method includes: in response to the second address information or the third address information existing in the second sub-table, moving the second address information or the third address information to the first sub-table, so that the priority of the second address information or the third address information in the first sub-table is the lowest priority; or, in response to the second address information and the third address information existing in the second sub-table, moving the second address information and the third address information to the first sub-table, wherein the priority of the second address information in the first sub-table is the lowest priority and the priority of the third address information in the first sub-table is the second lowest priority, or, the priority of the second address information in the first sub-table is the second lowest priority and the priority of the third address information in the first sub-table is the lowest priority.

[0119] In some embodiments, the control method further includes: when the amount of address information stored in the second sub-table is greater than a set threshold, deleting at least one address information in the second sub-table.

[0120] In some embodiments, the control method further includes: in response to the second address information and / or the third address information being inserted into the second sub-table so that the amount of address information stored in the second sub-table is greater than a set threshold, deleting at least one address information in the second sub-table.

[0121] In some embodiments, the control method includes: deleting the address information in the second sub-table in order of priority; wherein, the address information with a lower priority is deleted first.

[0122] In some embodiments, the control method includes: in response to deleting the refreshed highest priority address information from the refresh table, raising the priority levels of the remaining address information in the refresh table by one level, and inserting the fourth address information corresponding to the fourth storage row into the refresh table, wherein the priority level of the fourth address information in the refresh table is the lowest priority level.

[0123] In some embodiments, the priority of each of the plurality of address information is determined according to the probability that the storage row corresponding to the address information is attacked by a row hammer.

[0124] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory device, It is characterized in that include: A memory array and a peripheral circuit coupled to the memory array, the memory array comprising a plurality of memory rows, each of the memory rows comprising a plurality of memory cells coupled to a word line; The peripheral circuit is configured as: In response to a read command, determining whether there is address information in a refresh table that is the same as first address information of a first storage row corresponding to the read command; the refresh table stores a plurality of address information, each of which corresponds to one of the plurality of storage rows; In response to the presence of address information identical to the first address information in the refresh table, the address information identical to the first address information is deleted from the refresh table.

2. The memory device according to claim 1, It is characterized in that The plurality of address information are sorted according to priority; the peripheral circuit is further configured as follows: A refresh operation is performed on the corresponding storage row according to the address information with the highest priority in the refresh table, and the refreshed address information with the highest priority is deleted from the refresh table.

3. The memory device according to claim 1, It is characterized in that The peripheral circuit is further configured as: Determine whether there is address information of a storage row adjacent to the first storage row in the refresh table; In response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, inserting address information of a storage row adjacent to the first storage row into the refresh table; In response to the presence of address information of a storage row adjacent to the first storage row in the refresh table, the priority of the address information of the storage row adjacent to the first storage row in the refresh table is adjusted.

4. The memory device according to claim 3, It is characterized in that The refresh table includes a first sub-table and a second sub-table; the priority of the address information in the first sub-table is higher than the priority of the address information in the second sub-table.

5. The memory device according to claim 4, It is characterized in that The peripheral circuit is further configured as: In response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, the address information of the storage row adjacent to the first storage row is inserted into the second sub-table, and the address information of the storage row adjacent to the first storage row has the highest priority in the second sub-table.

6. The memory device according to claim 5, It is characterized in that The storage rows adjacent to the first storage row include a second storage row and a third storage row, and the peripheral circuit is further configured as follows: In response to the absence of address information identical to the second address information corresponding to the second storage row and address information identical to the third address information corresponding to the third storage row in the refresh table, the second address information and the third address information are inserted into the second sub-table; wherein the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority; or, the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority.

7. The memory device according to claim 4, It is characterized in that The peripheral circuit is further configured as: In response to address information of a storage row adjacent to the first storage row existing in the first sub-table, the priority of the address information of the storage row adjacent to the first storage row is adjusted to the highest priority in the first sub-table.

8. The memory device according to claim 4, It is characterized in that The peripheral circuit is further configured as: In response to address information of a storage row adjacent to the first storage row existing in the second sub-table, the address information of the storage row adjacent to the first storage row is adjusted to the first sub-table.

9. The memory device according to claim 8, It is characterized in that The priority of the address information of the storage row adjacent to the first storage row in the first sub-table is the lowest priority.

10. The memory device according to claim 5, It is characterized in that The peripheral circuit is further configured as: When the amount of address information stored in the second sub-table is greater than a set threshold, at least one address information in the second sub-table is deleted.

11. The memory device according to claim 10, It is characterized in that The peripheral circuit is configured to delete the address information in the second sub-table in order of priority; wherein the address information with a lower priority is deleted first.

12. The memory device according to claim 2, It is characterized in that The peripheral circuit is also configured to: in response to deleting the refreshed highest priority address information from the refresh table, increase the priority levels of the remaining address information in the refresh table by one level, and insert the fourth address information corresponding to the fourth storage row into the refresh table, wherein the priority level of the fourth address information in the refresh table is the lowest priority level.

13. The memory device according to claim 2, It is characterized in that The priority of each of the plurality of address information is determined according to the probability that the storage row corresponding to the address information is attacked by a row hammer.

14. The memory device according to claim 1, It is characterized in that The peripheral circuit comprises: control logic, and a comparison unit coupled thereto; wherein, The comparison unit is configured to: in response to the read command, obtain each address information in the refresh table, and compare the first address information with each address information one by one to generate a comparison result; and send the comparison result to the control logic; The control logic is configured to: determine whether there is address information identical to the first address information in the refresh table according to the comparison result; and in response to the existence of address information identical to the first address information in the refresh table, delete the first address information from the refresh table.

15. A memory system, It is characterized in that The invention comprises the memory device as claimed in claim 1, and a memory controller coupled to the memory and controlling the memory device.

16. A method for controlling a memory device, It is characterized in that include: In response to a read command, determining whether there is address information in a refresh table that is the same as first address information of a first storage row corresponding to the read command; wherein the refresh table stores a plurality of address information, each of which corresponds to one of the plurality of storage rows; and each of the storage rows includes a plurality of storage cells coupled to a word line; In response to the presence of address information identical to the first address information in the refresh table, the address information identical to the first address information is deleted from the refresh table.

17. The control method according to claim 16, It is characterized in that The plurality of address information are sorted according to priority, and the control method further comprises: A refresh operation is performed on the corresponding storage row according to the address information with the highest priority in the refresh table, and the refreshed address information with the highest priority is deleted from the refresh table.

18. The control method according to claim 16, It is characterized in that The control method comprises: Determine whether there is address information of a storage row adjacent to the first storage row in the refresh table; In response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, inserting address information of a storage row adjacent to the first storage row into the refresh table; In response to the presence of address information of a storage row adjacent to the first storage row in the refresh table, the priority of the address information of the storage row adjacent to the first storage row in the refresh table is adjusted.

19. The control method according to claim 18, It is characterized in that The refresh table includes a first sub-table and a second sub-table; the priority of the address information in the first sub-table is higher than the priority of the address information in the second sub-table.

20. The control method according to claim 19, It is characterized in that The control method comprises: In response to the absence of address information of a storage row adjacent to the first storage row in the refresh table, the address information of the storage row adjacent to the first storage row is inserted into the second sub-table, and the address information of the storage row adjacent to the first storage row has the highest priority in the second sub-table.

21. The control method according to claim 20, It is characterized in that The storage rows adjacent to the first storage row include a second storage row and a third storage row, and the control method includes: In response to the absence of address information identical to the second address information corresponding to the second storage row and address information identical to the third address information corresponding to the third storage row in the refresh table, the second address information and the third address information are inserted into the second sub-table; wherein the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority; or, the priority of the second address information in the second sub-table is the highest priority, and the priority of the third address information in the second sub-table is the second highest priority.

22. The control method according to claim 19, It is characterized in that The control method comprises: In response to address information of a storage row adjacent to the first storage row existing in the first sub-table, the priority of the address information of the storage row adjacent to the first storage row is adjusted to the highest priority in the first sub-table.

23. The control method according to claim 19, It is characterized in that The control method comprises: In response to address information of a storage row adjacent to the first storage row existing in the second sub-table, the address information of the storage row adjacent to the first storage row is adjusted to the first sub-table.

24. The control method according to claim 23, It is characterized in that The priority of the address information of the storage row adjacent to the first storage row in the first sub-table is the lowest priority.

25. The control method according to claim 20, It is characterized in that The control method further comprises: When the amount of address information stored in the second sub-table is greater than a set threshold, at least one address information in the second sub-table is deleted.

26. The control method according to claim 25, It is characterized in that The control method comprises: The address information in the second sub-table is deleted in order of priority; wherein, the address information with a lower priority is deleted first.

27. The control method according to claim 17, It is characterized in that The control method comprises: In response to deleting the refreshed highest priority address information from the refresh table, the priorities corresponding to the remaining address information in the refresh table are all increased by one level, and the fourth address information corresponding to the fourth storage row is inserted into the refresh table, wherein the priority of the fourth address information in the refresh table is the lowest priority.

28. The control method according to claim 17, It is characterized in that The priority of each of the plurality of address information is determined according to the probability that the storage row corresponding to the address information is attacked by a row hammer.

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