Shared bit line-based flash memory structure test structure
By designing shared conductive plugs and independent conductive plugs in flash memory devices, a snake-shaped test circuit is formed to monitor current abnormalities, and the problem that the existing technology cannot monitor the connection between the shared bit line interconnect structure and the bit line doped region in flash memory devices is solved, and the yield of the device is improved.
Patent Information
- Application Number
- CN202510107917.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-23
AI Technical Summary
The prior art cannot monitor whether there is an abnormality in the connection between the metal interconnect structure of the shared bit lines and the bit line doped region in the flash memory device, resulting in a yield loss.
A test structure of a flash memory structure based on shared bit lines is designed. By setting a shared conductive plug and an independent conductive plug between the flash memory cells, and forming a snake-shaped test circuit to monitor whether there is an abnormality in the current to judge the connection between the shared conductive plug and the bit line doped region.
By monitoring the current abnormality in the snake-shaped test circuit, the connection between the shared conductive plug and the bit line doped region in the flash memory device is effectively monitored, which improves the yield of the device.
Smart Images
Figure CN120032698A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor testing technology, and in particular to a test structure of a flash memory structure based on a shared bit line. Background Art
[0002] In flash memory devices, in order to save area, flash memory devices that share bit lines (BL) have become the mainstream design of flash memory devices.
[0003] Among them, the bit lines between adjacent different flash memory devices are connected through a metal interconnect structure, which can achieve bit line sharing. However, if there is an abnormality in the connection between the metal interconnect structure connecting the bit lines and the bit line doping area (active area), it will cause a loss in the yield of the flash memory device.
[0004] However, the WAT (wafer acceptance test) currently available in the market does not have a test structure for monitoring whether there is an abnormality in the connection between the interconnect structure of the shared bit line and the bit line doping region in the flash memory device. Summary of the invention
[0005] The present application provides a test structure of a flash memory structure based on a shared bit line, which can solve the problem of being unable to monitor whether a metal interconnect structure of a shared bit line in a flash memory device has an abnormality.
[0006] The embodiment of the present application provides a test structure of a flash memory structure based on a shared bit line, comprising: flash memory cells arranged in an array, a plurality of shallow trench isolation structures, an interlayer insulating layer, a plurality of independent conductive plugs, a plurality of shared conductive plugs and a patterned metal layer, wherein: The shallow trench isolation structure is located in the substrate between adjacent flash memory cells and is used to isolate different flash memory cells; Each of the flash memory cells comprises: a substrate, a gate oxide layer located on the surface of the substrate, a floating gate layer, an ONO film layer and a control gate layer located on the gate oxide layer and stacked in sequence, a groove located in the floating gate layer, the ONO film layer and the control gate layer, a word line polysilicon filling the groove, a bit line doping region located in the substrate outside the control gate layer, and a metal silicide layer covering the bit line doping region; The interlayer insulating layer covers all flash memory cells, the independent conductive plugs and the shared conductive plugs respectively penetrate the interlayer insulating layer and are in direct contact with the metal silicide layer, and the patterned metal layer covers the independent conductive plugs and the shared conductive plugs and a portion of the surface of the interlayer insulating layer; wherein, in the horizontal direction, adjacent flash memory cells are connected through one shared conductive plug; in the vertical direction, adjacent flash memory cells are connected through two independent conductive plugs and the patterned metal layer covering the two independent conductive plugs; The patterned metal layer, the shared conductive plug, the flash memory cell, the shared conductive plug and the patterned metal layer are connected in series in this order to form a serpentine test circuit for the flash memory cells in the same row; Through the independent conductive plugs, the serpentine test circuits of the flash memory cells in each adjacent row are connected in series to form a serpentine test circuit with an integral structure.
[0007] Optionally, in the test structure of the flash memory structure based on a shared bit line, each of the flash memory cells is gated vertically.
[0008] Optionally, in the test structure of the flash memory structure based on a shared bit line, each of the shared conductive plugs spans a shallow trench isolation structure between two adjacent flash memory cells in the same row and a bit line doping region between two adjacent flash memory cells in the same row.
[0009] Optionally, in the test structure of the flash memory structure based on shared bit lines, the test structure of the flash memory structure based on shared bit lines also includes: at least two pairs of test pads, a first pair of test pads respectively connected to the two ends of the serpentine test circuit of the same row of flash memory cells, and a second pair of test pads respectively connected to the two ends of the serpentine test circuit of the overall structure.
[0010] Optionally, in the test structure of the flash memory structure based on a shared bit line, the thickness of the metal silicide layer is 100Å~300Å.
[0011] Optionally, in the test structure of the flash memory structure based on a shared bit line, the material of the metal silicide layer is nickel silicide, tank silicide or titanium silicide.
[0012] Optionally, in the test structure of the flash memory structure based on a shared bit line, the flash memory unit further includes: a dielectric layer and a word line protection layer, the dielectric layer covers the control gate layer, and the word line protection layer covers the word line polysilicon.
[0013] Optionally, in the test structure of the flash memory structure based on a shared bit line, the ONO film layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence, and the first silicon oxide layer is located on the floating gate layer.
[0014] The technical solution of this application has at least the following advantages: The present application provides a test structure of a flash memory structure based on a shared bit line, including: flash memory cells arranged in an array, a plurality of shallow trench isolation structures, an interlayer insulating layer, a plurality of independent conductive plugs, a plurality of shared conductive plugs and a patterned metal layer, wherein, in the horizontal direction, adjacent flash memory cells are connected by a shared conductive plug; in the vertical direction, adjacent flash memory cells are connected by two independent conductive plugs and the patterned metal layer thereon. The present application forms a serpentine test circuit of the flash memory cells in the same row by sequentially and repeatedly connecting the shared conductive plug, the flash memory cells, the shared conductive plug and the patterned metal layer in series; and then connects the serpentine test circuits of the flash memory cells in each row in series through independent conductive plugs to form a serpentine test circuit of the overall structure, and further effectively monitors whether there is an abnormality in the connection between the shared conductive plug and the active area in contact with the bottom of the flash memory device by monitoring whether there is an abnormality in the current in the serpentine test circuit, thereby improving the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0016] Figure 1 is a top view of a test structure of a flash memory structure before a patterned metal layer is formed according to an embodiment of the present invention; Figure 2 is a top view of a test structure of a flash memory structure sharing a bit line after a patterned metal layer is formed according to an embodiment of the present invention; Figure 3 yes Figure 2 A schematic cross-sectional view of the test structure along the AA' tangent line; Figure 4 yes Figure 2 A schematic cross-sectional view of the test structure along the BB' tangent line; The reference numerals are described as follows: 10-substrate, 11-shallow trench isolation structure, 20-gate oxide layer, 30-floating gate layer, 40-ONO film layer, 50-control gate layer, 51-word line polysilicon, 60-interlayer insulating layer, 71-independent conductive plug, 72-shared conductive plug, 80-metal silicide layer, 81-bit line doping region, 90-patterned metal layer, 91-dielectric layer, 92-word line protection layer, 93-side wall, 94-tunneling oxide layer, 95-test pad. DETAILED DESCRIPTION
[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0021] The present application embodiment provides a test structure of a flash memory structure based on a shared bit line, referring to Figure 1-Figure 4 , Figure 1 is a top view of a test structure of a flash memory structure before a patterned metal layer is formed according to an embodiment of the present invention, Figure 2 is a top view of a test structure of a flash memory structure sharing a bit line after a patterned metal layer is formed according to an embodiment of the present invention, Figure 3 yes Figure 2 Schematic diagram of the cross-section of the test structure along the AA' tangent line, Figure 4 yes Figure 2 The cross-sectional schematic diagram of the test structure along the BB' cut line in the figure, the test structure of the flash memory structure based on the shared bit line includes: flash memory cells arranged in an array, a plurality of shallow trench isolation structures 11, an interlayer insulating layer 60, a plurality of independent conductive plugs 71, a plurality of shared conductive plugs 72 and a patterned metal layer 90.
[0022] The shallow trench isolation structure 11 is located in the substrate 10 between adjacent flash memory units and is used to isolate different flash memory units. That is, the structure between two adjacent shallow trench isolation structures 11 is a flash memory unit.
[0023] For further reference, Figure 3 Each of the flash memory cells includes: a substrate 10, a gate oxide layer 20 located on the surface of the substrate 10, a floating gate layer 30, an ONO film layer 40 and a control gate layer 50 located on the gate oxide layer 20 and stacked in sequence, and a groove located in the floating gate layer 30, the ONO film layer 40 and the control gate layer 50, and a word line polysilicon 51 filling the groove, and a bit line doping region 81 located in the substrate 10 outside the control gate layer 50, and a metal silicide layer 80 covering the bit line doping region 81.
[0024] In this embodiment, the thickness of the metal silicide layer 80 is 100Å-300Å.
[0025] Preferably, the material of the metal silicide layer 80 is nickel silicide, titanium silicide or titanium silicide.
[0026] Furthermore, the flash memory unit further includes: a dielectric layer 91 and a word line protection layer 92 , wherein the dielectric layer 91 covers the control gate layer 50 , and the word line protection layer 92 covers the word line polysilicon 51 .
[0027] Preferably, the flash memory unit also includes: a side wall 93 and a tunneling oxide layer 94, the side wall 93 is located on the floating gate layer 30 and between the control gate layer 50 and the word line polysilicon 51, the tunneling oxide layer 94 covers the side wall 93, the inner surface of the floating gate layer 30 and the gate oxide layer 20, and the tunneling oxide layer 94 is U-shaped to wrap the bottom and sides of the word line polysilicon 51.
[0028] In this embodiment, the ONO film layer 40 includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence, and the first silicon oxide layer is located on the floating gate layer.
[0029] Preferably, the interlayer insulating layer 60 covers all flash memory cells, the independent conductive plugs 71 and the shared conductive plugs 72 respectively penetrate the interlayer insulating layer 60 and are in direct contact with the metal silicide layer 80, and the patterned metal layer 90 covers the independent conductive plugs 71 and the shared conductive plugs 72 and a portion of the surface of the interlayer insulating layer 60.
[0030] Preferably, the flash memory device in the present application is a split-gate flash memory device. In this embodiment, each of the flash memory units is split-gate along the longitudinal direction.
[0031] Among them, reference Figure 1 and Figure 2 In the lateral direction, the adjacent flash memory cells are connected through a shared conductive plug 72; in the longitudinal direction, the adjacent flash memory cells are connected through two independent conductive plugs 71 and the patterned metal layer 90 covering the two independent conductive plugs 71.
[0032] Preferably, the patterned metal layer 90, the shared conductive plug 72, the flash memory unit, the shared conductive plug 72 and the patterned metal layer 90 are connected in series in this order to form a serpentine test circuit for the flash memory units in the same row; and the above-mentioned series structure (the series structure composed of the patterned metal layer 90, the shared conductive plug 72, the flash memory unit, the shared conductive plug 72 and the patterned metal layer 90) can be a repeating unit, and the repeating units are then connected in series in sequence to still form a serpentine test circuit for the flash memory units in the same row.
[0033] Furthermore, through the independent conductive plugs 71, the serpentine test circuits of the flash memory cells in each adjacent row are connected in series to form a serpentine test circuit with an integral structure.
[0034] Better, reference Figure 4 Each of the shared conductive plugs 72 spans the shallow trench isolation structure 11 between two adjacent flash memory cells in the same row and covers the bit line doping region 81 of two adjacent flash memory cells in the same row.
[0035] For further reference, Figure 2 The test structure of the flash memory structure based on shared bit lines also includes: at least two pairs of test pads 95. In this embodiment, the first pair of test pads 95 are respectively connected to the two ends of the serpentine test circuit of the same row of flash memory cells, and the second pair of test pads 95 are respectively connected to the two ends of the serpentine test circuit of the overall structure.
[0036] Among them, when the test structure is working, a certain voltage difference is applied to any pair of test pads 95, and current flows through at least one serpentine test circuit to perform WAT electrical test. The present application monitors whether there is an abnormality in the connection between the shared conductive plug and the active area in contact with the bottom of the flash memory device by monitoring whether there is an abnormality in the current in the serpentine test circuit. Specifically, in a serpentine test circuit, if the current value is monitored to be within the preset threshold interval, it is diagnosed that the connection between the shared conductive plug and the active area in contact with the bottom of the flash memory device on the serpentine test circuit is normal; if the current value is monitored to be greater than the upper limit of the preset threshold interval, it is diagnosed that the connection between the shared conductive plug and the active area in contact with the bottom of the flash memory device on the serpentine test circuit is normal; if the current value is monitored to be less than the lower limit of the preset threshold interval, it is diagnosed that the connection between at least one shared conductive plug in the flash memory device on the serpentine test circuit and the active area in contact with the bottom is abnormal.
[0037] In the present application, a serpentine test circuit of the flash memory cells in the same row is formed by sequentially connecting a shared conductive plug, a flash memory cell, a shared conductive plug and a patterned metal layer in series and repeatedly connecting them in series; then, the serpentine test circuits of the flash memory cells in each row are connected in series through independent conductive plugs to form a serpentine test circuit of the overall structure. By monitoring whether the current in the serpentine test circuit is abnormal, it is further effectively monitored whether there is an abnormality in the connection between the shared conductive plug in the flash memory device and the active area (bit line doping area) in contact with its bottom, thereby improving the yield of the device.
[0038] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A test structure of a flash memory structure based on a shared bit line, characterized in that: include: Flash memory cells arranged in an array, a plurality of shallow trench isolation structures, an interlayer insulating layer, a plurality of independent conductive plugs, a plurality of shared conductive plugs and a patterned metal layer, wherein: The shallow trench isolation structure is located in the substrate between adjacent flash memory cells and is used to isolate different flash memory cells; Each of the flash memory cells comprises: a substrate, a gate oxide layer located on the surface of the substrate, a floating gate layer, an ONO film layer and a control gate layer located on the gate oxide layer and stacked in sequence, a groove located in the floating gate layer, the ONO film layer and the control gate layer, a word line polysilicon filling the groove, a bit line doping region located in the substrate outside the control gate layer, and a metal silicide layer covering the bit line doping region; The interlayer insulating layer covers all flash memory cells, the independent conductive plugs and the shared conductive plugs respectively penetrate the interlayer insulating layer and are in direct contact with the metal silicide layer, and the patterned metal layer covers the independent conductive plugs and the shared conductive plugs and a portion of the surface of the interlayer insulating layer; wherein, in the horizontal direction, adjacent flash memory cells are connected through one shared conductive plug; in the vertical direction, adjacent flash memory cells are connected through two independent conductive plugs and the patterned metal layer covering the two independent conductive plugs; The patterned metal layer, the shared conductive plug, the flash memory cell, the shared conductive plug and the patterned metal layer are connected in series in this order to form a serpentine test circuit for the flash memory cells in the same row; Through the independent conductive plugs, the serpentine test circuits of the flash memory cells in each adjacent row are connected in series to form a serpentine test circuit with an integral structure.
2. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: Each of the flash memory units is divided into gates along the longitudinal direction.
3. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: Each of the shared conductive plugs spans the shallow trench isolation structure between two adjacent flash memory cells in the same row and the bit line doping regions of two adjacent flash memory cells in the same row.
4. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: The test structure of the flash memory structure based on shared bit lines also includes: at least two pairs of test pads, the first pair of test pads are respectively connected to the two ends of the serpentine test circuit of the same row of flash memory cells, and the second pair of test pads are respectively connected to the two ends of the serpentine test circuit of the overall structure.
5. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: The thickness of the metal silicide layer is 100Å~300Å.
6. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: The material of the metal silicide layer is nickel silicide, titanium silicide or titanium silicide.
7. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: The flash memory unit further includes: a dielectric layer and a word line protection layer, wherein the dielectric layer covers the control gate layer, and the word line protection layer covers the word line polysilicon.
8. The test structure of the flash memory structure based on the shared bit line according to claim 1, characterized in that: The ONO film layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence, and the first silicon oxide layer is located on the floating gate layer.