Semiconductor device etching method and image sensor formed by same
By reducing the line width of the lithographic pattern, forming a second lithographic pattern, etching to form a first trench and forming a dielectric layer on its surface, the problem of easy destruction of the shallow trench side walls is solved, and the pass rate of the device is improved and the cost is reduced.
Patent Information
- Application Number
- CN202311551087.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-20
- Publication Date
- 2025-05-23
AI Technical Summary
When etching the isolation trench between pixel units forming the image sensor, the shallow trench side walls after the initial etching are easily damaged, affecting the subsequent process, resulting in the device being unable to meet the design standards and reducing the device yield.
By reducing the line width of the first lithographic pattern, a second lithographic pattern is formed, the semiconductor substrate is etched according to the second lithographic pattern to form a first trench, and a dielectric layer is formed on its surface to protect the side walls. The second trench is etched again using the same mask layer to ensure that the side walls of the first trench are not damaged.
The device pass rate is improved, ensuring that the side walls of the first trench are not damaged, and cost is reduced, since no additional mask is required during the two etchings.
Smart Images
Figure CN120033077A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device etching method and an isolation trench between pixel units of an image sensor formed therein. Background Art
[0002] When etching to form the isolation trenches between the pixel units of the image sensor, a secondary etching process is used to form a deep trench. After the primary etching, a shallow trench is formed, and the secondary etching is continued in the shallow trench to finally form a deep trench. However, during the secondary etching process, the sidewalls of the shallow trench formed initially are easily damaged, which affects the subsequent manufacturing process, causing the device to fail to meet the design standard and reducing the device yield.
[0003] The statements herein merely provide background art related to the present invention and do not necessarily constitute prior art. Summary of the invention
[0004] The purpose of the present invention is to provide a semiconductor device etching method and an image sensor formed therefrom, which ensures that the side wall of the first groove will not be damaged, improves the qualified rate of the device, and does not require additional masks during the two etching processes, which is conducive to cost control.
[0005] In order to achieve the above object, the present invention provides a semiconductor device etching method, comprising:
[0006] Reducing the line width of the first photolithography pattern to obtain a second photolithography pattern, and etching the semiconductor substrate according to the second photolithography pattern to form a first trench;
[0007] forming a dielectric layer on a surface of the first trench;
[0008] According to the first photolithography pattern, etching the dielectric layer and the semiconductor substrate to form a second trench;
[0009] The width of the first trench is greater than the width of the second trench.
[0010] The method of forming the first trench comprises:
[0011] forming a first mask layer on the surface of the semiconductor substrate;
[0012] forming a second mask layer on the surface of the first mask layer according to the first photolithography pattern;
[0013] performing transverse etching on the second mask layer to reduce the line width of the second mask layer to obtain a second photolithography pattern;
[0014] According to the second photolithography pattern, etching the first mask layer;
[0015] The semiconductor substrate is etched according to the remaining first mask layer to form the first trench.
[0016] The method for laterally etching the second mask layer comprises: laterally etching from both sides of the second mask layer, the line widths of the two sides of the second mask layer are reduced in the same size, and the line width reduced on one side is 5nm to 15nm.
[0017] The width of the first trench is 15 nm to 25 nm greater than the width of the second trench.
[0018] When the dielectric layer is formed on the surface of the first trench, the dielectric layer is also formed on the surface of the remaining first mask layer.
[0019] The semiconductor substrate includes a first substrate layer and a second substrate layer with different doping concentrations. The second substrate layer is located on the surface of the first substrate layer, and the first mask layer is located on the surface of the second substrate layer. When etching the semiconductor substrate to form the first groove, etching stops when the interface between the second substrate layer and the first substrate layer is reached.
[0020] The first substrate layer is a silicon doped layer, and the second substrate layer is an intrinsic layer.
[0021] The method of forming the second trench comprises:
[0022] According to the first photolithography pattern, forming a second mask layer on the surface of the dielectric layer on the surface of the first mask layer;
[0023] According to the second mask layer, etching the dielectric layer located at the bottom surface of the first trench;
[0024] The dielectric layer and the first substrate layer on the sidewall of the first trench are etched according to the second mask layer to form the second trench.
[0025] The material of the dielectric layer is oxide and polyethylene oxide.
[0026] The first mask layer includes a pad oxide layer, a silicon nitride layer located on a surface of the pad oxide layer, and a polyethylene oxide layer located on a surface of the silicon nitride layer.
[0027] The present invention also provides an image sensor, which adopts the semiconductor device etching method to form isolation grooves between pixel units of the image sensor.
[0028] When etching the first groove, the present invention performs transverse etching on the second mask layer having the first photolithography pattern to reduce the line width of the second mask layer. The second mask layer after the line width is reduced forms a second photolithography pattern. The first groove is formed by etching the second mask layer after the line width is reduced. At this time, the width of the first groove is wider than the width of the isolation groove that needs to be obtained in the end, thereby providing space to form a dielectric layer on the surface of the first groove, and the dielectric layer is used to protect the side wall of the first groove. The second mask layer having the first photolithography pattern is used again to etch and form the second groove. The second mask layer is reused in two etchings without adding other masks, which is conducive to cost control. In the process of etching the second groove, the dielectric layer ensures that the side wall of the first groove will not be damaged, thereby improving the qualified rate of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figures 1 to 9 It is a schematic diagram of the operation flow of a semiconductor device etching method provided in an embodiment. DETAILED DESCRIPTION
[0030] The following is based on Figures 1 to 9 , specifically describe the preferred embodiments of the present invention.
[0031] The present invention provides a semiconductor device etching method for forming an isolation trench between pixel units of an image sensor, the etching method specifically comprising the following steps:
[0032] Step S1: Figure 1 As shown, a semiconductor substrate 1 is prepared, wherein the semiconductor substrate 1 comprises a first substrate layer 101 with different doping concentrations and a second substrate layer 102 located on the surface of the first substrate layer 101, wherein the first substrate layer 101 is a silicon doped layer, which may be P-type silicon doped or N-type silicon doped, and the second substrate layer 102 is an intrinsic layer, and the thickness is 0.3um to 0.5um.
[0033] Step S2: Figure 1 As shown, a first mask layer 2 is deposited on the surface of the second substrate layer 102, and the first mask layer 2 includes: a hard mask layer 21 located on the surface of the second substrate layer 102 and a photoresist layer 22 located on the surface of the hard mask layer 21, the hard mask layer 21 includes a pad oxide layer 201 located on the surface of the second substrate layer 102, a silicon nitride (SiN) layer 202 located on the surface of the pad oxide layer 201, and a polyethylene oxide (PEOX) layer 203 located on the surface of the silicon nitride layer 202, the photoresist layer 22 includes an APF layer 204 located on the surface of the polyethylene oxide layer 203, and a dielectric anti-reflective coating (DARC) layer 205 located on the surface of the APF layer 204.
[0034] Step S3: Figure 2 As shown, according to the first photolithography pattern, a second mask layer 3 is formed on the surface of the first mask layer 2. At this time, the line width of the second mask layer 3 is D1.
[0035] Step S4: Figure 3 As shown, the second mask layer 3 is laterally etched from both sides of the second mask layer 3 to reduce the line width of the second mask layer 3 and obtain a second photolithography pattern. The line widths reduced on both sides of the second mask layer 3 are the same, and the line width reduced on one side is 5nm to 15nm, so that the line width of the second mask layer 3 is finally reduced to D2, and the overall reduced line width of the second mask layer 3 is d=D1-D2, and the range of the reduced line width value d is generally 15nm to 25nm.
[0036] Step S5: Figure 4 As shown, according to the second mask layer 3 with reduced line width, the first mask layer 2 is etched, and the etching is stopped when it reaches the top surface of the second substrate layer 102, so that the line width of the hard mask layer 21 is D2, and the photoresist layer 22 on the surface of the hard mask layer 21 is completely removed.
[0037] Step S6: Figure 5 As shown, the second substrate layer 102 is continuously etched according to the hard mask layer 21 , and the etching is stopped when the second substrate layer 102 and the first substrate layer 101 meet at the interface, thereby forming a first trench 4 .
[0038] Step S6: Figure 6 As shown, a dielectric layer 5 is formed on the surface of the first groove 4. The material of the dielectric layer 5 is oxide and polyethylene oxide. The dielectric layer 5 is uniformly deposited to cover the bottom surface and side walls of the first groove 4, and also covers the top surface and side walls of the hard mask layer 21 at the same time, thereby forming complete protection for the first groove 4 and the hard mask layer 21.
[0039] Step S7: Figure 7 As shown, according to the first photolithography pattern, a second mask layer 3 is formed again on the surface of the dielectric layer 5 on the surface of the hard mask layer 21. At this time, the line width of the second mask layer 3 is still D1.
[0040] Step S8: Figure 8 As shown, according to the second mask layer 3 , the dielectric layer 5 located at the bottom surface of the first trench 4 is etched, and the etching stops when it reaches the top surface of the first substrate layer 101 .
[0041] Step S9: Fig. 9As shown, according to the second mask layer 3, the dielectric layer 5 and the first substrate layer 101 on the sidewall of the first trench 4 are continuously etched downward until a predetermined depth is reached to form a second trench 6, and finally an isolation trench between pixel units of the image sensor is formed. Figure 5 and Fig. 9 As shown, the width of the first groove 4 is greater than the width of the second groove 6, and the difference between the width of the first groove 4 and the width of the second groove 6 is equal to the line width value d of the overall reduction of the second mask layer 3. Therefore, the width of the first groove 4 is 15nm to 25nm larger than the width of the second groove 6.
[0042] When etching the first groove, the present invention performs transverse etching on the second mask layer having the first photolithography pattern to reduce the line width of the second mask layer. The second mask layer after the line width is reduced forms a second photolithography pattern. The first groove is formed by etching the second mask layer after the line width is reduced. At this time, the width of the first groove is wider than the width of the isolation groove that needs to be obtained in the end, thereby providing space to form a dielectric layer on the surface of the first groove, and the dielectric layer is used to protect the side wall of the first groove. The second mask layer having the first photolithography pattern is used again to etch and form the second groove. The second mask layer is reused in two etchings without adding other masks, which is conducive to cost control. In the process of etching the second groove, the dielectric layer ensures that the side wall of the first groove will not be damaged, thereby improving the qualified rate of the device.
[0043] It should be noted that, in the embodiments of the present invention, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0044] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0045] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.
Claims
1. A semiconductor device etching method, It is characterized in that Include: Reducing the line width of the first photolithography pattern to obtain a second photolithography pattern, and etching the semiconductor substrate according to the second photolithography pattern to form a first trench; forming a dielectric layer on a surface of the first trench; According to the first photolithography pattern, etching the dielectric layer and the semiconductor substrate to form a second trench; The width of the first trench is greater than the width of the second trench.
2. The semiconductor device etching method according to claim 1, It is characterized in that The method of forming the first trench comprises: forming a first mask layer on the surface of the semiconductor substrate; According to the first photolithography pattern, forming a second mask layer on the surface of the first mask layer; performing transverse etching on the second mask layer to reduce the line width of the second mask layer to obtain a second photolithography pattern; According to the second photolithography pattern, etching the first mask layer; The semiconductor substrate is etched according to the remaining first mask layer to form the first trench.
3. The semiconductor device etching method according to claim 2, It is characterized in that The method for laterally etching the second mask layer comprises: laterally etching from both sides of the second mask layer, the line widths of the two sides of the second mask layer are reduced in the same size, and the line width reduced on one side is 5nm to 15nm.
4. The semiconductor device etching method according to claim 3, It is characterized in that The width of the first trench is 15 nm to 25 nm greater than the width of the second trench.
5. The semiconductor device etching method according to claim 2, It is characterized in that When the dielectric layer is formed on the surface of the first trench, the dielectric layer is also formed on the surface of the remaining first mask layer.
6. The semiconductor device etching method according to claim 5, It is characterized in that The semiconductor substrate includes a first substrate layer and a second substrate layer with different doping concentrations. The second substrate layer is located on the surface of the first substrate layer, and the first mask layer is located on the surface of the second substrate layer. When etching the semiconductor substrate to form the first groove, etching stops when the interface between the second substrate layer and the first substrate layer is reached.
7. The semiconductor device etching method according to claim 6, It is characterized in that The first substrate layer is a silicon doped layer, and the second substrate layer is an intrinsic layer.
8. The semiconductor device etching method according to claim 6, It is characterized in that The method of forming the second trench comprises: According to the first photolithography pattern, forming a second mask layer on the surface of the dielectric layer on the surface of the first mask layer; According to the second mask layer, etching the dielectric layer located at the bottom surface of the first trench; The dielectric layer and the first substrate layer on the sidewall of the first trench are etched according to the second mask layer to form the second trench.
9. The semiconductor device etching method according to claim 5, It is characterized in that The material of the dielectric layer is oxide and polyethylene oxide.
10. The semiconductor device etching method according to claim 9, It is characterized in that The first mask layer includes a pad oxide layer, a silicon nitride layer located on a surface of the pad oxide layer, and a polyethylene oxide layer located on a surface of the silicon nitride layer.
11. An image sensor, It is characterized in that The semiconductor device etching method according to any one of claims 1 to 10 is used to form isolation trenches between pixel units of the image sensor.