Preparation method of semiconductor device isolation groove structure
By filling and leveling the isolation material layer with a fluidizable flowable material layer, combined with dry etching method, the problems of complex isolation trench structure preparation process and etching residue in the prior art are solved, and a more efficient and higher quality preparation of isolation trench structures for semiconductor devices are achieved.
Patent Information
- Application Number
- CN202311573628.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-23
- Publication Date
- 2025-05-23
AI Technical Summary
The preparation process of the isolation trench structure of existing semiconductor devices is complex, which is prone to etching residues, which seriously restricts the improvement of device efficiency and quality.
The flowable material layer is used to fill the uneven surface of the isolation material layer, and the flow material layer and the isolation material layer are removed by dry etching to ensure that the surface of the isolation material layer is flat, and then the isolation material layer on the substrate surface is selectively removed.
Reduces process complexity, improves production efficiency, reduces costs, and avoids impurity particles in the etching barrier layer, improving product yield.
Smart Images
Figure CN120033141A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for preparing an isolation trench structure of a semiconductor device. Background Art
[0002] With the continuous development of integrated circuit technology, the number of active devices integrated per unit area of semiconductor substrate is increasing (e.g., millions), so the devices are placed more closely in the chip to fit the available space of the chip. In order to prevent the devices from affecting each other, isolation technology is needed to isolate the active devices from each other. As the density of active devices per unit area of semiconductor substrate continues to increase, effective insulation isolation between devices becomes more important.
[0003] At present, the trench isolation structure (Shallow Trench Isolation, referred to as STI) is a commonly used isolation technology, which has good isolation effects, such as process isolation effect and electrical isolation effect, and has gradually become one of the mainstream isolation technologies for device active area isolation. Figures 1 to 6 , which is a main step in the STI preparation process of an exemplary semiconductor device, includes: forming a silicon nitride layer 102 on a silicon dioxide layer 101 on the surface of a silicon substrate 100, and sequentially etching the silicon nitride layer 102, the silicon dioxide layer 101 and the silicon substrate 100 to form a trench 103, as shown in FIG. Figure 1 Then, the trench 103 is filled with an oxide filling layer 105, as shown in FIG. Figure 2 Then, the oxide filling layer 105 is planarized by chemical mechanical polishing (CMP), and the silicon nitride layer 102 is used as an etch stop layer, as shown in FIG. Figure 3 Then, the oxide filling layer 105 of a preset thickness is etched to maintain the smoothness of the surface of the oxide filling layer 105 after the subsequent removal of the silicon nitride layer 102, as shown in FIG. Figure 4 Then, the silicon nitride layer 102 is removed by a wet etching process, as shown in FIG. Figure 5 As shown; finally, the oxide filling layer 105 of a preset thickness in the groove 103 is removed alternately by wet etching process and dry etching process to achieve a horizontal and flat groove 106 with better effect. The preparation process of the STI needs to go through a series of complex processes such as deposition, CMP, dry etching and wet etching, which seriously reduces production efficiency and increases costs; in addition, an etching stop layer, such as a silicon nitride layer 102, needs to be formed during etching. The deposition and removal of the etching stop layer will cause a high content of impurity particles in the film layer, affecting the device yield. The existing STI preparation process is complex and prone to etching residues, which seriously restricts the improvement of the efficiency and quality of semiconductor devices. Summary of the invention
[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method for preparing an isolation trench structure of a semiconductor device, so as to solve the problem that the process of preparing an STI structure with a groove of a semiconductor device in the prior art is complex, and etching residues are easily generated, which seriously restricts the improvement of the efficiency and quality of the semiconductor device.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an isolation trench structure of a semiconductor device, the preparation method comprising the following steps:
[0006] Providing a substrate, and etching the substrate to form a trench in the substrate;
[0007] forming an isolation material layer on the substrate and in the trench, wherein the isolation material layer at least fills the trench, and the surface of the isolation material layer is uneven;
[0008] A flowable material layer having fluidity is formed on the surface of the isolation material layer; the flowable material layer fills the uneven surface of the isolation material layer;
[0009] Using a dry etching process to remove the flow material layer and the isolation material layer of a preset thickness, so that the remaining isolation material layer has a flat surface, and the etching selectivity ratio of the flow material layer to the isolation material layer is 1.2:1 to 1:1.2;
[0010] The isolation material layer on the surface of the substrate is selectively etched away to form the isolation material layer only in the trench.
[0011] Optionally, a dry etching process is adopted and the etching time is controlled to remove the isolation material layer on the surface of the substrate, so as to form the isolation material layer only in the trench.
[0012] Optionally, a surface of the isolation material layer in the trench is flush with a surface of the substrate, or a surface of the isolation material layer in the trench is lower than a preset depth from a surface of the substrate.
[0013] Furthermore, when the surface of the isolation material layer in the trench is lower than a preset depth of the substrate surface, a pad oxide layer is formed between the trench surface and the isolation material layer.
[0014] Optionally, the material of the flow material layer is SOC material or SOD material or polysilazane.
[0015] Furthermore, the material of the isolation material layer is silicon dioxide.
[0016] Further, the material of the flow material layer is SOC material; in the step of removing the flow material layer and the isolation material layer of a preset thickness by a dry etching process, the etching gas source of the dry etching process includes H 2 or C x H y F z .
[0017] Furthermore, the substrate material is silicon, and in the step of removing the isolation material layer on the substrate surface by dry etching, the etching gas source of the dry etching process includes CHF 3 .
[0018] Optionally, the flowable material layer is formed by a spin coating process.
[0019] Optionally, a dry etching process is adopted to remove the flow material layer and the isolation material layer of a preset thickness by controlling the etching time or monitoring the composition of the final etching product.
[0020] As described above, the preparation method of the semiconductor device isolation groove structure of the present invention adopts a flowable material with fluidity to fill the isolation material layer. Based on the fluidity of the material layer, the isolation material layer with an uneven surface (i.e., bump) can be filled during the formation process and the surface of the flowable material layer can be made flat. Then, the isolation material layer with a flat surface can be obtained by dry etching the flowable material layer and the isolation material layer with a similar etching selectivity ratio. Then, the isolation material layer on the surface of the substrate is selectively removed by dry etching, so that the isolation material layer formed only in the groove can be obtained, thereby realizing the preparation of the isolation groove structure. The process method utilizes the flow characteristics of the flowable material layer and does not require CMP flattening and an etching barrier layer for endpoint detection, thereby effectively reducing the process complexity, improving production efficiency and reducing costs; at the same time, it avoids impurity particles caused by the deposition and removal of the etching barrier layer, thereby effectively improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figures 1 to 6 The figure shows a schematic cross-sectional structure after each step of the STI preparation process of an exemplary semiconductor device is completed.
[0022] Figures 7 to 12 It is a schematic diagram of the cross-sectional structure presented after each step in the method for preparing the isolation trench structure of a semiconductor device of the present invention is completed.
[0023] Description of Reference Numerals
[0024] 100 Silicon substrate
[0025] 101 Silicon dioxide layer
[0026] 102 Silicon Oxynitride Layer
[0027] 103 Groove
[0028] 105 Oxide filling layer
[0029] 106 grooves
[0030] 10 Substrate
[0031] 11 Oxygen cushion layer
[0032] 12 Isolation material layer
[0033] 13 Flowing material layer
[0034] 14 Grooves
[0035] 16 Grooves DETAILED DESCRIPTION
[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] See also Figures 7 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0038] This embodiment provides a method for preparing an isolation trench structure of a semiconductor device, which is used to prepare an isolation trench structure in which a groove needs to be formed. The preparation method includes the following steps:
[0039] S1, providing a substrate, and etching the substrate to form a groove in the substrate;
[0040] S2, forming an isolation material layer on the substrate and in the trench, wherein the isolation material layer at least fills the trench, and the surface of the isolation material layer is uneven;
[0041] S3, forming a flowable material layer with fluidity on the surface of the isolation material layer; since the flowable material layer has good fluidity, the flowable material layer can fill the uneven surface of the isolation material layer, and the surface of the flowable material layer is flat;
[0042] S4, removing the flow material layer and the isolation material layer of a preset thickness by a dry etching process, so that the remaining isolation material layer has a flat surface, and the etching selectivity ratio of the flow material layer to the isolation material layer is 1.2:1 to 1:1.2;
[0043] S5. Use a dry etching process to remove the isolation material layer on the surface of the substrate to form the isolation material layer only in the trench.
[0044] The preparation method of the semiconductor device isolation trench structure of the present embodiment adopts a flowable material with fluidity to fill the isolation material layer. Based on the fluidity of the material layer, the isolation material layer with an uneven surface (i.e., bump) can be filled during the formation process and the surface of the flowable material layer can be made flat. Then, the isolation material layer with a flat surface can be obtained by dry etching the flowable material layer and the isolation material layer with a similar etching selectivity ratio. Then, the isolation material layer on the surface of the substrate is selectively removed by dry etching, so that the isolation material layer formed only in the trench can be obtained, thereby realizing the preparation of the isolation trench structure. The process method utilizes the flow characteristics of the flowable material layer and does not require CMP flattening and an etching barrier layer for endpoint detection, thereby effectively reducing the process complexity, improving production efficiency and reducing costs. At the same time, it avoids impurity particles caused by the deposition and removal of the etching barrier layer, thereby effectively improving the product yield.
[0045] The method for preparing the isolation trench structure of the semiconductor device of this embodiment is described in detail below with reference to the specific drawings.
[0046] like Figure 7 As shown, step S1 is first performed to provide a substrate 10 and etch the substrate 10 to form a trench 16 in the substrate 10 .
[0047] The material of the substrate 10 is selected according to the device structure to be prepared, and can be a semiconductor material, an insulating material, a conductor material or any combination thereof; it can be a single-layer structure or a stacked-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. In this embodiment, a commonly used silicon substrate or silicon-based substrate is selected.
[0048] As an example, a pad oxide layer 11 is formed on the surface of the substrate to protect the substrate when etching the groove 16 and subsequently etching the isolation material layer, and can be formed by a thermal oxidation process, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer chemical vapor deposition (ALCVD) process. In this embodiment, the pad oxide layer 11 is selected as a silicon dioxide layer.
[0049] As an example, the method for forming the groove 16 includes: coating a photoresist layer on the substrate 10, and when a pad oxide layer 11 is formed on the substrate 10, coating the photoresist layer on the pad oxide layer 11; patterning the photoresist layer to form a patterned photoresist layer, the patterned photoresist layer having a window that can define the position of the groove; etching the substrate 10 based on the patterned photoresist layer to form the groove 16. It should be noted here that the number, formation position, depth and other parameters of the groove 16 are selected according to the specific device needs, and no excessive restrictions are made here.
[0050] The method for preparing the semiconductor device isolation trench structure of the present embodiment can be used to prepare an isolation trench structure in which a groove needs to be formed. As a preferred example, when it is necessary to prepare an isolation trench structure in which a groove needs to be formed, after forming the trench 16, a pad oxide layer can be first formed on the surface of the trench 16, and a subsequent isolation material layer is formed on the surface of the pad oxide layer.
[0051] like Figure 8 As shown, step S2 is then performed to form an isolation material layer 12 on the substrate 10 and in the groove 16, and the isolation material layer 12 at least fills the groove 16, and the surface of the isolation material layer 12 is uneven. The uneven surface of the isolation material layer 12 is based on the different sparseness and density of the underlying material and the objective phenomenon existing in the existing deposition process.
[0052] The isolation material layer 12 can be formed by conventional chemical vapor deposition processes, such as high density plasma chemical vapor deposition (HDPCVD) or high aspect ratio process (HARP). The isolation material layer 12 can be made of any dielectric material suitable for isolating the active region of the substrate, such as silicon dioxide. Generally, the isolation material layer 12 needs to be prepared to be relatively thick to ensure that the trench 16 is completely filled.
[0053] like Fig. 9 As shown, step S3 is then performed to form a flowable material layer 13 with fluidity on the surface of the isolation material layer 12. Since the flowable material layer 13 has good fluidity, the flowable material layer 13 can fill the uneven surface of the isolation material layer 12 and make the surface of the flowable material layer 13 flat.
[0054] Based on the fluidity of the material of the flowable material layer 13, the unevenness (ie, bumps) on the surface of the isolation material layer 12 can be filled and leveled while ensuring the flatness of the surface, thereby obtaining a flowable material layer 13 with a flat surface.
[0055] As a preferred example, the flow material layer 13 is formed by a spin coating process. Other suitable coating processes may also be used to form the flow material layer 13.
[0056] The material of the flow material layer 13 is generally selected to have a certain fluidity and is suitable for use in semiconductor processes, such as materials in the spin coating process, SOC (spin on carbon) materials or SOD (spin on dielectric) materials or polysilazane, etc. Such materials have low cost, simple formation process, and high process compatibility. For example, when the flow material layer 13 is polysilazane, polysilazane can be decomposed into SiO under heating conditions. 2 Or silicon nitride; at this time, if the material of the isolation material layer 12 is also selected as SiO 2 When the SiO2 or Si3O2 is etched, the two materials are the same and have the same etching rate. However, since the flow material layer 13 adopts the spin coating process, the uneven area on the surface of the isolation material layer 12 can be filled, so that the generated SiO2 2 Has a flatter surface.
[0057] The minimum thickness requirement of the flow material layer 13 is to fill the unevenness of the surface of the isolation material layer 12. The specific thickness is set according to actual needs and the selected material, and no excessive restrictions are made here.
[0058] like Fig.10 As shown, step S4 is then performed, in which the flow material layer 13 and the isolation material layer 12 of a preset thickness are removed by a dry etching process, so that the remaining isolation material layer 12 has a flat surface, and the etching selectivity ratio of the flow material layer 13 to the isolation material layer 12 is 1.2:1 to 1:1.2.
[0059] This step is implemented based on the fact that the material of the flow material layer is generally an organic polymer material that is easy to etch, and it is easy to select a suitable etching material so that the etching has a close or even the same etching selectivity ratio for the flow material layer and the isolation material layer, so that in the etching process of this step, the etching of the flow material layer 13 and the isolation material layer 12 is performed at a substantially same etching rate, that is, 1.2:1 to 1:1.2 selected in this embodiment, for example, it can be 1.2:1, 1.1:1, 1:1, 1:1.1, 1:1.2, and of course, the best etching selectivity ratio for the flow material layer 13 and the isolation material layer 12 is 1:1. For example, when the material of the flow material layer 13 is selected as SOC material and the material of the isolation material layer 12 is selected as silicon dioxide, the etching gas source selected for dry etching includes H 2 or C x H y F z .
[0060] In this step, the dry etching process is used to remove the flow material layer 13 and the isolation material layer 12 of a preset thickness. This can be achieved by controlling the etching time; it can also be achieved by monitoring the composition of the final etching product, for example, by monitoring whether the final etching product contains the final product after etching the flow material layer 13. Since the etching rates of the flow material layer 13 and the isolation material layer 12 are basically the same, when the final etching product does not contain the final product after etching the flow material layer 13, it can be understood that the surface of the remaining isolation material layer 12 is already flat. This control method can make the thickness of the remaining isolation material layer 12 thicker, but the thickness of the remaining isolation material layer 12 is not easy to adjust; and by controlling the etching time, the thickness of the remaining isolation material layer 12 can be adjusted according to the length of the etching time.
[0061] It should be noted here that after removing the flow material layer 13 and the isolation material layer 12 of preset thickness in this step, a certain thickness of the isolation material layer 12 will remain on the substrate 10 to avoid damage to the substrate when etching stops on the surface of the substrate 10.
[0062] like Fig.11 and Fig.12 As shown, step S5 is finally performed to selectively remove the isolation material layer 12 on the surface of the substrate 10 to form the isolation material layer 12 only in the trench 16 .
[0063] The isolation material layer 12 on the surface of the substrate 10 can be selectively removed by a dry etching process or a wet etching process. In principle, the isolation material layer 12 is selectively etched with a high etching selectivity ratio to the substrate 10, so that the etching of the isolation material layer 12 will not damage the substrate 10. For example, the isolation material layer 12 on the surface of the substrate 10 can be selectively removed by a dry etching process, and an etching gas with a high selective etching ratio to the substrate 10 is selected for etching. For example, when the material of the substrate 10 is silicon and the material of the isolation material layer 12 is silicon dioxide, the etching gas source of the dry etching process includes CHF 3 The etching gas can achieve etching of silicon dioxide without etching silicon. Further, selective removal of the isolation material layer 12 on the surface of the substrate 10 by dry etching can be achieved by controlling the etching time. For example, the height of the isolation material layer 12 remaining in the groove 16 can be controlled by controlling the etching time. Fig.11 As shown, the etching time is controlled to be short, so that the isolation material layer 12 can fill the trench 16, that is, the surface of the isolation material layer 12 in the trench 16 is flush with the surface of the substrate 10; Fig.12 As shown, the etching time is controlled to be longer, so that the isolation material layer 12 remaining in the groove 16 is thinner, and a groove 14 is formed on the upper part of the groove 16, that is, the surface of the isolation material layer 12 in the groove 16 is lower than the preset depth of the surface of the substrate 10. The depth of the groove 14 can be set according to actual needs, and the groove 14 can be used to implement subsequent process.
[0064] In summary, the present invention provides a method for preparing an isolation groove structure of a semiconductor device, wherein a flowable material with fluidity is used to fill the isolation material layer. Based on the fluidity of the material layer, an isolation material layer with an uneven surface (i.e., a bump) can be filled during the formation process and the surface of the flowable material layer can be made flat. Then, a flat isolation material layer can be obtained by dry etching the flowable material layer and the isolation material layer with a similar etching selectivity ratio. Then, the isolation material layer on the surface of the substrate is selectively removed by dry etching, so that an isolation material layer formed only in the groove can be obtained, thereby realizing the preparation of the isolation groove structure. The process method utilizes the flow characteristics of the flowable material layer and does not require CMP flattening and an etch barrier layer for endpoint detection, thereby effectively reducing process complexity, improving production efficiency and reducing costs. At the same time, it avoids impurity particles caused by the deposition and removal of the etch barrier layer, thereby effectively improving the product yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0065] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor device isolation trench structure, It is characterized in that The preparation method comprises the following steps: Providing a substrate, and etching the substrate to form a trench in the substrate; forming an isolation material layer on the substrate and in the trench, wherein the isolation material layer at least fills the trench, and the surface of the isolation material layer is uneven; forming a flowable material layer having flowability on the surface of the isolation material layer; The surface of the flowing material layer filling the insulating material layer is uneven; Using a dry etching process to remove the flow material layer and the isolation material layer of a preset thickness, so that the remaining isolation material layer has a flat surface, and the etching selectivity ratio of the flow material layer to the isolation material layer is 1.2:1 to 1:1.2; The isolation material layer on the surface of the substrate is selectively etched away to form the isolation material layer only in the trench.
2. The method for preparing the semiconductor device isolation trench structure according to claim 1, Features: The isolation material layer on the surface of the substrate is removed by adopting a dry etching process and controlling the etching time, so as to form the isolation material layer only in the trench.
3. The method for preparing a semiconductor device isolation trench structure according to any one of claims 1 or 2, Features: The surface of the isolation material layer in the trench is flush with the substrate surface, or the surface of the isolation material layer in the trench is lower than the substrate surface by a preset depth.
4. The method for preparing the semiconductor device isolation trench structure according to claim 3, Features: When the surface of the isolation material layer in the trench is lower than the substrate surface by a preset depth, a pad oxide layer is formed between the trench surface and the isolation material layer.
5. The method for preparing the semiconductor device isolation trench structure according to claim 1, Features: The material of the flow material layer is SOC material, SOD material or polysilazane.
6. The method for preparing the semiconductor device isolation trench structure according to claim 1, Features: The material of the isolation material layer is silicon dioxide.
7. The method for preparing the semiconductor device isolation trench structure according to claim 6, Features: The material of the flow material layer is SOC material; in the step of removing the flow material layer and the isolation material layer of a preset thickness by a dry etching process, the etching gas source of the dry etching process includes H 2 or C x H y F z .
8. The method for preparing the semiconductor device isolation trench structure according to claim 6, Features: The substrate material is silicon, and in the step of removing the isolation material layer on the substrate surface by dry etching, the etching gas source of the dry etching process includes CHF 3 .
9. The method for preparing a semiconductor device isolation trench structure according to any one of claims 1 or 5, Features: The flow material layer is formed by a spin coating process.
10. The method for preparing the semiconductor device isolation trench structure according to claim 1, Features: The flow material layer and the isolation material layer with a preset thickness are removed by adopting a dry etching process and controlling the etching time or monitoring the composition of the final etching product.