Package substrate and manufacturing method thereof

Abstract

Embodiments relate to a package substrate and a method of manufacturing the same. A package substrate according to an embodiment includes a core layer including a glass core having a first surface and a second surface facing each other, a cavity portion, a surface recessed to be open in a direction toward the first surface, and provided with an internal space, and a plurality of core through-holes penetrating the glass core in a thickness direction; the glass core comprises a structure formed by combining first glass and second glass which are stacked up and down, a bonding interface is configured between the first glass and the second glass, and the taper angle of the cavity part can be 86-90 degrees.

Description

Technical Field

[0001] The embodiments relate to a packaging substrate, a semiconductor package, a method for manufacturing the packaging substrate, a method for manufacturing the semiconductor package, and the like. Background Art

[0002] When manufacturing electronic components, the process of realizing circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers into a state that can be used in actual products is called the back-end process (BE). The back-end process includes the packaging process.

[0003] Recently, the four core technologies of the semiconductor industry that enable the rapid development of electronic products include semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology.

[0004] Semiconductor technology is developing in various forms, such as line widths of nanometers below micrometers, more than 10 million cells, high-speed operation, and high heat dissipation. However, there is a lack of technical support for perfect packaging.

[0005] Therefore, the electrical performance of a semiconductor is more determined by the packaging technology and its electrical connections than the performance of the semiconductor technology itself.

[0006] As the material of the package substrate, ceramic or resin is used. For ceramic substrates such as silicone substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or high dielectric constant. For resin substrates, relatively high-performance, high-frequency semiconductor devices can be mounted. However, there are limitations on reducing the wiring pitch.

[0007] Recently, silicone substrates or glass substrates can be used as high-end packaging substrates. Through holes are formed on silicone substrates or glass substrates, and conductive substances are applied to the through holes to shorten the wiring length between the device and the motherboard, and excellent electrical characteristics can be achieved.

[0008] Relevant prior arts include Chinese Patent Publication CN114171491 A, European Patent Publication EP4152365A2, etc. Summary of the invention

[0009] Problem that the invention aims to solve

[0010] An object of the embodiment is to provide a method for manufacturing a packaging substrate and a packaging substrate using the same. The packaging substrate is a packaging substrate using a glass core, and the packaging substrate includes a glass core generated by bonding two or more glasses through an anodic bonding process.

[0011] In addition, an embodiment aims to provide a method for manufacturing a device packaging substrate and a packaging substrate using the same, wherein the device packaging substrate includes a glass substrate having a core through hole formed thereon, wherein the glass substrate is formed by bonding two or more sheets of glass through an anodic bonding process, and has a core through hole having an inflection point that changes the side angle when observed from a cross-section.

[0012] Means used to solve problems

[0013] To achieve the objective, one embodiment relates to a packaging substrate and a method for manufacturing the packaging substrate.

[0014] According to one or more embodiments, a packaging substrate includes a core layer; the core layer includes: a glass core having a first surface and a second surface facing each other, a cavity portion, the surface of which is recessed to be open toward the first surface and is provided with an internal space, and a plurality of core through holes penetrating the glass core along the thickness direction; and the glass core includes a structure in which a first glass and a second glass are stacked up and down.

[0015] A bonding interface is configured between the first glass and the second glass.

[0016] The taper angle of the cavity may be 86 degrees to 90 degrees.

[0017] The core through hole includes: a first opening portion, which is connected to the first surface when each core through hole is observed from a cross-section; a second opening portion, which is connected to the second surface; a side line, which connects the first opening portion and the second opening portion along the inner diameter surface of each core through hole; and an inflection point, which is a point on the side line where the angle changes.

[0018] An inflection point of the core through hole may be located at the location of the bonding interface.

[0019] The side line may have more than one or more than three inflection points.

[0020] The cavity core through hole is a core through hole arranged in the cavity portion.

[0021] The cavity core through hole includes: a first opening portion, which is connected to the bottom surface of the cavity portion when each cavity core through hole is observed from a cross section; a second opening portion, which is connected to the second surface; a side line, which connects the first opening portion and the second opening portion along the inner diameter surface of each core through hole; and an inflection point, which is a point where the side line bends at a certain angle.

[0022] One or more inflection points may be arranged on the side surface line of the cavity core through hole.

[0023] The bonding interface may be an anodic bonding interface.

[0024] The glass core may have a thickness of 500 μm or more.

[0025] The cavity is disposed in the first glass, and the cavity may correspond to a recessed surface or a penetrating portion of the first glass.

[0026] Electronic devices may be arranged in the inner space of the cavity.

[0027] A device module obtained by modularizing one or more electronic devices may be disposed in the internal space of the cavity.

[0028] According to one or more embodiments, the manufacturing method of the packaging substrate includes: a preparation step of preparing a first glass and a second glass, wherein the first glass has a recessed surface or a through portion, and the second glass has a plurality of core through holes; and a bonding step of aligning the first glass and the second glass and bonding them through an anodic bonding process to generate a glass core.

[0029] The core layer and its constituent elements have the above-mentioned characteristics.

[0030] The method for manufacturing the package substrate may further include: a wiring step, and after the bonding step, forming a redistribution layer on the first surface or the second surface.

[0031] The method for manufacturing the packaging substrate may further include: a device inserting step, after the bonding step, configuring the device in the cavity.

[0032] Effects of the Invention

[0033] The manufacturing method of the packaging substrate of the embodiment and the packaging substrate using the same form a concave tapered zone at the edge of the cavity to gradually narrow the interval along the thickness direction, thereby maintaining the device margin and facilitating the pick and place tolerance of the electronic devices arranged in this way. At the same time, since the space in which the electronic devices can move after the pick and place process is small, the problem of the electronic devices deviating from the specified arrangement position can be prevented.

[0034] In addition, the method for manufacturing a package substrate and the package substrate using the same according to the embodiment can achieve the effect of reducing back cracks (seware), a defect occurring during the manufacturing process of a multi-layer redistribution layer (RDL), by generating a thick glass core.

[0035] In addition, the manufacturing method of the packaging substrate of the embodiment and the packaging substrate using the same can more easily manufacture a glass core with a semi-cavity and enhance the bonding force between glasses so as to prevent the problem of glass delamination of the glass core formed in multiple high-temperature processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a package substrate according to an embodiment.

[0037] Figure 2 is a conceptual diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0038] Figure 3 Parts (a) and (b) of FIG. 1 are conceptual diagrams each illustrating a portion of a package substrate according to an embodiment in cross section.

[0039] Figure 4 is a flow chart illustrating, using cross sections, a process of generating a core distribution layer in a process of manufacturing a package substrate according to an embodiment.

[0040] Figure 5 FIG. 1 is a flow chart for explaining, using cross sections, a process of generating an insulating layer in a process of manufacturing a package substrate according to an embodiment.

[0041] Figure 6 FIG. 4 is a diagram illustrating, using cross sections, a process of producing a glass core having a semi-cavity according to an embodiment.

[0042] 7A to 7C is a conceptual diagram illustrating, in cross section, a core layer including a glass core having a semi-cavity generated according to an embodiment.

[0043] Figure 8 The application is illustrated by cross section. Figure 7B Conceptual diagram of a glass core packaging substrate.

[0044] Description of Reference Numerals

[0045] 100: Semiconductor device 10: Motherboard

[0046] 30: Semiconductor device section 32: First device

[0047] 34: Second device 36: Third device

[0048] 20: Package substrate 21, 21a: Glass core

[0049] 22: core layer 223: core insulation layer

[0050] 26: Upper layer 28: Cavity

[0051] 213: First surface 214: Second surface

[0052] 23: Core through hole 24: Core distribution layer

[0053] 241: Core distribution pattern

[0054] 25: Upper distribution layer 251: Upper distribution pattern

[0055] 253: Upper insulation layer

[0056] 27: Upper surface connection layer 271: Upper surface connection electrode

[0057] 272: Upper surface connection pattern 28: Cavity

[0058] 281: Internal space 282: Cavity distribution layer

[0059] 40: Electronic device 50: Connecting part

[0060] 51: Device connection part 52: Board connection part

[0061] 61: First glass 62: Second glass

[0062] 71: Turning point DETAILED DESCRIPTION

[0063] In order to help the comprehensive understanding of the method, device and / or system described in this specification, the following detailed description will be provided. However, various changes, modifications and equivalents of the method, device and / or system described in this specification will become clear after understanding the content proposed in this application. For example, the operating process described in this specification is only an example and is not limited to the operation recorded in this specification. Except for the steps that must be performed in a certain order, the operating process can be changed according to the understanding of the content proposed in this application. In addition, after understanding the disclosure of the application, the description of known features can be omitted to improve clarity and conciseness. However, the omission of its features and their description is not meant to be considered as general knowledge.

[0064] The features described in this specification may be implemented in different forms and should not be construed as being limited to the examples described in this specification. Rather, the embodiments described in this specification are intended to illustrate some of the many possible implementations of the methods, devices, and / or systems described in this specification that will become clear after understanding the disclosure of this application.

[0065] In this specification, the terms "first", "second", "third", etc. may be used to describe various components, constituent elements, fields, layers or sections, but these components, constituent elements, fields, layers or sections are not limited to these words. On the contrary, these terms are used to distinguish one component, constituent element, field, layer or section from another component, constituent element, field, layer or section. Therefore, the first component, constituent element, field, layer or section mentioned in the embodiments recorded in this specification may also be referred to as the second component, constituent element, field, layer or section without departing from the teachings of the embodiments.

[0066] Throughout the specification, when an element such as a layer, a field or a substrate is described as being "on", "connected to" or "coupled to" another element, it may be described as being directly "on" or "connected to" another element, or one or more other elements may be interposed between them. Conversely, when an element is described as being "directly on", "directly connected to" or "directly coupled to", no other elements may be interposed between them. Similarly, for example, expressions such as "wherein" and "directly between" and "adjacent" and "directly in contact with" may also be interpreted as described above.

[0067] The terms used in this specification are only used to illustrate specific examples and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the form of a single quantity used in this specification is also intended to include the form of multiple quantities. The term "and / or" in this specification includes all combinations of any one or more of the relevant enumerated items. The terms "including", "consisting of..." and "reserved" used in this specification clarify the existence of features, numbers, actions, elements, constituent elements and / or their combinations, but do not exclude the existence or addition of more than one other features, numbers, actions, elements, constituent elements and / or their combinations. In this specification, with respect to examples or embodiments (for example, what examples or embodiments may include or implement), the use of the word "may" means that there are at least examples or embodiments that include or implement these features, but not all examples are limited to this.

[0068] In the present application, “B is located on A” means that B is in direct contact with A, or other layers or structures are interposed therebetween and configured on A, and therefore should not be interpreted as B being in direct contact with A.

[0069] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of the ordinary skills in the technical field to which the present invention belongs. Terms such as terms defined in commonly used dictionaries should be interpreted as having the same meaning as those in the prior art and the context of the present invention, and should not be interpreted as idealized or overly formalized unless explicitly defined herein.

[0070] In the one or more examples, "A and / or B" means "A, B, or A and B."

[0071] In more than one of the above examples, terms such as "first," "second," "A," or "B" are used to distinguish the same terms from each other.

[0072] In the above-mentioned one or more examples, unless otherwise specified, a single quantity form includes not only a single quantity form but also a plural quantity form.

[0073] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a package substrate according to an embodiment, Figure 2 A conceptual diagram illustrating a structure of a package substrate according to another embodiment in cross section is shown. Figure 3 Parts (a) and (b) of FIG. 1 are conceptual diagrams each illustrating a portion of a package substrate according to an embodiment in cross section.

[0074] In order to achieve the stated purpose, the semiconductor device 100 according to the embodiment includes: a semiconductor device portion 30, in which one or more semiconductor devices (a first device 32, a second device 34, a third device 36) are located; a packaging substrate 20, which is electrically connected to the semiconductor device; and a motherboard 10, which is electrically connected to the packaging substrate 20 and transmits electrical signals between the semiconductor device (the first device 32, the second device 34, the third device 36) and the outside, and connects them to each other.

[0075] The package substrate 20 according to an embodiment includes: a core layer 22 ; an upper layer 26 located on one surface of the core layer 22 ; and a cavity 28 in which an electronic device 40 may be located.

[0076] The semiconductor device section 30 refers to a device installed in a semiconductor device, and is installed on the package substrate 20 through connection electrodes, etc. Specifically, for example, a computing element (first device 32, second device 34) of a central processing unit (CPU), a graphics processing unit (GPU), etc., a storage element (third device 36) of a memory chip, etc., etc. can be used as the semiconductor device section 30, but as long as it is a semiconductor device installed in a semiconductor device, it can be used without limitation.

[0077] The motherboard 10 may be a motherboard of a printed circuit board, a printed wiring board, etc.

[0078] Optionally, the package substrate 20 may further include a lower layer (not shown) located below the core layer.

[0079] The core layer 22 may include: a glass core 21, including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 thinner than the first thickness; a plurality of core through holes 23, penetrating the glass core 21 along the thickness direction; and a core distribution layer 24, located on the surface of the glass core 21 or the core through holes 23, and electrically connecting the first surface 213 of the glass core 21 and the second surface 214 facing the first surface through the core through holes 23.

[0080] The second region 222 of the core layer 22 may function as a cavity structure.

[0081] In the same region, the glass core 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are substantially parallel to each other, so that the glass core 21 has a constant thickness as a whole.

[0082] The inner space 281 formed due to the thickness difference between the first region 221 and the second region 222 serves to accommodate a part or all of the electronic device 40 .

[0083] The glass core 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through hole 23 may be formed in both the first region 221 and the second region 222, and may be formed at a desired pitch and pattern.

[0084] In the past, a stack of silicone substrates and organic substrates was used as a packaging substrate for semiconductor devices. As for silicone substrates, due to the characteristics of semiconductors, there is a risk of generating parasitic elements when applied to high-speed circuits, and there is a disadvantage of relatively large power loss. In addition, as for organic substrates, it is necessary to enlarge the area to form a more complex distribution pattern, but this is inconsistent with the trend of ultra-miniaturization manufacturing of electronic instruments. In order to form a complex distribution pattern within a specified size, a fine pattern is actually required, but due to the characteristics of materials such as polymers used for organic substrates, fine patterns actually have limitations.

[0085] As a method for solving these problems, the glass core 21 is used as a support for the core layer 22 in the embodiment. In addition, a package substrate 20 is provided, which further shortens the current length by using a core through hole 23 formed by penetrating the glass core 21 together with the glass core 21, and has the characteristics of more miniaturization, faster response, and less loss.

[0086] The glass core 21 is preferably a glass substrate used in semiconductors, such as a borosilicate glass substrate, an alkali-free glass substrate, etc., but is not limited thereto.

[0087] The core through hole 23 passes through the glass core 21. The core through hole 23 may be formed by removing a predetermined region of the glass core 21, and specifically, may be formed by etching a plate-shaped glass by a physical and / or chemical method.

[0088] Specifically, the core through hole 23 may be formed by forming a defect (flaw) on the surface of the glass core by laser or the like, and then performing laser etching or the like by chemical etching, but the present invention is not limited thereto.

[0089] Based on the unit area (1 cm×1 cm) of the glass core 21, the number of the core through holes 23 may be 100 to 3000, 100 to 2500, or 225 to 1024. When such pitch conditions are met, the formation of the conductive layer and the performance of the packaging substrate may be improved.

[0090] The core distribution layer 24 includes: a core distribution pattern 241, which is a conductive layer that electrically connects the first surface and the second surface of the glass core through a through hole; and a core insulation layer 223, surrounding the core distribution pattern. The core layer 22 has a conductive layer formed inside it through the core through hole, which serves as an electrical channel that penetrates the glass core 21 and connects the upper and lower parts of the glass core at a shorter distance, thereby having the characteristics of faster transmission of electrical signals and low loss. The conductive layer can be, for example, a copper plating layer, but is not limited thereto.

[0091] The shape of the cavity 28 is basically not limited, and may be, for example, circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc.

[0092] The shape of the electronic device 40 can be roughly cylindrical, rectangular or polygonal.

[0093] The cavity portion 28 may include: a cavity distribution pattern which is a conductive layer electrically connecting the electronic device 40 and the core distribution layer 24 ; and an insulating layer surrounding the cavity distribution pattern.

[0094] On the other hand, the cavity according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity may be formed according to the same process as the core through hole 23, and the area and shape of the penetrating glass core 21 may be different from the core through hole 23.

[0095] In these embodiments, the insulating layer may be formed after the electronic device 40 is arranged in the cavity. That is, the insulating layer may be formed in the cavity through the above-mentioned process of forming the core insulating layer 223 .

[0096] The core distribution pattern 241 may be patterned so as to be electrically connected to the electronic device 40 .

[0097] The electronic device 40 may include an active device such as a transistor or a power transmission device such as a multi-layer ceramic capacitor (MLCC), that is, may include a passive device.

[0098] When a device such as a transistor that converts an electrical signal between a motherboard and a semiconductor device portion into an appropriate level is used as the electronic device 40, the transistor or the like is applied to the junction of the package substrate 20, thereby providing a semiconductor apparatus 100 with higher efficiency and higher speed.

[0099] In addition, power transmission devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. There are more than 200 power transmission devices that are passive devices commonly used in semiconductor devices. When transmitting power, their performance is also affected by the characteristics of the conductive layer around the device. In one embodiment, a non-circular core via can be applied where a low-resistance conductive layer is required, such as this power transmission device.

[0100] On the other hand, the electronic device 40 can be applied in the form of a passive device such as a capacitor inserted alone, or can be formed into a device group including a plurality of passive devices in the form of being embedded between insulator layers (electronic device insulating layers) so that the electrodes are exposed and then inserted into the electronic device. In the latter case, the manufacturing workability of the package substrate can be improved more smoothly, and it is more conducive to ensuring that the insulating layer is fully and reliably located in the space between complex devices.

[0101] The glass core 21 serves as an intermediate member and a medium for connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core through hole 23 serves as a channel for transmitting electrical signals to ensure smooth signal transmission. In order to distinguish it from the core through hole in the second area 222 described later, the core through hole arranged in the first area 221 is referred to as the first area core through hole 231.

[0102] The upper layer 26 is located on the first surface 213 .

[0103] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25. The uppermost surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein and directly connected to the connection electrode of the semiconductor device.

[0104] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251 having a predetermined pattern and being a conductive layer at least partially electrically connected to the core distribution layer 24, and built into the upper insulation layer 253. A plurality of upper distribution layers 25 arranged one above the other may be connected to each other through blind vias.

[0105] The upper insulating layer 253 can be any material that can be used as an insulating layer in a semiconductor device or a package substrate. For example, epoxy resin containing a filler can be used, but the invention is not limited thereto.

[0106] The insulator layer may be formed by forming a coating layer and curing it, or by laminating an insulator film (made in an uncured or semi-cured state) on the core layer 22 and curing it. At this time, if a reduced pressure lamination method or the like is applied, the insulator is recessed into the inner space of the core through hole 23, so that the process can be performed efficiently.

[0107] According to an embodiment, even if multiple insulator layers are stacked and applied, it may be difficult to distinguish between the insulator layers in practice, and the multiple insulator layers are collectively referred to as the upper insulating layer. In addition, the core insulating layer 223 and the upper insulating layer 253 may adopt the same insulating material, and in this case, the boundary is basically indistinguishable. Alternatively, according to another embodiment, the pressure and temperature of curing the multiple insulator layers may also be set differently, so that the boundary of the insulator layer can be generated.

[0108] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a preset shape, and can be formed, for example, in the form of a build-up layer. Specifically, after forming the insulator layer, the unnecessary part of the insulator layer is removed, and then the conductive layer is formed by copper plating or the like, and the unnecessary part of the conductive layer is optionally removed, and then the insulator layer is formed again on the conductive layer, and the unnecessary part is removed again, and then the conductive layer is formed by electroplating or the like, and the above method is repeated, so that the upper distribution pattern 251 of the conductive layer formed in the vertical or horizontal direction can be formed in a desired pattern.

[0109] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor device portion 30, it can be formed to include a fine pattern at least in a portion thereof, so that the transmission of electrical signals with the semiconductor device portion 30 is smooth and the desired complex pattern can be fully accommodated. At this time, the fine pattern can have a width and spacing of less than 4 μm, less than 3.5 μm, less than 3 μm, less than 2.5 μm, or less than 2.3 μm, respectively. The width and spacing can be more than 1 μm (hereinafter, the description of the fine pattern is the same).

[0110] The upper surface connection layer 27 includes: an upper surface connection pattern 272 , at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253 ; and an upper surface connection electrode 271 , which electrically connects the semiconductor device portion 30 and the upper surface connection pattern 272 .

[0111] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded therein in a manner that at least a portion of the upper surface connection pattern 272 is exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and when the upper surface connection pattern is embedded therein in a manner that a portion of the upper surface connection pattern is exposed on the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or the conductive layer may be removed by surface grinding, surface etching or the like.

[0112] As with the upper distribution pattern 251, the upper surface connection pattern 272 may include a fine pattern in at least a portion thereof. The upper surface connection pattern 272 including such a fine pattern can electrically connect a greater number of devices even in a narrow area, thereby making the electrical signal connection between devices or with the outside smoother and realizing a more integrated package.

[0113] The upper surface connection electrode 271 may be directly connected to the semiconductor device portion 30 through a terminal or the like, or may be connected through a device connection portion 51 such as a solder ball.

[0114] The cavity portion 28 includes: a cavity distribution layer 282 located above and / or below the second region 222 and electrically connected to the core distribution pattern 241 ; and an inner space 281 in which the electronic device 40 is located.

[0115] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the electronic device 40 may be located in the inner space 281 formed by the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass core 21 serve as an electrical connection structure for connecting the electronic device 40 and external devices.

[0116] In addition, as described above, a cavity having a form of penetrating the first region 221 instead of the second region 222 , that is, penetrating the first surface 213 and the second surface 214 of the glass core 1 may be generated, and the electronic device 40 may be arranged in the cavity.

[0117] The package substrate 20 is also connected to the motherboard 10. With respect to the motherboard 10, the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 may be directly connected to the terminal of the motherboard 10, or may be electrically connected via a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 connected to the motherboard 10 may also be connected to the motherboard 10 via a lower layer (not shown) located at the lower portion of the core layer 22.

[0118] According to an example, on the package substrate 20 located between the semiconductor device portion 30 and the motherboard 10 , except for the glass core 21 , substantially no other substrate may be used additionally.

[0119] In the past, an interposer and an organic substrate were stacked together between the device and the motherboard. It is understood that there are at least two reasons for using this multi-stage format. One is that there are scale issues when directly bonding the fine pattern of the device to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, wiring damage caused by the difference in thermal expansion coefficient may occur.

[0120] In the embodiment, a glass core having a thermal expansion coefficient similar to that of a semiconductor device is used, and a fine pattern having a fine scale sufficient for device mounting is formed on the first surface of the glass core and the upper layer thereof to solve this problem.

[0121] Hereinafter, a method of manufacturing a package substrate according to an embodiment of the present invention will be described.

[0122] Figure 4 and Figure 5 FIG. 1 is a flowchart illustrating a manufacturing process of a package substrate according to an embodiment using cross sections.

[0123] First, if Figure 4 As shown in part (a), a glass core 21a having a flat first surface and a flat second surface is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position in order to form a core through hole. The glass may use a glass core used for a substrate of an electronic device, for example, an alkali-free glass core, but is not limited thereto. As commercially available products, products manufactured by manufacturers such as Corning, SCHOTT, and AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or the like.

[0124] like Figure 4As shown in part (b) of FIG. 1 , the glass core 21a having the defect (groove) 21b is subjected to an etching step to form a core through hole 23 by a physical or chemical etching process. During the etching process, a through hole is formed in the defective portion of the glass core, and at the same time, the surface of the glass core 21a may also be etched. In order to prevent such etching of the glass surface, a mask or the like may be used, but considering the tediousness of using and removing the mask, etc., the glass core itself having the defect may be etched, and in this case, the thickness of the glass core having the core through hole may be slightly thinner than the thickness of the initial glass core.

[0125] Then, if Figure 4 As shown in parts (c) and (d) of FIG. 1 , a core layer manufacturing step can be performed by forming a conductive layer 21d on the glass core. The conductive layer can generally use a metal layer including copper metal, but is not limited thereto.

[0126] The surface of the glass (including the surface of the glass core and the surface of the core through hole) and the surface of the copper metal have different properties, so their adhesion is low. In the embodiment, the adhesion between the glass surface and the metal can be improved by both dry and wet methods.

[0127] The dry method refers to a method of using sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. In the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel can be sputtered together with copper, etc., and in this case, the glass-metal adhesion can be improved through the surface morphology of the glass and the anchoring effect of the interaction between the metal particles.

[0128] Wet type refers to the mode of primer treatment, which is the mode of pre-treatment with chemical substances having functional groups such as amine to form primer layer 21c. According to the degree of desired adhesion, after pre-treatment with silane coupling agent, primer treatment can be performed by compounds or particles having amine functional groups. As mentioned above, the support substrate of the embodiment needs to be high-performance enough to form fine patterns, and the performance should also be maintained after primer treatment. Therefore, when this primer contains nanoparticles, it is preferred to use nanoparticles with an average diameter of less than 150nm, for example, nanoparticles are preferably used for particles with amine groups. Exemplarily, the primer layer can be formed using a bonding force modifier manufactured by the CZ series of Japan MEC Company, etc.

[0129] In the seed layer / primer layer 21c, a metal layer can be selectively formed through a conductive layer in a state where a portion where a conductive layer is not required to be formed is removed, or in a state where a portion where a conductive layer is not required to be formed is not removed. In addition, the seed layer / primer layer 21c selectively processes a portion where a conductive layer is required or not required to be formed into an activated state or an inactivated state for metal plating so that subsequent processes can be performed. For example, the activation or inactivation treatment can use a light irradiation treatment of a laser of a certain wavelength, a chemical treatment, etc. The formation of the metal layer can use a copper plating method applied to semiconductor device manufacturing, etc., but is not limited thereto.

[0130] like Figure 4 As shown in part (e), when a portion of the core distribution layer is not needed, it can be removed, and metal plating is performed after a portion of the seed layer is removed or non-activated to form a conductive layer according to a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0131] Figure 5 A manufacturing step of forming an insulating layer and an upper distribution pattern according to an embodiment is described.

[0132] like Figure 5 As shown in part (a), the core through hole can be formed by an insulating layer after the core distribution layer as the conductive layer is formed, and the empty space is filled with an insulating layer. At this time, the insulating layer used can be manufactured in the form of a film, for example, a method of performing reduced pressure lamination on the insulating layer in the form of a film, etc. When the reduced pressure lamination is performed in this way, the insulating layer can be fully recessed into the empty space inside the core through hole, so that a core insulating layer without forming a gap can be formed.

[0133] Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer manufacturing steps.

[0134] The upper layer manufacturing step is a step of forming an upper insulating layer and an upper distribution layer including an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition forming an insulating layer 23a or stacking insulating films. As a simple method, the method of stacking insulating films is preferred. The stacking of insulating films can be carried out by laminating and curing the insulating films. At this time, if a decompression lamination method is used, the insulating resin can be fully recessed into the layer where the conductive layer is not formed inside the core through hole, etc. At least a part of the upper insulating layer is directly connected to the glass core, so a layer with sufficient adhesion is used. Specifically, the glass core and the upper insulating layer preferably have a property that the adhesion test value according to ASTM D3359 meets 4B or above.

[0135] The upper distribution pattern can be formed by repeating the formation of the insulating layer 23a, forming the conductive layer 23c according to a predetermined pattern and etching the unnecessary part to form an etching layer 23d of the conductive layer. When the conductive layer is formed with an insulating layer in the middle and adjacent to each other, it can be formed by forming a blind through hole 23b in the insulating layer and then performing an electroplating process. The blind through hole can be formed by dry etching such as laser etching and plasma etching, wet etching using a mask layer and an etching solution, etc.

[0136] Thereafter, although not shown, an upper surface connection layer and a cover layer may be formed.

[0137] The upper surface connection pattern and the upper surface connection electrode can also be formed by a process similar to the formation of the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e and then forming a conductive layer thereon, and then forming an etching layer of the conductive layer, etc. However, it is also possible to use a method that selectively forms only the conductive layer without using an etching method. The covering layer can be formed to form an opening portion (not shown) at a position corresponding to the upper surface connection electrode to expose the upper surface connection electrode, and can be directly connected to the device connection portion or the terminal of the device, etc.

[0138] If the upper layer is generated, the lower surface connection layer and the covering layer can be formed to perform the lower layer process. The lower distribution layer and / or the lower surface connection layer can be formed in a similar manner to the above-mentioned upper surface connection layer and covering layer formation steps, and the covering layer (not shown) can be selectively formed.

[0139] On the other hand, as described above, the core layer may include a glass core, and the glass core may be a glass substrate having a first surface and a second surface facing each other. In addition, as described above, the glass core may include a cavity.

[0140] The cavity has a space for configuring an electric device, which is open and recessed toward the first surface or the second surface, or passes through the glass core; the cavity has an internal space for accommodating an electric device, which is open and recessed toward the first surface or the second surface of the glass core, or passes through the glass core.

[0141] A cavity having an inner space that is open and recessed toward the first surface or the second surface may be referred to as a half cavity, and a cavity having an inner space that penetrates the glass core may be referred to as a full cavity. Electronic devices may be arranged in the inner space of the cavity.

[0142] On the other hand, the following method is generally used to generate a glass core having a half-cavity. As an example, in the conventional manufacturing technology of the half-cavity, as a method of using a sheet of glass, a method of selectively irradiating energy onto the glass to generate the half-cavity may be used. In this case, a tapered zone with gradually narrowed intervals may be generated at the edge of the cavity, and the margin area may become wider. Therefore, the problem of reduced device space for mounting electronic devices in the cavity may occur.

[0143] In addition, as another example, in the conventional manufacturing technology of the semi-cavity, a method of bonding two sheets of glass together using an adhesive such as a polymer adhesive and then etching to generate the semi-cavity may be used. In this case, when the lamination process for forming the distribution layer is repeatedly performed on the glass core, the polymer adhesive has poor heat resistance and changes over time, which weakens the adhesive force of the polymer adhesive, and thus the problem of delamination of the glass forming the glass core may occur.

[0144] To this end, this specification proposes an embodiment of manufacturing a semi-cavity for solving the above-mentioned problems.

[0145] A method for manufacturing a package substrate including a core layer according to one or more embodiments includes: a preparation step of preparing a first glass and a second glass, wherein the first glass has a recessed surface or a through portion and a plurality of core through holes, and the second glass has a plurality of core through holes; and a bonding step of aligning the first glass and the second glass and bonding them through an anodic bonding process to generate a glass core.

[0146] After the bonding step, a wiring step may be further included to form a redistribution layer on the first surface or the second surface. The redistribution layer may be formed by the above method, but is not limited thereto. After the bonding step, a device insertion step may be further included to configure a device in the cavity.

[0147] For example, a sheet of glass having a full cavity and a plurality of core through holes penetrating the glass in the thickness direction and another sheet of glass having a plurality of core through holes penetrating in the thickness direction are prepared, and a glass core can be generated by aligning and bonding the first glass and the second glass. As needed, the glass can be aligned so that the plurality of core through holes can penetrate in the thickness direction of the glass core. Exemplarily, although the description is based on the sheet of glass having a full cavity, a glass having a half cavity formed on a whole sheet of glass before bonding can also be applied. In addition, a glass having a full cavity formed on a sheet of glass before bonding and a half cavity formed on another sheet of glass before bonding can also be applied.

[0148] Figure 6 FIG. 4 is a diagram illustrating, using cross sections, a process of producing a glass core having a semi-cavity according to an embodiment.

[0149] Reference Figure 6 In part (a), a first glass 61 is prepared, which has a cavity portion penetrating the first glass 61 and a plurality of core through holes. The first glass 61 having a cavity formed therein may be referred to as a cavity glass.

[0150] Reference Figure 6 In part (b), the second glass 62 is formed with a plurality of core through holes that penetrate the second glass 62. The second glass 62 may be glass without a cavity. In this case, the second glass 62 may be referred to as bare glass. Figure 6 Although not shown in the figure, according to an embodiment, the second glass may also be formed with a semi-cavity.

[0151] Next, refer to Figure 6 In part (c), after preparing the first glass 61 and the second glass, the first glass 61 and the second glass 62 may be aligned and bonded to generate a glass core 21. The glass core 21 may include: a semi-cavity that is open and recessed toward the first surface or the second surface; and a plurality of core through holes that penetrate the glass core 21 in the thickness direction. The bonding is preferably performed using an anodic bonding process. Anodic bonding will be described later.

[0152] The glass core 21 will be described in more detail.

[0153] For example, when viewed from a cross section, the side angle of the inner space of the cavity may be a specific angle based on the first surface or the second surface. For example, the specific angle may be 90 degrees (or 89 to 90 degrees). The side angle of the inner space of the cavity may have a tapered angle that gradually narrows along the thickness direction.

[0154] The internal space of the cavity portion may be arranged with electronic devices. The electronic device 40 may be inserted and arranged in the internal space of the cavity portion. For example, an adhesive (paste) such as a polyimide tape (PI) may or may not be attached to the bottom surface of the cavity portion, and the electronic device may be selected and disposed in the internal space of the cavity portion (designation of the position of the electronic device). Alternatively, a device group (including a plurality of electronic devices in a manner embedded between insulator layers (electronic device insulating layers)) is formed so that the electrodes are exposed and then inserted into the internal space of the cavity portion. The electronic device 40 may include an active device such as a transistor or a power transmission device such as a multi-layer ceramic capacitor (MLCC), that is, a passive device.

[0155] In addition, for example, the core through-hole may include: a first opening portion that abuts on the first surface of the glass core 21; a second opening portion that abuts on the second surface; and an inflection point where the angle of the side surface changes when observing the cross-section of the entire core through-hole connecting the first opening portion and the second opening portion. For example, the core through-hole may include: a first section where the angle of the side surface is a first angle based on the first surface or the second surface when observing the cross-section; a second section where the angle of the side surface is inclined by a second angle based on the first surface or the second surface when observing the cross-section; and an inflection point connecting the first section and the second section. In addition, for example, the core through-hole may include 4 or more than 6 inflection points, and the distance from the surface of the glass core (the first surface or the second surface) to the inflection point may not be limited. Alternatively, for example, the core through-hole may include 2 or more inflection points, and the distance from the surface of the glass core (the first surface or the second surface) to the inflection point may be 300 μm.

[0156] The first glass 61 and the second glass 62 may each independently use flat glass applied to semiconductor processes. In addition, preferably, the first glass 61 and the second glass 62 are each independently flat glass having the following characteristics.

[0157] The content of Na 2 O 3 in at least one of the first glass 61 and the second glass 62 may be 2.5 wt% or more, 3 wt% or more, or 3.5 wt% or more. In addition, the content of Na 2 O 3 in the glass may be 6 wt% or less. When glass having such a content of Na 2 O 3 is applied to at least one of the first glass 61 and the second glass 62, anodic bonding can be easily applied.

[0158] The maximum use temperature of the first glass 61 and the second glass 62 may be 240° C. or more, 250° C. or more, 260° C. or more, 280° C. or more, or 300° C. or more, respectively, and the maximum use temperature may be 600° C. or less, 580° C. or less, or 560° C. or less. In this case, sufficient heat resistance can be achieved during manufacturing and driving.

[0159] The first glass 61 and the second glass 62 are preferably glasses with substantially the same or slightly different linear thermal expansion coefficients α(°C) (unit: °C^-1). The linear thermal expansion coefficients may be 2.8*10^-6 to 4.5*10^-6 or 3*10^-6 to 4*10^-6.

[0160] The first glass 61 and the second glass 62 are preferably glass having excellent chemical resistance. Specifically, when immersed in a 10 wt % hydrofluoric acid solution at 23° C. for 20 minutes, the thickness per unit area (cm 2 ) can be 2 mg or less or 1.5 mg or less. Specifically, when immersed in a 5 wt % sodium hydroxide solution at 95°C for 6 hours, the weight loss per unit area (cm 2 ) may be less than 0.5 mg or less than 0.3 mg.

[0161] The thermal diffusivity of at least one of the first glass 61 and the second glass 62 may be 0.02 cm 2 / second or less, or 0.01cm 2 / sec or less. The thermal diffusivity may be 0.0001 cm 2 / When glass with low thermal diffusivity is used, it can facilitate smoother bonding and other processes.

[0162] For example, at least one of the first glass 61 and the second glass 62 may be Corning 7740 (Pyrex), Schott Glass Borofloat, etc., but is not limited thereto.

[0163] The thickness of the first glass 61 and the thickness of the second glass 62 may be 200 μm or more, 300 μm or more, 400 μm or more, or 500 μm or more, and may be 1000 μm or less.

[0164] In the glass core 21 generated by bonding the first glass 61 and the second glass 62 by an anodic bonding process, a bonding interface between the first glass 61 and the second glass 62 can be formed. By using an anodic bonding process, the bonding strength of the bonding interface is increased, and thus, delamination problems at the interface can be substantially prevented.

[0165] The anodic bonding process refers to a bonding process of sealing glasses without introducing an intermediate layer such as a polymer bonding composition between the glasses being bonded.

[0166] At the interface, molecular bonds of Si and O located in the first glass and the second glass are induced to generate a relatively strong interface bonding force, and even in repeated high-temperature processes that may be applied during the formation of the glass core or the packaging substrate, sufficient adhesion can be maintained and the reliability of the product can be basically maintained. Therefore, the problem of delamination of the glass of the glass core 21 at the interface can be basically prevented.

[0167] That is, the glass core 21 includes molecular bonds of Si and O at the interface between the first glass 61 and the second glass 62. This may be induced by the anodic bonding process.

[0168] The anodic bonding process is a process for bonding the stacked material interface using electricity, heat and pressure. The process can be performed using equipment such as SB-6E Bonder or EVG 520IS, but is not limited thereto. The anodic bonding process can be performed as follows. 1) The flattened and washed bonding object surfaces are configured to be in contact with each other. In an embodiment, a stacked body in which the first glass and the second glass are configured to be in contact is prepared. 2) The temperature of the stacked body is increased and a voltage is applied. Exemplarily, the temperature can be 180°C to 500°C, but can be adjusted according to the characteristics of the glass. In addition, the voltage can be 200V to 1000V. The voltage uses a DC voltage. At the temperature and voltage, the glass is activated, and charges such as sodium ions can be moved with the voltage. At this time, metal atoms (such as silicon) on the surface of other glasses and oxygen atoms in the activated glass meet each other so that atomic bonds can be formed, and a strong bonding effect can be obtained at the interface by forming a metal oxide. In addition, since a separate polymer adhesive layer is not used, there is virtually no possibility of problems such as particles in the semiconductor manufacturing process, and the metal oxide formed at the interface by anodic bonding basically overlaps with the constituent components of the glass, so through-hole formation in the etching step can also be easily applied to conventional processes.

[0169] According to the glass core with a half cavity of the above-mentioned embodiment, by forming a tapered zone at the edge of the cavity so that the interval along the thickness direction gradually narrows, the device margin can be widened compared with the conventional method of using a piece of glass to generate a glass core. As a result, it is beneficial to arrange the pick and place tolerance of the electronic device, and at the same time, there is less space for the electronic device to move after the pick and place process, so the problem of the electronic device being out of the designated arrangement position can be prevented. In addition, the glass core generates a relatively thick glass core with a bonding interface by bonding, so that the effect of reducing the defect that occurs in the multi-layer redistribution layer (RDL) manufacturing process, namely, back cracking (seware). In addition, when the first glass 61 and the second glass 62 are bonded by the anodic bonding process to generate the glass core 21, the interface bonding force is strong, and the reliability will not deteriorate even in repeated high-temperature processes. That is, when a high-temperature process such as a lamination process is repeated, the problem of weakening the bonding force or delamination due to the time-dependent change of the bonding layer can be prevented.

[0170] 7A to 7C Conceptual diagrams of core layers including a glass core having a semi-cavity generated according to an embodiment are exemplarily illustrated with cross sections, respectively.

[0171] Reference Fig. 7A The core layer 22 may include: a glass core 21 having a first surface and a second surface facing each other; a cavity 28 that is open and recessed toward the first surface or the second surface; and a plurality of core through holes 23 that penetrate the glass core 21 along the thickness direction.

[0172] Reference Fig. 7A , the glass core 21 may include a first glass 61 and a second glass 62. The first glass 61 may include a through portion corresponding to the cavity and a plurality of core through holes. The second glass 62 may include a plurality of core through holes penetrating the second glass 62. The plurality of core through holes of the first glass 61 and the plurality of core through holes of the second glass 62 are connected to each other as predetermined so that a core through hole penetrating the glass core 21 may be formed.

[0173] The glass core 21 may form a bonding interface (hereinafter referred to as "interface") by bonding the first glass and the second glass. Alternatively, for example, the bonding interface may include a bonding layer. The bonding layer may be a Si-O layer or a Si-O-Si bonding layer. For example, an O-Si-O structure in which Si / Si of the first glass and O of the second glass are bonded may be configured at the bonding interface.

[0174] In addition, refer to Fig. 7A The glass core 21 having a first surface and a second surface facing each other can be divided into a first area (bare area) having a first thickness, and a second area (cavity area) in which the cavity is located and having a second thickness thinner than the first thickness.

[0175] The thickness of the first region is referred to as the first thickness, and the thickness of the second region is referred to as the second thickness. For example, the first thickness of the glass core 21 may be greater than 400 μm, greater than 500 μm, greater than 600 μm, or greater than 700 μm. The first thickness may be less than 1500 μm, less than 1400 μm, less than 1300 μm, less than 1200 μm, less than 1100 μm, or less than 1000 μm. The second thickness may be greater than 200 μm, greater than 300 μm, greater than 400 μm, or greater than 500 μm. The second thickness may be less than 1000 μm. However, the second thickness is thinner than the first thickness. In this case, a glass core with reduced warping of the core layer, etc. may be prepared.

[0176] In addition, for example, the side angle of the internal space of the cavity when observed from a cross section can be a specific angle based on the first surface or the second surface. This angle is called a taper angle. For example, the specific angle can be more than 86 degrees, more than 87 degrees, more than 88 degrees, or more than 89 degrees. The specific angle can be less than 92 degrees, less than 91 degrees, or less than 90 degrees. The internal space of the cavity can have a shape whose width gradually narrows along the thickness direction. The tapered angle refers to the angle measured from the first surface to the side of the cavity along the internal space when a line substantially perpendicular to the first surface or the second surface of the glass core is regarded as 90 degrees.

[0177] In addition, for example, refer to Fig. 7A An electronic device 40 may be disposed in the inner space 281 of the cavity 28. The electronic device 40 may be inserted into the inner space of the cavity.

[0178] For example, the bottom surface of the cavity may be attached with or without an adhesive such as polyimide tape (PI), and electronic devices may be selected and configured in the internal space of the cavity (designation of the position of the electronic device). Alternatively, a device group (including multiple electronic devices in a manner embedded between insulator layers (electronic device insulating layers), also known as a device module) is formed in such a way that the electrodes are exposed and then inserted into the internal space of the cavity. The electronic device 40 may include an active device such as a transistor or a power transmission device such as a multi-layer ceramic capacitor (MLCC), i.e., a passive device.

[0179] According to the above-mentioned embodiment, the internal space of the cavity formed in the glass core is recessed in a manner that the angle of the side of the internal space of the cavity gradually narrows along the thickness direction, so that the device margin can be maintained. This is beneficial to the pick and place tolerance of arranging electronic devices. At the same time, there is less space for the electronic devices to move after the pick and place process, thereby preventing the electronic devices from deviating from the specified arrangement position.

[0180] Reference Figure 7B The core layer 22 may include: a glass core 21 having a first surface and a second surface facing each other; a cavity 28 (opened toward the first surface in the drawing, but not limited to this, and may also be open toward the second surface, and a composite form thereof may also be used), which is open and recessed toward the first surface; and a plurality of core through holes 23, which penetrate the glass core 21 along the thickness direction.

[0181] Reference Figure 7B The glass core 21 may include a cavity recessed into a portion of the first surface of the glass core and a plurality of core through holes penetrating the glass core. The first glass and the second glass are bonded, and the specific description of their interface, thickness, taper angle, and devices configured in the cavity are the same as the above description, and the detailed description will be omitted.

[0182] In addition, for example, refer to Figure 7B When observing each core through hole from a cross-section, the core through hole includes: a first opening portion connected to the first surface; a second opening portion connected to the second surface; a side line connecting the first opening portion and the second opening portion along the inner diameter surface of each core through hole; and an inflection point, which is a point on the side line where the angle changes. Figure 7B The example in FIG. 1 shows that the core through hole arranged in the first region (bare region) has three inflection points. However, the inflection point may also be 0 (in fact, no inflection point is observed, Fig. 7A ), 1 (described later Figure 7C ) and other forms to achieve this.

[0183] In each embodiment, the number of inflection points may be more than one, more than two, or more than three.

[0184] The inflection points of the core through holes penetrating the glass core arranged in the first region (bare region) of the glass core 21 may be located at substantially the same height, which facilitates easy control when forming a conductive layer or the like in the core through holes.

[0185] At least one of the inflection points of the core through hole arranged in the first region (bare region) of the glass core 21 may be arranged at the same height as the bonding interface.

[0186] The height refers to a height measured along the thickness direction of the glass core based on the second surface.

[0187] A distance from a surface of the glass core (the first surface or the second surface) to an inflection point may be 25% or less of a thickness of the glass core.

[0188] The distance from the surface of the glass core (the first surface or the second surface) to the inflection point may be greater than 100 μm, greater than 150 μm, or greater than 200 μm, and less than 900 μm, less than 800 μm, or less than 700 μm. In addition, the distance may be less than 550 μm, less than 450 μm, or less than 350 μm. In this case, it may be more advantageous to manufacture a core layer using a glass core.

[0189] For example, the core through hole may include: a first section, when viewed from a cross section, the angle of the side surface is the first angle when the first surface or the second surface is used as a reference; a second section, when viewed from a cross section, the angle of the side surface is inclined at a second angle based on the first surface or the second surface; a third section, when viewed from a cross section, the angle of the side surface is inclined at a third angle based on the first surface or the second surface; a fourth section, when viewed from a cross section, the angle of the side surface is inclined at a fourth angle based on the first surface or the second surface; a first inflection point connecting the first section and the second section; a second inflection point connecting the second section and the third section; and a third inflection point connecting the third section and the fourth section. The first angle, the second angle, the third angle, and the fourth angle may be angles of -10 degrees or more, -8 degrees or more, or -6 degrees or more, respectively, based on a virtual line perpendicular to the plane of the second surface. In addition, it may be less than +10 degrees, less than +8 degrees, or less than +6 degrees. At this time, + refers to the angle from the vertical virtual line toward the inner side of the core through hole, and - refers to the angle toward the glass direction.

[0190] The core through hole configured in the cavity portion is a cavity core through hole, and the cavity core through hole includes: a first opening portion, which is connected to the bottom surface of the cavity portion when each cavity core through hole is observed from a cross-section; a second opening portion, which is connected to the second surface; a side line, which connects the first opening portion and the second opening portion along the inner diameter surface of each core through hole; and an inflection point, which is a point on the side line where the angle changes.

[0191] The side surface line of the cavity core through hole may have more than one inflection point.

[0192] The height of at least one of the inflection points of the core through hole configured in the first area (bare area) may be substantially the same as the height of the inflection point of the cavity core through hole. At this time, whether the heights are substantially the same can be determined based on whether the position difference between the inflection points is within the error range. At this time, the error range can be considered to be within 10% or within 5% based on the length of the side line located in the bare area (in this specification, it can also be used to determine whether the heights are substantially the same).

[0193] Reference Figure 7C The core layer 22 may include: a glass core 21 having a first surface and a second surface facing each other; a cavity 28 that is open and recessed toward the first surface or the second surface; and a plurality of core through holes 23 that penetrate the glass core 21 along the thickness direction.

[0194] For example, Figure 7C The specific descriptions of the glass core 21, the first glass 61, the second glass 62, their thickness, physical properties, etc., the cavity, the characteristics of the cavity, the multiple core through holes, their characteristics, the bonding interface, the characteristics of the inflection point, etc. in the embodiment are the same as the above contents and will be omitted.

[0195] The height of the inflection point of the core through hole disposed in the first region (bare region) may be substantially the same as the bottom surface of the cavity region.

[0196] The ratio of the height of the first surface of the first area (bare area) to the height of the inflection point of the core through hole configured in the first area can be basically the same as the ratio of the height of the first surface (recessed cavity bottom surface) of the second area (cavity area) to the height of the inflection point of the cavity core through hole configured in the second area.

[0197] Figure 8 The application is illustrated by cross section. Figure 7B Conceptual diagram of a glass core packaging substrate.

[0198] Reference Figure 8 The package substrate 20 includes a core portion having the glass core 21 described above, and an upper layer 26 and a lower layer 29 may be disposed on the core portion. Figure 8Although an example in which both the upper layer and the lower layer are included is shown, the upper layer 26 may be provided without providing the lower layer 29 as required.

[0199] Rewiring layers are arranged at the upper and lower layers, and can transmit the electrical signal of the core to the upper and lower parts of the package substrate. Figure 8 The use of Figure 7B The glass core package substrate, as described above, comprises Figures 1 to 5 The above contents, including those described in, are applicable.

[0200] According to the method for manufacturing a package substrate and the package substrate using the same according to the above-described embodiment, by generating a thick glass core, it is possible to obtain an effect of reducing back cracks, which are defects occurring during the manufacturing process of a multi-layer redistribution layer (RDL).

[0201] In addition, according to the manufacturing method of the packaging substrate and the packaging substrate using the same according to the embodiment described above, the bonding force between the glasses forming the glass core with the semi-cavity can be enhanced so as to prevent the problem of glass delamination forming the glass core even in multiple high-temperature processes.

[0202] The present specification is described above with reference to the embodiments in the accompanying drawings, but these are only examples, and those skilled in the art will understand that various modifications and modifications of the embodiments can be made accordingly. That is, the scope of rights of the present specification is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the attached claims also fall within the scope of rights of the present embodiments. Therefore, the true technical protection scope of the present specification should be determined by the technical ideas of the attached claims.

Claims

1. A packaging substrate, characterized in that: The packaging substrate comprises a core layer, The core layer comprises: A glass core having a first surface and a second surface facing each other, a cavity portion, the surface of which is concave and open toward the first surface, and is provided with an internal space, and A plurality of core through holes, penetrating the glass core in a thickness direction; The glass core includes a structure in which a first glass and a second glass are stacked up and down and combined. A bonding interface is arranged between the first glass and the second glass, The cone angle of the cavity is 86 degrees to 90 degrees.

2. The packaging substrate according to claim 1, characterized in that: When each of the core through holes is viewed from a cross section, the core through hole comprises: a first opening portion connected to the first surface, The second opening is connected to the second surface. a side line connecting the first opening portion and the second opening portion along the inner diameter surface of each of the core through holes, and Inflection point, which is the point where the side line bends at a certain angle; The inflection point of the core through hole is located at the bonding interface.

3. The packaging substrate according to claim 2, characterized in that: The side line has more than one or more than three inflection points.

4. The packaging substrate according to claim 1, characterized in that: The cavity core through hole is a core through hole arranged in the cavity portion. When observing each cavity core through hole from a cross section, the cavity core through hole includes: The first opening is connected to the bottom surface of the cavity. The second opening is connected to the second surface. a side line connecting the first opening portion and the second opening portion along the inner diameter surface of each of the core through holes, and Inflection point, which is the point on the side line where the angle changes; One or more inflection points are arranged on the side surface line of the cavity core through hole.

5. The packaging substrate according to claim 1, characterized in that: The bonding interface is an anodic bonding interface.

6. The packaging substrate according to claim 1, characterized in that: The thickness of the glass core was 500 μm.

7. The packaging substrate according to claim 1, characterized in that: The cavity is disposed on the first glass. The cavity portion corresponds to a recessed surface or a through portion of the first glass.

8. The packaging substrate according to claim 1, characterized in that: Electronic devices are arranged in the inner space of the cavity.

9. A method for manufacturing a packaging substrate, the packaging substrate comprising a core layer, characterized in that: include: a preparation step of preparing a first glass and a second glass, wherein the first glass has a concave surface or a through portion and a plurality of core through holes, and the second glass has a plurality of core through holes, and a bonding step of aligning the first glass and the second glass and bonding them by an anodic bonding process to form a glass core; The core layer comprises: A glass core having a first surface and a second surface facing each other, a cavity portion, the surface of which is concave and open toward the first surface, and is provided with an internal space, and A plurality of core through holes, penetrating the glass core in a thickness direction; The glass core includes a structure in which a first glass and a second glass are stacked up and down and combined. A bonding interface is arranged between the first glass and the second glass, The cone angle of the cavity is 86 degrees to 90 degrees.

10. The method for manufacturing a packaging substrate according to claim 9, wherein: The method for manufacturing the package substrate, after the bonding step, further comprises: A wiring step is to form a redistribution layer on the first surface or the second surface.

11. The method for manufacturing a packaging substrate according to claim 9, wherein: The method for manufacturing the package substrate, after the bonding step, further comprises: a device insertion step, configuring the device in the cavity, The device has the form of a device module in which one or more electronic devices are configured and molded.

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