Class D amplifier and method for operating class D amplifier

Abstract

The invention provides a class-D amplifier and a method for operating the class-D amplifier. The class-D amplifier comprises a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a driving circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor. The driving circuit receives an input signal, generates a p-type output transistor control signal applied to the gate of the p-type output transistor, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor. When the input signal becomes logically high, the control signal of the n-type output transistor quickly becomes logically low, and the control signal of the p-type output transistor gradually becomes logically low. When the input signal becomes logically low, the control signal of the p-type output transistor quickly becomes logically high, and the control signal of the n-type output transistor gradually becomes logically high.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits in audio systems. More particularly, the present invention relates to automatic calibration control of class D amplifier driver circuits. Background Art

[0002] A Class D amplifier (also called a switching amplifier) ​​is an electronic amplifier in which the transistors act as a binary switch, operating either fully on or fully off. Class D amplifiers employ rail-to-rail output switching, wherein, ideally, the output transistors of the Class D amplifiers carry virtually zero current or zero voltage at all times. As a result, the power dissipation of the Class D amplifiers is minimal, and they provide high efficiency over a wide range of power levels. The advantageous high efficiency of the Class D amplifiers has driven their use in a variety of audio applications, from cellular phones to flat screen televisions and home theater receivers. Class D audio power amplifiers are more efficient than Class AB audio power amplifiers. Because of the higher efficiency of the Class D amplifiers, the Class D amplifiers require smaller power supplies and do not require heat sinks, thereby significantly reducing overall system cost, size, and weight. Summary of the invention

[0003] In one aspect, an embodiment of the present invention provides a class D amplifier. The class D amplifier includes a p-type output transistor. The class D amplifier also includes an n-type output transistor connected in series with the p-type output transistor. The class D amplifier also includes: a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor, wherein the drive circuit receives an input signal, and the drive circuit generates a p-type output transistor control signal applied to the gate of the p-type output transistor in response to the input signal, and the drive circuit generates an n-type output transistor control signal applied to the gate of the n-type output transistor in response to the input signal. When the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, and the p-type output transistor control signal gradually becomes logic low. When the input signal becomes logic low, the p-type output transistor control signal quickly becomes logic high, and the n-type output transistor control signal gradually becomes logic high.

[0004] Optionally, when the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, while the p-type output transistor control signal gradually becomes logic low, so that the p-type output transistor gradually turns on after the n-type output transistor turns off.

[0005] Optionally, when the input signal becomes logic high, the p-type output transistor control signal becomes logic low in a step-by-step manner.

[0006] Optionally, when the input signal becomes logic low, the p-type output transistor control signal quickly becomes logic high, while the n-type output transistor control signal gradually becomes logic high, so that the n-type output transistor gradually turns on after the p-type output transistor turns off.

[0007] Optionally, when the input signal becomes logic low, the n-type output transistor control signal becomes logic high in a step-by-step manner.

[0008] Optionally, the driving circuit includes: a pulse width modulation (PWM) signal generator for generating the input signal; a multi-bit delay line circuit for receiving the input signal and generating a plurality of delayed input signals; an n-type current digital-to-analog converter (IDAC) for generating a first current in response to the plurality of delayed input signals; an n-type transistor connected between the p-type output transistor and the n-type current digital-to-analog converter; a p-type current digital-to-analog converter for generating a second current in response to the plurality of delayed input signals; and a p-type transistor connected between the n-type output transistor and the p-type current digital-to-analog converter.

[0009] Optionally, when the input signal becomes logic high, the p-type transistor is turned off, thereby disconnecting the p-type current digital-to-analog converter from the n-type output transistor, and the n-type output transistor control signal becomes logic low.

[0010] Optionally, when the input signal becomes logic high, the n-type transistor is turned on to connect the n-type current digital-to-analog converter to the p-type output transistor, and the p-type output transistor control signal decreases as the first current increases.

[0011] Optionally, when the input signal becomes logic low, the n-type transistor is turned off, thereby disconnecting the n-type current digital-to-analog converter from the p-type output transistor, and the p-type output transistor control signal becomes logic high.

[0012] Optionally, when the input signal becomes logic low, the p-type transistor is turned on to connect the p-type current digital-to-analog converter to the n-type output transistor, and the n-type output transistor control signal increases as the second current increases.

[0013] Optionally, the input signal is a pulse width modulation signal.

[0014] Optionally, the multi-bit delay line circuit comprises a plurality of delay units connected in series, each of the plurality of delay units providing a delay time.

[0015] Optionally, the delay times of the multiple delay units are different.

[0016] Optionally, the p-type current digital-to-analog converter comprises: a first current source; a first p-type transistor; and a plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current components.

[0017] Optionally, the n-type current digital-to-analog converter comprises: a second current source; a first n-type transistor; and a plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current components.

[0018] On the other hand, an embodiment of the present invention provides a method for operating a class D amplifier. In some embodiments, the class D amplifier includes a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor. The method includes receiving an input signal; using a drive circuit connected to a gate of the n-type output transistor and a gate of the p-type output transistor to generate a p-type output transistor control signal in response to the input signal; using the drive circuit to generate an n-type output transistor control signal in response to the input signal; applying the p-type output transistor control signal to the gate of the p-type output transistor; applying the n-type output transistor control signal to the gate of the n-type output transistor. When the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, while the p-type output transistor control signal gradually becomes logic low. When the input signal becomes logic low, the p-type output transistor control signal quickly becomes logic high, while the n-type output transistor control signal gradually becomes logic high.

[0019] Optionally, when the input signal becomes logic high, the p-type output transistor control signal becomes logic low in a step-by-step manner.

[0020] Optionally, when the input signal becomes logic low, the n-type output transistor control signal becomes logic high in a step-by-step manner.

[0021] Optionally, it also includes: using a multi-bit delay line circuit to generate a plurality of delayed input signals; using an n-type current digital-to-analog converter to generate a first current in response to the plurality of delayed input signals; and using a p-type current digital-to-analog converter to generate a second current in response to the plurality of delayed input signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The state of the present application will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of description.

[0023] Figure 1A FIG. 4 is a simplified schematic diagram of a conventional class-D amplifier.

[0024] Figure 1B To illustrate Figure 1A A waveform diagram of the modulation of the signal in a Class D amplifier.

[0025] Figure 2 A schematic block diagram of a class-D amplifier with improved slew rate is shown.

[0026] Figure 3A FIG. 4 is a schematic diagram illustrating the operation of a class-D amplifier when a p-type output transistor is gradually turned on.

[0027] Figure 3B FIG. 4 is a schematic diagram illustrating the operation of a class-D amplifier when an n-type output transistor is gradually turned on.

[0028] Figure 4 is a diagram illustrating a portion of a class-D amplifier according to some embodiments.

[0029] Figure 5 FIG. 5 is a diagram illustrating another portion of a class-D amplifier according to some embodiments.

[0030] Figure 6 is a diagram illustrating an example multi-bit delay line circuit.

[0031] Figure 7 FIG. 4 is a diagram illustrating a p-type output transistor control signal, an n-type output transistor control signal, an input signal, and an output signal when an input signal becomes logic high.

[0032] Figure 8 FIG. 4 is a diagram illustrating a p-type output transistor control signal, an n-type output transistor control signal, an input signal, and an output signal when an input signal becomes logic low.

[0033] Fig. 9 A flow chart illustrating an example method for operating a class-D amplifier is shown.

[0034] Description of reference numerals:

[0035] 100, 200: Class D amplifier; 101: first comparator; 102: second comparator; 103: oscillator; 106: first PWM signal; 107: second PWM signal; 110: speaker load; 191, 192, 193, 194: output transistor; 201: drive circuit; 210: output load; 220: first block; 222: p-type bias current generator; 224: n-type bias current generator; 226: PWM signal generator; 240: second block; 242: n-type current digital-to-analog converter (IDAC); 244: p-type IDAC; 246: multi-bit delay line circuit ; 290: third block; 291: p-type output transistor; 292: n-type output transistor; 293, 294: parasitic capacitance; 302: operation; 304: operation; 306: operation; 308: operation; 400, 500: part; 404: p-type pre-driver; 412: n-type transistor; 414, 416, 418, 420, 522, 527: p-type transistor; 422, 427, 512, 520: n-type transistor; 424, 524: current source; 428-0, 428-1, 428-2, 428-3, 428-N: n-type current generating transistor; 430-0, 43 0-1, 430-2, 430-3, 430-N, 530-0, 530-1, 530-2, 530-3, 530-N: access transistors; 432-0, 432-1, 432-2, 432-3, 432-N, 532-0, 532-1, 532-2, 532-3, 532-N: current branches; 504: n-type pre-driver; 528-0, 528-1, 528-2, 528-3, 528-N: p-type current generating transistors; 602-0: first delay unit; 602-1: second delay unit; 602-N: last delay unit; 612-1: first inverter; 612-2: second inverter; 614: parasitic capacitor; 900: method; 902, 904, 906, 908, 910: steps; C, C', D, D': nodes; IN: input signal; INB: inverted input signal; INM: second audio input signal / differential audio input signal; INP: first audio input signal / differential audio input signal; L1: inductor; NGATE: n-type output transistor control signal; OUT: output signal; OUTM: first output signal; OUTP: second output signal; PGATE: p-type output transistor control signal; R1: resistor; SEL <0> : The first delayed input signal; SEL <1> : The second delayed input signal; SEL <2> , SEL <3> , SEL <n>: Delayed input signal; VREF: triangle wave signal. DETAILED DESCRIPTION

[0036] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present application. Of course, these components and configurations are only examples and are not intended to be restrictive. In addition, the present application can repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations described.

[0037] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0038] Additionally, source / drain ("S / D") regions may be referred to individually or collectively as source or drain, depending on the context. For example, a device may include a first source / drain region and a second source / drain region, among other components. The first source / drain region may be a source region and the second source / drain region may be a drain region, or vice versa. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0039] Some embodiments of the present application are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Some of the features described below may be replaced or eliminated for different embodiments, and additional features may be added. Although some embodiments are discussed in conjunction with operations performed in a particular order, these operations may be performed in another logical order.

[0040] Class D audio power amplifiers convert audio input signals into high frequency pulses that switch output transistors based on the audio input signal. Some Class D amplifiers use a pulse width modulator (PWM) to generate a series of modulated pulses whose width varies based on the amplitude of the audio input signal. The varying width pulses switch the output transistors at a fixed frequency. Other Class D amplifiers may rely on other types of pulse modulators. The following discussion will primarily refer to modulated pulse width modulators, and those skilled in the art will recognize that Class D amplifiers may be configured with other types of modulators.

[0041] Figure 1A FIG. 1 is a simplified schematic diagram of a class-D amplifier 100 as a conventional class-D amplifier. Figure 1A As shown in FIG. 1 , the class-D amplifier 100 is a differential amplifier. A pair of differential audio input signals INP and INM (i.e., a first audio input signal INP and a second audio input signal INM) are input to a first comparator 101 and a second comparator 102, respectively. Each of the pair of differential audio input signals INP and INM is compared with a triangular signal (i.e., a signal having a triangular waveform) VREF generated from an oscillator 103 to generate a first PWM signal 106 and a second PWM signal 107, respectively. Since the first audio input signal INP and the second audio input signal INM are differential signals and the same triangular signal VREF is used as a reference signal, the first PWM signal 106 and the second PWM signal 107 are also differential signals (i.e., inverse to each other).

[0042] The first PWM signal 106 is coupled to the gates of the output transistors 191 and 192 which are electrically connected together. Therefore, the first PWM signal 106 controls the on and off of the output transistors 191 and 192. The second PWM signal 107 is coupled to the gates of the output transistors 193 and 194 which are electrically connected together. Therefore, the second PWM signal 107 controls the on and off of the output transistors 193 and 194. Therefore, the first output signal OUTM and the second output signal OUTP of the class D amplifier 100 are also differential output signals. Figure 1A As shown in FIG. 1 , the first output signal OUTM and the second output signal OUTP are applied to both ends of the speaker load 110. Figure 1A In the figure, it is represented by inductor L1 and resistor R1.

[0043] Figure 1B To illustrate Figure 1A 1 is a waveform diagram of the modulation of the signal in the class D amplifier 100. Figure 1B As shown in FIG. 1 , the first audio input signal INP and the second audio input signal INM are compared with the triangle wave signal VREF. Figure 1A The output signals of the first comparator 101 and the second comparator 102 are pulse signals at a fixed frequency (i.e., a fixed period), and the pulse widths of the pulse signals are proportional to the corresponding audio input signals. Therefore, the first output signal OUTM and the second output signal OUTP are two PWM signals, such as Figure 1B as shown in .

[0044] The techniques disclosed in this application help improve the output slew rate of a Class D amplifier during switching when the Class D amplifier uses a rail-to-rail output voltage swing. The goal is to minimize any overshoot or undershoot that would degrade the power efficiency of the Class D amplifier. Typically, Class D amplifiers provide efficiencies in excess of 90% or even about 95%. In order to keep the efficiency as high as possible, the slew rate must be carefully controlled.

[0045] Slew rate is defined as the change in voltage (or current, or any other electrical quantity in other cases) per unit time. In the case of SI units, the measurement unit of slew rate is volts per second (V / s) or volts per microsecond (V / μs). When given the output of a circuit such as an amplifier (e.g., a Class D amplifier), the slew rate specification guarantees that the speed at which the output signal changes will be at least a given minimum value or at most a given maximum value. When applied to the input of a circuit, it indicates that the external drive circuit system needs to meet those restrictions in order to ensure the correct operation of the receiving device. If these restrictions are violated, some errors may occur and correct operation is no longer guaranteed.

[0046] Figure 2 FIG. 2 is a schematic block diagram of a class D amplifier 200 with improved slew rate. Figure 2 As shown in FIG. 1 , the output terminal of the class D amplifier 200 is connected to an output load (eg, a speaker load) 210, which is composed of an inductor L1 and a resistor R1 (eg, Figure 1A The inductor and resistor shown in are represented.

[0047] exist Figure 2 In the example shown in , the class D amplifier 200 includes a PWM signal generator 226, a p-type bias current generator (also referred to as a "first bias current generator") 222, an n-type bias current generator (also referred to as a "second bias current generator") 224, a multi-bit delay line circuit 246, an n-type current digital-to-analog converter (IDAC) (also referred to as a "first IDAC") 242, a p-type IDAC (also referred to as a "second IDAC") 244, a p-type output transistor 291, an n-type output transistor 292, and other components. From another perspective, the class D amplifier 200 includes a driver circuit 201, a p-type output transistor 291, an n-type output transistor 292, and other components. The driver circuit 201 includes a PWM signal generator 226, a p-type bias current generator 222, an n-type bias current generator 224, a multi-bit delay line circuit 246, an n-type IDAC 242, a p-type IDAC 244, and other components.

[0048] The p-type output transistor 291 and the n-type output transistor 292 are connected in series between a lower power rail (e.g., ground) and a higher power rail (e.g., VDD). Compared to other transistors in the class D amplifier 200, the p-type output transistor 291 and the n-type output transistor 292 are characterized by large dimensions (e.g., channel length, channel width, etc.) to drive the output load 210 to meet the desired power efficiency. Therefore, the parasitic capacitances 293 and 294 are characterized by large capacitances, which will make the slew rate smaller (i.e., slow down the slew rate). In one embodiment, the p-type output transistor 291 is a PMOS transistor and the n-type output transistor 292 is an NMOS transistor. It should be understood that other types of transistors may be used for the p-type output transistor 291 and the n-type output transistor 292. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0049] The PWM signal generator 226 generates an input signal (in Figure 2 The PWM signal generator 226 may further generate an inverted input signal (which may be referred to as an “INB” signal and is shown in FIG. Figure 4 and Figure 5 In one embodiment, the PWM signal generator 226 may include a comparator and an oscillator that generates a triangular wave. Figure 1A and Figure 1B It should be understood that in other embodiments, PWM signal generators with other architectures may be used.

[0050] The multi-bit delay line circuit 246 receives the input signal IN and generates a plurality of delayed input signals, which are fed to the n-type IDAC 242 and the p-type IDAC 244. Each of these plurality of delayed input signals is delayed by a delay time relative to its previous delayed input signal. Figure 6 FIG. 2 is a diagram illustrating an example multi-bit delay line circuit 246. Figure 6 In the example shown in FIG. 2 , the multi-bit delay line circuit 246 includes a plurality of delay units 602-0, 602-1, ..., 602-N (collectively referred to as "602") connected in series. The first delay unit 602-0 receives the input signal IN from the PWM signal generator 226 and delays it by a first delay time, thereby generating a first delayed input signal (at Figure 6 In the section marked "SEL <0> The second delay unit 602-1 receives the output signal (ie, the first delayed input signal SEL) from the first delay unit 602-0. <0> ) and delay it by a second delay time, thereby generating a second delayed input signal (at Figure 6 In the section marked "SEL <1> This process continues until the last delay unit 602-N produces the last delayed input signal (at Figure 6 In the section marked "SEL <n>”), the last delayed input signal is delayed (N+1) times relative to the input signal IN. Therefore, the last delay unit 602-N can also be referred to as the "(N+1)th delay unit 602-N". Figure 4 and Figure 5 As discussed, the number of delay cells 602 determines the width of the n-type IDAC 242 and the width of the p-type IDAC 244 .

[0051] exist Figure 6 In the embodiment shown in , each delay unit may include a first inverter 612-1 and a second inverter 612-2 connected in series. The first inverter 612-1 and the second inverter 612-2 may both be NOT gates. The parasitic capacitor 614 is connected between the output terminal of the first inverter 612-1 and the ground. It should be understood that other types of delay units may be used in other embodiments. In some embodiments, the delay time of each delay unit 602 is the same. In other embodiments, the delay time of each delay unit 602 is different.

[0052] Return to reference Figure 2 The p-type bias current generator 222 is controlled by the input signal IN (and the inverted input signal INB). The p-type bias current generator 222 and the n-type IDAC 242 operate to provide a p-type output transistor control signal (at Figure 2 The p-type output transistor control signal is applied to the gate of the p-type output transistor 291. Similarly, the n-type bias current generator 224 is controlled by the input signal IN (and the inverted input signal INB). The n-type bias current generator 224 and the p-type IDAC 244 operate to provide the n-type output transistor control signal (in Figure 2 The n-type output transistor control signal is applied to the gate of the n-type output transistor 292 (labeled “NGATE” in FIG. 1 ).

[0053] The following will discuss Figure 4 Exemplary implementations of the p-type bias current generator 222 and the n-type IDAC 242 are discussed below. Figure 5 Exemplary implementations of the n-type bias current generator 224 and the p-type IDAC 244 are discussed.

[0054] Figure 3A FIG. 2 is a schematic diagram illustrating the operation of the class-D amplifier 200 when the p-type output transistor 291 is gradually turned on. Figure 3B FIG. 2 is a schematic diagram illustrating the operation of the class-D amplifier 200 when the n-type output transistor 292 is gradually turned on.

[0055] like Figure 3A As shown in FIG, when the output signal OUT changes from a logic low (ie, “0”) to a logic high (ie, “1”) (in Figure 3A When the n-type output transistor 292 is turned off and the p-type output transistor 291 is turned on, the output signal OUT is pulled to a higher power rail (e.g., VDD). Importantly, the turning off of the n-type output transistor 292 is rapid (i.e., the n-type output transistor control signal NGATE decreases quickly from a logic high to a logic low); the turning on of the p-type output transistor 291 is gradual (i.e., the p-type output transistor control signal PGATE decreases or pulls down from a logic high to a logic low one step at a time (in Figure 3A Thus, when the p-type output transistor 291 is gradually turned on, the breakdown current flowing through the n-type output transistor 292 is lower because the n-type output transistor 292 is turned off before the p-type output transistor 291 is gradually turned on. In some embodiments, it takes about 25 ns to turn on the p-type output transistor 291 (hence, about 10 ns). Figure 3A ), and turning off the n-type output transistor 292 takes about 1 ns (hence, Figure 3A In some embodiments, the ratio of the on time of the p-type output transistor 291 to the off time of the n-type output transistor 292 is a first ratio. In some instances, the first ratio is greater than 50. In some instances, the first ratio is greater than 30. In some instances, the first ratio is greater than 25. In some instances, the first ratio is greater than 20. Figure 4 As discussed, this is accomplished by the multi-bit delay line circuit 246 , the n-type IDAC 242 , and the p-type bias current generator 222 .

[0056] like Figure 3B As shown in FIG, when the output signal OUT changes from logic high to logic low (in Figure 3B When the p-type output transistor 291 is turned off and the n-type output transistor 292 is turned on, the output signal OUT is pulled to a lower power rail (e.g., ground). Importantly, the turning off of the p-type output transistor 291 is rapid (i.e., the p-type output transistor control signal PGATE increases quickly from a logic low to a logic high); the turning on of the n-type output transistor 292 is gradual (i.e., the n-type output transistor control signal NGATE increases or pulls up from a logic low to a logic high one step at a time (in Figure 3B Thus, when the n-type output transistor 292 is gradually turned on, the breakdown current flowing through the p-type output transistor 291 is lower because the p-type output transistor 291 is turned off before the n-type output transistor 292 is gradually turned on. In some embodiments, it takes about 25 ns to turn on the n-type output transistor 292 (hence, about 10 ns). Figure 3B ), and turning off the p-type output transistor 291 takes about 1 ns (hence, Figure 3B In some embodiments, the ratio of the on time of the n-type output transistor 292 to the off time of the p-type output transistor 291 is a second ratio. In some instances, the second ratio is greater than 50. In some instances, the second ratio is greater than 30. In some instances, the second ratio is greater than 25. In some instances, the second ratio is greater than 20. Figure 5 As discussed, this is accomplished by the multi-bit delay line circuit 246 , the p-type IDAC 244 , and the n-type bias current generator 224 .

[0057] in addition, Figure 2 The class D amplifier 200 shown in FIG. 2 can be considered to include three blocks. The first block 220 includes a PWM signal generator 226, a p-type bias current generator 222, and an n-type bias current generator 224. The first block 220 operates to generate the input signal IN (and the inverted input signal INB) and the bias current required by the second block 240. The second block 240 includes a multi-bit delay line circuit 246, an n-type IDAC 242, and a p-type IDAC 244. The second block 240 operates to generate a p-type output transistor control signal PGATE and an n-type output transistor control signal NGATE to be provided to the third block 290. The third block 290 includes a p-type output transistor 291 and an n-type output transistor 292. The third block 290 operates to generate an output signal OUT based on the p-type output transistor control signal PGATE and the n-type output transistor control signal NGATE. It should be understood that this provides one possible perspective of the class D amplifier 200, and all components of the class D amplifier 200 function as a whole.

[0058] Figure 4 4 is a diagram illustrating a portion 400 of a Class D amplifier 200 according to some embodiments. As described above, portion 400 acts as Figure 2 2 and 3. The p-type bias current generator 222 and the n-type IDAC 242 are shown in FIG. It should be understood that those skilled in the art will recognize many variations, modifications, and alternatives.

[0059] exist Figure 4 In the example shown in FIG. 4 , portion 400 receives input signal IN and inverted input signal INB and generates p-type output transistor control signal PGATE to be applied to the gate of p-type output transistor 291. As discussed above, inverted input signal INB is a complementary signal to input signal IN.

[0060] Portion 400 includes p-type bias current generator 222, p-type pre-driver 404, and n-type IDAC 242, among other components. Figure 4 In the example shown in FIG. 1 , the p-type bias current generator 222 includes a Figure 4 2 and 4. The topology shown in FIG. 2 shows an n-type transistor 412 and three p-type transistors 414, 416, and 418. The n-type transistor 412, the p-type transistors 414, and 416 are connected in series between ground and a positive voltage (e.g., VCCH). In one example, VCCH is 12 volts, but in other embodiments, it can be other values. The gate of the n-type transistor 412 receives the inverted input signal INB. The gates of the p-type transistors 416 and 418 are connected together. The p-type bias current generator 222 acts as a current mirror.

[0061] exist Figure 4 In the example shown in FIG. 1 , the p-type pre-driver 404 includes a positive voltage (eg, VCCH) connected in series with the n-type IDAC 242. Figure 4 The topology shown in FIG. 4 is an n-type transistor 422 and a p-type transistor 420. The gate of the n-type transistor 422 receives the input signal IN.

[0062] P-type transistors 418 and 420 are connected in parallel. A first source / drain (S / D) terminal of p-type transistor 420 is connected to a positive voltage (e.g., VCCH), and a second S / D terminal of p-type transistor 420 is connected to both its own gate and the first S / D terminal of p-type transistor 420.

[0063] exist Figure 4 In the example shown in FIG. 1 , the n-type IDAC 242 includes a current source 424, an n-type transistor 427 connected in series with the current source 424, and a plurality of current branches 432-0, 432-1, 432-3, ..., 432-N (collectively referred to as "432"). Each current branch includes an access transistor 430-0, 430-1, 430-3, ..., 430-N (collectively referred to as "430") and an n-type current generating transistor 428-0, 428-1, 428-3, ..., 428-N (collectively referred to as "428"). The n-type current generating transistor 428 has a common gate configuration. The access transistor 430 corresponds to Figure 6 The gate of each access transistor 430 receives a signal from the delay cell 602 of the multi-bit delay line circuit 246 shown in FIG. Figure 6 The multiple delayed input signals SEL generated by the multi-bit delay line circuit 246 shown in FIG. <0> To SEL <n>If the delayed input signal is logic high, the corresponding current branch 432 is selected, and Figure 4 The current flowing through the corresponding n-type current generating transistor 428 is collected at the node C shown in FIG.

[0064] exist Figure 4 In the example shown in FIG. 4 , n-type current generating transistor 428 is characterized by different sizes so that the current generated thereby is 2(N+1) times the current flowing through n-type transistor 427, where N is 0, 1, 2, 3, ..., N. Therefore, the more current branches 432 there are, the higher the granularity or resolution that n-type IDAC 242 can provide.

[0065] exist Figure 4 In the example shown in , when the input signal IN is logic low, the inverting input signal INB is logic high. Therefore, the n-type transistor 422 is turned off, and the n-type transistor 412 is turned on. The p-type transistors 414, 416, and 418 are turned on, and the voltage at the node D is pulled up to a positive voltage (e.g., VCCH). The current flowing through the p-type transistors 414 and 416 is mirrored into the current flowing through the p-type transistor 418.

[0066] Therefore, the p-type transistor 420 is turned on because the gate of the p-type transistor 420 is connected to the node D. Therefore, the p-type output transistor 291 is disconnected from the n-type IDAC 242, and the p-type output transistor control signal PGATE is pulled up to the power supply voltage (e.g., VCCH), thereby turning off the p-type output transistor 291. Figure 5 As discussed, when the input signal IN is logic low, the n-type output transistor control signal NGATE gradually increases, thereby gradually turning on the n-type output transistor 292. Therefore, the output signal OUT is logic low.

[0067] On the other hand, when the input signal IN is logic high, the inverting input signal INB is logic low. Therefore, the n-type transistor 422 is turned on, thereby connecting the p-type output transistor 291 to the n-type IDAC 242, and the n-type transistor 412 is turned off. The p-type transistors 414, 416 and 418 are turned off. The p-type transistor 420 is a diode-connected transistor (e.g., a diode-connected MOSFET). Therefore, the p-type output transistor control signal PGATE is equal to the power supply voltage (e.g., VCCH) minus the voltage across the p-type transistor 420, and the voltage across the p-type transistor 420 is determined by the current provided by the n-type IDAC 242 and the size of the p-type transistor 420.

[0068] As discussed above, the n-type IDAC 242 includes a plurality of delayed input signals SEL <0> To SEL <n>The multiple current branches 432 are independently controlled, and the multiple delayed input signals are Figure 6 The multi-bit delay line circuit 246 shown in FIG. 1 is generated. Therefore, the current provided by the n-type IDAC 242 at the node C can be changed one step at a time. Therefore, the p-type output transistor control signal PGATE gradually decreases, such as Figure 3A As shown in FIG. Therefore, the p-type output transistor 291 is gradually turned on. Figure 5 As described, when the input signal IN is logic high, the n-type output transistor control signal NGATE quickly becomes logic high, thereby quickly turning off the n-type output transistor 292. Therefore, the output signal OUT is logic high.

[0069] In one example, the n-type output transistor control signal NGATE varies within a range between about 7 V and about 12 V. It should be understood that in other embodiments, the range may be fine-tuned as needed depending on specific design requirements.

[0070] Figure 5 2 is a diagram illustrating a portion 500 of a Class D amplifier 200 according to some embodiments. As described above, portion 500 acts as Figure 2 2 and 3. The n-type bias current generator 224 and the p-type IDAC 244 are shown in FIG. It should be understood that those skilled in the art will recognize many variations, modifications, and alternatives.

[0071] exist Figure 5 In the example shown in , portion 500 receives an input signal IN and generates an n-type output transistor control signal NGATE to be applied to the gate of n-type output transistor 292 .

[0072] Portion 500 includes n-type bias current generator 224, n-type pre-driver 504, and p-type IDAC 244, among other components. Figure 5 In the example shown in , the n-type bias current generator 224 includes an n-type transistor 512 and a p-type transistor 522, wherein their gates are connected together. The n-type transistor 512 and the p-type transistor 522 form an inverter. The n-type transistor 512 and the p-type transistor 522 are connected in series between the ground and the node C'. The gate of the n-type transistor 512 and the gate of the p-type transistor 522 both receive the inverted input signal INB. The n-type bias current generator 224 acts as an inverter.

[0073] exist Figure 5 In the example shown in FIG. 1 , the n-type pre-driver 504 includes a first transistor connected in series between ground and the p-type IDAC 244. Figure 5 The topology shown in FIG. 5 is a p-type transistor 522 and an n-type transistor 520. The gate of the p-type transistor 522 receives an input signal IN.

[0074] The n-type transistors 512 and 520 are connected in parallel. A first source / drain (S / D) terminal of the n-type transistor 520 is connected to ground, and a second S / D terminal of the n-type transistor 520 is connected to its own gate.

[0075] exist Figure 5 In the example shown in FIG. 1 , the p-type IDAC 244 includes a current source 524, a p-type transistor 527 connected in series with the current source 524, and a plurality of current branches 532-0, 532-1, 532-3, ..., 532-N (collectively referred to as "532"). Each current branch includes an access transistor 530-0, 530-1, 530-3, ..., 530-N (collectively referred to as "530") and a p-type current generating transistor 528-0, 528-1, 528-3, ..., 528-N (collectively referred to as "528"). The access transistor 530 corresponds to Figure 6 The gate of each access transistor 530 receives a signal from the delay cell 602 of the multi-bit delay line circuit 246 shown in FIG. Figure 6 The multiple delayed input signals SEL generated by the multi-bit delay line circuit 246 shown in FIG. <0> To SEL <n>If the delayed input signal is logic high, the corresponding current branch 532 is selected, and Figure 5 The current flowing through the corresponding current generating transistor 528 is collected at the node C′ shown in FIG.

[0076] exist Figure 5 In the example shown in FIG. 5 , p-type current generating transistor 528 is characterized by different sizes so that the current generated thereby is 2(N+1) times the current flowing through p-type transistor 527, where N is 0, 1, 2, 3, ..., N. Therefore, the more current branches 532 there are, the higher the granularity or resolution that p-type IDAC 244 can provide.

[0077] exist Figure 5 In the example shown in , when the input signal IN is logic high, the p-type transistor 522 is turned off, and the n-type transistor 512 is turned on, and the voltage at the node D′ is pulled up to ground.

[0078] Therefore, the n-type output transistor 292 is disconnected from the p-type IDAC 244, and the n-type output transistor control signal NGATE is pulled up to ground, thereby turning off the n-type output transistor 292. Figure 4 As discussed, when the input signal IN is logic high, the p-type output transistor control signal PGATE gradually decreases, thereby gradually turning on the p-type output transistor 291. Therefore, the output signal OUT is logic high.

[0079] On the other hand, when the input signal IN is logic low, the p-type transistor 522 is turned on, thereby connecting the n-type output transistor 292 to the p-type IDAC 244, and the n-type transistor 512 is turned off. The n-type transistor 520 is a diode-connected transistor (e.g., a diode-connected MOSFET). Therefore, the n-type output transistor control signal NGATE is equal to the voltage across the n-type transistor 520, and the voltage across the n-type transistor 520 is determined by the current provided by the p-type IDAC 244 and the size of the n-type transistor 520.

[0080] As discussed above, the p-type IDAC 244 includes a plurality of delayed input signals SEL <0> To SEL <n>The multiple current branches 532 are independently controlled, and the multiple delayed input signals are Figure 6 The multi-bit delay line circuit 246 shown in FIG. 1 is generated. Therefore, the current provided by the p-type IDAC 244 at the node C' can be changed one step at a time. Therefore, the n-type output transistor control signal NGATE gradually increases, such as Figure 3B As shown in . Therefore, the n-type output transistor 292 is gradually turned on. Figure 4 As discussed, when the input signal IN is logic low, the p-type output transistor control signal PGATE quickly becomes logic high, thereby quickly turning off the p-type output transistor 291. Therefore, the output signal OUT is logic low.

[0081] In one example, the n-type output transistor control signal NGATE varies within a range between approximately 0 V and approximately 4.5 V. It should be understood that in other embodiments, the range may be fine-tuned as needed depending on specific design requirements.

[0082] Figure 7 FIG. 1 is a diagram illustrating a p-type output transistor control signal PGATE, an n-type output transistor control signal NGATE, an input signal, and an output signal when an input signal becomes logic high. Figure 7 In the example shown in , at time t1, the input signal IN becomes logic high. Therefore, the n-type output transistor control signal NGATE quickly becomes logic low, and the p-type output transistor control signal PGATE gradually becomes logic low. Therefore, the n-type output transistor 292 is quickly turned off, and the p-type output transistor 291 is gradually turned on. Therefore, when the p-type output transistor control signal PGATE reaches logic low, the output signal OUT starts to become logic high at time t2. Figure 7 As shown in , the conversion rate is improved.

[0083] Figure 8 FIG. 1 is a diagram illustrating a p-type output transistor control signal PGATE, an n-type output transistor control signal NGATE, an input signal, and an output signal when an input signal becomes logic low. Figure 8 In the example shown in , at time t1, the input signal IN becomes logic low. Therefore, the n-type output transistor control signal NGATE gradually becomes logic high, and the p-type output transistor control signal PGATE quickly becomes logic high. Therefore, the p-type output transistor 291 quickly turns off, and the n-type output transistor 292 gradually turns on. Therefore, when the n-type output transistor control signal NGATE reaches logic high, the output signal OUT starts to become logic low at time t2. Figure 8 As shown in , the conversion rate is improved. Fig. 9 To illustrate the operation of a Class D amplifier (e.g., Figure 2 Flowchart of an example method 900 of a Class D amplifier 200 shown in FIG. The method 900 begins at step 902 by receiving an input signal (eg, Figure 2 At step 904, a p-type output transistor control signal (eg, Figure 2 In one embodiment, a driver circuit (eg, PGATE shown in FIG. 1 ) connected to the gate of the n-type output transistor and the gate of the p-type output transistor is used. Figure 2 The driving circuit 201 shown in FIG. 1 is used to generate a p-type output transistor control signal. At step 906, an n-type output transistor control signal (eg, Figure 2 Similarly, using a driver circuit (e.g., Figure 2 The driving circuit 201 shown in FIG. 2 is used to generate the n-type output transistor control signal. At step 908, the p-type output transistor control signal is applied to the p-type output transistor (e.g., Figure 2 At step 910, an n-type output transistor control signal is applied to the n-type output transistor (eg, at Figure 2 When the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, while the p-type output transistor control signal gradually becomes logic low (e.g., as shown in FIG. 1 ). Figure 3A When the input signal becomes logic low, the p-type output transistor control signal quickly becomes logic high, while the n-type output transistor control signal gradually becomes logic high (e.g., as shown in FIG. 1 ). Figure 3B ). It should be understood that additional steps may be employed. It should also be understood that in other embodiments, the order of the steps may be varied.

[0084] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the status of the present application. Those skilled in the art will appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present application, and that those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present application.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A class D amplifier, characterized in that: include: p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; as well as a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor, wherein the drive circuit receives an input signal and generates a p-type output transistor control signal applied to the gate of the p-type output transistor in response to the input signal, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor in response to the input signal; wherein when the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, while the p-type output transistor control signal gradually becomes logic low; and When the input signal changes to logic low, the p-type output transistor control signal quickly changes to logic high, while the n-type output transistor control signal gradually changes to logic high.

2. The class D amplifier according to claim 1, wherein: When the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, while the p-type output transistor control signal gradually becomes logic low, so that the p-type output transistor gradually turns on after the n-type output transistor turns off.

3. The class D amplifier according to claim 1, wherein: When the input signal becomes logic high, the p-type output transistor control signal becomes logic low in a step-by-step manner.

4. The class D amplifier according to claim 1, wherein: When the input signal becomes logic low, the p-type output transistor control signal quickly becomes logic high, while the n-type output transistor control signal gradually becomes logic high, so that the n-type output transistor gradually turns on after the p-type output transistor turns off.

5. The class D amplifier according to claim 1, wherein: When the input signal becomes logic low, the n-type output transistor control signal becomes logic high in a step-by-step manner.

6. The class D amplifier of claim 1, wherein: The driving circuit comprises: A pulse width modulation signal generator, used to generate the input signal; a multi-bit delay line circuit for receiving the input signal and generating a plurality of delayed input signals; An n-type current digital-to-analog converter for generating a first current in response to the plurality of delayed input signals; an n-type transistor connected between the p-type output transistor and the n-type current digital-to-analog converter; A p-type current digital-to-analog converter for generating a second current in response to the plurality of delayed input signals; and The p-type transistor is connected between the n-type output transistor and the p-type current digital-to-analog converter.

7. The class D amplifier according to claim 6, wherein: When the input signal becomes logic high, the p-type transistor turns off, thereby disconnecting the p-type current digital-to-analog converter from the n-type output transistor, while the n-type output transistor control signal becomes logic low.

8. The class D amplifier of claim 7, wherein: When the input signal becomes logic high, the n-type transistor is turned on, thereby connecting the n-type current digital-to-analog converter to the p-type output transistor, and the p-type output transistor control signal decreases as the first current increases.

9. The class D amplifier of claim 6, wherein: When the input signal becomes logic low, the n-type transistor turns off, thereby disconnecting the n-type current digital-to-analog converter from the p-type output transistor, while the p-type output transistor control signal becomes logic high.

10. The class D amplifier of claim 9, wherein: When the input signal becomes logic low, the p-type transistor is turned on, thereby connecting the p-type current digital-to-analog converter to the n-type output transistor, and the n-type output transistor control signal increases as the second current increases.

11. The class D amplifier of claim 6, wherein: The input signal is a pulse width modulation signal.

12. The class D amplifier of claim 6, wherein: The multi-bit delay line circuit includes a plurality of delay units connected in series, each of the plurality of delay units providing a delay time.

13. The class D amplifier of claim 12, wherein: The delay times of the plurality of delay units are different.

14. The class D amplifier of claim 6, wherein: The p-type current digital-to-analog converter comprises: a first current source; a first p-type transistor; and A plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current components.

15. The class D amplifier of claim 6, wherein: The n-type current digital-to-analog converter comprises: a second current source; a first n-type transistor; and A plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current components.

16. A method for operating a class D amplifier, characterized in that The class D amplifier includes a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor, and the method includes: receiving an input signal; generating a p-type output transistor control signal in response to the input signal using a drive circuit connected to a gate of the n-type output transistor and a gate of the p-type output transistor; generating an n-type output transistor control signal using the drive circuit in response to the input signal; applying the p-type output transistor control signal to the gate of the p-type output transistor; and applying the n-type output transistor control signal to the gate of the n-type output transistor; and wherein when the input signal becomes logic high, the n-type output transistor control signal quickly becomes logic low, while the p-type output transistor control signal gradually becomes logic low, and wherein when the input signal becomes logic low, the p-type output transistor control signal quickly becomes logic high, while the n-type output transistor control signal gradually becomes logic high.

17. The method according to claim 16, characterized in that When the input signal becomes logic high, the p-type output transistor control signal becomes logic low in a step-by-step manner.

18. The method according to claim 16, characterized in that When the input signal becomes logic low, the n-type output transistor control signal becomes logic high in a step-by-step manner.

19. The method according to claim 16, characterized in that Also includes: generating a plurality of delayed input signals using a multi-bit delay line circuit; generating a first current in response to the plurality of delayed input signals using an n-type current digital-to-analog converter; as well as A p-type current digital-to-analog converter is used to generate a second current in response to the plurality of delayed input signals.

20. The method of claim 19, wherein: Also includes: When the input signal becomes logic high: disconnecting the p-type current digital-to-analog converter from the n-type output transistor; as well as connecting the n-type current digital-to-analog converter to the p-type output transistor, and wherein the p-type output transistor control signal decreases as the first current increases; and When the input signal becomes logic low: disconnecting the n-type current digital-to-analog converter from the p-type output transistor; and The p-type current digital-to-analog converter is connected to the n-type output transistor, and wherein the n-type output transistor control signal increases as the second current increases.

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