Two-channel arbitrary waveform generator and triggering method

Abstract

The invention provides a two-channel arbitrary waveform generator and a triggering method, and the generator comprises a first signal output unit which is used for generating and outputting a first control signal; the second signal output unit is used for generating and outputting a second control signal; the comparison phase discrimination unit is respectively connected with the first signal output unit and the second signal output unit and is used for comparing and outputting the phase difference between the first control signal and the second control signal and respectively feeding back the phase difference to the first signal output unit and the second signal output unit; and the first signal output unit and the second signal output unit respectively and dynamically adjust the first phase of the first control signal and the second phase of the second control signal in real time. According to the scheme of the invention, the phase of the control signal can be dynamically adjusted, so that different phases can be set in a short time, the test preparation time is shortened, and the overall test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a dual-channel arbitrary waveform generator and a triggering method. Background Art

[0002] Common multi-channel function (arbitrary signal) generators have a phase adjustment function, but it is manually adjusted under observation with an oscilloscope. In the field of integrated circuit testing, this manual phase adjustment method has certain limitations; and common multi-channel function (arbitrary signal) generators rely on source clocks and can only achieve synchronous output functions but cannot dynamically adjust the phase. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a dual-channel arbitrary waveform generator and a triggering method to dynamically adjust the phase of a control signal to achieve different phase settings in a short time, thereby shortening the test preparation time and improving the overall test efficiency.

[0004] In order to solve the above technical problems, an embodiment of the present invention provides a dual-channel arbitrary waveform generator, comprising:

[0005] A first signal output unit, used to generate and output a first control signal;

[0006] A second signal output unit, configured to generate and output a second control signal; and

[0007] A comparison phase detection unit, wherein the comparison phase detection unit is connected to the first signal output unit and the second signal output unit respectively, and is used to compare and output the phase difference between the first control signal and the second control signal, and feed back to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit can respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically.

[0008] In one embodiment, the comparison phase detection unit comprises:

[0009] a comparator circuit, the comparator circuit being electrically connected to the first signal output unit and the second signal output unit, and configured to compare the first control signal with the second control signal and convert the first control signal into a third control signal in a preset format and convert the second control signal into a fourth control signal in a preset format; and

[0010] A phase detection circuit is electrically connected to the comparator circuit and is used to measure a phase difference between the third control signal and the fourth control signal.

[0011] In one embodiment, the comparator circuit comprises:

[0012] a first comparator, wherein a positive input terminal of the first comparator is connected to a first low-pass filter in the first signal output unit, and an output terminal of the first comparator is connected to the phase detection circuit; and

[0013] A second comparator, wherein a positive input terminal of the second comparator is connected to a second low-pass filter in the second signal output unit, and an output terminal of the second comparator is connected to the phase detection circuit;

[0014] In one embodiment, both the first comparator and the second comparator are zero-crossing comparators.

[0015] In one embodiment, the phase detection circuit comprises:

[0016] a first D flip-flop, wherein a first clock input terminal of the first D flip-flop is connected to an output terminal of the first comparator;

[0017] a second D flip-flop, wherein a second clock input terminal of the second D flip-flop is connected to the output terminal of the second comparator, and a second data input terminal of the second D flip-flop is connected to the first output terminal of the first D flip-flop;

[0018] an XOR gate module, wherein a first input terminal of the XOR gate module is connected to an output terminal of the first comparator, and a second input terminal of the XOR gate module is connected to an output terminal of the second comparator; and

[0019] A third D flip-flop, wherein a third clock input terminal of the third D flip-flop is connected to the output terminal of the XOR gate module.

[0020] In one embodiment, the first signal output unit includes: a first phase accumulator, a first waveform data storage device, a first DAC digital-to-analog converter, and a first low-pass filter, which are connected in sequence; wherein the output end of the first low-pass filter is connected to the input end of the first comparator in the comparison phase detection unit, the first phase accumulator is connected to the phase detection circuit in the comparison phase detection unit through a first functional module, and the first phase accumulator provides a first clock signal through a first clock circuit, and generates a first control signal according to the frequency of the first clock signal.

[0021] In one embodiment, the first signal output unit further includes a first amplitude adjustment module and a first offset adjustment module.

[0022] In one embodiment, the second signal output unit includes: a second phase accumulator, a second waveform data storage, a second DAC digital-to-analog converter and a second low-pass filter connected in sequence; wherein the output end of the second low-pass filter is connected to the input end of the second comparator in the comparison phase detection unit, the second phase accumulator is connected to the phase detection circuit in the comparison phase detection unit through a second functional module, and the second phase accumulator provides a second clock signal through a second clock circuit, and generates a second control signal according to the frequency of the second clock signal.

[0023] In one embodiment, the second signal output unit further includes a second amplitude adjustment module and a second offset adjustment module.

[0024] An embodiment of the present invention further provides a triggering method for a dual-channel arbitrary waveform generator, comprising:

[0025] Generate and output a first control signal through a first signal output unit;

[0026] Generate and output a second control signal through a second signal output unit;

[0027] The first control signal and the second control signal are received by a comparison phase detector, and the first control signal and the second control signal are converted and detected, and the phase difference between the first control signal and the second control signal is compared and calculated, and the phase difference is fed back to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically.

[0028] The above solution of the present invention includes at least the following beneficial effects:

[0029] The above-mentioned scheme of the present invention provides a dual-channel arbitrary waveform generator and a triggering method, wherein the generator includes: a first signal output unit for generating and outputting a first control signal; a second signal output unit for generating and outputting a second control signal; a comparison phase detection unit, the comparison phase detection unit is connected to the first signal output unit and the second signal output unit respectively, and is used to compare and output the phase difference between the first control signal and the second control signal, and feed back to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically. The scheme of the present invention can dynamically adjust the phase of the control signal to achieve different phase settings in a short time, thereby shortening the test preparation time and improving the overall test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of the module frame of a dual-channel arbitrary waveform generator provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of the circuit structure of a comparison and phase discrimination unit provided by an optional embodiment of the present invention;

[0032] Figure 3 is a comparison diagram of signal waveforms before and after being processed by an input comparator and output after being processed by the comparator provided by an optional embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of a partial structure of a phase discrimination circuit provided by an optional embodiment of the present invention;

[0034] Figure 5 is a comparison diagram of signal waveforms before and after being processed by first and second D flip-flops and output after being processed by the first and second D flip-flops provided by an optional embodiment of the present invention;

[0035] Figure 6 is a waveform diagram of the output signal of an exclusive-OR gate module provided by an optional embodiment of the present invention. Detailed implementation manners

[0036] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0037] In the following description, certain specific details are set forth for the purpose of explaining various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments can be practiced without one or more of these specific details. In other instances, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail so as not to unnecessarily obscure the description of the embodiments.

[0038] The reference to "one embodiment" or "an embodiment" throughout the specification means that the particular features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily all refer to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0039] In the following description, in order to clearly show the structure and working mode of the present invention, many directional words will be used for description, but the words "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

[0040] like Figure 1 As shown, an embodiment of the present invention provides a dual-channel arbitrary waveform generator, including a first signal output unit, a second signal output unit and a comparison phase detector unit. The first signal output unit is used to generate and output a first control signal; the second signal output unit is used to generate and output a second control signal; the comparison phase detector unit is connected to the first signal output unit and the second signal output unit respectively, and is used to compare and output the phase difference between the first control signal and the second control signal, and feed back to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically.

[0041] In this embodiment, the first control signal and the second control signal may be sinusoidal wave signals, and the frequencies of the first control signal and the second control signal when they are generated and output are determined; the comparison phase detection unit may receive the first control signal and the second control signal respectively, and when the first control signal is input to the comparison phase detection unit, the comparison phase detection unit will generate a first jump at the rising edge of the first control signal, and output a first logic level change corresponding to the first control signal to generate a first trigger signal; when the second control signal is input to the comparison phase detection unit, the comparison phase detection unit will generate a second jump at the rising edge of the second control signal, and output a second logic level change corresponding to the second control signal to generate a second trigger signal; in the comparison phase detection unit, according to the time interval between the received first trigger signal and the second trigger signal and the frequency of the first control signal and the second control signal when they are output, the phase difference between the first control signal and the second control signal can be determined, and then the phase difference is fed back to the first signal output unit and the second signal output unit to realize dynamic adjustment of the phase of the corresponding control signal, so that the generator can realize different phase settings in a short time, thereby shortening its test preparation time and improving the overall test efficiency.

[0042] In actual phase alignment or compensation applications, the phase difference can be used as an error signal to calculate the proportional term, integral term, and differential term respectively. The proportional term directly produces a control effect based on the current phase difference, so that the phase quickly approaches the target value; the integral term is used to eliminate the long-standing static phase error to ensure that accurate phase alignment can be achieved in the end; the differential term can predict the changing trend of the phase difference and make adjustments in advance to improve the dynamic response performance and stability of the system. Here, by adjusting the parameters of the PID algorithm (proportional coefficient, integral time constant, and differential time constant), the phase adjustment process can be optimized to adapt to different system requirements and dynamic characteristics.

[0043] In an optional embodiment of the present invention, the first signal output unit includes: a first phase accumulator, a first waveform data storage device, a first DAC digital-to-analog converter, and a first low-pass filter connected in sequence; wherein the output end of the first low-pass filter is connected to the input end of the first comparator in the comparison phase detection unit, the first phase accumulator is connected to the phase detection circuit in the comparison phase detection unit through the first functional module, and the first phase accumulator provides a first clock signal through the first clock circuit, and generates a first control signal according to the frequency of the first clock signal.

[0044] In this embodiment, the first functional module can be an oscilloscope and is connected to the comparison phase detection unit; the first phase accumulator is composed of an N-bit adder and an N-bit register; in each clock cycle, the phase increment word is added to the value of the register, and as the clock continues to advance, the value of the phase accumulator continues to increase, thereby achieving linear growth of the phase.

[0045] The first waveform data memory stores a period of waveform data, such as a sine wave, and its address line is connected to the phase accumulator. When the value of the phase accumulator changes, it will be used as an address to find the corresponding waveform amplitude value in the memory to convert the phase information into waveform amplitude information, thereby obtaining the desired waveform.

[0046] The first DAC digital-to-analog converter converts the digital amplitude value output from the first waveform data memory into an analog signal. The resolution of the first DAC digital-to-analog converter determines the accuracy of the output signal. For example, a 1-bit DAC can convert a digital signal into an analog signal with discrete levels.

[0047] Since the signal output by the first DAC digital-to-analog converter contains high-frequency components (such as the sampling frequency and its harmonics, etc.), it is necessary to filter out these unnecessary frequency components through the first low-pass filter to obtain a pure analog signal of the required frequency; at the same time, the first low-pass filter is connected to the comparison phase detection unit to facilitate the subsequent detection and adjustment of the phase of the first control signal.

[0048] Furthermore, the first signal output unit may further include a first amplitude adjustment module and a first bias adjustment module.

[0049] In this embodiment, the first amplitude adjustment module is used to change the amplitude of the first control signal to meet the requirements of different loads or subsequent processing circuits for the signal amplitude; for example, in an audio system, in order to match speakers with different powers, it is necessary to adjust the amplitude of the audio signal to avoid sound distortion or insufficient volume caused by too large or too small signal amplitude.

[0050] Here, the adjustment of the amplitude of the first control signal can be achieved in various ways; for example, a variable gain amplifier (VGA) is used after the first DAC digital-to-analog converter, and the gain of the VGA can be adjusted by an external control voltage or a digital signal; or, in a communication system, according to the voltage-gain characteristic curve, the gain value can be precisely adjusted by changing the control voltage.

[0051] The first bias adjustment module is used to set the DC bias level of the first control signal to ensure that the first control signal is in a suitable operating range for the subsequent circuit; for example, in some sensor signal processing circuits, the weak signal output by the sensor may require a specific bias to be effectively amplified by the subsequent amplifier, and a suitable bias helps to avoid problems such as clipping distortion during signal processing.

[0052] Here, the setting of the DC bias level of the first control signal is achieved by adding a DC bias circuit to the path of the first control signal. For example, an adder circuit composed of operational amplifiers can be used to add a suitable DC voltage to the signal; in some systems that need to process AC-coupled signals, bias adjustment can raise or lower the signal level to a suitable operating range for subsequent circuits to process correctly.

[0053] Furthermore, the first control signal after being set can be output and amplified through the first output driving module so that the first control signal can successfully drive the subsequent load. For example, in a radar transmission system, the first output driving module needs to provide a sufficiently large power signal for the antenna so that electromagnetic waves can be effectively radiated.

[0054] Here, the first output driving module can be a circuit such as a power amplifier. For a power amplifier, it achieves power amplification by adopting different topological structures (such as Class A, Class B, Class AB, Class D, etc.). Taking the Class AB power amplifier as an example, it combines the advantages of Class A and Class B, and makes the transistor conduct for most of the signal cycle through appropriate biasing, so as to effectively amplify the signal power.

[0055] In an optional embodiment of the present invention, the second signal output unit includes: a second phase accumulator, a second waveform data storage device, a second DAC digital-to-analog converter, and a second low-pass filter connected in sequence; wherein the output end of the second low-pass filter is connected to the input end of the second comparator in the comparison phase detection unit, the second phase accumulator is connected to the phase detection circuit in the comparison phase detection unit through a second functional module, and the second phase accumulator provides a second clock signal through a second clock circuit, and generates a second control signal according to the frequency of the second clock signal.

[0056] Furthermore, the second signal output unit may also include a second amplitude adjustment module and a second offset adjustment module.

[0057] In this embodiment, the second functional module may also be an oscilloscope, and is connected to the comparison phase detector unit; the second low-pass filter is connected to the comparison phase detector unit to facilitate the subsequent detection and adjustment of the phase of the second control signal. Here, the processing and action process of the second control signal by other functional modules in the second signal output unit (second phase accumulator, second waveform data storage, second DAC digital-to-analog converter, second amplitude adjustment module, second offset adjustment module and second output drive module) is the same as the processing and action process of the first signal output unit, and will not be repeated here.

[0058] In an optional embodiment of the present invention, the comparison phase detection unit includes a comparator circuit and a phase detection circuit. The comparator circuit is electrically connected to the first signal output unit and the second signal output unit, and is used to compare the first control signal with the second control signal and convert the first control signal into a third control signal of a preset format and convert the second control signal into a fourth control signal of a preset format; the phase detection circuit is electrically connected to the comparator circuit and is used to measure the phase difference between the third control signal and the fourth control signal.

[0059] In this embodiment, the comparator circuit mainly converts the first control signal and the second control signal transmitted by the first low-pass filter and the second low-pass filter into signals that can be recognized by the phase detection circuit, and generates a trigger signal accordingly for the phase detection circuit to detect; it should be known that the control signal that needs to detect the phase difference needs to be input into the comparator circuit before the amplitude is adjusted to obtain a square wave signal that can be recognized by the phase detection circuit (such as Figure 3 ), and then perform detection and phase adjustment.

[0060] like Figure 2As shown, in an optional embodiment of the present invention, the comparator circuit includes a first comparator U1A and a second comparator U1B. The positive input terminal of the first comparator U1A is connected to the first low-pass filter in the first signal output unit, and the output terminal of the first comparator U1A is connected to the phase detection circuit; the positive input terminal of the second comparator U1B is connected to the second low-pass filter in the second signal output unit, and the output terminal of the second comparator U1B is connected to the phase detection circuit.

[0061] In this embodiment, when the first control signal A and the second control signal B are respectively input into the first comparator U1A and the second comparator U1B; the first comparator U1A generates a first jump at the rising edge of the first control signal A; for example, when the voltage of the first control signal A is higher than (or lower than, depending on the type of comparator) its reference voltage, the first comparator U1A outputs a corresponding first logic level change and serves as a first trigger signal; the second comparator U1B generates a second jump at the rising edge of the first control signal B; for example, when the voltage of the second control signal B is higher than (or lower than, depending on the type of comparator) its reference voltage, the second comparator U1B outputs a corresponding first logic level change and serves as a second trigger signal for detection by the phase detector circuit;

[0062] Preferably, both the first comparator U1A and the second comparator U1B are zero-crossing comparators to improve the accuracy and stability of the measurement.

[0063] Preferably, the comparator circuit also includes four resistors and four diodes; wherein the resistor R1 is connected in series between the output end of the first low-pass filter and the positive input end of the first comparator U1A, the resistor R2 is connected in series between the output end of the second low-pass filter and the positive input end of the second comparator U1B, the resistor R3 is connected in parallel with the output end of the first comparator U1A, and the resistor R4 is connected in parallel with the output end of the second comparator U1B; the diode D1 is connected in series with the diode D2, and the first end of the diode D2 is electrically connected between the resistor R1 and the positive input end of the first comparator U1A, and the second end of the diode D1 is electrically connected between the resistor R1 and the positive input end of the first comparator U1A; the diode D3 is connected in series with the diode D4, and the first end of the diode D4 is electrically connected between the resistor R2 and the positive input end of the second comparator U1B, and the second end of the diode D3 is electrically connected between the resistor R2 and the positive input end of the second comparator U1B.

[0064] like Figure 2As shown, in an optional embodiment of the present invention, the phase detection circuit includes a first D flip-flop U2A, a second D flip-flop U2B, an XOR gate module U3A and a third D flip-flop U4A. Among them, the first clock input terminal of the first D flip-flop U2A is connected to the output terminal of the first comparator U1A; the second clock input terminal of the second D flip-flop U2B is connected to the output terminal of the second comparator U1B, and the second data input terminal of the second D flip-flop U2B is connected to the first output terminal of the first D flip-flop U2A; the first input terminal of the XOR gate module U3A is connected to the output terminal of the first comparator U1A, and the second input terminal of the XOR gate module U3A is connected to the output terminal of the second comparator U1B; the third clock input terminal of the third D flip-flop U4A is connected to the output terminal of the XOR gate module U3A.

[0065] In this embodiment, the first D flip-flop U2A and the second D flip-flop U2B form a phase difference capture circuit.

[0066] like Figure 4 As shown, the a terminal (the first clock input terminal of the first D flip-flop U2A) is connected to the output terminal of the first comparator U1A, and the b terminal (the second clock input terminal of the second D flip-flop U2B) is connected to the output terminal of the second comparator U1B. After reset, the outputs of the first D flip-flop U2A and the second D flip-flop U2B are both low level. After the rising edge of the a terminal arrives, the Rising_at output becomes high level, and after the rising edge of the b terminal arrives, the Rising_b output becomes high level, and the b terminal signal is detected only after the rising edge of the a terminal arrives first;

[0067] like Figure 5 As shown, by measuring the time between the dotted lines, the rising edge interval time of the first control signal and the second control signal can be obtained; further, when the frequencies of the first control signal and the second control signal are known, the phase difference between the first control signal and the second control signal can be calculated based on the period and the rising edge interval time.

[0068] Preferably, the phase detection circuit also includes a bidirectional switch S1. Since the two input ends of the XOR gate module U3A are respectively connected to the output ends of the first comparator U1A and the second comparator U1B, when the signal level states input from the two comparators are inconsistent, the XOR gate module U3A will output a pulse, such as Figure 6 As shown, by capturing the rising edge of the output of the XOR gate module U3A, it is possible to know whether there is a phase difference between the two input signals; when there is a phase difference between the two input signals, the bidirectional switch S1 is grounded to detect the phase difference, and when there is no phase difference between the two input signals, the bidirectional switch S1 is placed at the power supply, and phase detection is no longer performed.

[0069] An embodiment of the present invention further provides a triggering method for a dual-channel arbitrary waveform generator, comprising:

[0070] Step 11, generating and outputting a first control signal through a first signal output unit;

[0071] Step 12, generating and outputting a second control signal through a second signal output unit;

[0072] Step 13, receiving the first control signal and the second control signal through a comparison phase detection unit, converting and detecting the first control signal and the second control signal, comparing and calculating the phase difference between the first control signal and the second control signal, and feeding back the phase difference to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically.

[0073] In this embodiment, the first control signal and the second control signal are converted and processed by two comparators of the comparison circuit in the comparison phase detection unit, and a trigger signal is generated, so that the phase detection circuit in the comparison phase detection unit detects the rising interval time of the first control signal and the second control signal, thereby realizing the phase difference detection of the two signals;

[0074] Since the frequencies of the first control signal and the second control signal are known, their periods are also fixed (assuming that the period of the first control signal A is T A , the period of the second control signal B is T B , in the same generator, T A =T B =T). There is a specific relationship between the measured rising edge interval time Δt and the signal period T, so the phase difference The formula can be (degree system) calculated.

[0075] Furthermore, the phase adjustment word is modified according to the measured phase difference: since the phase of the output signal is controlled by its internal phase accumulator, and the input of the phase accumulator includes the phase increment word (determines the frequency) and the initial phase word. In this case, the phase can be adjusted by modifying the initial phase word of one of the channels;

[0076] When the measurement results show that the phase difference is According to the phase-digital relationship (assuming the resolution of the phase control word is ), calculate the phase control word that needs to be adjusted Furthermore, the phase control word ΔP to be adjusted is added to the current phase control word, thereby achieving phase adjustment.

[0077] The above scheme of the present invention can realize dynamic adjustment of the phase of the generator output control signal by comparing the phase detection unit, and then can realize different phase settings in a short time, which greatly shortens the test preparation time compared with the traditional manual or fixed phase signal source. In large-scale integrated circuit testing, the test under different phase conditions can be completed faster, improving the overall test efficiency;

[0078] At the same time, dynamically adjusting the phase, frequency and amplitude can simulate a wider range of actual working scenarios, increase the diversity of test cases, improve test coverage, help discover more potential design defects and failure modes, and ensure that integrated circuits can work normally under various complex conditions. For example, when testing the performance of integrated circuits in a multipath fading environment, the phase and other parameters of the dual-channel DDS can be adjusted to simulate different signal reflection paths, thereby more comprehensively evaluating the chip's anti-interference ability;

[0079] In addition, the generator of the present invention can replace multiple single-function signal source devices, reducing the number and complexity of hardware devices in the test system, reducing hardware procurement costs, reducing the connection and calibration work between devices, and reducing maintenance costs and the risk of failure caused by equipment compatibility issues.

[0080] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0081] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A dual-channel arbitrary waveform generator, characterized in that: include: A first signal output unit, used to generate and output a first control signal; A second signal output unit, used to generate and output a second control signal; as well as A comparison phase detection unit, wherein the comparison phase detection unit is connected to the first signal output unit and the second signal output unit respectively, and is used to compare and output the phase difference between the first control signal and the second control signal, and feed back to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit can respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically.

2. The dual-channel arbitrary waveform generator according to claim 1, characterized in that: The comparison phase detection unit comprises: a comparator circuit, the comparator circuit being electrically connected to the first signal output unit and the second signal output unit, and configured to compare the first control signal with the second control signal and convert the first control signal into a third control signal in a preset format and convert the second control signal into a fourth control signal in a preset format; and A phase detection circuit is electrically connected to the comparator circuit and is used to measure a phase difference between the third control signal and the fourth control signal.

3. The dual-channel arbitrary waveform generator according to claim 2, characterized in that: The comparator circuit comprises: a first comparator, wherein a positive input terminal of the first comparator is connected to a first low-pass filter in the first signal output unit, and an output terminal of the first comparator is connected to the phase detection circuit; and A second comparator, wherein the positive input terminal of the second comparator is connected to the second low-pass filter in the second signal output unit, and the output terminal of the second comparator is connected to the phase detection circuit.

4. The dual-channel arbitrary waveform generator according to claim 3, characterized in that: The first comparator and the second comparator are both zero-crossing comparators.

5. The dual-channel arbitrary waveform generator according to claim 3, characterized in that: The phase detection circuit comprises: a first D flip-flop, wherein a first clock input terminal of the first D flip-flop is connected to an output terminal of the first comparator; a second D flip-flop, wherein a second clock input terminal of the second D flip-flop is connected to the output terminal of the second comparator, and a second data input terminal of the second D flip-flop is connected to the first output terminal of the first D flip-flop; an XOR gate module, wherein a first input terminal of the XOR gate module is connected to an output terminal of the first comparator, and a second input terminal of the XOR gate module is connected to an output terminal of the second comparator; and A third D flip-flop, wherein a third clock input terminal of the third D flip-flop is connected to the output terminal of the XOR gate module.

6. The dual-channel arbitrary waveform generator according to claim 1, characterized in that: The first signal output unit includes: a first phase accumulator, a first waveform data storage device, a first DAC digital-to-analog converter and a first low-pass filter, which are connected in sequence; wherein the output end of the first low-pass filter is connected to the input end of the first comparator in the comparison phase detection unit, the first phase accumulator is connected to the phase detection circuit in the comparison phase detection unit through a first functional module, and the first phase accumulator provides a first clock signal through a first clock circuit, and generates a first control signal according to the frequency of the first clock signal.

7. The dual-channel arbitrary waveform generator according to claim 6, characterized in that: The first signal output unit further includes a first amplitude adjustment module and a first offset adjustment module.

8. The dual-channel arbitrary waveform generator according to claim 1, characterized in that: The second signal output unit includes: a second phase accumulator, a second waveform data storage device, a second DAC digital-to-analog converter and a second low-pass filter, which are connected in sequence; wherein the output end of the second low-pass filter is connected to the input end of the second comparator in the comparison phase detection unit, the second phase accumulator is connected to the phase detection circuit in the comparison phase detection unit through a second functional module, and the second phase accumulator provides a second clock signal through a second clock circuit, and generates a second control signal according to the frequency of the second clock signal.

9. The dual-channel arbitrary waveform generator according to claim 8, characterized in that: The second signal output unit further includes a second amplitude adjustment module and a second offset adjustment module.

10. A triggering method for a dual-channel arbitrary waveform generator, characterized in that: include: Generate and output a first control signal through a first signal output unit; Generate and output a second control signal through a second signal output unit; The first control signal and the second control signal are received by a comparison phase detector unit, and the first control signal and the second control signal are converted and detected, and the phase difference between the first control signal and the second control signal is compared and calculated, and fed back to the first signal output unit and the second signal output unit respectively, so that the first signal output unit and the second signal output unit can respectively adjust the first phase of the first control signal and the second phase of the second control signal in real time and dynamically.

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