Ixinjiang machine

Abstract

The invention discloses an Isin machine which comprises N nodes for simulating spinning, a spinning state register, a processor and an input signal generating circuit. Each node generates a digital signal based on an input analog signal, the probability that the output digital signal is 1 being determined by the input analog signal. And the processor obtains the spinning of the N nodes after the mth iteration. The processor calculates a target input value for each node based on the spin of the N nodes. The processor determines an input signal combination Inm + 1 (In1m + 1, In2m + 1,... Innm + 1) and a corresponding criterion according to the target input value. Each of In1m + 1, In2m + 1, to Innm + 1 is selected from a first candidate input analog signal and a second candidate input analog signal. The input signal combinations are sequentially input to nodes, and the processor obtains n output digital signals from each node. And if the output digital signal output by the node is the same as the judgment standard, the spin of the node after (m + 1) th iteration is judged to be a first value, otherwise, the spin of the node is judged to be a second value. According to the invention, the number of digital-to-analog converters is reduced.

Description

Technical Field

[0001] The present application generally relates to the field of computer technology, and more particularly to an Ising machine. Background Art

[0002] NP-complete problems are widely used in artificial intelligence, transportation, network communications, economics, molecular biology and other fields. Computers with traditional von Neumann architectures are difficult to efficiently handle NP-complete problems. Ising machine is a solution to NP-complete problems. By mapping NP-complete problems into Ising models, the optimal solution to NP-complete problems is converted into the solution of finding the ground state (lowest energy state) of the Ising model.

[0003] Existing Ising machines include: Ising machines based on superconducting circuits (for example, D-Wave quantum annealing system), coupled Ising machines based on optically coupled circuits, Ising machines based on complementary metal-oxide-semiconductor (CMOS), and Ising machines based on magnetic tunnel junctions (MTJ).

[0004] Both the Ising machine based on superconducting circuits and the coupled Ising machine based on optically coupled circuits require complex and expensive hardware. The Ising machine based on CMOS and the Ising machine based on MTJ can be implemented based on existing semiconductor manufacturing processes, so they have better industrial prospects. Compared with the Ising machine based on CMOS, the circuit unit for generating random numbers in the MTJ-based Ising machine is simpler, and the number of transistors used is greatly reduced. The Ising machine needs to be further optimized, such as reducing hardware costs and improving computing efficiency. Summary of the invention

[0005] The embodiment of the present application provides an Ising machine, which reduces the hardware cost of the Ising machine.

[0006] The Ising machine includes: N nodes, a spin state register, a processor, and an input signal generating circuit. The N nodes are used to simulate N spins, where N is an integer greater than 1. Each node generates an output digital signal based on an input analog signal, and the probability P that the output digital signal is 1 is determined by the input analog signal. The spin state register is used to store the spins of the N nodes. The spin of the node is one of a first value and a second value, one of the first value and the second value is +1, and the other of the first value and the second value is -1. The processor is connected to the output ends of the N nodes. The input signal generating circuit is connected to the input ends of the N nodes, and is used to generate a first candidate input analog signal and a second candidate input analog signal corresponding to each node.

[0007] The m+1th iteration process of the N nodes comprises the following steps: the processor obtains the spins of the N nodes after the mth iteration from the spin state register, where m is an integer greater than 0. the processor determines the target input value IN of each node according to the spins of the N nodes after the mth iteration m+1 The processor generates a signal according to the target input value IN m+1 Determine the input signal combination In of each node m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard. The input signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) includes a first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 , n is an integer greater than 1. The first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 Each of the first candidate input analog signal and the second candidate input analog signal is selected from one of the first candidate input analog signal and the second candidate input analog signal. The input signal generating circuit converts the first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 The processor sequentially inputs the n output digital signals to the corresponding nodes, and obtains n output digital signals from each node. If the n output digital signals obtained from the node are the same as the spin judgment standard, the processor determines that the spin of the node after the m+1th iteration is the first value; if the n output digital signals obtained from the node are different from the spin judgment standard, the processor determines that the spin of the node after the m+1th iteration is the second value.

[0008] In some embodiments, the input analog signal is an input analog voltage, and the node includes: a random magnetic tunnel junction, a transistor, a resistor, and a comparator, wherein the random magnetic tunnel junction, the transistor, and the resistor are connected in series between a power supply terminal and a ground, a gate of the transistor receives the input analog voltage, a drain of the transistor is connected to a first input terminal of the comparator, a second input terminal of the comparator receives a reference voltage, and an output terminal of the comparator serves as an output terminal of the node.

[0009] In some embodiments, the first candidate input analog signal and the second candidate input analog signal are analog voltage signals, or the first candidate input analog signal and the second candidate input analog signal are analog current signals.

[0010] In some embodiments, when the input analog signal of the node is the first candidate input analog signal, the probability P1 that the output digital signal of the node is 1 is greater than 50%; when the input analog signal of the node is the second candidate input analog signal, the probability P2 that the output digital signal of the node is 1 is less than 50%.

[0011] In some embodiments, the processor determines the target input value IN of node i according to the spins of the N nodes and the following formula: m+1 , 1≤i≤N,

[0012] IN m+1 =∑J ij σ jm +h i

[0013] Among them, h i is the external magnetic field coefficient of the node i, J ij is the interaction coefficient between the node i and the node j, σ jm is the spin of the node j after the mth iteration, 1≤j≤N, j≠i.

[0014] In some embodiments, the Ising machine also includes a memory, which stores a first lookup table for each node, the first lookup table including multiple entries, each of which is (probability P*, candidate input signal combination, candidate spin judgment criterion), wherein the candidate input signal combination includes n input signals, each input signal is selected from one of a first candidate input analog signal and a second candidate input analog signal, and when the n input signals are input to the node in sequence, the probability that the n output digital signals output by the node are equal to the candidate spin judgment criterion is P*.

[0015] The processor determines the input signal combination In by the following method m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard: the processor determines the probability P m+1 , where the probability P m+1 is when the target input value IN m+1 The probability that the output digital signal of the node is 1 when the corresponding analog signal is input to the node; and the processor determines the probability P in the first lookup table m+1The closest probability P* is obtained, and the candidate input signal combination and the candidate spin judgment standard corresponding to the closest probability P* are used as the input signal combination and the spin judgment standard.

[0016] In some embodiments, the memory further stores a second lookup table for each node, and the processor determines the probability P according to the second lookup table. m+1 .

[0017] In some embodiments, the Ising machine further includes a memory storing a third lookup table for each node, wherein the third lookup table includes a plurality of entries, each of which is (input analog signal value, candidate input signal combination, candidate spin judgment criterion).

[0018] The processor calculates the target input value IN according to the third lookup table and the target input value IN m+1 Determine the input signal combination In of the node m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and spin judgment criteria.

[0019] In some embodiments, the first candidate input analog signal and the second candidate input analog signal are analog voltage signals, and the input signal generating circuit includes a Bandgap circuit, and the Bandgap circuit is used to generate the first candidate input analog signal and the second candidate input analog signal.

[0020] In some embodiments, the N nodes simultaneously input the corresponding first input signal In1 m+1 , the N nodes simultaneously input the corresponding second input signal In2 m+1 , the N nodes simultaneously input the corresponding nth input signal Inn m+1 .

[0021] The Ising machine of the present application implements the iteration of the Ising model by providing n input analog signals to the node, where n is an integer greater than 1. The spin of the node after iteration is determined according to the n output digital signals output by the node. The n input analog signals of each iteration are selected from the first candidate input analog signal and the second candidate input analog signal. In this way, it is only necessary to set an analog circuit for generating the two candidate input analog signals for each node, and there is no need to set a high-precision digital-to-analog converter for each node, thereby reducing the hardware cost of the Ising machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0023] Figure 1 shows a block diagram of an exemplary Ising machine of the present invention;

[0024] Figure 2 An exemplary node array of the present invention is shown;

[0025] Figure 3 shows the input and output of an exemplary node of the present invention;

[0026] Figure 4 Shows Figure 2 Two nodes interacting with each other;

[0027] Figure 5 A circuit diagram showing an exemplary node of the present invention;

[0028] Figure 6 It is shown that the free layer of the magnetic tunnel junction is randomly in the parallel state and the antiparallel state under the influence of thermal noise;

[0029] Figure 7 The relationship curve between the probability that the output digital signal of the node is 1 and the input analog signal is shown;

[0030] Figure 8 A circuit diagram showing another exemplary node of the present invention;

[0031] Fig. 9 An exemplary input signal generating circuit of the present invention is shown;

[0032] Fig.10 An exemplary method of operating the Ising machine of the present invention is shown;

[0033] Fig.11 shows the timing of input signal combinations and n output digital signals;

[0034] Fig.12 An output unit of an exemplary input signal generating circuit of the present invention is shown; and

[0035] Fig.13 Another exemplary operation method of the Ising machine of the present invention is shown. DETAILED DESCRIPTION

[0036] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are all for illustrative purposes and that the drawings are not necessarily drawn to scale.

[0037] It should be understood that when an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it can be directly connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly connected to" another element, it means that there is no intermediate element between the two.

[0038] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0039] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0040] The Ising model was proposed by Wilhelm Lenz and his student Ernst Ising in 1920 to study the relationship between the spin state of particles in ferromagnetic materials and the macroscopic magnetic moment. Formula (1) is the energy formula of the Ising model involving N spins.

[0041]

[0042] σ i Represents the i-th spin, and its value is "-1" or "+1". "-1" means the spin direction is downward, and "+1" means the spin direction is upward. ij is the interaction coefficient between the ith spin and the jth spin, h i is the external magnetic field coefficient of the i-th spin. The Ising model is self-convergent and can gradually converge to the spin state that makes the system energy E the lowest through iteration under the interaction between spins and the external magnetic field. Each iteration updates the spin σ of each node. i .

[0043] The Ising model is used to solve NP problems such as combinatorial optimization. The state with the minimum energy E corresponds to the solution of the NP problem. The number of spins determines the size of the problem that can be mapped and solved. Computers with traditional von Neumann architecture can usually only obtain local optimal solutions. Solving the Ising model can obtain global optimal solutions. The Ising model can be simulated using a physical system, usually called an Ising machine or a Boltzmann machine.

[0044] The parameters in the combinatorial optimization problem in the actual scenario need to be mapped to the spin state of the spin particles in the Ising model. How to map the parameters in the actual problem to the spin state of the spin particles in the Ising model can be referred to A. Lucas. Ising formulations of many NP problems. Frontiers in Physics, 2014.

[0045] Figure 1 The structural block diagram of an exemplary Ising machine of the present application is shown. The Ising machine comprises: a node array 10, a processor 21, an input signal generating circuit 22, a memory 23, and a spin state register 24. The node array 10 is used to simulate the above-mentioned Ising model.

[0046] Figure 2 An exemplary node array 10 of the present application is shown. The node array 10 includes N nodes, where N is a positive integer greater than or equal to 2. Each node is used to simulate a spin particle. Each node has the following information: spin direction, other interacting nodes and interaction coefficients, and external magnetic field coefficients. The spin σ of the node is stored in the spin state register 24. The value of the spin σ of the node is one of a first value and a second value. One of the first value and the second value is +1, and the other of the first value and the second value is -1. If the spin direction of the node is upward, σ is equal to +1, and if the spin direction of the node is downward, σ is equal to -1. In the solution process of the Ising model, each iteration will update the node spin σ stored in the spin state register 24. The information of the interacting nodes and interaction coefficients, and the external magnetic field coefficients is stored in the memory 23 and called in the solution process of the Ising model.

[0047] Each node has an input terminal and an output terminal. The output terminal of the node is connected to a processor 21. The input terminal of the node is connected to an input signal generating circuit 22. The processor 21 is, for example, a microcontroller, a dedicated integrated chip, an FPGA, etc. The input signal generating circuit 22 is used to provide an input analog signal to the node. The input analog signal can be an analog voltage signal or an analog current signal. Figure 3As shown, each node generates an output digital signal. The output digital signal is 1 bit, and its value is 0 or 1. The probability P of the output digital signal taking the value of 1 depends on the input analog signal. Therefore, the output digital signal of the node is a probabilistic bit (p-bit).

[0048] Each node in the node array 10 can interact with one or more other nodes. The "interaction" mentioned above means that there is an interaction coefficient. Figure 4 Shows Figure 2 Consider two example nodes i and j that interact with each other. The spin of node i is σ i , the external magnetic field coefficient of node i is h i , the spin of node j is σ j , the external magnetic field coefficient of node j is h j , J ij is the interaction coefficient between node i and node j.

[0049] In the process of solving the Ising model, the processor 21 obtains the output digital signal of each node, determines the updated value of the spin σ of each node, determines the input signal combination used by each node in the next iteration, and controls the input signal generating circuit 22 to input the input signal combination to the corresponding node. This cycle is repeated until the Ising model converges.

[0050] exist Figure 2 In one example, each node interacts with other nodes adjacent to the left and right, adjacent to the top and bottom, and adjacent to the diagonal. In another example, each node interacts with all other nodes. In another example, each node interacts with other nodes adjacent to the left and right and adjacent to the top and bottom. The number of nodes N and which nodes interact can be set according to the problem to be solved and the accuracy requirements.

[0051] Figure 5 An exemplary circuit diagram of a node according to an embodiment of the present application is shown. Figure 5 The input analog signal of the node shown is an analog voltage signal Vin. Figure 5As shown, the node includes: a stochastic magnetic tunnel junction 110, a transistor 120, a resistor R, and a comparator 130. The stochastic magnetic tunnel junction 110, the transistor 120, and the resistor R are connected in series between the power supply terminal VDD and the ground. The transistor 120 is, for example, an NMOS transistor. The gate of the transistor 120 receives the input voltage Vin. The resistor R is arranged between the source of the transistor 120 and the ground. The stochastic magnetic tunnel junction 110 is arranged between the drain of the transistor 120 and VDD. The drain of the transistor 120 is connected to the first input terminal of the comparator 130. The second input terminal of the comparator 130 receives the reference voltage Vref. The first input terminal is one of the in-phase input terminal and the inverting input terminal, and the second input terminal is the other of the in-phase input terminal and the inverting input terminal. The comparator 130 is used to compare the drain voltage Vo of the transistor 120 with the reference voltage Vref. The gate of the transistor 120 serves as the input terminal of the node, and the output terminal OUT of the comparator 130 serves as the output terminal of the node.

[0052] The random magnetic tunnel junction 110 includes a free layer 111, a reference layer 113, and a tunnel barrier layer 115. The tunnel barrier layer 115 is disposed between the free layer 111 and the reference layer 113 to separate the free layer 111 and the reference layer 113. The material of the tunnel barrier layer 115 includes, for example, MgO. The free layer 111 and the reference layer 113 are two magnetic layers, and the material includes, for example, CoFeB. The reference layer 113 has a fixed magnetization orientation. The free layer 111 has a variable magnetization orientation. When the magnetization orientations of the free layer 111 and the reference layer 113 are the same, it is called a parallel (P) state. When the magnetization orientations of the free layer 111 and the reference layer 113 are opposite, it is called an antiparallel (AP) state. The resistance of the random magnetic tunnel junction 110 in the parallel state is less than that in the antiparallel state. The resistance difference is caused by the spin-related quantum tunneling effect. In the antiparallel state, it will be more difficult for the spin polarized current to tunnel through the tunneling barrier layer 115 .

[0053] Figure 6A model of the parallel state and the antiparallel state of the free layer 111 is shown. There is a potential barrier ΔE when the free layer 111 switches between the parallel state and the antiparallel state. In the present application, by designing the material and structure of the free layer 111, the potential barrier ΔE is low enough so that thermal noise can cause the free layer 111 to be randomly in the parallel state and the antiparallel state. How to regulate the potential barrier ΔE so that the free layer 111 is randomly in the parallel state and the antiparallel state can be referred to: William A. Borders. Integerfactorization using stochastic magnetic tunnel junctions. Nature 2019 and Ran Zhang. Probability-Distribution-Configurable True Random Number Generators Based on Spin-Orbit Torque Magnetic Tunnel Junctions. Advanced Science 2024.

[0054] The free layer 111 is randomly in one of the parallel state and the antiparallel state under the effect of thermal noise. The drain voltage Vo of the transistor 120 when the free layer 111 is in the parallel state is greater than the drain voltage Vo of the transistor 120 when the free layer 111 is in the antiparallel state.

[0055] When the first input terminal is the non-inverting input terminal and the second input terminal is the inverting input terminal, if the drain voltage Vo of the transistor 120 is greater than the reference voltage Vref, the output of the comparator 130 is a high level, and if the drain voltage Vo of the transistor 120 is less than the reference voltage Vref, the output of the comparator 130 is a low level. When the first input terminal is the inverting input terminal and the second input terminal is the non-inverting input terminal, if the drain voltage Vo of the transistor 120 is greater than the reference voltage Vref, the output of the comparator 130 is a low level, and if the drain voltage Vo of the transistor 120 is less than the reference voltage Vref, the output of the comparator 130 is a high level. Therefore, the output of the node is a 1-bit digital signal. The following is an example in which the first input terminal is the inverting input terminal and the second input terminal is the non-inverting input terminal.

[0056] As described above, the drain voltage Vo is determined by the input voltage Vin and whether the free layer 111 is in a parallel state or an anti-parallel state. Under the action of thermal noise, whether the free layer 111 is in a parallel state or an anti-parallel state is random. Therefore, the output digital signal of the node is also random, and the probability P of the output digital signal of the node being 1 is related to the input voltage Vin.

[0057] Figure 7The graph shows the relationship between the probability P of the output digital signal of a node being 1 and the input voltage Vin. Figure 7 The horizontal axis is the input voltage Vin, and the vertical axis is the probability P that the output digital signal is 1. Figure 7 As shown, the curve has an upper limit voltage VH and a lower limit voltage VL. When the input voltage Vin is greater than the upper limit voltage VH, the probability P of the output digital signal being 1 is 100%, and when the input voltage Vin is less than the lower limit voltage VL, the probability P of the output digital signal being 1 is 0. When the input voltage Vin is less than the upper limit voltage VH and greater than the lower limit voltage VL, the probability P of the output digital signal being 1 is greater than 0 and less than 100%. The upper limit voltage VH and the lower limit voltage VL define the working range of the node.

[0058] It should be noted that: (1) the upper limit voltage VH and the lower limit voltage VL of different nodes can be different, and (2) when the input voltage Vin is the same, the probability P of different nodes can also be different. For example, for the same input voltage Vin, the probability P of the output digital signal of one node being 1 is 75%, and the probability P of the output digital signal of another node being 1 is 90%. This is because the nodes actually manufactured are not exactly the same, and there is device to device variation.

[0059] Figure 7 The curve shown can be obtained by measurement and fitting. For example, multiple input voltages Vin are selected as test points, and multiple outputs of the comparator 130 are obtained at each test point, so as to calculate the probability P at the input voltage test point. After obtaining multiple sets of (input voltage Vin, probability P) data, the probability P can be obtained by fitting (for example, Sigmoidal fitting). Figure 7 The curve shown.

[0060] Figure 8 Another node circuit with an analog voltage signal as input signal is shown. Figure 5 Compared to the node circuit shown, Figure 8 The node circuit in FIG. 1 replaces the comparator 130 with an inverter 140. The input terminal of the inverter 140 is connected to the drain terminal of the transistor 120, and the output terminal OUT of the inverter 140 serves as the output terminal of the node. Figure 5 and Figure 8In the exemplary node circuit, randomness is injected through the random magnetic tunnel junction 110. It is understandable that randomness can also be injected into the node in other ways. In addition, the input signal of the node can also be an analog current signal, and the probability P of the output digital signal of the node being 1 is related to the magnitude of the analog current. It is understandable that when the input analog signal of the node is an analog current signal, the relationship curve between the probability P of the output digital signal of the node being 1 and the input current can also be obtained by measurement and fitting. The input current also has a working range.

[0061] In the prior art, after the mth iteration, the spin σ of the node is determined according to the 1-bit digital signal output by the node i. i For example, when the 1 bit output by node i is 1, the spin σ i is +1, when the 1bit output of node i is 0, spin σ i = -1. The magnitude of the input analog signal In of the m+1th iteration of node i is calculated according to formula (2). The magnitude of the input analog signal In of the m+1th iteration of node i and the spin σ of other nodes j interacting with node i are j related.

[0062] In=∑J ij σ j +h i (2)

[0063] In the process of solving the Ising model, the size of the input simulation signal of a single node has many possible values.

[0064] In the prior art, the microcontroller MCU calculates the size (target voltage value or target current value) of the input analog signal In used in the m+1th iteration according to the above formula (2), generates an input voltage according to the target voltage value through a high-precision and complex digital-to-analog converter DAC, or generates an input current according to the target current value through a high-precision and complex current source circuit. If the input analog signal is provided to N nodes at the same time, N digital-to-analog converters DAC or complex current source circuits are required, resulting in a high cost of the Ising model.

[0065] The present application provides a solution that does not use a digital-to-analog converter DAC (or a complex current source) or reduces the number of digital-to-analog converters DAC (or a complex current source). In each iteration of the Ising model, n input analog signals are sequentially provided to the node to obtain n output digital signals of the node, and the spin σ of the node is determined based on the n output digital signals. That is, each time the spin σ of the node is updated, n input analog signals need to be sequentially input to the node. n is an integer greater than 1, and n is, for example, 2, 3, 4, or 5. The n input analog signals are called input signal combinations.

[0066] Each of the n input analog signals is selected from two candidate input analog signals. The two candidate input analog signals are analog voltage signals or analog current signals. The two candidate input analog signals are selected from the working interval of the corresponding node. For example, the two candidate input analog signals are analog voltages, both of which are less than the upper limit voltage VH and greater than the lower limit voltage VL.

[0067] The two candidate input analog signals include: the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2. When the first candidate input analog signal Analog1 is input to the node, the probability that the output digital signal of the node is 1 is P1. When the second candidate input analog signal Analog2 is input to the node, the probability that the output digital signal of the node is 1 is P2. The n output digital signals generated by the node based on the combination of input signals constitute an n-bit digital signal, and the value of n bit includes 2 n There are possibilities, and the probability that an n-bit digital signal takes a certain value can be calculated based on P1 and P2. For example, n=3, the input signal combination is (Analog1, Analog2, Analog1), the probability that the 3-bit digital signal output by the node is 111 is P1*P2*P1, and the input signal combination is (Analog1, Analog2, Analog1), the probability that the 3-bit digital signal output by the node is 101 is P1*(1-P2)*P1. Fig. 9 FIG. 2 shows an exemplary input signal generating circuit 22 of the present invention. The input signal generating circuit 22 includes a plurality of output units, each of which corresponds to a node and is used to generate an input analog signal of the node. Fig. 9 As shown, the exemplary output unit includes: a first input signal generating circuit 221, a second input signal generating circuit 222, and a selector 220. The first input signal generating circuit 221 is used to generate a first candidate input analog signal Analog1. The second input signal generating circuit 222 is used to generate a second candidate input analog signal Analog2. The selector 220 is used to provide one of the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2 to the input end of the node according to the selection signal of the processor 21. The output unit can provide the input signal combination to the node by outputting n times.

[0068] When the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2 are analog voltage signals, the first input signal generating circuit 221 and the second input signal generating circuit 222 are, for example, bandgap circuits.

[0069] When the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2 are analog current signals, the first input signal generating circuit 221 and the second input signal generating circuit 222 are, for example, current sources, and each current source only needs to generate a constant current of a target magnitude.

[0070] When the mth iteration of the N nodes is completed, the processor 21 determines the value of the spin σ of each node according to the output of the node, and stores it in the spin state register 24. Wherein, m is an integer greater than 0, indicating the number of iterations.

[0071] like Fig.10 As shown, the m+1th iteration process of N nodes includes the following steps.

[0072] Step S101: the processor 21 obtains the spin states σ of the N nodes after the mth iteration from the spin state register 24. m .

[0073] Step S102: the processor 21 calculates the spin σ of the N nodes after the mth iteration. m Determine the target input value IN for each node m+1 . Target input value IN m+1 is a numerical value and can be calculated according to formula (2).

[0074] Step S103: the processor 21 generates a signal according to the target input value IN. m+1 Determine the input signal combination In of each node m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard. The spin judgment standard is an n-bit binary number.

[0075] Input signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) includes a first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 The first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 Each of the first candidate input analog signal In1 is the first candidate input analog signal Analog1 or the second candidate input analog signal Analog2. m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1Any two of them can select the same candidate input analog signal or different candidate input analog signals.

[0076] In some embodiments, the memory 23 stores a first lookup table for each node. The first lookup table includes a plurality of entries, each of which is (probability P*, candidate input signal combination, candidate spin judgment standard). The candidate input signal combination includes n input signals, each of which is selected from one of the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2. When the n input signals in the candidate input signal group are sequentially input to the node, the probability that the output digital signal output by the node is equal to the candidate spin judgment standard is P*.

[0077] The processor 21 determines the input signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment criteria are as follows. Processor 21 determines the probability P m+1 , where the probability P m+1 is when the target input value IN m+1 The probability that the output digital signal of the node is 1 when the corresponding analog signal is input to the node. The processor 21 determines the probability P in the first lookup table. m+1 The closest probability P* is obtained, and the candidate input signal combination and the candidate spin judgment standard corresponding to the closest probability P* are used as the input signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and spin judgment criteria.

[0078] The first lookup table includes multiple entries, each of which includes a probability P*, a candidate input signal combination, and a candidate spin judgment standard. By appropriately selecting the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2, the multiple probabilities P* are more evenly distributed between 0 and 100%. The processor 21 generates a plurality of spin judgment criteria based on the target input value IN. m+1 The probability P* is determined, and the candidate input signal combination and the candidate spin judgment criteria to be used are further determined.

[0079] It can be understood that when n is larger, each candidate input signal combination includes more input signals, the number of candidate input signal combinations is larger, the number of entries in the first lookup table is larger, and more P* is distributed between probability 0 and probability 1.

[0080] In some embodiments, the memory further stores a second lookup table for each node, and the processor determines the probability P according to the second lookup table. m+1 The second lookup table of each node describes the relationship between the probability P of the output digital signal of the node being 1 and the magnitude of the input analog signal.

[0081] In some embodiments, the memory 23 stores a third lookup table for each node, the third lookup table includes a plurality of entries, each entry is (input analog signal value, candidate input signal combination, candidate spin judgment criterion).

[0082] The processor 21 determines the input signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard are as follows. The processor 21 determines the target input value IN in the third lookup table m+1 The closest input analog signal value, the corresponding candidate input signal combination and the candidate spin judgment standard are used as the input signal combination In of the node m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and spin judgment criteria.

[0083] Step 104: the input signal generating circuit 23 generates the first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 The signals are sequentially input to the corresponding nodes, and the processor 21 obtains n output digital signals from each node. These n output digital signals constitute n-bit binary numbers. Fig.11 shows the first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 The input timing of the node and the timing of obtaining n output digital signals from the node.

[0084] Step 105: If the n output digital signals output by the node are the same as the spin judgment standard, the processor 21 judges the spin σ of the node after the m+1th iteration. m+1 is the first value. If the n output digital signals output by the node are different from the spin judgment standard, the processor 21 judges the spin σ of the node after the m+1th iteration. m+1 The processor 21 updates the spin state register 24 and determines whether the formula (1) converges.

[0085] Ising probability calculation is a kind of random calculation. In the prior art, the target input voltage value IN is calculated. m+1 After that, the high-precision digital-to-analog converter DAC generates a signal with a size of IN m+1 The target input voltage value IN m+1 Corresponding to the target probability of the node spin state. In the Ising machine of the present application, the input voltage combination of the node is selected from two candidate input analog signals set for each node. These two candidate input analog signals correspond to two probabilities. More probabilities can be obtained by the combined multiplication of the probabilities corresponding to these two candidate input analog signals. For example, when n=2, 10 probabilities can be obtained by the combined multiplication of 2 probabilities. Among these 10 probabilities, the probability closest to the target probability is selected, and the Ising model can still converge to the global optimal solution. And using only two candidate input analog signals can greatly reduce the circuit area of ​​the node input end. Therefore, the input analog signal generated by the high-precision digital-to-analog converter DAC in the prior art can be replaced by the input voltage combination and the corresponding spin judgment standard.

[0086] In the Ising machine of the present invention, by inputting the signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard "replace" the 1 input analog signal and 1bit judgment standard in the prior art, the input signal In1 m+1 ,In2 m+1 ,…Inn m+1 Each of the candidate input analog signals is selected from the first candidate input analog signal Analog1 and the second candidate input analog signal Analog2. In this way, for each node, only a circuit capable of generating two candidate input analog signals is needed, without a large digital-to-analog converter or a complex current source, thereby reducing the cost of the Ising machine.

[0087] The following is a specific embodiment of the Ising machine of the present invention. In this embodiment, n=2, and the input analog signal is an analog voltage signal. This embodiment can be applied to Figure 5 and Figure 8 The nodes shown.

[0088] We select a first candidate voltage V+ and a second candidate voltage V- for each node. In the iteration process of the Ising model, the combination of the first candidate voltage V+ and the second candidate voltage V- is used as the input of the node, and two output digital signals are obtained from the node, and the two output digital signals constitute 2 bits.

[0089] The first candidate voltage V+ and the second candidate voltage V- are both greater than the lower limit voltage VL and less than the upper limit voltage VH. Optionally, when the input voltage of the node is the first candidate voltage V+, the probability P1 that the output digital signal of the node is 1 is greater than 50%, and when the input voltage of the node is the second candidate voltage V-, the probability P2 that the output digital signal of the node is 1 is less than 50%. Probabilities P1 and P2 can be obtained by pre-measurement. For different nodes, the first candidate voltage V+ and the second candidate voltage V- can be the same or different.

[0090] If the first candidate voltage V+ and the second candidate voltage V- are input to the node successively (first input voltage combination), the probability that the two output digital signals of the node are "00" is (1-P1)*(1-P2), the probability that the two output digital signals of the node are "01" is (1-P1)*P2, the probability that the two output digital signals of the node are "10" is P1*(1-P2), and the probability that the two output digital signals of the node are "11" is P1*P2.

[0091] If the first candidate voltage V+ is input to the node twice (second input voltage combination), the probability that the two output digital signals of the node are "00" is (1-P1)*(1-P1), the probability that the two output digital signals of the node are "01" is (1-P1)*P1, the probability that the two output digital signals of the node are "10" is P1*(1-P1), and the probability that the two output digital signals of the node are "11" is P1*P1.

[0092] If the second candidate voltage V- is input to the node twice (third input voltage combination), the probability that the two output digital signals of the node are "00" is (1-P2)*(1-P2), the probability that the two output digital signals of the node are "01" is (1-P2)*P2, the probability that the two output digital signals of the node are "10" is P2*(1-P2), and the probability that the two output digital signals of the node are "11" is P2*P2.

[0093] If the second candidate voltage V- and the first candidate voltage V+ are input to the node successively (the fourth input voltage combination), the probability that the two output digital signals of the node are "00" is (1-P2)*(1-P1), the probability that the two output digital signals of the node are "01" is (1-P2)*P1, the probability that the two output digital signals of the node are "10" is P2*(1-P1), and the probability that the two output digital signals of the node are "11" is P2*P1.

[0094] A first lookup table can be summarized based on the above four input voltage combinations. The four probability values ​​of the first input voltage combination and the four probability values ​​of the fourth input voltage combination are the same, so the fourth input voltage combination is omitted.

[0095] Probability P* Candidate input signal combinations Candidate spin criteria (1-P1)*(1-P2) First input voltage combination 00 (1-P1)*P2 First input voltage combination 01 P1*(1-P2) First input voltage combination 10 P1*P2 First input voltage combination 11 (1-P1)*(1-P1) Second input voltage combination 00 (1-P1)*P1 Second input voltage combination 01 P1*(1-P1) Second input voltage combination 10 P1*P2 Second input voltage combination 11 (1-P2)*(1-P2) The third input voltage combination 00 (1-P2)*P2 The third input voltage combination 01 P2*(1-P2) The third input voltage combination 10 P2*P2 The third input voltage combination 11

[0096] First Lookup Table

[0097] The first lookup table is stored in the memory 23. The relationship curve between the input voltage Vin of each node and the probability P of the output digital signal being 1 is stored in the memory 23 in the form of a second lookup table.

[0098] Fig.12 The output unit of the exemplary input signal generating circuit is shown. Each output unit can output the first candidate voltage V+ or the second candidate voltage V- according to the selection signal provided by the processor 21, thereby realizing the first input voltage combination, the second input voltage combination and the third input voltage combination. The exemplary output unit includes: a first voltage generating circuit 221, a second voltage generating circuit 222, and a selector 220. The first voltage generating circuit 221 is used to generate the first candidate voltage V+, and the second voltage generating circuit 222 is used to generate the second candidate voltage V-. The first voltage generating circuit 221 and the second voltage generating circuit 222 are, for example, Bandgap circuits. When multiple nodes have the same first candidate voltage V+ or second candidate voltage V-, multiple output units can share the first voltage generating circuit 221 or the second voltage generating circuit 222.

[0099] Fig.13 FIG. 4 shows the operation method of the Ising machine of this embodiment. Fig.13 As shown, the m+1th iteration process of N nodes includes the following steps.

[0100] Step S121, obtaining the spin σ of each node after the mth iteration m The spin σ of each node m The spin state register 24 stores the spin state of each node. The processor 21 can obtain the spin state of each node from the spin state register 24. m . Spin σ m The value of is +1 or -1.

[0101] Step S122: the processor 21 calculates the spin σ of each node. m And the following formula calculates the target input value VIN of the m+1th iteration of each node m+1 .

[0102] VIN m+1 =∑J ij σ jm +h i

[0103] Step S123, the processor 21 generates a voltage according to the target input value VIN. m+1Determine the input voltage combination Vin for the m+1th iteration m+1 (V1 m+1 ,V2 m+1 ) and spin judgment criteria.

[0104] In some embodiments, the processor 21 determines the input voltage combination Vin according to the first lookup table and the second lookup table. m+1 (V1 m+1 ,V2 m+1 ) and spin judgment criteria.

[0105] The processor 21 calculates the value of the target input value VIN according to the second lookup table m+1 Determine the probability P m+1 , probability P m+1 When the target input value VIN m+1 The probability that the digital signal output by the node is 1 when the analog voltage is input to the node.

[0106] The processor 21 determines in the first lookup table the probability P m+1 The closest probability P* is obtained, and the candidate input voltage combination and the candidate spin judgment standard corresponding to the closest probability P* are used as the input voltage combination Vin m+1 (V1 m+1 ,V2 m+1 ) and spin judgment criteria.

[0107] For example, the processor 21 determines the probability value P1*P1 and the target input value VIN m+1 The corresponding probability P m+1 closest, then select (first candidate voltage V+, first candidate voltage V+) as the input voltage combination Vin m+1 , that is, the first input voltage V1 m+1 and the second input voltage V2 m+1 Both are the first candidate voltage V+. Furthermore, the processor 21 selects "11" as the spin determination criterion.

[0108] As shown in the first lookup table, the probability P* corresponding to the second input voltage combination and "01" is the same as the probability P* corresponding to the second input voltage combination and "10". m+1 When the closest probability is determined to be the probability P*, either "01" or "10" can be selected as the spin judgment standard.

[0109] In some other embodiments, for each node, the first lookup table and the second lookup table are combined into a third lookup table, and the third lookup table includes multiple voltage values, each voltage value corresponds to a candidate input voltage combination and a candidate spin judgment standard. The processor 21 generates a signal according to the target input value VIN. m+1The input voltage combination Vin is determined by accessing the third lookup table m+1 (V1 m+1 ,V2 m+1 ) and spin judgment criteria.

[0110] Step S124: input the corresponding input voltage combination Vin to each node. m+1 (V1 m+1 ,V2 m+1 ), and obtain 2 output digital signals from each node.

[0111] The input signal generating circuit 22 successively converts V1 m+1 and V2 m+1 Input to the node. Input the first input voltage V1 to the node m+1 After that, the processor 21 obtains an output digital signal from the node. A second input voltage V2 is input to the node m+1 After that, the processor 21 obtains an output digital signal from the node again. In this way, the processor 21 obtains a 2-bit digital signal from each node.

[0112] Preferably, the N nodes simultaneously input the corresponding first input voltage V1 m+1 , and input the corresponding second input voltage V2 m+1 .

[0113] Step S125, determine the spin σ of each node m+1 , and updates the spin state register 24.

[0114] The processor 21 determines the spin σ of the node after the m+1th iteration based on the 2-bit digital signal obtained from the node and the spin judgment standard determined in step S123. m+1 If the output digital signal obtained from the node is the same as the spin judgment standard, the processor judges the spin σ of the node after the m+1th iteration. m+1 is a first value, if the output digital signal obtained from the node is different from the spin judgment standard, the processor judges the spin σ of the node after the m+1th iteration m+1 The first value is, for example, +1, and the second value is, for example, -1.

[0115] For example, in step S123, the processor 21 determines the input voltage combination Vin of the m+1th iteration of a certain node. m+1 (V1 m+1 ,V2 m+1 ) is (V+, V+), and the spin judgment standard is 11. If the output digital signal obtained by the processor 21 from the node is 11, then the spin σ of the node after iteration m+1+1, if the output digital signal obtained by processor 21 from the node is 00, 01 or 10, then the spin σ of the node after iteration m+1 is -1.

[0116] After the spin state register 24 is updated, the (m+2)th iteration is performed and the above steps are repeated until the Ising model converges.

[0117] According to the Ising machine provided in this embodiment, the iteration of the Ising model is realized by inputting two voltages to the node, and the spin of the node after the iteration is determined according to the two output digital signals output by the node. The two input voltages of each iteration are selected from the first candidate voltage and the second candidate voltage. In this way, it is only necessary to set an analog circuit for generating the first candidate voltage and the second candidate voltage for each node, and there is no need to set a digital-to-analog converter for each node, thereby reducing the hardware cost of the Ising machine.

[0118] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An Ising machine, comprising: N nodes, for simulating N spins, N is an integer greater than 1, wherein each node generates an output digital signal based on an input analog signal, and a probability P of the output digital signal being 1 is determined by the input analog signal; A spin state register, used for storing the spins of the N nodes; a processor connected to output terminals of the N nodes; and an input signal generating circuit, connected to the input ends of the N nodes, and used to generate a first candidate input analog signal and a second candidate input analog signal corresponding to each node, The processor obtains the spins of the N nodes after the mth iteration from the spin state register, wherein m is an integer greater than 0, the spin of the node is one of a first value and a second value, one of the first value and the second value is +1, and the other of the first value and the second value is -1, The processor determines the target input value IN of each node according to the spin of the N nodes after the mth iteration m+1 , The processor determines the target input value IN m+1 Determine the input signal combination In of each node m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard, wherein the input signal combination In m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) includes a first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 , n is an integer greater than 1, the first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 each of which is selected from one of the first candidate input analog signal and the second candidate input analog signal, The first input signal In1 m+1 , the second input signal In2 m+1 , to the nth input signal Inn m+1 are sequentially input to the corresponding nodes, and the processor obtains n output digital signals from each node, If the n output digital signals output by the node are the same as the spin judgment standard, the processor determines that the spin of the node after the m+1th iteration is the first value; if the n output digital signals output by the node are different from the spin judgment standard, the processor determines that the spin of the node after the m+1th iteration is the second value.

2. The Ising machine according to claim 1, wherein: The input analog signal is an input analog voltage, and the node includes: a random magnetic tunnel junction, a transistor, a resistor, and a comparator, wherein the random magnetic tunnel junction, the transistor, and the resistor are connected in series between a power supply terminal and a ground, a gate of the transistor receives the input analog voltage, a drain of the transistor is connected to a first input terminal of the comparator, a second input terminal of the comparator receives a reference voltage, and an output terminal of the comparator serves as an output terminal of the node.

3. The Ising machine according to claim 1, wherein: The first candidate input analog signal and the second candidate input analog signal are analog voltage signals, or The first candidate input analog signal and the second candidate input analog signal are analog current signals.

4. The Ising machine according to claim 1, wherein: When the input analog signal of the node is the first candidate input analog signal, the probability P1 that the output digital signal of the node is 1 is greater than 50%; when the input analog signal of the node is the second candidate input analog signal, the probability P2 that the output digital signal of the node is 1 is less than 50%.

5. The Ising machine according to claim 1, wherein: The processor determines the target input value IN of node i according to the spins of the N nodes and the following formula: m+1 , 1≤i≤N, IN m+1 =∑J ij σ jm +h i Among them, h i is the external magnetic field coefficient of the node i, J ij is the interaction coefficient between the node i and the node j, σ jm is the spin of the node j after the mth iteration, 1≤j≤N, j≠i.

6. The Ising machine according to claim 1, wherein: The Ising machine also includes a memory, which stores a first lookup table for each node, wherein the first lookup table includes a plurality of entries, each of which is (probability P*, candidate input signal combination, candidate spin judgment standard), wherein the candidate input signal combination includes n input signals, each input signal is selected from one of a first candidate input analog signal and a second candidate input analog signal, and when the n input signals are sequentially input to the node, the probability that the n output digital signals output by the node are equal to the candidate spin judgment standard is P*, The processor determines the input signal combination In by the following method m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and the spin judgment standard: The processor determines the probability P m+1 , where the probability P m+1 is when the target input value IN m+1 the probability that the output digital signal output by the node is 1 when the corresponding analog signal is input to the node; and The processor determines in a first lookup table the probability P m+1 The closest probability P* is obtained, and the candidate input signal combination and the candidate spin judgment standard corresponding to the closest probability P* are used as the input signal combination and the spin judgment standard.

7. The Ising machine according to claim 6, wherein: The memory also stores a second lookup table for each node, and the processor determines the probability P according to the second lookup table. m+1 .

8. The Ising machine according to claim 1, wherein: The Ising machine also includes a memory, wherein the memory stores a third lookup table for each node, wherein the third lookup table includes a plurality of entries, each of which is (input analog signal value, candidate input signal combination, candidate spin judgment criterion). The processor calculates the target input value IN according to the third lookup table and the target input value IN m+1 Determine the input signal combination In of the node m+1 (In1 m+1 ,In2 m+1 ,…Inn m+1 ) and spin judgment criteria.

9. The Ising machine according to claim 1, wherein: The first candidate input analog signal and the second candidate input analog signal are analog voltage signals, and the input signal generating circuit includes a Bandgap circuit, and the Bandgap circuit is used to generate the first candidate input analog signal and the second candidate input analog signal.

10. The Ising machine according to claim 1, wherein: The N nodes simultaneously input the corresponding first input signal In1 m+1 , the N nodes simultaneously input the corresponding second input signal In2 m+1 , the N nodes simultaneously input the corresponding nth input signal Inn m+1 .

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