Noise shaping pipeline successive approximation type analog-to-digital converter and control method

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a noise-shaping pipeline successive approximation analog-to-digital converter and its control method. Background Technology

[0002] In existing technologies, medium-to-high-speed noise-shaping pipelined SAR analog-to-digital converters often employ an error feedback architecture, a cascaded integrator feed-forward (CIFF) structure, or a hybrid of both. The loop filter used for quantization noise shaping is located in the first-stage SAR ADC, the second-stage SAR ADC, or both. In the loop filter, voltage-domain amplifiers and switched capacitors are typically used to amplify and filter the quantization noise. After the SAR ADC completes the quantization of the input voltage signal, a quantization residual corresponding to the quantization noise is generated on the capacitor plates of the capacitive digital-to-analog converter. The voltage-domain amplifier then amplifies the residual voltage, and the amplified residual voltage is then filtered by the switched capacitors. This process involves charge sharing among several capacitors and attenuation of the amplified quantization noise. The voltage amplification factor of the loop filter and the ratio of each capacitor in the switched capacitor bank determine the noise transfer function of the system, which directly determines the performance of the noise-shaping analog-to-digital converter.

[0003] However, existing successive approximation analog-to-digital converters (ADCs) with noise shaping pipelines suffer from the following limitations due to their inherent structure: In the EF structure of the loop filter, the zeros of the noise transfer function, which affects system performance, vary with fluctuations in the residual voltage amplification factor, resulting in unstable noise shaping performance. Furthermore, the noise transfer function of the CIFF structure exhibits low noise shaping efficiency at low oversampling rates, making it unsuitable for the low oversampling and high bandwidth requirements of medium- to high-speed noise-shaping ADCs. The residual voltage amplifier in the loop filter is a dynamic open-loop amplifier, and its voltage amplification factor is unstable with variations in process technology, supply voltage, and temperature, affecting the noise shaping effect of the loop filter. The longer amplification time of the dynamic amplifier slows down the overall conversion speed of the ADC.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a noise-shaping pipeline successive approximation analog-to-digital converter and its control method, which can accelerate the analog-to-digital conversion speed, reduce the influence of zero point on the residual voltage amplification factor, reduce the conversion time, and stabilize the input and output common-mode voltage of the time-domain converter.

[0006] To achieve the above objectives, one aspect of this application provides a noise-shaping pipelined successive approximation analog-to-digital converter, comprising:

[0007] The first stage includes an auxiliary successive approximation analog-to-digital converter and a first-stage voltage processing module. The auxiliary successive approximation analog-to-digital converter is used to quantize and decompose the input voltage signal and output a digital code. The first-stage voltage processing module obtains the first-stage residual voltage based on the digital code.

[0008] The second stage includes a dual-channel noise-shaping successive approximation analog-to-digital converter and a loop filter; each channel of the noise-shaping successive approximation analog-to-digital converter includes a comparator; the loop filter includes an integrating capacitor, a noise feedback capacitor, and an integrator output feedback capacitor in each of the two channels, as well as a first extraction capacitor and a second extraction capacitor shared by the two channels.

[0009] A residual amplifier, the input of which is connected to the first-stage voltage processing module, and the output of which is connected to the noise-shaping successive approximation analog-to-digital converter.

[0010] A sampling switch module, wherein the input terminal of the sampling switch module is connected to the differential input voltage signal, and the output terminal of the sampling switch module is connected to the first-stage voltage processing module and the auxiliary voltage processing module of the auxiliary successive approximation analog-to-digital converter, respectively.

[0011] A digital code aligner, wherein the first input terminal of the digital code aligner is connected to the output terminal of the comparator of the auxiliary analog-to-digital converter, and the second input terminal of the digital code aligner is connected to the output terminal of the comparator of the second stage.

[0012] In some embodiments, the quantization bit depth of the first and second stages and the bit depth of the analog-to-digital converter are set according to the performance of the noise-shaping pipeline successive approximation analog-to-digital converter.

[0013] In some embodiments, the residual amplifier includes a dynamic open-loop voltage amplifier.

[0014] In some embodiments, a voltage-to-time converter and a time-to-voltage converter are further included, wherein:

[0015] The scanning reference voltage is obtained by scanning from high level to low level through the discharge capacitor.

[0016] The voltage-time converter compares the differential input voltage signal with the scanning reference voltage; and generates two time pulse signals with a time delay difference based on the comparison result of the differential input voltage signal and the scanning reference voltage.

[0017] The time-voltage converter starts after a fixed delay after the voltage-time converter starts working, and converts the time pulse signal into a differential voltage difference signal through different discharge times;

[0018] The voltage-time converter and the time-voltage converter operate in parallel, and the time-voltage converter completes its conversion simultaneously when the voltage-time converter completes its conversion.

[0019] In some embodiments, a replica voltage-time converter is also included;

[0020] The replica voltage-time converter is used to generate a replica delay signal that is a fixed time shorter than the delay of the voltage-time converter. The replica delay signal is used to stabilize and control the output common-mode voltage of the time domain converter.

[0021] The loop filter feeds back the output common-mode voltage of the time-to-voltage converter to the input common-mode voltage.

[0022] To achieve the above objectives, another aspect of this application proposes a control method for a noise-shaping pipelined successive approximation analog-to-digital converter. The method is applied to the aforementioned noise-shaping pipelined successive approximation analog-to-digital converter and includes the following steps:

[0023] The input voltage signal of the auxiliary capacitor digital-to-analog converter is quantized by the auxiliary successive approximation analog-to-digital converter to obtain the first-level digital code.

[0024] The first-level digital code is processed by the detection skip logic, and the first-level voltage processing module is controlled to generate the first-level residual.

[0025] After the residual amplifier amplifies the first-stage residual, the amplified first-stage residual is quantized by the dual-channel noise-shaping successive approximation analog-to-digital converter to obtain the second-stage digital code.

[0026] The loop filter is used to filter the quantization noise generated by the noise-shaping successive approximation analog-to-digital converter in the second-level digital code.

[0027] The filtered quantization noise and the amplified first-stage residual are summed using a charge-sharing circuit to obtain a mixed signal.

[0028] The mixed signal is quantized using a multi-input comparator to obtain a digital output.

[0029] In some embodiments, the loop filter, in conjunction with the dual-channel noise-shaping successive approximation analog-to-digital converter, includes four operating states:

[0030] First working state: The charge sharing circuit enables the second extraction capacitor to share charge with the integrating capacitor of the second stage channel one and the integrator output feedback capacitor;

[0031] The charge-sharing circuit enables the first extraction capacitor to share charge with the integrator output feedback capacitor and noise feedback capacitor of the second-stage channel two.

[0032] The voltage of the noise feedback capacitor and the integrating capacitor in the second channel are summed and quantized by a multi-input comparator, and the voltage signal on the voltage processing module of the second stage are added together.

[0033] Second operating state: The noise feedback capacitor of channel one is reset by connecting to the common-mode voltage through switch control;

[0034] The switching control keeps the integrating capacitor and the integrator output feedback capacitor of channel one in their current state. At this time, channel one is performing successive approximation quantization on the amplified first-stage residual signal.

[0035] The sum of the quantization residual voltage of channel two and the voltage across the noise feedback capacitor is amplified by a time-domain converter and sampled onto the first extraction capacitor and the second extraction capacitor of the differential circuit.

[0036] Third working state: Channel 1 and Channel 2 alternately perform the same operations as in the first working state;

[0037] Fourth working state: Channel 1 and Channel 2 alternately perform the same operations as in the second working state.

[0038] In some embodiments, the summation of the filtered quantization noise and the amplified first-stage residual via a charge-sharing circuit includes the following steps:

[0039] In the first and third operating states of the loop filter, charge sharing is achieved through a differential capacitor network;

[0040] In the second and fourth operating states of the loop filter, the voltage signal is summed and amplified by the time-domain converter.

[0041] In some embodiments, the auxiliary successive approximation analog-to-digital converter quantizes the input voltage signal of the auxiliary capacitor digital-to-analog converter using a capacitor analog-to-digital converter control algorithm to obtain the first-level digital code.

[0042] In some embodiments, quantizing the amplified first-stage residual using a dual-channel noise-shaping successive approximation analog-to-digital converter includes the following steps:

[0043] When channel one is in the reset and idle phase of the capacitor digital-to-analog converter, channel two quantizes the amplified first-stage residual.

[0044] When the first channel is in the first stage residual after sampling and amplification, the second channel amplifies the quantized residual voltage and samples it onto the first extraction capacitor.

[0045] The embodiments of this application include at least the following beneficial effects: This application provides a noise-shaping pipelined successive approximation analog-to-digital converter and its control method. By adopting a pipelined structure, the speed of analog-to-digital conversion is accelerated; each stage of the successive approximation analog-to-digital converter only needs to convert a portion of the digital code; This application provides a hybrid loop filter with a first-order noise feedback and a first-order cascaded integrator feedforward structure, based on the traditional 1+1 order hybrid structure, providing a pair of optimized conjugate complex zeros, while the influence of the zeros on the residual voltage amplification factor is less than that of the noise feedback structure and the cascaded integrator feedforward structure; This application adopts a time-domain assisted residual amplification mechanism, i.e., voltage-time-voltage conversion process... The process obtains a stable voltage amplification coefficient by the proportional relationship between the current and capacitance values ​​between the two conversion coefficients. Simultaneously, the two conversion processes are performed in parallel, saving conversion (amplification) time. The voltage-to-time converter of this application does not discharge the input signal sampling capacitor, thus decoupling the conversion coefficient from the capacitor-type digital-to-analog converter capacitor without damaging the input signal voltage. This allows for flexible design of the voltage-to-time conversion coefficient and enables subsequent processing or utilization of the quantization residual. This application uses a replicated voltage-to-time converter to track the voltage-to-time conversion delay and control the time-to-voltage conversion, stabilizing the input and output common-mode voltages of the time-domain converter and ensuring the linearity of the time-domain converter and the quantization noise shaping effect of the system. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the successive approximation analog-to-digital converter module structure of the noise shaping pipeline with time-domain assisted residual amplification provided in the embodiments of this application;

[0047] Figure 2 This is a schematic diagram of the top-level structure of the time-domain assisted residual amplification noise shaping pipeline successive approximation analog-to-digital converter circuit provided in the embodiments of this application;

[0048] Figure 3 This is a schematic diagram of the circuit structure for a time-domain converter used to amplify the second-stage quantization residual;

[0049] Figure 4 This is a schematic diagram of the circuit structure of the replica voltage-time converter in the time-domain converter used to amplify the second-stage quantization residual;

[0050] Figure 5 This is a schematic diagram of the working process of a noise-shaping pipeline analog-to-digital converter;

[0051] Figure 6 This is a schematic diagram of the control algorithm for detecting the first-stage voltage processing module of the skip logic control;

[0052] Figure 7 This is a schematic diagram of the overall signal flow;

[0053] Figure 8 This is a schematic diagram of a single-channel structure of a second-stage noise-shaping successive approximation analog-to-digital converter;

[0054] Figure 9 This is a schematic diagram of the structure in the first working state;

[0055] Figure 10 This is a schematic diagram of the structure in the second working state;

[0056] Figure 11 This is a structural diagram of the third working state;

[0057] Figure 12 This is a structural diagram of the fourth working state;

[0058] Figure 13 This is a flowchart of the CDAC control algorithm quantizing into digital code. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0060] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0061] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0063] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0064] ADC: Analog-to-Digital Converter, which converts analog voltage signals into digital signals and is widely used in the field of signal processing.

[0065] CDAC: Capacitor-to-Digital Converter, which converts digital to analog voltage through a capacitor network.

[0066] SAR ADC: Successive approximation analog-to-digital converter, which uses a successive approximation method, has high accuracy, high speed and low power consumption.

[0067] One aspect of this application provides a noise-shaping pipelined successive approximation analog-to-digital converter, comprising: a first stage, a second stage, a residual amplifier, a sampling switch module, and a digital code aligner. The system comprises the following stages: The first stage includes an auxiliary successive approximation analog-to-digital converter (ADC) and a first-stage voltage processing module. The ADC quantizes and decomposes the input voltage signal and outputs a digital code. The voltage processing module obtains the first-stage residual voltage based on the digital code. The second stage includes a dual-channel noise-shaping successive approximation ADC and a loop filter. Each channel of the noise-shaping ADC includes a comparator. The loop filter includes an integrating capacitor, a noise feedback capacitor, and an integrator output feedback capacitor for each channel, as well as a first extraction capacitor and a second extraction capacitor shared by both channels. The input of the residual amplifier is connected to the first-stage voltage processing module, and its output is connected to the noise-shaping ADC. The input of the sampling switch module is connected to the differential input voltage signal, and its output is connected to both the first-stage voltage processing module and the auxiliary voltage processing module of the ADC. The first input of the digital code aligner is connected to the output of the comparator of the ADC, and its second input is connected to the output of the comparator in the second stage.

[0068] Specifically, such as Figure 1 As shown, Figure 1 The overall architecture and the signal flow and functional relationships between modules are clearly demonstrated. After the signal is input from the signal input terminal, it enters the first-stage voltage processing module, which is connected to the residual amplifier. The output of the residual amplifier is connected to the second-stage voltage processing module, and the output of the second-stage voltage processing module is sent to the second-stage comparator module, and then to the second-stage successive approximation logic circuit. A loop filter plays a corresponding role in this process. Simultaneously, the signal is also input to the auxiliary successive approximation analog-to-digital converter (ADC). This converter includes an auxiliary voltage processing module, an auxiliary comparator module, and an auxiliary successive approximation logic circuit. A detection skip logic circuit is connected to the first-stage voltage processing module and the auxiliary successive approximation ADC to process relevant signals. The reference signal terminal also provides a reference signal for the entire analog-to-digital conversion process.

[0069] like Figure 2 As shown, Figure 2The circuit details the connections and operating mechanisms of its key internal circuits. On the left side, the voltage signal is processed through a capacitor array and other structures, amplified by a residual amplifier, and then connected to the right side. The right side contains a circuit structure composed of multiple capacitors, working in conjunction with a loop filter, and also includes a second-stage successive approximation logic circuit. Furthermore, the signal processed by the auxiliary successive approximation analog-to-digital converter is processed by a digital signal alignment module, ultimately outputting a digital output signal. Through ingenious connections and logic control, the entire circuit achieves analog-to-digital conversion of the input voltage signal.

[0070] More specifically, structurally, the ADC of this invention consists of two stages. The first stage comprises an auxiliary successive approximation analog-to-digital converter (ADC) and a main CDAC generated from the first-stage residual. A residual amplifier connects the first and second stages. The second stage is a two-channel noise-shaping successive approximation ADC, including the noise-shaping loop filter provided in this application. The differential input voltage signal of the ADC is input to the first-stage voltage processing module and the auxiliary voltage processing module of the auxiliary successive approximation ADC via a sampling switch module. The first-stage voltage processing module is the main CDAC, and the auxiliary voltage processing module is the auxiliary CDAC. The auxiliary successive approximation ADC quantizes the input signal and outputs a control signal to the main CDAC to generate the first-stage residual. The input of the residual amplifier is connected to the first-stage voltage processing module to amplify the first-stage residual. The input of the second-stage noise-shaping ADC is connected to the output of the residual amplifier, and the two channels work alternately to sample the amplified first-stage residual. The loop filter filters the second-stage quantization noise and then weights and sums it with the amplified first-stage residual before connecting it to the comparator of the second-stage analog-to-digital converter (ADC) for quantization. The first input of the digital code aligner is connected to the output of the comparator of the auxiliary ADC, and the second input is connected to the output of the comparator of the second-stage ADC, used to align the digital codes obtained from the two-stage ADC quantization.

[0071] In some embodiments, the quantization bit depth of the first and second stages and the bit depth of the analog-to-digital converter (ADC) are set according to the performance of the noise-shaping pipeline successive approximation ADC. That is, the quantization bit depth of the two-stage ADC and the bit depth of the digital-to-analog converter (DAC) can be set according to the performance requirements of the ADC.

[0072] In some embodiments, the residual amplifier between the first stage and the second stage can be a dynamic open-loop voltage amplifier.

[0073] In some embodiments, a noise-shaping pipelined successive approximation analog-to-digital converter further includes a voltage-time converter and a time-voltage converter, wherein: a scanning reference voltage is obtained by discharging from a high level to a low level through a discharge capacitor; the voltage-time converter compares the differential input voltage signal with the scanning reference voltage; two time pulse signals with a delay difference are generated based on the comparison result of the differential input voltage signal and the scanning reference voltage; the time-voltage converter starts after a fixed delay time after the voltage-time converter starts working, and converts the time pulse signal into a differential voltage difference signal through different discharge times; wherein the voltage-time converter and the time-voltage converter work in parallel, and the time-voltage converter also completes its conversion synchronously when the voltage-time converter completes its conversion.

[0074] Specifically, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the circuit structure used to amplify the second-stage quantization residual in a time-domain converter. Figure 3 The core circuit structures of the voltage-to-time converter and the time-to-voltage converter are shown. These include: a voltage-to-time converter consisting of a reference scan voltage module, a threshold trigger detector, and logic circuit units; and a time-to-voltage converter consisting of a control logic unit and a discharge current source module.

[0075] The reference scanning voltage module in the voltage-time converter consists of a reference signal capacitor and a discharge current source; the basic working principle of the reference scanning voltage module is as follows: During the reset phase, the reference signal capacitor is charged to a preset voltage V. VTC_RST This serves as the starting point for the reference scan voltage; after the voltage-to-time converter is started, the control clock signal CLK is activated. VT When the signal rises to a high level, the discharge current source and the reference signal capacitor are turned on, discharging the reference signal capacitor at a preset speed. The reference voltage signal stored in the reference signal capacitor decreases at a constant speed from the starting point until the control clock signal CLK is reached. VT Falling to a low level; such as Figure 3 As shown, the rate of decrease of the reference voltage signal is:

[0076]

[0077] Among them, I REF C represents the magnitude of the current discharged through the reference signal capacitor. REF This indicates the capacitance value of the reference signal capacitor.

[0078] The threshold-triggered detector in the voltage-to-time converter is a dynamic comparator. Its positive input is connected to the output of the reference electrical scanning voltage module, and its negative input is connected to a differential input of the voltage-to-time converter. During the reset phase, the control clock signal CLK is used. VTWhen the signal is low, the dynamic comparator is not working, and the output of the logic circuit is the time pulse signal T. P / T N It is reset to a high level; after the voltage-to-time converter starts, the control clock signal CLK is activated. VT The voltage rises to a high level, controlling the dynamic comparator to start comparison; when the reference voltage signal drops to a value lower than the input voltage at one of the differential input terminals of the voltage-time converter, a time pulse signal T is generated after a preset time. P / T N The logic circuit is lowered to a low level; the output of the logic circuit is the output of the voltage-to-time converter.

[0079] The positive and negative terminals of the voltage-to-time converter provided in this application embodiment are the same, so the delays of the threshold trigger detector and the logic circuit unit are also the same; therefore, the output time pulse signal T at the positive terminal is... P The output time pulse signal T at the negative terminal N The time difference Δt between the falling edges of the reference scan voltage is the time difference between the moment when the reference scan voltage is exactly equal to the positive input voltage signal of the voltage-time converter and the moment when the reference scan voltage is exactly equal to the negative input voltage signal of the voltage-time converter. This is the time difference between the falling edges of the reference scan voltage V. IN The time spent; therefore, the conversion factor of the voltage-to-time converter is:

[0080]

[0081] Among them, F VT This represents the conversion factor of the voltage-to-time converter.

[0082] This application provides a time-to-voltage converter comprising a control logic unit and a discharge current source module; the output terminal is connected to the output load capacitor, which is the output terminal of the time-to-voltage converter; the discharge current source module can charge, reset, and discharge the output load capacitor at a constant speed under the control of the control logic unit; the working principle of this time-to-voltage converter is as follows: the first input terminal of the control logic unit is connected to the total control signal CLK. TV The second input terminal is connected to the input time pulse signal; in the total control signal CLK TV When the signal is low, the current source of the discharge current source module is not connected to the output load capacitor, but it can reset the connection terminal of the output load capacitor to the preset voltage value; in the total control signal CLK TV When the signal is high, the current source of the discharge current source module is controlled by the total control signal CLK at the first output of the control logic unit. TVThe time pulse signals at the second and second input terminals are jointly controlled by logic. Since the widths of the time pulse signals at the two differential input terminals of the time-to-voltage converter are different, the corresponding conduction times of the output load capacitor and the discharge current source are different, resulting in different discharge voltage differences. Because the output voltage signals at the two differential output terminals of the time-to-voltage converter are reset to the same discharge starting point, the output voltages at the two differential output terminals will differ after the discharge ends. Figure 3 As shown, if the capacitance value of the output load capacitor is C EX Then the differential output voltage signal V of the final time-to-voltage converter OUT The relationship between the time pulse signals at the two differential input terminals and the time difference Δt is:

[0083]

[0084] Among them, V OUT I represents the output voltage of the time-to-voltage converter. RES C represents the discharge current of the time-to-voltage converter to the load capacitor. EX This represents the two sets of extraction capacitors in the ring filter, which also serve as the load capacitors of the time-to-voltage converter.

[0085] The time-domain amplifier provided in this application embodiment is a voltage-to-time-to-voltage converter composed of a voltage-to-time converter and a time-to-voltage converter connected in series. Combining the voltage-to-time conversion coefficient and the time-to-voltage conversion coefficient mentioned above, the gain of this time-domain amplifier is:

[0086]

[0087] It should be noted that this gain is only related to the ratio of the currents of the discharge current sources in the voltage-to-time converter and the time-to-voltage converter, as well as the ratio of the capacitance values ​​of the reference signal capacitor and the output load capacitor. In integrated circuit design, the current ratio of the current sources can be precisely controlled by a current mirror. Appropriate arrangement in the layout design can make the ratio of the capacitance values ​​of several capacitors very accurate. Therefore, compared with the open-loop dynamic voltage amplifier in related technologies, the voltage gain of the time domain amplifier provided in this embodiment of the invention is more accurate and stable.

[0088] It is worth noting that, firstly, the delay of the threshold-triggered detector is related to the common-mode voltage value of the input signal, and as mentioned above, the linearity of the threshold trigger's delay time is closely related to the linearity of the voltage-to-time converter; secondly, the output common-mode voltage of the time-domain amplifier is also related to the delay of the voltage-to-time converter (threshold trigger); thirdly, in the noise-shaping analog-to-digital converter, the presence of the loop filter creates a positive feedback loop between the input and output common-mode voltages of the time-domain amplifier; therefore, the input and output common-mode voltages of the time-domain amplifier are stabilized; unlike the voltage-domain amplifiers in related technologies, this time-domain amplifier does not have the existing common-mode feedback circuit; this application provides a control method for a voltage-to-time-voltage converter to stabilize the output voltage of the voltage-to-time-voltage converter, the specific control principle of which is as follows: Figure 4 As shown.

[0089] As shown above, the start-up of the time-to-voltage converter is delayed by a preset time t compared to the start-up of the voltage-to-time converter. del When the input common-mode voltage of the voltage-to-time converter is stable, the average time for the reference voltage signal to reach the threshold point is t0, and the delay times of the threshold trigger detector and the logic circuit unit are t1 and t2, respectively. As mentioned above, one way to stabilize the output common-mode voltage of the time-domain amplifier (the output common-mode voltage of the time-to-voltage converter) is to stabilize the conduction time of the discharge current source of the time-to-voltage converter. The time and amplifier control method provided in this embodiment uses a preset delay time t... del Setting it to (t0+t1-Δt) stabilizes the discharge time of the time-to-voltage converter at (Δt+t2).

[0090] In some embodiments, the preset delay time is specifically generated by replicating a voltage-to-time converter. The replica voltage-to-time converter generates a replica delay signal that is a fixed time shorter than the delay of the voltage-to-time converter. The replica delay signal is used to stabilize and control the output common-mode voltage of the time-domain converter; the output common-mode voltage of the time-to-voltage converter is fed back to the input common-mode voltage through a loop filter.

[0091] Specifically, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the circuit structure of the replica voltage-time converter used in the time-domain converter for amplifying the second-stage quantization residual. Figure 4 A replicated voltage-to-time converter and a replicated threshold-triggered detector are presented, wherein the ratio between the replicating circuit and the main circuit can be changed as needed, optionally to 0.2:1. The replicated voltage-to-time converter employs... Figure 3A similar structure to the medium-voltage time converter, but with adjusted component parameters, is used to generate a fixed-delay replication delay signal to control the start time of the time-voltage converter. The replication threshold-triggered detector is also... Figure 3 The threshold-triggered detector was replicated, and the component parameters were scaled accordingly. It works in conjunction with the replicated voltage-to-time converter to ensure the stability and linearity of the time-to-voltage conversion. Overall, Figure 4 Through structural design and coordination, a voltage-time-voltage conversion process is achieved, and conversion performance is optimized using a replication circuit and parameter adjustment. More specifically, a replicated voltage-time converter is used, which replicates a delay (t1-Δt) that is a fixed time shorter than the voltage-time converter's delay t1. This delay is used to control the start time of the time-voltage converter, resulting in a stable operating time Δt. Since the discharge start voltage and discharge current of the time-voltage converter are fixed, the output common-mode voltage of the time-domain converter corresponding to the discharge end voltage is relatively stable. Furthermore, because the input common-mode voltage of the time-domain converter is coupled to its output common-mode voltage through a loop filter, this control method can achieve stable input common-mode voltage and linearity.

[0092] It should be noted that, firstly, in related technologies, the operation of voltage-to-time converters differs: the input signal of the voltage-to-time converter is the output terminal of the voltage processing module composed of capacitor banks, and the discharge current source conducts not a reference signal capacitor, but the negative input terminal of the threshold trigger detector of the positive and negative differential segments, which is the positive terminal of the capacitor of the voltage processing module; in this implementation, the reference signal voltage remains unchanged, while the input voltage signal of the voltage-to-time converter continuously decreases; the voltage-to-time conversion in related technologies will destroy the input voltage signal. However, the embodiment of this application does not destroy the input voltage signal. Secondly, in related technologies, the working cycles of the time-to-voltage converter and the voltage-to-time converter are arranged serially, that is, the time-to-voltage converter only starts discharging the output load capacitor after the time pulse signal of the voltage-to-time converter is generated, and finally the discharge current source of the positive and negative terminals stops discharging at a preset time point. In the embodiment of this invention, the working cycles of the time-to-voltage converter and the voltage-to-time converter are partially parallel; for example... Figure 3 As shown, the control clock CLK of the time-to-voltage converter TV The effective change edge (rising edge) is greater than the control clock signal CLK of the voltage-time converter. TVThe effective change edge (rising edge) is delayed by a preset time; that is, the start of the discharge current source's operating cycle of the time-to-voltage converter is delayed by a preset time compared to the start of the voltage-to-time converter's operating cycle. As described above, the end of the discharge current source's operating cycle of the time-to-voltage converter is the moment when the output of the voltage-to-time converter generates a time pulse signal. At the moment when the voltage-to-time converter completes the conversion, the time-to-voltage converter also completes the conversion simultaneously. Compared with the serial voltage-to-time-to-voltage conversion of related technologies, the parallel voltage-to-time and time-to-voltage conversion provided in this application embodiment saves the operating time of the time domain amplifier and improves the speed of voltage amplification.

[0093] In related technologies, the loop filter of a noise-shaping analog-to-digital converter (ADC) using a successive approximation ADC as the quantizer is typically an FIR (finite impulse response) filter, corresponding to an EF (error feedback) structure; or an IIR (infinite impulse response) filter, corresponding to a CIFF (cascade integrator error feed-forward) structure; or a hybrid of the two. The loop filter provided in this application is a first-order EF + first-order CIFF structure with an integrator voltage feedback path. Compared to the traditional first-order EF + first-order CIFF structure, the system's quantization noise transfer function has two conjugate complex zeros, achieving notch filtering of quantization noise. For the high-speed noise-shaping ADC provided in this application, strong quantization noise suppression is still achieved even at low oversampling rates. Compared to the traditional second-order EF structure, the system's transfer function is less sensitive to the residual amplification gain in the loop filter, increasing the robustness of the quantization noise suppression effect.

[0094] In noise-shaping successive approximation analog-to-digital converters (ADCs) related to this technology, the system's NTF (noise transfer function) typically has the following form:

[0095]

[0096] Here, H_EF is the transfer function for FIR, corresponding to the EF structure; H_CIFF is the transfer function for IIR, corresponding to the CIFF structure. Their first-order general forms are:

[0097] H EF =az -1 ;

[0098]

[0099] Therefore, the general form of the two zeros of the NTF of the first-order EF + first-order CIFF structure noise shaping successive approximation analog-to-digital converter in the related art is:

[0100] z1 = a, z2 = c;

[0101] Both of these zeros are real zeros; for a low-over-sampling noise shaping analog-to-digital converter, the suppression effect of quantization noise is limited by the oversampling ratio; in the traditional related art, a second-order noise feedback structure can achieve two complex zeros and achieve a notch filtering effect; the general form of the NTF therein is:

[0102] NIF(z) = 1 - H EF = 1 - 2az -1 + az -2 ;

[0103] Among them, 0 < a < 1, so such a system has two complex zeros as:

[0104]

[0105] In the related art, the loop filter in the noise shaping successive approximation analog-to-digital converter usually relies on an amplifier to amplify the quantization residue of the successive approximation analog-to-digital converter; the gain of the loop filter residue amplifier directly affects the coefficient a; in the related art, a dynamic open-loop amplifier is usually used to achieve higher energy efficiency and simple design complexity; however, the corresponding amplifier has a problem of unstable gain, that is, the NTF of the system is unstable; this will destroy the quantization noise suppression effect of the system.

[0106] A first-order EF + first-order CIFF structure loop filter with an integrator voltage feedback path provided by an embodiment of the present application, compared with the prior art, feeds back the output of the IIR to the input of the loop filter after delaying one cycle and adds it to the output of the FIR; as Figure 7 shown, the general form of the NTF of the system is:

[0107]

[0108] where d is the feedback coefficient of the integrator voltage; in some embodiments, as Figure 7 shown, the forms of the transfer function of the FIR and the transfer function of the IIR are:

[0109] H EF = Az -1 = Gaz <着 -1 ;

[0110]

[0111] Where G represents the gain of the quantization residual amplifier (time-domain amplifier) ​​in the loop filter, a represents the ratio of the value of the first extraction capacitor in the loop filter to the value of the parallel capacitor of the noise feedback capacitor plus the extraction capacitor, b represents the ratio of the value of the second extraction capacitor in the loop filter to the value of the two sets of integrating capacitors, the integrator feedback capacitor, and the parallel capacitor of the second extraction capacitor, and c represents the ratio of the values ​​of the two sets of integrating capacitors in the loop filter to the value of the parallel capacitor of the two sets of integrating capacitors, the integrator feedback capacitor, and the second extraction capacitor.

[0112] If the FIR and IIR have the above forms, then a pair of conjugate zeros of the system are:

[0113]

[0114] The embodiments of this application can achieve notch filtering of quantization noise, while the NTF is less sensitive to the gain of the loop filter residual amplifier in the loop filter.

[0115] In some embodiments, to achieve the above objectives, another aspect of this application provides a control method for a noise-shaping pipeline successive approximation analog-to-digital converter, the method comprising the following steps:

[0116] The input voltage signal of the auxiliary capacitor digital-to-analog converter is quantized by an auxiliary successive approximation analog-to-digital converter to obtain the first-level digital code. The first-level digital code is processed by a skip detection logic to control the first-level voltage processing module to generate the first-level residual. The residual amplifier amplifies the first-level residual, and then the amplified first-level residual is quantized by a dual-channel noise-shaping successive approximation analog-to-digital converter to obtain the second-level digital code. The quantization noise generated by the noise-shaping successive approximation analog-to-digital converter in the second-level digital code is filtered by a loop filter. The filtered quantization noise and the amplified first-level residual are summed by a charge-shaping circuit to obtain a mixed signal. The mixed signal is quantized by a multi-input comparator to obtain the digital output.

[0117] Specifically, such as Figure 5 As shown, the auxiliary successive approximation analog-to-digital converter quantizes the input voltage signal on the auxiliary CDAC into digital code, and simultaneously through... Figure 7 The detection skip logic controls the first-stage voltage processing module to generate the first-stage residual. The residual amplifier amplifies the first-stage residual and outputs it to the second-stage voltage processing module, where it is alternately quantized by the second-stage two-channel analog-to-digital converter.

[0118] Figure 5 It shows the working status of multiple modules at different stages. Figure 5It includes modules such as an auxiliary successive approximation analog-to-digital converter (ADC), a first-stage voltage processing module, a residual amplifier, a second-stage ADC, a loop filter, and a timing-triggered amplifier. Each module has a corresponding operating stage, such as input signal sampling, first-stage ADC, idle, first-stage residual amplification, amplifier reset, amplification, second-stage ADC voltage processing module reset, channel one noise feedback capacitor reset, channel two first-stage ADC, and channel two residual amplification. These stages are distinguished by different colors and labels, clearly presenting the timing arrangement and operating state transitions of each module throughout the entire ADC process. Figure 6 The table shows the rows representing different values ​​of the first-level conversion result, from 1111 to 0000, and the columns representing the first, second, and third capacitor groups. Gray fills indicate that the capacitor group is in a skipped state under the corresponding conversion result, while white fills indicate it is in a switched state. This table provides a clear visual representation of the detection skip logic for each capacitor group under different conversion results, helping to understand the switching and skipping mechanisms of capacitor groups during analog-to-digital conversion.

[0119] In some embodiments, the dual-channel noise-shaping successive approximation analog-to-digital converter with a loop filter includes four operating states: First operating state: The second extraction capacitor shares charge with the integrating capacitor of the first channel of the second stage and the integrator output feedback capacitor through a charge-sharing circuit; The first extraction capacitor shares charge with the integrator output feedback capacitor and noise feedback capacitor of the second channel of the second stage through a charge-sharing circuit; The voltage after the noise feedback capacitor and the integrating capacitor of the second channel are connected in series and the voltage signal on the voltage processing module of the second stage are summed and quantized through a multi-input comparator;

[0120] Second operating state: The noise feedback capacitor of channel one is reset by connecting to the common-mode voltage through switch control; the integrating capacitor and the integrator output feedback capacitor of channel one are kept in their current state by switch control. At this time, channel one is in the process of successive approximation quantization of the amplified first-stage residual signal; the sum of the quantization residual voltage of channel two and the voltage across the noise feedback capacitor is amplified by the time domain converter and sampled onto the first and second extraction capacitors of the differential signal.

[0121] Third working state: Channel 1 and Channel 2 alternately perform the same operations as in the first working state;

[0122] Fourth working state: Channel 1 and Channel 2 alternately perform the same operations as in the second working state.

[0123] Specifically, such as Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12As shown. A schematic diagram of the overall signal flow of the system is shown below. Figure 7 As shown, in order to achieve Figure 7 The noise shaping and loop filter circuit implementation are as follows: Figures 8 to 12 As shown. Figure 8 The single-channel structure diagram of the second-stage noise-shaping successive approximation analog-to-digital converter (ADC) details the internal circuit structure and working principle of a single channel of the ADC. This channel includes components such as capacitors, amplifiers, and comparators. The capacitors are used to sample and store the charge of the input signal, the amplifiers are used to amplify the signal, and the comparators are used to compare the amplified signal with a reference voltage, thereby realizing analog-to-digital conversion. Figure 8 The clock signal controls the timing of each component, ensuring that the circuit performs sampling, amplification, and comparison operations at the correct times. This structure allows a single channel to perform analog-to-digital conversion on the input voltage signal, while the coordinated operation of multiple channels further improves conversion performance and flexibility.

[0124] like Figure 8 As shown, the loop filter includes first and second noise feedback capacitors, first and second integrating capacitors, first and second integrator feedback capacitors, a loop filter residual amplifier, and a residual extraction capacitor bank. The negative terminals of the first and second noise feedback capacitors are the input terminals of the loop filter and are connected to the output terminals of the voltage processing modules of the corresponding first and second channels respectively through a switching unit. The positive terminals of the first and second noise feedback capacitors are connected in series with the first and second integrating capacitors respectively to the second input terminals of the comparison modules of the corresponding first and second channels. The positive terminals of the first and second noise feedback capacitors can be connected to the input terminals of the loop filter residual amplifier through a switching unit. The loop filter provided in this embodiment can be called an amplifier-assisted, capacitor-stacking, first-order noise feedback + first-order cascaded integrator feedforward loop filter with an integrator voltage feedback path.

[0125] More specifically, the loop filter works in conjunction with a two-channel SAR ADC and has four operating states. In some implementations, the loop filter operates as follows: Figures 9 to 12 As shown: When the loop filter is in its first operating state, the first channel is in the reset and idle phase, and the second channel is in the analog-to-digital conversion phase; as... Figure 9As shown, the filtered quantization noise is summed with the amplified first-stage residual through a charge-sharing circuit; the first extraction capacitors (CEX1 P / CEX1 N) of the two differential circuits are respectively connected to the integrator output feedback capacitors (CFBP) of the two differential circuits in channel two. <2> / CFBN <2> ) and the two differential noise feedback capacitors (CINT1 P) of channel two. <2> / CINT1 N <2> Charge sharing is achieved in parallel; the two differential second extraction capacitors (CEX2P / CEX2N) are respectively connected to the two differential integrator output feedback capacitors (CFBP) of channel one. <1> / CFBN <1> ), Channel 1 integrating capacitor (CINT2P) <1> / CINT2N <1> ) and the integrating capacitor (CINT2P) of channel two <2> / CINT2N <2> Charge sharing is achieved in parallel; the noise feedback capacitor (CINT1 P) of channel two <2> / CINT1 N <2> ) and integrating capacitor (CINT2P) <2> / CINT2N <2> The filtered second-stage residual differential signal is obtained by cascading and summing the signals, and then passed through a multi-input comparator and a second-stage voltage processing module (CDACP). <2> / CDACN <2> The voltage signals on the two differential noise feedback capacitors of channel two are summed and quantized. The signals stored in the two differential extraction capacitors (CEX2P / CEX2N) of channel two are the signals stored in the first extraction capacitors (CEX2P / CEX2N) of channel two and the signals stored in the two differential integrator output feedback capacitors (CFBP) of channel two. <2> / CFBN <2> The weighted sum of the stored signals; the two differential integrating capacitors (CINT2P) of channel two. <2> / CINT2N <2> The stored signal is the result of integrating the signal stored by the second extraction capacitor (CEX2P / CEX2N) of the previous two differentials; where the two differential integrator output feedback capacitors CFBP of channel one are... <1> / CFBN <1> The purpose of the parallel behavior is to extract the integrating capacitor (CINT2P) of storage channel two. <2> / CINT2N <2> The stored signal; the integrating capacitor (CINT2P) of channel one. <1> / CINT2N <1> The purpose of the parallel connection is to synchronize the integrating capacitors (CINT2P) between the two channels. <1> / CINT2N <1> and CINT2P <2> / CINT2N <2> The signals stored. For example... Figure 7 , Figure 8 As shown, the signals stored in the second FIR capacitor and the second IIR capacitor of the loop filter are:

[0126] V FIR =aG(V res +V FIR z -1 )-dV IIR z -1 ;

[0127] V IIR =bG(Vres +V FIR z -1 )+cV IIR z -1 ;

[0128] Where V_res represents the residual voltage, which is the second-level quantization residual stored at the output of the second-level voltage processing module after the second-level analog-to-digital conversion stage. FIR This represents the voltage signal stored in the noise feedback capacitor; in reality, due to the reset behavior, this value is 0. V IIR This represents the voltage signal stored in the integrating capacitor.

[0129] When Figure 5 As shown, when the first channel is in the first-stage residual sampling input stage and the second channel is in the second-stage quantization residual amplification stage, the loop filter is in the second operating state, and the two differential noise feedback capacitors (CINT1P) of channel one... <1> / CINT1N <1> The two ends of the circuit are connected to the common-mode voltage, i.e., in the reset state; the two differential integrator output feedback capacitors (CFBP) of channel one. <1> / CFBN <1> ) and integrating capacitor (CINT2P) <1> / CINT2N <1> ) is disconnected from other switches, i.e., maintains its state; the two differential noise feedback capacitors (CINT1P) of the second channel <2> / CINT1N <2> Each of these capacitors is connected in series with its corresponding CDAC, and then connected to the differential input of the time-domain converter; the first and second residual extraction capacitors are connected to the differential output of the loop filter residual amplifier (time-domain amplifier), sampling the amplified second-stage quantization residual. Figure 7 As shown, the signal V_EX stored in the first and second capacitors of the loop filter is:

[0130] V EX =G(V) res +V FIR z -1 );

[0131] When Figure 5 As shown, when the first channel is in the digital conversion stage and the second channel is in the reset and idle stage, the loop filter is in the third working state, with channel one and channel two working alternately, just like the first state of the loop filter. Similarly, when the first channel is in the residual amplification stage and the second channel is in the first stage residual input stage, the loop filter is in the fourth working state, with channel one and channel two working alternately, just like the second state of the loop filter.

[0132] In some embodiments, the filtered quantization noise and the amplified first-stage residual are summed by a charge-sharing circuit, including the following steps: in the first and third operating states of the loop filter, charge sharing is achieved through a differential capacitor network; in the second and fourth operating states of the loop filter, the voltage signal is summed and amplified through a time-domain converter.

[0133] Specifically, the second extraction capacitors (CEX2P / CEX2N) of the two differentials are respectively connected to the two differential integration capacitors (CINT2P) of the two channels. <1> / CINT2N <1> and CINT2P <2> / CINT2N <2> ) and the two differential integrator output feedback capacitors (CFBP) of channel one. <1> / CFBN <1> Charge sharing is performed. In the second-stage analog-to-digital converter, the amplified first-stage residual and the filtered second-stage quantization noise are summed and then quantized together.

[0134] Optional, Figure 7 The parameters in the system signal flow graph shown are... Figure 8 The correspondence between the device parameters in the loop filter circuit structure shown is as follows:

[0135]

[0136] Among them, C INT1 C INT2 These represent the capacitance values ​​of the FIR and IIR capacitors, respectively. EX1 C EX2 C represents the capacitance values ​​of the first and second residual extraction capacitors, respectively. FB This represents the capacitance value of the integrator feedback capacitor. It should be noted that the coefficients a, b, c, and d, which are related to the system's quantization noise transfer function, are related to the ratio of the capacitance values ​​of several capacitors in the loop filter circuit structure, but are independent of the absolute values ​​of these capacitors. In relevant integrated circuit manufacturing processes, the absolute capacitance values ​​of capacitors may have errors, but a reasonable arrangement on the layout can ensure that the capacitance ratios between several capacitors in the loop filter are very accurate. This ensures, from a circuit implementation perspective, the robustness of the quantization noise suppression effect of the noise-shaping pipelined analog-to-digital converter provided in this application embodiment.

[0137] Optionally, the ratio of the capacitance values ​​of the individual capacitors in the loop filter is:

[0138] C INT1 :C INT2 :C EX1 :C EX2 :C FB = 40:40:1:2:2;

[0139] Optionally, the coefficients related to the quantization noise transfer function in the corresponding system's signal flow graph are:

[0140]

[0141] Optionally, in order to achieve the quantization noise notch filtering effect of the analog-to-digital converter provided in this application embodiment, the gain of the loop filter residual amplifier needs to meet certain requirements; if the system parameters are as described above, then the gain of the loop filter residual amplifier needs to meet the following requirements:

[0142] 26.28 < G < 63.81;

[0143] In some embodiments, such as Figure 13 The flowchart shown illustrates the CDAC control algorithm quantizing into digital code. The auxiliary successive approximation analog-to-digital converter quantizes the input voltage signal of the auxiliary capacitor analog-to-digital converter using a capacitor analog-to-digital converter control algorithm to obtain the first-level digital code. Specifically, Figure 13 This describes the workflow of the capacitor bank during analog-to-digital conversion. First, during pre-discharge of the positive terminals of capacitor group i to the signal input port, the negative terminal of the first capacitor in the same group is connected to the reference signal terminal, and the negative terminal of the second capacitor is grounded. Then, the positive terminals of multiple capacitor groups are disconnected from the signal input port, and i is initialized to 1. Next, the comparison module determines whether the positive input voltage is greater than the negative input voltage. If yes, the negative terminal of the first capacitor in the i-th positive capacitor group is grounded, and the negative terminal of the second capacitor in the i-th negative capacitor group is connected to the reference signal terminal; if no, the negative terminal of the second capacitor in the i-th positive capacitor group is connected to the reference signal terminal, and the negative terminal of the first capacitor in the i-th negative capacitor group is grounded. Afterward, i is incremented by 1, and it is determined whether i equals N (the number of bits in the capacitor bank). If not, the comparison continues; if yes, the conversion is complete. This process achieves bit-by-bit analog-to-digital conversion through the control and comparison of the capacitor banks.

[0144] In some embodiments, the amplified first-stage residual is quantized by a dual-channel noise-shaping successive approximation analog-to-digital converter, including the following steps: when channel one is in the reset and idle phase of the capacitor-to-digital converter, channel two quantizes the amplified first-stage residual; when channel one is sampling the amplified first-stage residual, channel two amplifies the quantized residual voltage and samples it onto the first extraction capacitor.

[0145] In some embodiments, this application adds a hybrid structure of noise feedback and cascaded integrator feedforward, and adds a feedback path for the integrator output. A noise transfer function with a pair of conjugate complex zeros is constructed in the structure of first-order noise feedback and first-order cascaded integrator feedforward, achieving high-efficiency notch filtering and more stable noise shaping. To address the problem of unstable amplification coefficients in dynamic open-loop amplification in loop filters, this application employs a time-domain auxiliary converter based on the current-to-current ratio and capacitance-to-voltage ratio of the current source, i.e., voltage-time-to-voltage conversion, to achieve robust residual amplification due to process, supply voltage, and temperature. Finally, to address the problem of long residual amplification times in traditional methods, this application adopts a time-domain auxiliary converter that performs voltage-time conversion and time-voltage conversion in parallel.

[0146] In some embodiments, the overall architecture of the ADC system in this application is a pipelined analog-to-digital converter. The first stage uses an auxiliary analog-to-digital converter to generate a first-stage digital code, which is then used to generate a residual through a first-stage CDAC. The residual is amplified by a residual amplifier and output to a second-stage analog-to-digital converter for quantization. Noise shaping and analog-to-digital conversion are completed in the second stage. The loop filter consists of a residual amplifier and a switched-capacitor circuit, realizing residual amplification, residual feedback, residual integration feedforward, and feedback of the integrator output. The design of the voltage-to-time converter and the control method of the time-to-voltage converter enable the common-mode voltage voltage-to-time-to-voltage converter to achieve high speed, stable gain, and stable output for the noise-shaping pipelined successive approximation analog-to-digital converter.

[0147] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0148] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0149] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0151] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0152] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0153] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0154] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0156] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A noise-shaping pipelined successive approximation analog-to-digital converter, characterized in that, include: The first stage includes an auxiliary successive approximation analog-to-digital converter and a first-stage voltage processing module. The auxiliary successive approximation analog-to-digital converter is used to quantize and decompose the input voltage signal and output a digital code. The first-stage voltage processing module obtains the first-stage residual voltage based on the digital code. The second stage includes a dual-channel noise-shaping successive approximation analog-to-digital converter and a loop filter; each channel of the noise-shaping successive approximation analog-to-digital converter includes a comparator; the loop filter includes an integrating capacitor, a noise feedback capacitor, and an integrator output feedback capacitor in each of the two channels, as well as a first extraction capacitor and a second extraction capacitor shared by the two channels. A residual amplifier, the input of which is connected to the first-stage voltage processing module, and the output of which is connected to the noise-shaping successive approximation analog-to-digital converter. A sampling switch module, wherein the input terminal of the sampling switch module is connected to the differential input voltage signal, and the output terminal of the sampling switch module is connected to the first-stage voltage processing module and the auxiliary voltage processing module of the auxiliary successive approximation analog-to-digital converter, respectively. A digital code aligner, wherein the first input terminal of the digital code aligner is connected to the output terminal of the comparator of the auxiliary analog-to-digital converter, and the second input terminal of the digital code aligner is connected to the output terminal of the comparator of the second stage.

2. The noise-shaping pipeline successive approximation analog-to-digital converter according to claim 1, characterized in that, The quantization bit depth of the first and second stages and the bit depth of the analog-to-digital converter are set according to the performance of the noise-shaping pipeline successive approximation analog-to-digital converter.

3. The noise-shaping pipeline successive approximation analog-to-digital converter according to claim 1, characterized in that, The residual amplifier includes a dynamic open-loop voltage amplifier.

4. The noise-shaping pipeline successive approximation analog-to-digital converter according to claim 1, characterized in that, It also includes voltage-to-time converters and time-to-voltage converters, wherein: The scanning reference voltage is obtained by scanning from high level to low level through the discharge capacitor. The voltage-time converter compares the differential input voltage signal with the scanning reference voltage; and generates two time pulse signals with a time delay difference based on the comparison result of the differential input voltage signal and the scanning reference voltage. The time-voltage converter starts after a fixed delay after the voltage-time converter starts working, and converts the time pulse signal into a differential voltage difference signal through different discharge times; The voltage-time converter and the time-voltage converter operate in parallel, and the time-voltage converter completes its conversion simultaneously when the voltage-time converter completes its conversion.

5. The noise-shaping pipeline successive approximation analog-to-digital converter according to claim 4, characterized in that, It also includes a replica voltage-time converter; The replica voltage-time converter is used to generate a replica delay signal that is a fixed time shorter than the delay of the voltage-time converter. The replica delay signal is used to stabilize and control the output common-mode voltage of the time domain converter. The loop filter feeds back the output common-mode voltage of the time-to-voltage converter to the input common-mode voltage.

6. A control method for a successive approximation analog-to-digital converter in a noise-shaping pipeline, characterized in that, The method is applied to the noise-shaping pipeline successive approximation analog-to-digital converter as described in any one of claims 1-5, and the method includes the following steps: The input voltage signal of the auxiliary capacitor digital-to-analog converter is quantized by the auxiliary successive approximation analog-to-digital converter to obtain the first-level digital code. The first-level digital code is processed by the detection skip logic, and the first-level voltage processing module is controlled to generate the first-level residual. After the residual amplifier amplifies the first-stage residual, the amplified first-stage residual is quantized by the dual-channel noise-shaping successive approximation analog-to-digital converter to obtain the second-stage digital code. The loop filter is used to filter the quantization noise generated by the noise-shaping successive approximation analog-to-digital converter in the second-level digital code. The filtered quantization noise and the amplified first-stage residual are summed using a charge-sharing circuit to obtain a mixed signal. The mixed signal is quantized using a multi-input comparator to obtain a digital output.

7. The method according to claim 6, characterized in that, The noise-shaping successive approximation analog-to-digital converter, in conjunction with the loop filter and dual channels, includes four operating states: First operating state: The charge sharing circuit enables the second extraction capacitor to share charge with the integrating capacitor of the second stage channel one and the integrator output feedback capacitor. The charge-sharing circuit enables the first extraction capacitor to share charge with the integrator output feedback capacitor and noise feedback capacitor of the second-stage channel two. The voltage of the noise feedback capacitor and the integrating capacitor in the second channel, and the voltage signal on the voltage processing module of the second stage are summed and quantized by a multi-input comparator. Second operating state: The noise feedback capacitor of channel one is reset by connecting to the common-mode voltage through switch control; The switching control keeps the integrating capacitor and the integrator output feedback capacitor of channel one in their current state. At this time, channel one is performing successive approximation quantization on the amplified first-stage residual signal. The sum of the quantization residual voltage of channel two and the voltage across the noise feedback capacitor is amplified by a time-domain converter and sampled onto the first extraction capacitor and the second extraction capacitor of the differential circuit. Third working state: Channel 1 and Channel 2 alternately perform the same operations as in the first working state; Fourth working state: Channel 1 and Channel 2 alternately perform the same operations as in the second working state.

8. The method according to claim 7, characterized in that, The step of summing the filtered quantization noise with the amplified first-stage residual using a charge-sharing circuit includes the following steps: In the first and third operating states of the loop filter, charge sharing is achieved through a differential capacitor network; In the second and fourth operating states of the loop filter, the voltage signal is summed and amplified by the time-domain converter.

9. The method according to claim 6, characterized in that, The auxiliary successive approximation analog-to-digital converter quantizes the input voltage signal of the auxiliary capacitor digital-to-analog converter through a capacitor analog-to-digital converter control algorithm to obtain the first-level digital code.

10. The method according to claim 6, characterized in that, The quantization of the amplified first-stage residual using the dual-channel noise-shaping successive approximation analog-to-digital converter includes the following steps: When channel one is in the reset and idle phase of the capacitor digital-to-analog converter, channel two quantizes the amplified first-stage residual. When the first channel is in the first stage residual after sampling and amplification, the second channel amplifies the quantized residual voltage and samples it onto the first extraction capacitor.

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