Digital calibration method and system for multi-phase clock

Abstract

The invention discloses a digital calibration method and system for a multi-phase clock, and relates to the technical field of digital communication systems and digital signal processing, and the method comprises the steps: selecting a training sequence type, and configuring a sampling circuit; pI Codes are fixed, input data are sampled according to a set training sequence, corresponding clock phases of the initialized PI Codes are recovered through a curve fitting algorithm, and a plurality of PI Codes are fixed in sequence; analyzing the deviation between the actually measured phase of each phase clock and the ideal phase, and quantifying the systematic deviation by drawing a curve; calculating a pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; the pre-distortion function obtained through calculation is stored in a nonvolatile storage space of a chip; and when the chip works normally, the stored predistortion function is read, real-time compensation is carried out through the digital logic circuit, and a calibrated clock phase index is generated. According to the invention, high-efficiency clock recovery and data sampling alignment are realized through a digital calibration method and a pre-distortion function.

Description

Technical Field

[0001] The present invention relates to the technical field of digital communication system and digital signal processing, in particular to a digital calibration method and system for a multi-phase clock. Background Art

[0002] Clock signals play a fundamental and critical role in digital communication systems and digital signal processing. With the continuous increase in communication rates, multi-phase clock technology has become an indispensable part of high-speed data transmission systems. Phase Interpolator (PI), as the core component of multi-phase clock generation, generates multiple clock signals with different phases based on the reference clock signal to ensure that data bits can be sampled at the optimal phase point, thereby maximizing the signal-to-noise ratio (SNR) and improving the overall performance of the system. As the number of phases increases, systematic deviations of the phase delay module are inevitably introduced in the actual circuit implementation, resulting in significant deviations between the actual phase curve and the ideal phase curve. Such deviations not only reduce the accuracy of clock recovery, but also have a negative impact on the data sampling accuracy and system signal-to-noise ratio of the digital communication system.

[0003] Although the existing multi-phase clock recovery technology can reduce phase deviation to a certain extent through dynamic phase adjustment, it still has many shortcomings. First, traditional methods rely on the fine design and process matching of analog circuits, and it is difficult to achieve high-precision phase control in a digital environment. Especially when the number of phases is large, the complexity and cost of system design increase significantly. Secondly, as the number of phases increases, the power consumption and chip area of ​​the system also increase linearly or even nonlinearly, limiting its application in large-scale integrated circuits. In addition, since systematic deviations are difficult to completely eliminate through traditional methods, the error between the actual phase curve and the ideal phase curve still exists, which in turn affects the accuracy of data sampling and the stability of the communication system. Summary of the invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a digital calibration method and system for a multi-phase clock to solve the phase error problem caused by systematic deviation in actual circuit implementation of the multi-phase clock.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: In a first aspect, an embodiment of the present invention provides a digital calibration method for a multi-phase clock, which includes selecting a training sequence type and configuring a sampling circuit; fixing a PI Code, sampling input data according to a set training sequence, restoring the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and fixing multiple PI Codes in sequence; analyzing the deviation between the actual measured clock phase of each phase and the ideal phase, and quantifying the systematic deviation by drawing a curve; calculating a pre-distortion function based on the difference between the actual phase curve and the ideal phase curve; storing the calculated pre-distortion function in a non-volatile storage space of a chip; when the chip is working normally, reading the stored pre-distortion function, compensating in real time through a digital logic circuit, and generating a calibrated clock phase index.

[0007] As a preferred solution of the digital calibration method for a multi-phase clock of the present invention, the training sequence types include sine waves, triangle waves and sawtooth waves.

[0008] As a preferred solution of the digital calibration method of the multi-phase clock of the present invention, wherein: fixing the PICode, sampling the input data according to the set training sequence, restoring the corresponding clock phase of the initialized PI Code by a curve fitting algorithm, and fixing multiple PI Codes in sequence, the following steps are included: Set PI Code to 0 through the control interface and confirm that the phase interpolator outputs the clock signal, whose phase should correspond to the predetermined phase of PI Code 0; Use an oscilloscope or logic analyzer to monitor the output of the clock signal and confirm that the frequency of the clock signal is consistent with the reference clock source and the phase is as expected; According to the set training sequence, the receiving end uses the clock signal to sample the input data to obtain a digital signal sequence; Collect known training sequence parameters and acquired digital signal sequences; Use the least mean square error algorithm Fit the collected data and calculate the optimal clock phase , taking the sinusoidal training sequence as an example, its expression is, ; in, is the clock phase parameter to be determined, is the sampling number, For the The time interval between subsampling, For the The digital signal value obtained by sampling is is the signal amplitude, is the signal frequency; Set the initial phase estimate according to The optimization goal is to iteratively adjust until it converges to the optimal solution ; When the phase adjustment amount is less than the predetermined threshold ϵ, the iteration stops and the current As a result of recovery; Repeat the above steps, traverse the PI Code, and get the optimal phase As PI Code The clock phase corresponding to the time.

[0009] As a preferred solution of the digital calibration method of the multi-phase clock of the present invention, the deviation between the phase of each phase clock obtained by actual measurement and the ideal phase is analyzed, and the systematic deviation is quantified by drawing a curve, including the following steps: Determine the number of clock cycles and phases; For each PI Code , calculate its corresponding ideal clock phase; Get each PI Code recovered The actual clock phase corresponding to For each PI Code , calculate the deviation between its actual phase and the ideal phase; PI Code The horizontal axis is the calculated phase deviation, and the vertical axis is the phase deviation curve plotted against PI Code. Observe the plotted phase deviation curves to identify if there is an obvious pattern; Through statistical analysis methods, the characteristics of the deviation patterns are further quantified; Based on the identified deviation patterns, determine the main components and characteristics of the deviation; If the deviation curve is close to a straight line, it is considered a linear deviation. If the deviation curve presents a curve or other complex shapes, it is considered a nonlinear deviation. If the deviation curve shows periodic fluctuations, the frequency and amplitude of the periodic deviation are analyzed. For linear deviations, the slope and intercept are quantified; for nonlinear deviations, the high-order coefficients and low-order coefficients are quantified; for periodic deviations, the frequency and amplitude are quantified.

[0010] As a preferred solution of the digital calibration method of the multi-phase clock of the present invention, the pre-distortion function is calculated according to the difference between the actual phase curve and the ideal phase curve, including the following steps: The actual phase Forming an actual phase curve; Based on the calculated ideal phase, an ideal phase curve is defined; Define the objective function of the PI Code error after calibration; For each PI Code , corresponding to an actual phase ; Using numerical methods to Perform an approximate inverse operation and calculate the predistortion function based on the error minimization objective. The expression is: ; in, As the pre-distortion function, PI Code Mapped to new PI Code index , is the approximate inverse function of the actual phase curve, is the clock period, is the number of phases; Collect all actual phases = , and the corresponding PI Code index ; According to the characteristics of the actual phase curve, select the interpolation method, perform interpolation operation on the actual phase curve, and calculate The approximate value of The calculated pre-distortion function values ​​are organized into a discrete mapping table.

[0011] As a preferred solution of the digital calibration method of the multi-phase clock of the present invention, wherein: the calculated pre-distortion function is stored in the non-volatile storage space of the chip, comprising the following steps: Determine the storage capacity required for the pre-distortion function, evaluate the access speed requirements for the pre-distortion function when the chip is working normally, and consider the writing frequency of the pre-distortion function; Select the type of non-volatile memory based on storage requirements; According to the number of phases, the address range and data width of the memory are determined; Constructing a predistortion mapping table according to the calculated predistortion function; Convert the data of the pre-distortion mapping table into a format recognizable by the memory, ensuring that the encoding bit width of each mapping value meets the storage specification of the memory; According to the memory requirements, the pre-distortion mapping table data is organized into a programming format of the memory to ensure that the data arrangement sequence is consistent with the address correspondence of the memory; The pre-distortion map is written into the selected non-volatile memory through the programming interface.

[0012] As a preferred solution of the digital calibration method of the multi-phase clock of the present invention, when the chip is working normally, the stored pre-distortion function is read, and the calibrated clock phase index is generated by real-time compensation through the digital logic circuit, including the following steps: When the chip is working normally, the pre-distortion mapping table is read from the non-volatile memory; Monitor and obtain the PI Code of the current phase interpolator input , searching for the corresponding pre-distortion value in the loaded pre-distortion mapping table; Assign the found pre-distortion mapping value to the new PI Code index ; Index the new PI Code Passed to the phase interpolator to update the clock signal output.

[0013] In a second aspect, the present invention provides a digital calibration system for a multi-phase clock, comprising: a training sequence generation module, responsible for selecting a training sequence type and configuring a sampling circuit; a clock phase recovery module, responsible for fixing a PI Code, sampling input data according to a set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and fixing multiple PI Codes in sequence; a phase deviation analysis module, responsible for analyzing the deviation between the actual measured clock phase of each phase and the ideal phase, and quantifying the systematic deviation by drawing a curve; a pre-distortion function calculation module, responsible for calculating a pre-distortion function based on the difference between an actual phase curve and an ideal phase curve; a non-volatile storage module, responsible for storing the calculated pre-distortion function in a non-volatile storage space of a chip; and a pre-distortion application module, responsible for reading the stored pre-distortion function when the chip is working normally, performing real-time compensation through a digital logic circuit, and generating a calibrated clock phase index.

[0014] In a third aspect, an embodiment of the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, any step of the digital calibration method for a multi-phase clock as described in the first aspect of the present invention is implemented.

[0015] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, any step of the digital calibration method for a multi-phase clock as described in the first aspect of the present invention is implemented.

[0016] The beneficial effects of the present invention are as follows: by generating pre-distortion parameters for real-time compensation, it is ensured that the multi-phase clock system can dynamically adjust the PI Code in actual operation to achieve precise phase alignment; based on efficient and accurate pre-distortion function calculation, the systematic phase deviation is significantly reduced, the alignment accuracy of the clock signal and the signal-to-noise ratio of the overall system are improved, thereby enhancing the performance of the high-speed digital communication system and the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 This is a flow chart of the digital calibration method for a multi-phase clock in Example 1.

[0019] Figure 2 This is a flow chart of the digital calibration system for the multi-phase clock in Example 1. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0021] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0022] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0023] Example 1, reference Figure 1 and Figure 2 , which is the first embodiment of the present invention, provides a digital calibration method for a multi-phase clock, comprising the following steps: S1. Select the training sequence type and configure the sampling circuit; S1.1. According to the selected training sequence type (sine wave, triangle wave and sawtooth wave), switch the signal generator to the corresponding working mode; For sine waves, select a known and stable frequency, set a clear amplitude, ensure that the signal is within the linear range of the sampling circuit, and set the frequency and amplitude to predetermined values, and ensure that the phase is set to 0 or other predetermined values ​​to simplify the measurement; for triangle waves, set a known period and the slope of the signal rise and fall to ensure that the signal rise and fall phases are smooth and meet expectations; for sawtooth waves, set a known period, the slope of the signal rise and fall, and ensure that the sharp change part of the signal meets the measurement requirements; Use an oscilloscope or other measuring instruments to verify whether the parameters of the generated training sequence signal meet expectations. Based on the actual measurement results, fine-tune the signal generator parameters to ensure the accuracy and stability of the signal. Check the noise level and distortion of the training sequence signal to ensure the signal transmission quality in the sampling circuit. If necessary, add filters or other signal processing modules to optimize the signal quality.

[0024] S1.2. Use high-quality connecting wires or interfaces to firmly connect the output of the signal generator to the input of the sampling circuit, ensuring impedance matching of the connection path to avoid signal reflection and distortion; According to the input requirements of the sampling circuit, adjust the level of the training sequence signal to make it within the optimal working range of the circuit. If necessary, use an amplifier or attenuator to adjust the signal amplitude; Ensure that the transmission of the training sequence signal is synchronized with the system clock to avoid phase drift during signal transmission. Use a low-latency, high-stability transmission path to reduce phase errors during signal transmission. Use an oscilloscope or logic analyzer to detect the signal status at the input of the sampling circuit, confirm that the signal is transmitted correctly, and check whether the signal waveform is consistent with the output of the training sequence generator to ensure signal integrity; After confirming that the signal transmission is correct, set the sampling trigger conditions of the sampling circuit and prepare for the subsequent data acquisition process.

[0025] S2, fix the PI Code, sample the input data according to the set training sequence, restore the corresponding clock phase of the initialized PI Code through the curve fitting algorithm, and fix multiple PI Codes in sequence, including the following steps, S2.1. Set the PI Code to 0 through the control interface, that is, set the input PI Code of the phase interpolator to 0, and confirm that the phase of the phase interpolator output clock signal CLK[0] should correspond to the predetermined phase of PI Code 0; Use an oscilloscope or logic analyzer to monitor the output of the clock signal to ensure that the signal is stable and has no obvious distortion. Confirm that the frequency of the clock signal is consistent with the reference clock source and the phase is as expected.

[0026] S2.2. According to the set training sequence, the receiving end uses the clock signal to sample the input data to obtain a digital signal sequence; Specifically, the sampling circuit is activated so that it starts to sample the input training sequence according to the rising edge or falling edge of CLK[0], ensuring that the sampling clock is synchronized with the training sequence to avoid sampling errors caused by clock drift; under the control of the clock CLK[0], the receiving end samples the input training sequence M times, records the digital signal value of each sampling point, and obtains a digital signal sequence.

[0027] S2.3, collect known training sequence parameters (amplitude, frequency) and acquired digital signal sequence; Use the least mean square error algorithm Fit the collected data and calculate the optimal clock phase , so that the fitting error is minimized. Taking the sine training sequence as an example, its expression is: ; in, is the clock phase parameter to be determined, is the sampling number, For the The time interval between samplings, For the The digital signal value obtained by sampling is is the signal amplitude, is the signal frequency; Set the initial phase estimate according to The optimization goal is to iteratively adjust until it converges to the optimal solution ; When the phase adjustment amount is less than the predetermined threshold ϵ, the iteration stops and the current As a result of recovery.

[0028] S2.4, repeat the above steps S2.1, S2.2 and S2.3 to obtain the optimal phase As PI Code The clock phase corresponding to the time.

[0029] S3, analyzing the deviation between the actual measured phase of each phase clock and the ideal phase, and quantifying the systematic deviation by drawing a curve, including the following steps, S3.1. Determine the clock period, i.e., the duration of a single clock signal, and the number of phases, i.e., the number of different phases contained in a multi-phase clock; For each PI Code ( ), calculate the corresponding ideal clock phase, the expression is, ; in, PI Code The ideal clock phase at is the clock period, is the number of phases, It is the current PI Code index; Get each PI Code recovered The actual clock phase corresponding to ; For each PI Code , calculate the deviation between its actual phase and the ideal phase; S3.2, with PI Code The horizontal axis is the calculated phase deviation, and the vertical axis is the phase deviation curve plotted against PI Code. Observe the plotted phase deviation curve to identify whether there is an obvious pattern, such as linear deviation, nonlinear deviation or periodic deviation; Linear deviation: the deviation changes with Linear increase or decrease may be caused by systematic errors; nonlinear deviation: the deviation increases or decreases with It changes nonlinearly, which may be caused by nonlinear components or other complex factors. Periodic deviation: The deviation changes with It fluctuates periodically and may be caused by jitter or high-frequency interference of the clock signal.

[0030] Further quantify the characteristics of the deviation pattern through statistical analysis methods, such as regression analysis and Fourier transform; for example, fit the linear component of the deviation curve to determine the deviation growth rate, use Fourier transform to detect the frequency component in the deviation curve, and identify periodic interference; Prepare a phase deviation analysis report that describes in detail the identified deviation patterns and characteristics, and provides supporting graphs and statistical data.

[0031] S3.3. Based on the identified deviation patterns, determine the main components and characteristics of the deviation; If the deviation curve is close to a straight line, it is considered as a linear deviation, which can be described by a first-order polynomial model. If the deviation curve is a curve or other complex shape, it is considered as a nonlinear deviation, which may require a higher-order polynomial model or other nonlinear model to describe. If the deviation curve shows periodic fluctuations, analyze the frequency and amplitude of the periodic deviation. The periodic deviation may be caused by high-frequency noise or clock jitter, and filtering or noise suppression measures need to be considered. For linear deviations, the slope and intercept are quantified; for nonlinear deviations, the high-order coefficients and low-order coefficients are quantified; for periodic deviations, the frequency and amplitude are quantified.

[0032] S4, calculating the predistortion function according to the difference between the actual phase curve and the ideal phase curve, including the following steps: S4.1、The actual phase The actual phase curve is formed, which is expressed as, ; in, PI Code The actual phase at PI Code The actual clock phase at Based on the calculated ideal phase, the ideal phase curve is defined as, ; in, PI Code The ideal phase of Define the objective function of the PI Code error after calibration so that it can be minimized, expressed as, ; in, By pre-distortion function The actual phase after mapping; S4.2. For each PI Code , corresponding to an actual phase ; because Usually no analytical inverse function is available, and numerical methods are needed to To perform approximate inverse operations, commonly used numerical methods include interpolation and inverse interpolation; Based on the error minimization objective, the predistortion function is calculated and expressed as: ; in, As the pre-distortion function, PI Code Mapped to new PI Code index , is the approximate inverse function of the actual phase curve, mapping the ideal phase back to the actual phase, is the clock period, is the number of phases.

[0033] S4.3. Collect all actual phases = , and the corresponding PI Code index ; According to the characteristics of the actual phase curve, select the interpolation method: Linear interpolation: simple and less computational, suitable for situations where the phase change is relatively linear; Spline interpolation: suitable for situations where there is a nonlinear trend in the phase change, providing a smoother fitting effect; Polynomial interpolation: suitable for complex phase change models, but may introduce high-order oscillations; Use the selected interpolation method to interpolate the actual phase curve and calculate An approximation of ; for example (linear interpolation): For each ideal phase , find the two closest points on the actual phase curve and ; Calculate the corresponding PI Code index through linear interpolation , the expression is, ; in, ; The calculated predistortion function values ​​are organized into a predistortion mapping table to ensure the integrity and accuracy of the mapping table and the actual phase curve Closely correspond.

[0034] S5, storing the calculated pre-distortion function in the non-volatile storage space of the chip, including the following steps: S5.1. Determine the storage capacity required for the pre-distortion function. For N phases, the pre-distortion function is usually stored in the form of a lookup table (LUT). Each PI Code corresponds to an integer mapping value. Evaluate the access speed requirements for the pre-distortion function when the chip is working normally, ensure that the memory can meet the needs of real-time compensation, and consider the writing frequency of the pre-distortion function. The foreground calibration stage usually only needs one write, which is suitable for one-time programming or low-write memory; Select the type of non-volatile memory based on storage requirements, including but not limited to E-Fuse, one-time programmable memory, and electrically erasable programmable read-only memory; Determine the address range and data width of the memory according to the number of phases. For example, if N=8, 8 storage addresses are required, each address stores a pre-distortion function mapping value, ensuring that the selected memory can cover the storage requirements of all N PI Codes. S5.2. constructing a predistortion mapping table according to the calculated predistortion function; The data of the pre-distortion map is converted into a format recognizable by the memory, for example, each The value is converted to binary representation, ensuring that the encoding bit width of each mapped value conforms to the storage specification of the memory. For example, if The value range of is 0 to 15, so each mapping value can be represented by 4 bits of binary; According to the memory requirements, the pre-distortion mapping table data is organized into the programming format of the memory. For example, for EEPROM, the data can be formatted into a page programming format to ensure that the data arrangement order is consistent with the address correspondence of the memory to avoid data storage errors; The pre-distortion map is written into the selected non-volatile memory through the programming interface.

[0035] S6. When the chip is working normally, the stored pre-distortion function is read, and real-time compensation is performed through a digital logic circuit to generate a calibrated clock phase index, including the following steps: When the chip is working normally, the pre-distortion mapping table is read from the non-volatile memory; Read the pre-distortion mapping table one by one from the non-volatile memory through a programming interface (such as I²C, SPI or other protocols), perform preliminary verification on the read data to ensure data integrity and correctness, and load the effective pre-distortion function into the digital logic circuit for real-time compensation; Monitor and obtain the PI Code of the current phase interpolator input , searching for the corresponding pre-distortion value in the loaded pre-distortion mapping table; Assign the found pre-distortion mapping value to the new PI Code index ; Index the new PI Code Passed to the phase interpolator to update the clock signal output; Index the calibrated PI Code The input is to the phase interpolator, which outputs a calibrated clock signal to ensure the best alignment of the phase of the clock signal with the data bits.

[0036] The present embodiment also provides a digital calibration system for a multi-phase clock, including: a training sequence generation module, responsible for selecting a training sequence type and configuring a sampling circuit; a clock phase recovery module, responsible for fixing a PI Code, sampling input data according to a set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and fixing multiple PI Codes in sequence; a phase deviation analysis module, responsible for analyzing the deviation between the actual measured clock phase of each phase and the ideal phase, and quantifying the systematic deviation by drawing a curve; a pre-distortion function calculation module, responsible for calculating a pre-distortion function according to the difference between an actual phase curve and an ideal phase curve; a non-volatile storage module, responsible for storing the calculated pre-distortion function in a non-volatile storage space of a chip; a pre-distortion application module, responsible for reading the stored pre-distortion function when the chip is working normally, and generating a calibrated clock phase index by real-time compensation through a digital logic circuit.

[0037] This embodiment also provides a computer device, which is suitable for the digital calibration method of a multi-phase clock, including: a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute computer executable instructions to implement the digital calibration method of a multi-phase clock proposed in the above embodiment.

[0038] The computer device may be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covered on the display screen, or a key, trackball or touchpad provided on the housing of the computer device, or an external keyboard, touchpad or mouse, etc.

[0039] This embodiment also provides a storage medium on which a computer program is stored. When the program is executed by a processor, the digital calibration method for a multi-phase clock as proposed in the above embodiment is implemented; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, referred to as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, referred to as EEPROM), erasable programmable read-only memory (Erasable Programmable Read Only Memory, referred to as EPROM), programmable read-only memory (Programmable Red-Only Memory, referred to as PROM), read-only memory (Read-Only Memory, referred to as ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0040] In summary, the present invention achieves generation and capture of reference signals with known characteristics by selecting appropriate training sequence types and accurately configuring sampling circuits, ensuring that the training sequence signals have stable frequency and amplitude, completing accurate and consistent phase reference data acquisition, and providing reliable reference signals for subsequent phase measurements; systematically acquiring clock phase information at each phase to ensure high precision and consistency of phase recovery, achieving comprehensive phase mapping and accurate clock phase recovery, providing detailed data support for subsequent phase deviation analysis and pre-distortion function calculation, and improving the calibration accuracy of the multi-phase clock system; identifying the specific mode of the deviation, clarifying the nature and characteristics of the systematic deviation, and achieving accurate quantitative analysis of the deviation, so that the design of the pre-distortion function can be optimized for specific deviation characteristics, ensuring the effectiveness of the calibration effect and the improvement of system performance; generating pre-distortion parameters for real-time compensation, ensuring that the multi-phase clock system can dynamically adjust the PI Code in actual operation, achieving accurate phase alignment, and significantly reducing the systematic phase deviation based on efficient and accurate pre-distortion function calculation, improving the alignment accuracy of the clock signal and the signal-to-noise ratio of the overall system, thereby enhancing the performance of the high-speed digital communication system and the reliability of data transmission.

[0041] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A digital calibration method for a multi-phase clock, characterized in that: include, Select the training sequence type and configure the sampling circuit; Fix the PI Code, sample the input data according to the set training sequence, restore the corresponding clock phase of the initialized PI Code through the curve fitting algorithm, and fix multiple PI Codes in sequence; Analyze the deviation between the actual measured clock phase of each phase and the ideal phase, and quantify the systematic deviation by drawing a curve; Calculating a predistortion function according to a difference between an actual phase curve and an ideal phase curve; The calculated pre-distortion function is stored in the non-volatile storage space of the chip; When the chip is working normally, the stored pre-distortion function is read and compensated in real time through the digital logic circuit to generate a calibrated clock phase index.

2. The digital calibration method of a multi-phase clock according to claim 1, characterized in that: The training sequence types include sine wave, triangle wave and sawtooth wave.

3. The digital calibration method of a multi-phase clock according to claim 2, characterized in that: Fix the PI Code, sample the input data according to the set training sequence, restore the corresponding clock phase of the initialized PI Code through the curve fitting algorithm, and fix multiple PI Codes in sequence, including the following steps: Set PI Code to 0 through the control interface and confirm that the phase interpolator outputs the clock signal, whose phase should correspond to the predetermined phase of PICode 0; Use an oscilloscope or logic analyzer to monitor the output of the clock signal and confirm that the frequency of the clock signal is consistent with the reference clock source and the phase is as expected; According to the set training sequence, the receiving end uses the clock signal to sample the input data to obtain a digital signal sequence; Collect known training sequence parameters and acquired digital signal sequences; Use the least mean square error algorithm Fit the collected data and calculate the optimal clock phase , taking the sinusoidal training sequence as an example, its expression is, ； in, is the clock phase parameter to be determined, is the sampling number, For the The time interval between subsampling, For the The digital signal value obtained by sampling is is the signal amplitude, is the signal frequency; Set the initial phase estimate according to The optimization goal is to iteratively adjust until it converges to the optimal solution ; When the phase adjustment amount is less than the predetermined threshold ϵ, the iteration stops and the current As a result of recovery; Repeat the above steps, traverse the PI Code, and get the optimal phase As PI Code The clock phase corresponding to the time.

4. The digital calibration method of a multi-phase clock according to claim 3, characterized in that: Analyze the deviation between the actual measured clock phase and the ideal phase of each phase, and quantify the systematic deviation by drawing a curve, including the following steps: Determine the number of clock cycles and phases; For each PI Code , calculate its corresponding ideal clock phase; Get each PI Code recovered The actual clock phase corresponding to For each PI Code , calculate the deviation between its actual phase and the ideal phase; PI Code The horizontal axis is the calculated phase deviation, and the vertical axis is the phase deviation curve plotted against PI Code. Observe the plotted phase deviation curves to identify if there is an obvious pattern; Through statistical analysis methods, the characteristics of the deviation patterns are further quantified; Based on the identified deviation patterns, determine the main components and characteristics of the deviation; If the deviation curve is close to a straight line, it is considered a linear deviation. If the deviation curve presents a curve or other complex shapes, it is considered a nonlinear deviation. If the deviation curve shows periodic fluctuations, the frequency and amplitude of the periodic deviation are analyzed. For linear deviations, the slope and intercept are quantified; for nonlinear deviations, the high-order coefficients and low-order coefficients are quantified; for periodic deviations, the frequency and amplitude are quantified.

5. The digital calibration method of a multi-phase clock according to claim 4, characterized in that: According to the difference between the actual phase curve and the ideal phase curve, the predistortion function is calculated, including the following steps: The actual phase Forming an actual phase curve; Based on the calculated ideal phase, an ideal phase curve is defined; Define the objective function of the PI Code error after calibration; For each PI Code , corresponding to an actual phase ; Using numerical methods to Perform an approximate inverse operation and calculate the predistortion function based on the error minimization objective. The expression is: ； in, As the pre-distortion function, PI Code Mapped to new PI Code index , is the approximate inverse function of the actual phase curve, is the clock period, is the number of phases; Collect all actual phases = , and the corresponding PI Code index ; According to the characteristics of the actual phase curve, select the interpolation method, perform interpolation operation on the actual phase curve, and calculate The approximate value of The calculated pre-distortion function values ​​are organized into a discrete mapping table.

6. The digital calibration method of a multi-phase clock according to claim 5, characterized in that: The calculated pre-distortion function is stored in the non-volatile storage space of the chip. The following steps are included: Determine the storage capacity required for the pre-distortion function, evaluate the access speed requirements for the pre-distortion function when the chip is working normally, and consider the writing frequency of the pre-distortion function; Select the type of non-volatile memory based on storage requirements; According to the number of phases, the address range and data width of the memory are determined; Constructing a predistortion mapping table according to the calculated predistortion function; Convert the data of the pre-distortion mapping table into a format recognizable by the memory, ensuring that the encoding bit width of each mapping value meets the storage specification of the memory; According to the memory requirements, the pre-distortion mapping table data is organized into a programming format of the memory to ensure that the data arrangement sequence is consistent with the address correspondence of the memory; The pre-distortion map is written into the selected non-volatile memory through the programming interface.

7. The digital calibration method of a multi-phase clock according to claim 6, characterized in that: When the chip is working normally, the stored pre-distortion function is read and compensated in real time by the digital logic circuit to generate the calibrated clock phase index, including the following steps: When the chip is working normally, the pre-distortion mapping table is read from the non-volatile memory; Monitor and obtain the PI Code of the current phase interpolator input , searching for the corresponding pre-distortion value in the loaded pre-distortion mapping table; Assign the found pre-distortion mapping value to the new PI Code index ; Index the new PI Code Passed to the phase interpolator to update the clock signal output.

8. A digital calibration system for a multi-phase clock, based on the digital calibration method for a multi-phase clock according to any one of claims 1 to 7, characterized in that: include, The training sequence generation module is responsible for selecting the training sequence type and configuring the sampling circuit; The clock phase recovery module is responsible for fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through the curve fitting algorithm, and fixing multiple PI Codes in sequence; The phase deviation analysis module is responsible for analyzing the deviation between the actual measured clock phase of each phase and the ideal phase, and quantifying the systematic deviation by drawing a curve; The pre-distortion function calculation module is responsible for calculating the pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; A non-volatile storage module is responsible for storing the calculated pre-distortion function in the non-volatile storage space of the chip; The pre-distortion application module is responsible for reading the stored pre-distortion function when the chip is working normally, and generating a calibrated clock phase index through real-time compensation through a digital logic circuit.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the digital calibration method for a multi-phase clock according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the digital calibration method for a multi-phase clock according to any one of claims 1 to 7 are implemented.

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