Satellite communication link high dynamic latency simulation system, method, device and medium

Abstract

The application relates to a satellite communication link high-dynamic time delay simulation system, method, equipment and medium, the system comprises an upper computer parameter configuration module and an FPGA processing module, the upper computer parameter configuration module updates and issues time delay simulation parameter information, the FPGA processing module receives the time delay simulation parameter information through an FPGA board card, and the simulation of a dynamic time delay channel of a satellite communication system is realized, the FPGA processing module comprises a parameter processing module, an integer time delay module, a fractional time delay module and a dynamic time delay control module, the dynamic time delay control module shares hardware with the fractional time delay module, 2 times upsampling is integrated into the fractional time delay module during dynamic time delay simulation, and the number of parallel channels is increased from one to two through interpolation; the equipment and the medium are used for saving a computer program, and when the program is executed, the time delay simulation method is completed; the system can save resources occupied by upsampling and solve the problem of unmatched input and output data rates.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of satellite communication, and particularly relates to a satellite communication link high-dynamic time delay simulation system, method, device and medium. BACKGROUND

[0002] Satellite communication has the advantages of wide coverage and being not affected by land disasters, and can effectively make up for the defects of insufficient coverage of ground cellular networks, and has made an important contribution to the development of space-ground-sea integrated technology; in the development process of a satellite communication system, a channel environment of satellite communication needs to be simulated to analyze the actual communication performance of a satellite in orbit, specifically, due to high cost and difficulty in implementing channel testing of satellite communication, a channel simulation system is usually relied on for performance testing; in a satellite communication link, due to a relatively long distance between a transmitter and a receiver, a signal propagation time delay is much larger than that of a land mobile communication system, and simultaneously, due to the satellite being in constant high-speed motion, the relative position of the transmitter and the receiver is constantly changing, and the transmission time delay of the satellite channel link also constantly changes with time, which will affect the reliability and accuracy of the communication system.

[0003] Due to the dynamic change of the time delay, the input data rate and the output data rate of the dynamic time delay module will be mismatched, but in actual engineering, the output data still needs to be output at the frequency of the sampling clock; therefore, in the process of dynamic time delay simulation, the problem of matching the input data rate and the output data rate of the dynamic time delay module needs to be solved, so as to achieve the purpose of continuous output of data.

[0004] In the prior art, an invention with the patent publication number “CN111064503B” and the name “satellite channel high-dynamic time delay Doppler simulation system” proposes that the fractional time delay module runs at a clock slightly higher than the sampling frequency, which can solve the problem of mismatching of the input data and the output data rates; wherein, the higher the clock frequency used by the module, the higher the time delay change rate can be achieved, and the time delay change rate is determined by the ratio of the satellite radial flight rate to the speed of light, because the satellite radial flight rate is much lower than the speed of light, so the module running clock can be slightly higher than the sampling clock, which can ensure that the data is not read empty in the subsequent step of reading data at the sampling frequency, thereby solving the problem of mismatching of the input data and the output data rates; however, the clock resources in the FPGA are limited, and using a clock slightly higher than the sampling clock to run the module will consume additional clock resources, and cross-clock-domain processing will cause additional resource loss.

[0005] In the prior art, a master's thesis entitled "Key Technologies and Verification of Long Dynamic Delay Satellite Channel Simulation" (Xu Mengran. Key Technologies and Verification of Long Dynamic Delay Satellite Channel Simulation [D]. University of Electronic Science and Technology, 2023.) proposes that when the integer delay part needs to be adjusted, the read address of the memory is changed to adjust; in the case of increasing the integer delay, the read address of the memory remains unchanged by pausing data reading to adjust; in the case of reducing the integer delay, the read address of the memory is changed forward by skipping reading the next data to adjust; although this dynamic delay control algorithm solves the problem of mismatch between input data and output data rates, the continuity of the phase between output data is destroyed. SUMMARY

[0006] In order to overcome the above-mentioned shortcomings of the prior art, the purpose of the present application is to propose a satellite communication link high dynamic delay simulation system, method, device and medium; the system is designed by sharing the upsampling and fractional delay module in hardware, which integrates 2x upsampling into the fractional delay module while simulating dynamic delay, and increases the parallel number of data from 1 to 2 through interpolation; 2x upsampling is 2x interpolation, which, combined with the decimation processing part of the slowly changing dynamic delay, changes the decimation processing that causes the output data to be unable to be continuously read out into interpolation processing, solves the problem of mismatch between input data and output data rates caused by dynamic delay simulation, and accurately simulates the characteristics of the high dynamic delay of the satellite communication link.

[0007] To achieve the above technical purpose, the technical scheme adopted by the present application is as follows:

[0008] In a first aspect, a satellite communication link high dynamic delay simulation system includes a host computer parameter configuration module and an FPGA processing module; the host computer parameter configuration module updates and issues delay simulation parameter information in real time through a host computer, and transmits the delay simulation parameter information to the FPGA processing module through an Ethernet UDP protocol through a network port; the delay simulation parameter information includes integer delay, fractional delay and delay change rate; the FPGA processing module receives the delay simulation parameter information through an FPGA board card and realizes simulation of a dynamic delay channel of a satellite communication system; the FPGA processing module includes a parameter processing module, an integer delay module, a fractional delay module and a dynamic delay control module:

[0009] The parameter processing module is configured to configure and update the integer delay, fractional delay and delay change rate issued by the host computer, and to distribute the integer delay, fractional delay and delay change rate to the integer delay module and fractional delay module, respectively;

[0010] The integer delay module is configured to simulate the integer delay part of the integer multiple sampling period of the delay of the satellite communication link;

[0011] The fractional delay module simulates the fractional delay part of the non-integer multiple sampling period of the satellite communication link delay through a Farrow structure filter;

[0012] The dynamic delay control module, by sharing hardware of upsampling and the fractional delay module, integrates 2 times upsampling into the fractional delay module while simulating the dynamic delay, thereby increasing the parallel number of data from 1 to 2 through interpolation, and dynamically adjusts the integer delay module and the fractional delay module through the feedback signal, for real-time dynamic adjustment of the integer delay part and the fractional delay part of the satellite communication link delay.

[0013] In a second aspect, a high dynamic delay simulation method for a satellite communication link comprises the following steps:

[0014] S1: The host computer parameter configuration module transmits the integer delay, the fractional delay and the delay change rate to the FPGA processing module through the host computer;

[0015] S2: After the parameter processing module receives the integer delay, the fractional delay and the delay change rate issued by the host computer in step S1, it stores them, wherein the integer delay, the fractional delay and the delay change rate issued for the first time in step S1 are the integer delay initial value, the fractional delay initial value and the delay change rate initial value, and the delay change rate issued for the first time in step S1 is the delay change rate update value; the parameter processing module assigns the integer delay initial value to the integer delay module, and assigns the fractional delay initial value, the delay change rate initial value and the delay change rate update value to the fractional delay module;

[0016] S3: After the integer delay module receives the input baseband signal and the integer delay initial value in step S2, it simulates the long delay characteristics of the delay through DDR, FIFO or RAM, and outputs the signal simulated by the integer delay;

[0017] S4: After the fractional delay module receives the signal simulated by the integer delay in step S3 and the fractional delay initial value, the delay change rate initial value and the delay change rate update value in step S2, the fractional delay module uses the NCO (numerical control oscillator) in the Farrow structure filter to accumulate the fractional delay initial value and the delay change rate initial value, and updates them using the delay change rate update value, and then outputs the feedback signal;

[0018] S5: After the integer delay module receives the feedback signal in step S4, the dynamic delay control module inputs the storage data of the DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable in the integer delay module, and the fractional delay module performs fractional interpolation and finally outputs the data simulated by the dynamic delay to the outside world.

[0019] Further, step S1 specifically comprises the following steps:

[0020] S11: The host computer calculates the real-time communication distance L(t) between the satellite and the ground terminal through the spatial geometric position relationship of the satellite orbit and the ground terminal, so as to obtain the satellite communication link transmission delay T(t), and the expression is:

[0021]

[0022] Wherein, c is the speed of light;

[0023] S12: Assuming that the multiple of the signal sampling period delay at the kth moment is τ(k), the satellite communication link transmission delay T(t) described in step S11 is converted into the multiple of the signal sampling period delay τ(k), and the expression is:

[0024] τ(k) = T(t) f s

[0025] Wherein, f s is the sampling frequency, unit: Hz;

[0026] S13: The τ(k) described in step S12 is divided into two parts, the integer delay τ int (k) and the fractional delay τ frac (k), and the expression is:

[0027] τ(k) = τ int (k) + τ frac (k)

[0028] S14: Assuming that the multiple of the signal sampling period delay at the k+1th moment is τ(k+1), and Δτ(k) is the delay change from the kth moment to the k+1th moment, and the expression is:

[0029] Δτ(k) = τ(k+1) - τ(k)

[0030] S15: Assuming that Δt(k) is the time difference from the kth moment to the k+1th moment, and combining the τ(k) and τ(k+1) described in steps S13 and S14, the delay change rate τ var (k) can be expressed as:

[0031]

[0032] S16: The integer delay, fractional delay and delay change rate described in steps S13 and S15 are transmitted to the FPGA processing module through the network port by using the Ethernet UDP protocol.

[0033] Further, step S2 specifically comprises the following steps:

[0034] S21: The parameter processing module receives and stores the integer delay, fractional delay and delay rate sent by the host computer in step S1, and assigns the initial value of the integer delay sent by the host computer for the first time to the integer delay module, and assigns the initial values of the fractional delay and the delay rate to the fractional delay module;

[0035] S22: The parameter processing module updates the updated value of the delay rate sent by the host computer for the first time in step S1 to the fractional delay module.

[0036] Further, step S3 specifically comprises the following steps:

[0037] S31: The integer delay module receives the input baseband signal and the initial value of the integer delay in step S2, and performs bit width matching and cross clock domain processing on the baseband signal in FIFO1 of the integer delay module through write buffering, and the processed baseband signal is sent to DDR;

[0038] S32: The integer delay module completes long delay characteristic simulation of the processed baseband signal in step S31 in DDR and FIFO2. Specifically, through the control between the write enable of FIFO1 and the read enable of FIFO2, the integer delay simulation accurate to one clock cycle is realized, and the simulated DDR integer delay signal is output to FIFO2;

[0039] S33: In the integer delay simulation, FIFO2 performs bit width matching and cross clock domain processing on the DDR integer delay signal in step S32 through read buffering, obtains the signal after integer delay simulation and outputs it to the fractional delay module.

[0040] Further, step S4 specifically comprises the following steps:

[0041] S41: After receiving the signal after integer delay simulation in step S3, the NCO of the fractional delay module accumulates the input delay rate τ var (k) to update the read enable v(k) of the data buffering submodule in the fractional delay module in real time, and the specific process is as follows:

[0042] Assuming that the fractional delay factor of the accumulation register at the kth moment is R N (k), the working principle of the NCO can be represented as:

[0043] R N (k)=mod(R N (k-1)+τ var ,1)=μ(k)

[0044] v(k)=R N (k-1)+τ var -mod(RN (k-1)+τ var ,1)

[0045] S42: The data buffer submodule is controlled by the read enable v(k) updated in real time in step S41, receives the signal simulated by the integer time delay in step S33, generates and outputs a feedback signal by the amount of data stored in the FIFO.

[0046] Further, step S5 specifically comprises the following steps:

[0047] S51: The integer time delay module receives the feedback signal in step S4, the dynamic time delay control module adjusts the dynamic duty cycle of the read enable in the integer time delay module to realize dynamic adjustment of the time delay, and then inputs the stored data of the DDR, FIFO and RAM in the integer time delay module into the fractional time delay module according to the dynamic duty cycle of the read enable;

[0048] Specifically, when the amount of stored data in the data buffer submodule of the fractional time delay module is less than half of the maximum amount of stored data, the read enable of FIFO2 in the integer time delay module is changed from 0 to 1 through the feedback signal; when the amount of stored data in the data buffer submodule of the fractional time delay module is greater than or equal to half of the maximum amount of stored data, the read enable of FIFO2 in the integer time delay module is changed from 1 to 0 through the feedback signal; when the amount of stored data in FIFO2 in the integer time delay module is less than half of the maximum amount of stored data, the read enable of DDR in the integer time delay module is changed from 0 to 1 through the feedback signal; when the amount of stored data in FIFO2 in the integer time delay module is greater than or equal to half of the maximum amount of stored data, the read enable of DDR in the integer time delay module is changed from 1 to 0 through the feedback signal;

[0049] S52: The NCO accumulates the input time delay rate τ var (k) to calculate the fractional time delay factor μ(k) of each clock in real time and update the read enable v(k) of the data buffer submodule in the fractional time delay module;

[0050] S53: The data buffer submodule receives the signal simulated by the integer time delay output in step S3, and outputs the interpolation base point and the stored data matched with the fractional time delay factor μ(k) at each clock.

[0051] S54: The fractional time delay module receives the stored data of DDR, FIFO and RAM according to the dynamic duty cycle of the read enable in step S51, the Farrow structure filter in the fractional time delay module uses μ(k) output in step S52, v(k) and the interpolation base point and the stored data output in step S53, realizes fractional time delay simulation through the Farrow structure filter and the 3rd order Lagrange cubic interpolation, and finally outputs dynamic time delay simulation data to the outside world.

[0052] Further, in step S54, 2 times upsampling is integrated into the fractional delay module while simulating the dynamic time delay, so that the originally 1-way data is increased to 2-way data in parallel through interpolation, 2 times upsampling is 2 times interpolation, and is combined with the decimation processing part of the slowly changing dynamic time delay, so that the decimation processing which causes the output data to be unable to be continuously read out is changed to interpolation processing, that is, there is no τ int (k+1) = τ int (k)-1 such a situation.

[0053] In a third aspect, an electronic device includes a memory and a processor:

[0054] The memory is used to store a computer program for implementing the satellite communication link high dynamic time delay simulation method.

[0055] The processor is used to execute the computer program to implement the satellite communication link high dynamic time delay simulation method.

[0056] In a fourth aspect, a computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the satellite communication link high dynamic time delay simulation method.

[0057] Compared with the prior art, the beneficial effects of the present application are:

[0058] 1. In the satellite communication link high dynamic time delay simulation method of the present application, the host computer can simulate the dynamic time delay scenario of the satellite communication link in real time by issuing configuration parameters in real time in step S1, which has high flexibility and wide application range.

[0059] 2. In the satellite communication link high dynamic time delay simulation method of the present application, the Farrow structure filter used in step S4 does not need to change the filter coefficients when the fractional delay factor changes, so it does not need to store a large amount of space for filter coefficients, saving resource consumption.

[0060] 3. In the satellite communication link high dynamic time delay simulation method of the present application, the upsampling and fractional delay module are designed to share hardware in step S5, 2 times upsampling is integrated into the fractional delay module while simulating the dynamic time delay, so that the originally 1-way data is increased to 2-way data in parallel through interpolation, 2 times upsampling is 2 times interpolation, and is combined with the decimation processing part of the slowly changing dynamic time delay, so that the decimation processing which causes the output data to be unable to be continuously read out is changed to interpolation processing, that is, there is no τ

[0061] In summary, this method utilizes the collaborative processing among the integer delay module, fractional delay module, and dynamic delay control module. It shares hardware design between the upsampling and fractional delay modules, integrating double upsampling into the fractional delay module while simulating dynamic delay. This increases the number of parallel data streams from one to two through interpolation, transforming decimation processing into interpolation processing. This not only reduces resource consumption but also solves the input-output data rate mismatch problem caused by dynamic delay simulation, thereby accurately simulating the high dynamic delay characteristics of satellite communication links. Attached Figure Description

[0062] Figure 1 This is a block diagram of the high dynamic delay simulation system for satellite communication links described in this invention.

[0063] Figure 2 This is a flowchart of the high dynamic delay simulation method for satellite communication links described in this invention.

[0064] Figure 3 This is a diagram of the Farrow structure filter of the fractional delay module in the high dynamic delay simulation method for satellite communication links described in this invention.

[0065] Figure 4 This is a Farrow structure diagram of the Lagrange cubic interpolation filter of the fractional delay module in the satellite communication link high dynamic delay simulation method described in this invention.

[0066] Figure 5 This is a structural diagram of the dynamic delay control module in the satellite communication link high dynamic delay simulation method described in this invention.

[0067] Figure 6 This is a hardware structure diagram of the dynamic delay module in the satellite communication link high dynamic delay simulation method described in this invention. Detailed Implementation

[0068] The following is combined Figures 1 to 6 The present invention will be described in further detail below.

[0069] Firstly, such as Figure 1 As shown, a high dynamic delay simulation system for satellite communication links includes a host computer parameter configuration module and an FPGA processing module. The host computer parameter configuration module calculates, updates, and distributes delay simulation parameter information in real time via a host computer, and transmits the delay simulation parameter information to the FPGA processing module through a network port using the Ethernet UDP protocol. The delay simulation parameter information includes integer delay, fractional delay, and delay change rate. The FPGA processing module receives the delay simulation parameter information through an FPGA board and simulates the dynamic delay channel of the satellite communication system. The FPGA processing module includes a parameter processing module, an integer delay module, a fractional delay module, and a dynamic delay control module.

[0070] The parameter processing module is configured to configure and update the integer delay, the fractional delay, and the delay change rate transmitted by the upper computer, and to respectively allocate the integer delay, the fractional delay, and the delay change rate to the integer delay module and the fractional delay module.

[0071] The integer delay module is configured to simulate the integer delay part of the integer multiple of the sampling period of the satellite communication link delay.

[0072] The fractional delay module is configured to simulate the fractional delay part of the non-integer multiple of the sampling period of the satellite communication link delay through a Farrow structure filter.

[0073] The dynamic delay control module is configured to, through hardware sharing design of upsampling and the fractional delay module, integrate 2 times upsampling into the fractional delay module while simulating the dynamic delay, thereby increasing the parallel number of data from 1 to 2 through interpolation, and dynamically adjusting the integer delay module and the fractional delay module through a feedback signal, for real-time dynamic adjustment of the integer delay part and the fractional delay part of the satellite communication link delay.

[0074] In a second aspect, as shown in Figure 2 The satellite communication link high dynamic delay simulation method comprises the following steps:

[0075] S1: The upper computer parameter configuration module calculates the real-time communication distance between the satellite and the ground terminal within the satellite visible window time through the upper computer, thereby obtaining the transmission delay simulation parameter information of the satellite communication link. The transmission delay simulation parameter information includes the integer delay, the fractional delay, and the delay change rate. The upper computer parameter configuration module transmits the integer delay, the fractional delay, and the delay change rate to the FPGA processing module through the upper computer. Specifically, the upper computer transmits the transmission delay simulation parameter information to the FPGA board card of the FPGA processing module through the network port by using the Ethernet UDP protocol.

[0076] S2: After receiving the integer delay, the fractional delay, and the delay change rate transmitted by the upper computer in step S1, the parameter processing module stores them. The integer delay, the fractional delay, and the delay change rate transmitted for the first time in step S1 are respectively the integer delay initial value, the fractional delay initial value, and the delay change rate initial value. The delay change rate transmitted for the first time in step S1 is the delay change rate update value. The parameter processing module allocates the integer delay initial value to the integer delay module, and allocates the fractional delay initial value, the delay change rate initial value, and the delay change rate update value to the fractional delay module.

[0077] S3: The integer delay module receives the input baseband signal through an analog-to-digital converter and the integer delay initial value described in step S2, and then simulates the long delay characteristic of the delay through a DDR, FIFO or RAM memory, the delay length being the integer delay initial value, and outputs the signal after the integer delay simulation; as shown in Figure 6 , the wide-range delay simulation of the input baseband signal is realized through the reading and writing of the DDR memory, and the additional baseband input signal also completes the simulation of the partial integer multiple delay in the FIFO;

[0078] S4: The fractional delay module receives the signal after the integer delay simulation described in step S3 and the fractional delay initial value, the delay rate initial value and the delay rate update value described in step S2, and as shown in Figure 3 , the fractional delay module adds the fractional delay initial value and the delay rate initial value through the NCO (numerical control oscillator) in the Farrow structure filter (i.e. the variable fractional delay filter based on the Farrow structure), and updates using the delay rate update value, which can realize the high-precision characteristic of the delay, thereby outputting the feedback signal;

[0079] S5: After receiving the feedback signal described in step S4, the integer delay module receives the reading enable dynamic duty cycle of the output 2-way data in the dynamic delay control module, and inputs the storage data of the DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the reading enable dynamic duty cycle, and the fractional delay module finally outputs the data after the dynamic delay simulation to the outside world through fractional interpolation.

[0080] Further, step S1 specifically includes the following steps:

[0081] S11: The host computer calculates the real-time communication distance L(t) between the satellite and the ground terminal through the spatial geometric position relationship of the satellite orbit and the ground terminal, thereby obtaining the satellite communication link transmission delay T(t), and the expression is:

[0082]

[0083] Wherein, c is the speed of light, c = 3 × 10 8 m / s;

[0084] S12: The essence of the digital signal delay is to change the position of the signal sampling point, assuming that the multiple delay of the signal sampling period at the kth moment is τ(k), and the satellite communication link transmission delay T(t) described in step S11 is converted into the multiple delay τ(k) of the signal sampling period, and the expression is:

[0085] τ(k) = T(t) · f s

[0086] wherein f s is the sampling frequency, in Hz;

[0087] S13: divide the τ(k) in step S12 into an integer delay τ int (k) and a fractional delay τ frac (k), and the expression is:

[0088] τ(k) = τ int (k) + τ frac (k)

[0089] S14: assuming that the multiple of the signal sampling period at the k+1 time is τ(k+1), and Δτ(k) is the delay change from the k time to the k+1 time, and the expression is:

[0090] Δτ(k) = τ(k+1) - τ(k)

[0091] S15: assuming that Δt(k) is the time difference from the k time to the k+1 time, and combining the τ(k) and τ(k+1) in step S13 and step S14, then the delay change rate τ var (k) can be expressed as:

[0092]

[0093] S16: transmit the integer delay, the fractional delay, and the delay change rate in step S13 and step S15 to the FPGA processing module through the network port using the Ethernet UDP protocol; wherein the one-time parameters issued by the host computer parameter configuration module include the integer delay and the fractional delay; and the real-time parameters issued by the host computer parameter configuration module include the delay change rate.

[0094] Further, step S2 specifically includes the following steps:

[0095] S21: after the parameter processing module receives the integer delay, the fractional delay, and the delay change rate issued by the host computer in step S1, it stores them, and assigns the integer delay initial value issued by the host computer for the first time to the integer delay module, and assigns the fractional delay initial value and the delay change rate initial value to the fractional delay module;

[0096] S22: the parameter processing module updates the delay change rate update value issued by the host computer for the first time to the fractional delay module.

[0097] Further, step S3 specifically includes the following steps:

[0098] S31: After the integer delay module receives the input baseband signal through the analog-to-digital converter and the initial value of the integer delay described in step S2, the baseband signal is subjected to bit width matching and cross-clock domain processing through write buffering in FIFO1 of the integer delay module, and the processed baseband signal is sent to the DDR;

[0099] S32: The integer delay module completes long delay characteristic simulation of the processed baseband signal described in step S31 in the DDR and FIFO2;

[0100] Specifically, through control between the write enable of FIFO1 and the read enable of FIFO2, integer delay simulation accurate to one clock cycle is realized, and the simulated DDR integer delay signal is output to FIFO2;

[0101] The read and write operations of the DDR memory are based on burst mode, which enables the memory to efficiently perform continuous data transmission tasks, but also causes the waiting time of DDR data reading to be unknown; since the simulation of the integer delay is accurate to one clock cycle, the influence of the unknown waiting time of DDR data reading is eliminated through data buffering by FIFO2; through control between the write enable of FIFO1 and the read enable of FIFO2, the integer delay simulation required by us is realized;

[0102] S33: In the integer delay simulation, FIFO2 performs bit width matching and cross-clock domain processing on the DDR integer delay signal described in step S32 through read buffering, to obtain the signal subjected to integer delay simulation and output.

[0103] Further, as shown in Figure 3 , step S4 specifically includes the following steps:

[0104] S41: NCO (numerically controlled oscillator) is the core control part of the fractional delay module. After the fractional delay module receives the signal subjected to integer delay simulation described in step S3, NCO accumulates the input delay rate τ var (k) and updates the read enable v(k) of the data buffering submodule in the fractional delay module in real time. The data buffering submodule is composed of a FIFO and a shift register, and the specific process is as follows:

[0105] Suppose the fractional delay factor of the accumulation register at the kth moment is R N (k), then the working principle of NCO can be represented as:

[0106] R N (k) = mod(R N (k-1) + τ var , 1) = μ(k)

[0107] v(k) = RN (k-1)+τ var -mod(R N (k-1)+τ var ,1)

[0108] S42: The data buffer submodule is controlled by the read enable v(k) updated in real time in step S41, receives the signal simulated by the integer time delay in step S33, generates and outputs a feedback signal by the amount of data stored in the FIFO, and feeds back the feedback signal generated by the amount of data stored in the FIFO to the integer time delay module, so as to complete the adjustment of the dynamic time delay.

[0109] Further, step S5 specifically comprises the following steps:

[0110] S51: The integer time delay module receives the feedback signal in step S4, the dynamic time delay control module adjusts the dynamic time delay by controlling the dynamic duty cycle of the read enable in the integer time delay module, and then inputs the stored data of the DDR, FIFO and RAM in the integer time delay module into the fractional time delay module according to the dynamic duty cycle of the read enable;

[0111] Specifically, when the amount of stored data in the data buffer submodule of the fractional time delay module is less than half of the maximum amount of stored data during the dynamic adjustment, the read enable of FIFO2 in the integer time delay module is changed from 0 to 1 by the feedback signal, and data is continuously provided to the data buffer submodule; when the amount of stored data in the data buffer submodule of the fractional time delay module is greater than or equal to half of the maximum amount of stored data, in order to prevent data loss caused by overflow, the read enable of FIFO2 in the integer time delay module is changed from 1 to 0 by the feedback signal, and data is stopped being provided to the data buffer submodule in the fractional time delay module; when the amount of stored data in FIFO2 in the integer time delay module is less than half of the maximum amount of stored data, the read enable of DDR in the integer time delay module is changed from 0 to 1 by the feedback signal, and data is continuously provided to FIFO2 in the integer time delay module; when the amount of stored data in FIFO2 in the integer time delay module is greater than or equal to half of the maximum amount of stored data, in order to prevent data loss caused by overflow, the read enable of DDR in the integer time delay module is changed from 1 to 0 by the feedback signal, and data is stopped being provided to FIFO2 in the integer time delay module; in this way, the dynamic adjustment of DDR, FIFO2 in the integer time delay module and the data buffer submodule in the fractional time delay module is completed, so that the goal of dynamic time delay simulation is achieved.

[0112] S52: The NCO accumulates the input time delay rate τ var (k) to calculate the fractional time delay factor μ(k) of each clock in real time and update the read enable v(k) of the data buffer submodule in the fractional time delay module;

[0113] S53: The data buffer submodule receives the signal simulated by integer delay output in step S3, and outputs the interpolation base point and registered data that match the fractional delay factor μ(k) at each clock cycle; since the delay is constantly changing dynamically, the amount of data stored in the FIFO is used to generate a feedback signal to feed back to the integer delay module, thereby completing the dynamic delay adjustment.

[0114] S54: As Figure 4 As shown, in order to enable continuous reading of output data, the fractional delay module receives the stored data of DDR, FIFO and RAM according to the dynamic duty cycle of read enable as described in step S51. The Farrow structure filter in the fractional delay module uses μ(k) and v(k) output in step S52 and the interpolation base point and register data output in step S53 to simulate the fractional delay part through the Farrow structure filter and third-order Lagrange cubic interpolation, and finally outputs the dynamic delay simulation data to the outside world.

[0115] Furthermore, such as Figure 5 and Figure 6 As shown, in step S54, while simulating dynamic delay, a 2x upsampling is integrated into the fractional delay module. This increases the number of parallel channels from one to two through interpolation. The 2x upsampling is then combined with the decimation processing of the slowly changing dynamic delay, thus transforming the decimation processing that prevents continuous reading of output data into interpolation processing. In other words, there is no τ. int (k+1)=τ int This is the case of (k)-1.

[0116] This process, by sharing hardware between the upsampling and fractional delay modules, not only saves the resources occupied by upsampling but also solves the problem of continuous reading of output data, thus having certain advantages.

[0117] The dynamic delay control module processes the data as follows:

[0118]

[0119] Since the time delay range of the Farrow structure filter is (0,1], let 0 < τ. frac (k)≤1, when τ int (k+1)=τ int When (k), the data buffer submodule inputs new data into the Farrow structure filter, and the Farrow structure filter outputs data; under this condition, the input and output data are balanced.

[0120] When τ int (k+1)=τ int(k)+1, the data buffer sub-module does not input new data to the Farrow structure filter, and the Farrow structure filter outputs data; this condition occurs in the case that the distance between the transmitter and the receiver changes from near to far, and the data in the data buffer unit will increase, which is equivalent to the interpolation processing process;

[0121] When τ int (k+1) = τ int (k)-1, the data buffer sub-module inputs new data to the Farrow structure filter for two continuous clock periods, and the Farrow structure filter outputs data; this condition occurs in the case that the distance between the transmitter and the receiver changes from far to near, which is equivalent to the decimation processing process, and can cause the output data to be unable to be continuously read out.

[0122] The Farrow structure filter is composed of a direct FIR filter, and an advantage brought by the Farrow structure filter is that the fractional delay factor μ(k) is separated from the specific filter coefficients, so that the fractional delay factor μ(k) does not need to be changed when the fractional delay factor μ(k) is changed, thereby not needing a large amount of space to store the filter coefficients, and resource consumption is saved. Meanwhile, if the delay precision is to be changed, only the precision of the fractional delay factor μ(k) needs to be changed, for example, μ(k) = 0.2, which represents a delay of 0.2 sampling periods.

[0123] The implementation process of the Farrow structure filter is as follows:

[0124] In a communication system, the frequency response of an ideal fractional delay filter is expressed as:

[0125] H d (ω, μ) = e -jωμ

[0126] wherein H d (ω, μ) is the frequency response of the ideal fractional delay filter, j represents the imaginary part of a complex number, e represents the base number of a natural logarithm, ω represents a frequency, and μ ∈ (0, 1] is a fractional delay factor; in order to approximate the frequency response of the ideal fractional delay filter, the transfer function of the fractional delay filter to be designed is expressed as:

[0127]

[0128] wherein H(z, μ) is the transfer function of the fractional delay filter, h n (μ) is a filter coefficient, and the windowing function method is to obtain the corresponding filter coefficient h n (μ) according to different approximation criteria, so as to obtain the fractional delay filter for a specific μ(k). If a polynomial of M order μ(k) is used to approximate the filter coefficient h nIf the fractional delay factor μ(k) is separated from the specific filter coefficients, the expression of the fractional delay factor μ(k) can be obtained as follows:

[0129]

[0130] where M is the order of the polynomial, n is the number of filter coefficients, and according to the above H(z, μ) and h n (z, μ) two expressions, we have:

[0131]

[0132] Let:

[0133]

[0134] The expression of the filter transfer function can be simplified as:

[0135]

[0136] The interpolation algorithms commonly used in the fractional delay filter based on the Farrow structure include linear interpolation, piecewise parabolic interpolation and Lagrange cubic interpolation, etc. Figure 4 As shown in FIG. 1, the present application adopts the third-order Lagrange cubic interpolation as the interpolation algorithm of the interpolator in the fractional delay module.

[0137] The implementation process of the Lagrange interpolation method is as follows:

[0138] The frequency domain error function can measure the approximation degree of the filter, and the frequency domain error function E(e jω ) can be expressed as:

[0139] E(e jω ) = H(e jω ) - H id (e jω )

[0140] where H(e jω ) is the frequency domain response of the actual FIR fractional delay filter h(n), and H id (e jω ) is the frequency domain response of the ideal fractional delay filter h id (n).

[0141] According to the maximum flatness criterion, the frequency domain error function E(e jω ) is as flat as possible at a certain frequency ω0 of interest, that is, the approximation degree of H(e jω ) to H id (e jω ) is the best near the frequency ω0, which can be expressed in a mathematical formula as:

[0142]

[0143] Generally, ω0=0 is selected, and the following can be obtained:

[0144]

[0145] wherein μ is a fractional delay factor, and the matrix simplification can be represented as:

[0146] Vh=v

[0147] wherein the matrix V is a Vandermonde matrix of (N+1)×(N+1), h is a coefficient vector, and v is a fractional delay factor matrix, and V, h and v can be represented as:

[0148]

[0149] h=[h(0),h(1),...,h(N)] T

[0150] v=[1,μ,μ 2 ,...,μ N ] T

[0151] The coefficient h(n) of the N-order FIR fractional delay filter can be obtained:

[0152]

[0153] Since the essence of the digital signal delay is to change the position of the signal sampling point, the sampling offset can be used to describe the degree of change of the delay rate of change.

[0154] The range of the integer delay simulation depends on the sampling frequency of the signal and the storage capacity of the memory, in the embodiment of the present application, under the condition of 200MHz sampling frequency, real and imaginary part 16bits quantization, DDR storage capacity of 8GB, the maximum delay amount that can be simulated is 8GB / 32bits / 200M=10s, when the fractional delay factor μ(k) takes 0.2, the accuracy of the sampling offset can reach 2ppm, wherein the coefficient matrix is as follows:

[0155]

[0156] In a third aspect, an electronic device includes a memory and a processor:

[0157] The memory is used to store a computer program for implementing the satellite communication link high dynamic delay simulation method;

[0158] Processor: used to implement the satellite communication link high dynamic delay simulation method when the computer program is executed.

[0159] In a fourth aspect, a computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the satellite communication link high dynamic delay simulation method; the computer readable storage medium includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various storage program codes.

[0160] The working principle of the application is as follows:

[0161] In the system, the host computer parameter configuration module transmits the integer delay, the fractional delay and the delay change rate to the parameter processing module, the parameter processing module distributes and updates the above parameters to the integer delay module and the fractional delay module, the integer delay module realizes the simulation of the integer delay part of the integer multiple sampling period, and the fractional delay module realizes the simulation of the fractional delay part of the non-integer multiple sampling period through the Farrow structure filter; the dynamic delay control module realizes the hardware sharing design of the up-sampling and the fractional delay module, integrates the 2 times up-sampling into the fractional delay module while simulating the dynamic delay, thereby increasing the parallel number of the originally 1-way data to 2-way data through interpolation, and dynamically adjusting the integer delay module and the fractional delay module through the feedback signal, so as to solve the problem of the mismatch of the input data and the output data rate caused by the dynamic delay simulation.

Claims

1. A high dynamic delay simulation system for satellite communication links, comprising a host computer parameter configuration module and an FPGA processing module, characterized in that, The host computer parameter configuration module calculates, updates, and distributes latency simulation parameter information in real time via the host computer. It then transmits this information to the FPGA processing module via Ethernet UDP protocol through the network port. The latency simulation parameter information includes integer latency, fractional latency, and latency change rate. The FPGA processing module receives the latency simulation parameter information through the FPGA board and simulates the dynamic latency channel of the satellite communication system. The FPGA processing module includes a parameter processing module, an integer latency module, a fractional latency module, and a dynamic latency control module. The parameter processing module is used to configure and update the integer delay, fractional delay, and delay change rate issued by the host computer, and to allocate the integer delay, fractional delay, and delay change rate to the integer delay module and the fractional delay module, respectively. The integer delay module is used to simulate the integer delay portion of the sampling period, which is an integer multiple of the satellite communication link delay. The fractional delay module simulates the fractional delay portion of the non-integer multiple sampling period of the satellite communication link delay using a Farrow structure filter. The dynamic delay control module, by sharing hardware design between the upsampling and fractional delay modules, incorporates double upsampling into the fractional delay module while simulating dynamic delay. This increases the number of parallel channels from one to two by interpolation. The module also dynamically adjusts the integer and fractional delay modules through feedback signals, enabling real-time adjustment of the integer and fractional delay components of the satellite communication link delay.

2. A method for simulating high dynamic delay in satellite communication links, based on the high dynamic delay simulation system for satellite communication links as described in claim 1, characterized in that, Includes the following steps: S1: The host computer parameter configuration module transmits integer delay, fractional delay, and delay change rate to the FPGA processing module through the host computer; S2: The parameter processing module receives and stores the integer delay, fractional delay, and delay change rate sent by the host computer in step S1. The integer delay, fractional delay, and delay change rate sent for the first time in step S1 are the initial values ​​for the integer delay, fractional delay, and delay change rate, respectively. The delay change rate sent in subsequent steps of S1 is the updated value for the delay change rate. The parameter processing module assigns the initial integer delay value to the integer delay module and assigns the initial fractional delay value, the initial delay change rate value, and the updated delay change rate value to the fractional delay module. S3: After receiving the input baseband signal and the initial integer delay value described in step S2, the integer delay module simulates the long delay characteristics of the delay through DDR, FIFO or RAM, and outputs the signal simulated by the integer delay. S4: After receiving the signal simulated by integer time delay as described in step S3 and the initial value of fractional time delay, the initial value of time delay change rate, and the updated value of time delay change rate as described in step S2, the fractional time delay module accumulates the initial value of fractional time delay and the initial value of time delay change rate through the NCO (digitally controlled oscillator) in the Farrow structure filter and updates it using the updated value of time delay change rate, and then outputs a feedback signal; S5: After receiving the feedback signal described in step S4, the integer delay module controls the dynamic duty cycle of the read enable in the integer delay module to input the stored data of DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable. The fractional delay module performs fractional interpolation and finally outputs the data after dynamic delay simulation to the outside world.

3. The satellite communication link high dynamic delay simulation method as described in claim 2, characterized in that, Step S1 includes the following steps: S11: The host computer calculates the real-time communication distance L(t) between the satellite and the ground terminal based on the spatial geometric relationship between the satellite's trajectory and the ground terminal's position, thereby obtaining the satellite communication link transmission delay T(t), the expression of which is: Where c is the speed of light; S12: Assuming the signal sampling period delay at time k is a multiple of τ(k), the satellite communication link transmission delay T(t) described in step S11 is converted into a multiple of the signal sampling period delay τ(k), and its expression is: τ(k)=T(t)·f s Among them, f s Sampling frequency, in Hz; S13: Divide the τ(k) mentioned in step S12 into integer time delays τ int (k) and fractional delay τ frac (k) consists of two parts, and its expression is: τ(k)=τ int (k)+τ frac (k) S14: Assume the time delay of the signal sampling period at time k+1 is a multiple of τ(k+1), and Δτ(k) is the change in time delay from time k to time k+1, expressed as: Δτ(k)=τ(k+1)-τ(k) S15: Assuming Δt(k) is the time difference between the k-th time and the (k+1)-th time, combining τ(k) and τ(k+1) described in steps S13 and S14, then the rate of change of time delay τ var (k) can be represented as: S16: The integer delay, fractional delay, and delay change rate described in steps S13 and S15 are transmitted to the FPGA processing module via the Ethernet UDP protocol through the network port.

4. The satellite communication link high dynamic delay simulation method as described in claim 2, characterized in that, Step S2 includes the following steps: S21: The parameter processing module receives the integer delay, fractional delay, and delay change rate sent by the host computer in step S1 and stores them. It also allocates the initial integer delay value sent by the host computer to the integer delay module and allocates the initial fractional delay value and the initial delay change rate value to the fractional delay module. S22: The parameter processing module updates the delay change rate update value issued in step S1 (not the first time) to the fractional delay module.

5. The satellite communication link high dynamic delay simulation method as described in claim 2, characterized in that, Step S3 includes the following steps: S31: After receiving the input baseband signal and the initial integer delay value described in step S2, the integer delay module performs bit width matching and cross-clock domain processing on the baseband signal through the write buffer in the FIFO1 of the integer delay module. The processed baseband signal is then sent into the DDR. S32: The integer delay module simulates the long delay characteristics of the processed baseband signal described in step S31 in DDR and FIFO2. Specifically, by controlling the write enable of FIFO1 and the read enable of FIFO2, it realizes the integer delay simulation accurate to one clock cycle. The simulated DDR integer delay signal is output to FIFO2. S33: In the integer delay simulation, FIFO2 performs bit-width matching and cross-clock domain processing on the DDR integer delay signal described in step S32 through the read buffer, and obtains the signal after integer delay simulation and outputs it to the fractional delay module.

6. The satellite communication link high dynamic delay simulation method as described in claim 2, characterized in that, Step S4 includes the following steps: S41: After receiving the signal simulated with integer time delay as described in step S3, the fractional delay module (NCO) adjusts the input delay rate τ. var (k) is accumulated, and the read enable v(k) of the data cache submodule in the score delay module is updated in real time. The specific process is as follows: Assume the fractional delay factor of the accumulator register at time k is R. N (k), then the working principle of NCO can be expressed as: R N (k)=mod(R N (k-1)+τ var ,1)=μ(k) v(k)=R N (k-1)+τ var -mod(R N (k-1)+τ var ,1) S42: The data cache submodule is controlled by the real-time updated read enable v(k) described in step S41. The data cache submodule receives the signal simulated by integer time delay described in step S33 and generates and outputs a feedback signal based on the amount of data stored in the FIFO.

7. The satellite communication link high dynamic delay simulation method as described in claim 2, characterized in that, Step S5 includes the following steps: S51: The integer delay module receives the feedback signal described in step S4. The dynamic delay control module dynamically adjusts the delay by controlling the dynamic duty cycle of the read enable in the integer delay module, and then inputs the stored data of DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable. When the amount of data stored in the data cache submodule of the fractional delay module is less than half of the maximum data storage capacity, the read enable of FIFO2 in the integer delay module is changed from 0 to 1 via a feedback signal; when the amount of data stored in the data cache submodule of the fractional delay module is greater than or equal to half of the maximum data storage capacity, the read enable of FIFO2 in the integer delay module is changed from 1 to 0 via a feedback signal; when the amount of data stored in FIFO2 in the integer delay module is less than half of the maximum data storage capacity, the read enable of DDR in the integer delay module is changed from 0 to 1 via a feedback signal; when the amount of data stored in FIFO2 in the integer delay module is greater than or equal to half of the maximum data storage capacity, the read enable of DDR in the integer delay module is changed from 1 to 0 via a feedback signal. S52: The rate of change of NCO with respect to the input delay τ var (k) is accumulated, the fractional delay factor μ(k) of each clock cycle is calculated in real time, and the read enable v(k) of the data cache submodule in the fractional delay module is updated; S53: The data buffer submodule receives the signal simulated by integer time delay output in step S3, and outputs the interpolation base point and registered data that match the fractional time delay factor μ(k) at each clock cycle. S54: The fractional delay module receives the stored data from DDR, FIFO, and RAM according to the dynamic duty cycle of read enable as described in step S51. The Farrow structure filter in the fractional delay module uses μ(k) and v(k) output in step S52 and the interpolation base point and registered data output in step S53 to simulate the fractional delay part through the Farrow structure filter and third-order Lagrange cubic interpolation, and finally outputs the dynamic delay simulation data to the outside world.

8. The satellite communication link high dynamic delay simulation method as described in claim 7, characterized in that, In step S54, while simulating dynamic delay, a 2x upsampling is incorporated into the fractional delay module, thereby increasing the number of parallel channels from the original 1-channel data to 2-channel data through interpolation. The 2x upsampling is then combined with the decimation processing part of the slowly changing dynamic delay, thus transforming the decimation processing that causes the output data to be unable to be read continuously into the interpolation processing.

9. An electronic device comprising a memory and a processor, characterized in that: Memory: for storing a computer program that implements the satellite communication link high dynamic delay simulation method according to any one of claims 2 to 8; Processor: Used to implement the satellite communication link high dynamic delay simulation method according to any one of claims 2 to 8 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the satellite communication link high dynamic delay simulation method according to any one of claims 2 to 8.

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