Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method thereof. The memory device includes a channel layer surrounding a central axis and extending in a first direction, the channel layer including a side surface recessed toward the central axis and a side surface protruding from the central axis. The memory device also includes a tunnel isolation layer surrounding an outer side surface of the channel layer and a charge trapping layer surrounding an outer side surface of the tunnel isolation layer. The memory device further includes charge trapping patterns surrounding the recessed portion of the charge trapping layer and spaced apart from each other in the first direction. The memory device additionally includes a first blocking pattern surrounding the protruding portion of the charge trapping layer, a second blocking pattern surrounding the charge trapping pattern, and a gate line surrounding the second blocking pattern.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to memory devices and methods of manufacturing memory devices, and more particularly, to memory devices having a stacked structure and methods of manufacturing memory devices. Background Art

[0002] A memory device may include an array of memory cells storing data and peripheral circuits configured to perform a programming operation, a read operation, or an erase operation on the array of memory cells.

[0003] The array of memory cells may include a plurality of memory blocks, and each memory block may include a plurality of memory cells stacked vertically on a substrate.

[0004] A plurality of stacked memory cells may be formed in a cell plug.

[0005] The cell plug may include a charge trapping layer extending in a vertical direction. Even after a programming operation has been terminated, electrons trapped in the charge trapping layer by the programming operation need to be retained in the memory cell. However, as the memory device is highly integrated, electrons trapped in the charge trapping layer of the memory cell may escape from the memory cell region and move in a downward or upward direction. Accordingly, the reliability of the memory device may deteriorate. Summary of the Invention

[0006] A memory device according to an embodiment of the present disclosure may include: a channel layer surrounding a central axis and extending in a first direction, the channel layer including side surfaces recessed toward the central axis and side surfaces protruding from the central axis; a tunnel isolation layer surrounding an outer surface of the channel layer; a charge trapping layer surrounding an outer surface of the tunnel isolation layer; charge trapping patterns surrounding recessed portions of the charge trapping layer and spaced apart from each other in the first direction; a first blocking pattern surrounding a protruding portion of the charge trapping layer; a second blocking pattern surrounding the charge trapping patterns; and a gate line surrounding the second blocking pattern.

[0007] A method of manufacturing a memory device according to an embodiment of the present disclosure may include: forming an opening through first material layers and second material layers stacked alternately; modifying side surfaces of the opening to an uneven structure by increasing widths between the first material layers exposed through the opening; forming a blocking layer, a charge trapping layer, a tunnel isolation layer, and a channel layer along the side surfaces of the opening having the uneven structure; exposing a part of the blocking layer by removing the second material layer; exposing a part of the charge trapping layer by removing the exposed blocking layer; forming charge trapping patterns on the exposed charge trapping layer; and forming blocking patterns on the charge trapping patterns.

[0008] A memory device according to an embodiment of the present disclosure may include: a channel layer, which surrounds a central axis and extends in a first direction, the channel layer including a side surface recessed toward the central axis and a side surface protruding from the central axis; a tunnel isolation layer, which surrounds the outer side surface of the channel layer; a first charge capture pattern, which contacts the surface of the recessed portion of the tunnel isolation layer and is spaced apart from each other in the first direction; a second charge capture pattern, which is arranged in the recessed portion formed by the first charge capture pattern and is spaced apart from each other in the first direction; a blocking pattern, which contacts the side surface of the second charge capture pattern; and a gate line, which contacts the side surface of the blocking pattern.

[0009] A method for manufacturing a memory device according to an embodiment of the present disclosure may include: forming an opening through alternately stacked first material layers and second material layers; forming a sacrificial layer along the surface of the second material layer exposed through the opening; modifying the side surface of the opening into an uneven structure by increasing the width between the first material layers exposed through the opening; forming a charge capture layer, a tunnel isolation layer, and a channel layer along the side surface of the opening having the uneven structure; exposing a portion of the charge capture layer by removing the second material layer; exposing the sacrificial layer by removing the exposed portion of the charge capture layer, and forming a first charge capture pattern and a second charge capture pattern separated from each other; exposing the first charge capture pattern by removing the exposed sacrificial layer; forming a third charge capture pattern in contact with the exposed first charge capture pattern; and forming a blocking pattern on the third charge capture pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a memory device.

[0011] Figure 2 is a diagram illustrating a memory cell array.

[0012] Figure 3 is a diagram illustrating a storage block.

[0013] Figure 4 is a diagram illustrating a structure of a memory device according to a first embodiment of the present disclosure.

[0014] FIG. 5A to FIG. 5I is a diagram illustrating a method for manufacturing a memory device according to the first embodiment of the present disclosure.

[0015] Figure 6 is a diagram illustrating a structure of a memory device according to a second embodiment of the present disclosure.

[0016] 7A to 7J is a diagram illustrating a method for manufacturing a memory device according to a second embodiment of the present disclosure.

[0017] Figure 8FIG. is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied.

[0018] Fig. 9 FIG. is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0019] The specific structural or functional descriptions disclosed herein are illustrated for describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure should not be construed as limited to the embodiments described below, and can be modified in various forms and replaced with other equivalent embodiments.

[0020] Hereinafter, it will be understood that although the terms "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from other elements, rather than indicating the number or order of the elements.

[0021] Various embodiments of the present disclosure relate to a memory device capable of improving the reliability of a memory device and a method of manufacturing the memory device.

[0022] Figure 1 FIG. is a diagram illustrating a memory device.

[0023] Referring Figure 1 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 180.

[0024] The memory cell array 110 may include first to jth memory blocks BLK1 to BLKj. Each of the first to jth memory blocks BLK1 to BLKj may include memory cells capable of storing data. Drain select lines DSL, word lines WL, source select lines SSL, and source lines SL may be connected to each of the first to jth memory blocks BLK1 to BLKj, and bit lines BL may be commonly connected to the first to jth memory blocks BLK1 to BLKj.

[0025] Each of the first to jth memory blocks BLK1 to BLKj may be formed to have a three-dimensional (3D) structure. Each memory block having a 3D structure may include memory cells stacked in a vertical direction on a substrate.

[0026] According to a programming scheme, each memory cell can store 1 bit of data or 2 bits or more of data. For example, a scheme for storing 1 bit of data in one memory cell is called a single-level cell (SLC) scheme, and a scheme for storing 2 bits of data in one memory cell is called a multi-level cell (MLC) scheme. A scheme for storing 3 bits of data in one memory cell is called a triple-level cell (TLC) scheme, and a scheme for storing 4 bits of data in one memory cell is called a quad-level cell (QLC) scheme. In addition, 5 bits or more of data can be stored in one memory cell.

[0027] The peripheral circuit 180 can perform a programming operation of storing data in the memory cell array 110, a read operation of outputting the data stored in the memory cell array 110, and an erase operation of erasing the data stored in the memory cell array 110. For example, the peripheral circuit 180 can include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0028] The voltage generator 120 can generate various operation voltages Vop for a programming operation, a read operation, or an erase operation in response to an operation code OPCD. For example, the voltage generator 120 can generate a programming voltage, a conduction voltage, a cut-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 can be applied to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL of a selected memory block through the row decoder 130.

[0029] The programming voltage can be a voltage applied to a selected word line among the word lines WL during a programming operation, and can be used to increase the threshold voltage of a memory cell connected to the selected word line. The conduction voltage can be applied to the drain select line DSL or the source select line SSL, and can be used to turn on a drain select transistor or a source select transistor. The cut-off voltage can be applied to the drain select line DSL or the source select line SSL, and can be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage can be set to 0V. The precharge voltage can be a voltage higher than 0V, and can be applied to a bit line during a read operation. A verification voltage can be used during a verification operation of determining whether the threshold voltage of a selected memory cell has increased to a target level. The verification voltage can be set to various levels according to the target level, and can be applied to the selected word line.

[0030] During a read operation on a selected memory cell, a read voltage may be applied to the selected word line. For example, the read voltage may be set to various levels according to the programming scheme of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among word lines WL during a programming operation or a read operation, and may be used to turn on a memory cell connected to the unselected word line.

[0031] The erase voltage may be used during an erase operation of erasing memory cells included in a selected memory block, and may be applied to the source line SL.

[0032] The row decoder 130 may send an operation voltage Vop to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL coupled to a memory block selected according to a row address RADD. For example, the row decoder 130 may be coupled to the voltage generator 120 through a global line, and coupled to the first memory block BLK1 to the j-th memory block BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0033] The page buffer group 140 may include page buffers (not shown) respectively coupled to the first to j-th memory blocks BLK1 to BLKj. The page buffers (not shown) may be respectively coupled to the first to j-th memory blocks BLK1 to BLKj through the bit lines BL. During a read operation, the page buffers (not shown) may sense a current or voltage of a bit line that varies with a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and may temporarily store the sensed data.

[0034] The column decoder 150 may be configured so that data is transferred between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL and transmit an enable signal through the column line CL. The page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0035] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 170, and may send data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0036] The control circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 170 is a command corresponding to a programming operation, the control circuit 170 may control devices included in the peripheral circuit 180 such that a programming operation is performed on a memory block selected by the address ADD. When the command CMD input to the control circuit 170 is a command corresponding to a read operation, the control circuit 170 may control devices included in the peripheral circuit 180 such that a read operation is performed on the memory block selected by the address and the read data is output. When the command CMD input to the control circuit 170 is a command corresponding to an erase operation, the control circuit 170 may control devices included in the peripheral circuit 180 such that an erase operation is performed on the selected memory block.

[0037] Figure 2 FIG. is a diagram illustrating a memory cell array.

[0038] Referring to Figure 2 , the memory cell array 110 may include a first memory block BLK1 to a j-th memory block BLKj. Each of the first memory block BLK1 to the j-th memory block BLKj may include a plurality of memory cells stacked in a three-dimensional (3D) structure. The first memory block BLK1 to the j-th memory block BLKj may be arranged to be spaced apart from each other along the Y direction and may extend along the X direction. The first memory block BLK1 to the j-th memory block BLKj may be separated by a slit SLT.

[0039] Although Figure 2 not shown in, a peripheral circuit (e.g., Figure 1 180 of) may be provided below or above the memory cell array 110, or may be provided on the same substrate plane as the memory cell array 110.

[0040] Figure 3 FIG. is a diagram illustrating a memory block.

[0041] Referring to Figure 3 , by way of example, the first memory block BLK1 among the first memory block BLK1 to the j-th memory block BLKj shown in Figure 2 is illustrated.

[0042] The first memory block BLK1 may include a plurality of cell strings ST coupled between a source line SL and first to nth bit lines BL1 to BLn. The cell strings ST may be coupled to the source line SL in common. Some of the cell strings ST may be coupled to the first to nth bit lines BL1 to BLn, respectively, and other cell strings ST may be coupled to the same bit line among the first to nth bit lines BL1 to BLn. For example, the cell strings ST arranged along the X direction may be coupled to the first to nth bit lines BL1 to BLn, respectively, and the cell strings ST arranged along the Y direction may be coupled to the same bit line.

[0043] Each of the plurality of cell strings ST may include a source select transistor SST, first to i-th memory cells MC1 to MCi, and a drain select transistor DST. A cell string ST coupled to the first bit line BL1 among the plurality of cell strings ST will be described by way of example.

[0044] The source selection transistor SST may be coupled between the source line SL and the first memory cell MC1, and the drain selection transistor DST may be coupled between the i-th memory cell MCi and the first bit line BL1. The first to i-th memory cells MC1 to MCi may be coupled between the source selection transistor SST and the drain selection transistor DST. The number of the source selection transistors SST and the number of the drain selection transistors DST are not limited to Figure 3 In addition to the first to i-th memory cells MC1 to MCi, dummy cells (not shown) may be connected between the source selection transistor SST and the drain selection transistor DST. The first to i-th memory cells MC1 to MCi may store user data or normal data, and the dummy cells (not shown) may store dummy data.

[0045] The gates of the source selection transistors SST included in different cell strings ST may be coupled to the source selection line SSL. The gates of the first memory cell MC1 to the i-th memory cell MCi included in the different cell strings ST may be coupled to the first word line WL1 to the i-th word line WLi, respectively. The gates of the drain selection transistors DST included in the different cell strings ST may be coupled to the drain selection line DSL. A group of memory cells included in the cell strings ST arranged along the X direction and coupled to the same word line may be a page (PG). In the memory device, a program operation or a read operation may be performed on a selected memory block on a page (PG) basis.

[0046] Figure 4 is a diagram illustrating a structure of a memory device according to a first embodiment of the present disclosure.

[0047] Reference Figure 4, illustrates a portion of a memory block included in a memory device. The memory block may include a stacked structure STK and a cell plug CP disposed in the stacked structure STK. The cell plug CP may include a cell string (eg, Figure 3 The transistor TR can be used as a selection transistor or a memory cell.

[0048] The stacked structure STK may include a first material layer M1 and a gate line GL. Each first material layer M1 may be formed of an insulating material. For example, each first material layer M1 may be formed of an oxide layer. Each gate line GL may be formed of a conductive material. For example, each gate line GL may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si), but the material of the gate line GL is not limited thereto.

[0049] The cell plug CP may penetrate the stack structure STK. The cell plug CP may include a stem CR, a channel layer CH, a tunnel isolation layer TX, a charge trap layer CTL, a charge trap pattern CTLp, a first barrier pattern BXp1, and a second barrier pattern BXp2.

[0050] The stem column CR may be disposed in a central region of the cell plug CP and may extend along the Z direction. For example, the stem column CR may extend along a central axis AX perpendicular to the XY plane. The stem column CR may be formed of an insulating material or a conductive material. The side surface of the stem column CR may have an uneven structure. For example, in the region where the first material layer M1 is located, the side surface of the stem column CR may protrude from the central axis AX. In the region where the gate line GL is located, the side surface of the stem column CR may be recessed toward the central axis AX. The interface between the recessed portion and the protruding portion of the stem column CR may form a right angle or a curved surface.

[0051] The channel layer CH may surround the side surface of the core column CR. Therefore, a cross section of the channel layer CH taken along the XZ plane may have an uneven structure. The channel layer CH may be formed of polysilicon. Because the channel layer CH is formed along the side surface of the core column CR, the uneven structure of the channel layer CH may be an uneven structure corresponding to the core column CR. For example, a portion of the channel layer CH that is recessed toward the central axis AX may contact the recessed portion of the core column CR, and a portion of the channel layer CH that protrudes from the central axis AX may contact the protruding portion of the core column CR.

[0052] The tunnel isolation layer TX may surround the side surface of the channel layer CH. Therefore, the cross section of the tunnel isolation layer TX taken along the XZ plane may have an uneven structure. The tunnel isolation layer TX may be formed of an insulating material. For example, the tunnel isolation layer TX may be formed of an oxide layer. Because the tunnel isolation layer TX is formed along the side surface of the channel layer CH, the uneven structure of the tunnel isolation layer TX may be an uneven structure corresponding to the channel layer CH. For example, a portion of the tunnel isolation layer TX that is recessed toward the central axis AX may contact the recessed portion of the channel layer CH, and a portion of the tunnel isolation layer TX that protrudes from the central axis AX may contact the protruding portion of the channel layer CH.

[0053] The charge trapping layer CTL may surround the side surface of the tunnel isolation layer TX. Therefore, a cross section of the charge trapping layer CTL taken along the XZ plane may have an uneven structure. The charge trapping layer CTL may be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). Because the charge trapping layer CTL is formed along the side surface of the tunnel isolation layer TX, the uneven structure of the charge trapping layer CTL may be an uneven structure corresponding to the tunnel isolation layer TX. For example, a portion of the charge trapping layer CTL that is recessed toward the central axis AX may contact the recessed portion of the tunnel isolation layer TX, and a portion of the charge trapping layer CTL that protrudes from the central axis AX may contact the protruding portion of the tunnel isolation layer TX.

[0054] The charge trapping patterns CTLp may be disposed in a recessed portion of the charge trapping layer CTL and may be spaced apart from each other along the Z direction. Each charge trapping pattern CTLp may be formed of a material having a charge trapping density higher than that of the charge trapping layer CTL. For example, each charge trapping pattern CTLp may be formed of a silicon nitride layer. In order to have a charge trapping density higher than that of the charge trapping layer CTL, each charge trapping pattern CTLp may be formed of a silicon nitride layer having a nitrogen content lower than that of the charge trapping layer CTL. That is, as the nitrogen concentration in the charge trapping layer CTL is higher, the total charge trapping density of the charge trapping pattern CTLp and the charge trapping layer CTL may be reduced.

[0055] Because the charge capture pattern CTLp is located in the recessed portion of the charge capture layer CTL, the side surface adjacent to the central axis AX among the side surfaces of the charge capture pattern CTLp and some portions of the top surface and some portions of the bottom surface of the charge capture pattern CTLp may contact the charge capture layer CTL. The thickness of each charge capture pattern CTLp may be greater than the thickness of the charge capture layer CTL. Here, the thickness may refer to the length of each of the charge capture pattern CTLp and the charge capture layer CTL in the X direction. For example, assuming that the charge capture layer CTL has a first thickness TK1, and the charge capture patterns CTLp each have a second thickness TK2, the second thickness TK2 may be greater than the first thickness TK1. Even after the programming operation is terminated, some electrons captured in the charge capture layer CTL move to the outside of the transistor TR, and the electrons are captured in the charge capture pattern CTLp, thereby maintaining the threshold voltage of the transistor TR. In addition, because the charge capture layer CTL extending in the Z direction has an uneven structure, the length of the charge capture layer CTL in the Z direction may be increased. Therefore, it is possible to suppress a phenomenon in which electrons trapped in the charge trap layer CTL among the transistors TR adjacent in the Z direction move to other transistors adjacent in the Z direction.

[0056] The first blocking patterns BXp1 may surround the side surface of the protruding portion of the charge trap layer CTL and may be spaced apart from each other in the Z direction. For example, the first blocking patterns BXp1 may be separated from each other in the region where the gate line GL is located. Each first blocking pattern BXp1 may be formed of an insulating material. For example, each first blocking pattern BXp1 may be formed of an oxide layer. Some portions of the charge trap pattern CTLp may be located in the region where the first blocking pattern BXp1 is separated.

[0057] The second barrier patterns BXp2 may surround the outer side surface of the charge trapping pattern CTLp and may be spaced apart from each other in the Z direction. For example, the second barrier patterns BXp2 may be separated from each other in the region where the first material layer M1 is located. The second barrier patterns BXp2 may be formed of the same material as the first barrier patterns BXp1. For example, each second barrier pattern BXp2 may be formed of an insulating material. For example, each second barrier pattern BXp2 may be formed of an oxide layer.

[0058] FIG. 5A to FIG. 5I is a diagram illustrating a method for manufacturing a memory device according to the first embodiment of the present disclosure.

[0059] Reference Figure 5A, the first material layer M1 and the second material layer M2 may be alternately stacked on the lower structure (not shown) along the Z direction. The lower structure (not shown) may be, but is not limited to, a substrate or a peripheral circuit. The first material layer M1 may be an oxide layer, and the second material layer M2 may be a layer formed of a material having an etching selectivity different from that of the first material layer M1. For example, the second material layer M2 may be a nitride layer.

[0060] Reference Figure 5B , an opening OP for exposing the side surfaces of the first material layer M1 and the second material layer M2 may be formed. The opening OP may be formed by an etching process. For example, the etching process for forming the opening OP may be performed using an anisotropic dry etching method. The opening OP may pass through the first material layer M1 and the second material layer M2. The opening OP may have a first width W1.

[0061] Reference Figure 5C , the first recessed portion R1 may be formed by removing a portion of the first material layer M1 exposed through the opening OP. For example, the first recessed portion R1 may be formed by performing an anisotropic dry etching process or a wet etching process. Because the first recessed portion R1 is a region formed by removing some portions of the first material layer M1, the width between the first material layers M1 exposed through the opening OP may be a second width W2 that is greater than the first width W1 between the second material layers M2 exposed through the opening OP. That is, due to the first recessed portion R1, the side surface of the opening OP may have an uneven structure.

[0062] Reference Figure 5D , a blocking layer BX, a charge trapping layer CTL, a tunnel isolation layer TX, a channel layer CH, and a core column CR may be sequentially formed along the side surface of the opening OP having an uneven structure. For example, a blocking layer BX may be formed along the surface of the opening OP, and a charge trapping layer CTL may be formed along the inner surface of the blocking layer BX. A tunnel isolation layer TX may be formed along the inner surface of the charge trapping layer CTL, a channel layer CH may be formed along the inner surface of the tunnel isolation layer TX, and a core column CR may fill the area surrounded by the channel layer CH. The blocking layer BX may be formed of an insulating material. For example, the blocking layer BX may be formed of an oxide layer. The charge trapping layer CTL may be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). The tunnel isolation layer TX may be formed of an insulating material. For example, the tunnel isolation layer TX may be formed of an oxide layer. The channel layer CH may be formed of polysilicon. The core column CR may be formed of an insulating material or a conductive material.

[0063] Reference Figure 5E , a method for removing the second material layer (eg, Figure 5DThe etching process of the second material layer M2 can be performed by an anisotropic dry etching method or a wet etching method. The area from which the second material layer M2 is removed can be the second recessed portion R2. Therefore, the barrier layer BX can be exposed through the second recessed portion R2.

[0064] Reference Fig. 5F , a method for removing the barrier layer (e.g., Figure 5E The etching process of the portion of the first material layer M1 exposed by the second recessed portion R2 (BX) of the blocking layer BX is performed. The etching process may be performed using an anisotropic dry etching method or a wet etching method. When etching the blocking layer BX, some portions of the first material layer M1 having an etching selectivity similar to that of the blocking layer BX may also be etched. Due to this, the height HG of the second recessed portion R2 between the first material layers M1 may be increased compared to the height before a portion of the blocking layer BX is etched. That is, by an etching process for removing a portion of the blocking layer BX, a portion of the charge trapping layer CTL may be exposed, and the volume of the second recessed portion R2 may be increased. The portion of the blocking layer BX that remains between the second recessed portion R2 may become a first blocking pattern BXp1. The first blocking pattern BXp1 may be disposed between the first material layer M1 and the charge trapping layer CTL.

[0065] Reference Figure 5G , a charge trapping pattern CTLp may be formed in the charge trapping layer CTL exposed by the second recess R2. The charge trapping pattern CTLp may be formed by a selective growth method. Therefore, the charge trapping pattern CTLp may be selectively grown on the charge trapping layer CTL exposed by the second recess R2. Each charge trapping pattern CTLp may be formed of a material having a higher charge trapping density than that of the charge trapping layer CTL. For example, each charge trapping pattern CTLp may be formed of a silicon nitride layer. In order to have a higher charge trapping density than that of the charge trapping layer CTL, each charge trapping pattern CTLp may be formed of a silicon nitride layer having a lower nitrogen content than that of the charge trapping layer CTL. The charge trapping pattern CTLp may be formed until the first blocking pattern BXp1 is not exposed in the second recess R2. Therefore, after the charge trapping pattern CTLp is formed, the first material layer M1 and the charge trapping pattern CTLp may be exposed through the second recess R2.

[0066] Reference Figure 5H, a second blocking pattern BXp2 may be formed along the surface of the charge capture pattern CTLp exposed by the second recess R2. The second blocking pattern BXp2 may be formed of the same material as the first blocking pattern BXp1. For example, each second blocking pattern BXp2 may be formed of an oxide layer. The second blocking pattern BXp2 may be formed by an oxidation method. For example, the second blocking pattern BXp2 may be formed by oxidizing a portion of the charge capture pattern CTLp exposed via the second recess R2. When the side surface of the charge capture pattern CTLp is oxidized, some portions of the charge capture pattern CTLp become the second blocking pattern BXp2, and thus some portions of the second blocking pattern BXp2 may overlap with some portions of the first blocking pattern BXp1. Because the second blocking pattern BXp2 may also be formed on the side surface of the charge capture pattern CTLp, the volume of the second recess R2 may be reduced.

[0067] Reference Fig.5I , a third material layer M3 may be formed in the second recessed portion R2. Since the third material layers M3 may be used as gate lines GL, they may be formed of a conductive material. For example, each of the third material layers M3 may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si), but the material of the third material layer M3 is not limited thereto.

[0068] Figure 6 is a diagram illustrating a structure of a memory device according to a second embodiment of the present disclosure.

[0069] Reference Figure 6 , illustrates a portion of a memory block included in a memory device. The memory block may include a stacked structure STK and a cell plug CP disposed in the stacked structure STK. The cell plug CP may include a cell string (eg, Figure 3 The transistor TR can be used as a selection transistor or a memory cell.

[0070] The stacked structure STK may include a first material layer M1 and a gate line GL. Each first material layer M1 may be formed of an insulating material. For example, each first material layer M1 may be formed of an oxide layer. Each gate line GL may be formed of a conductive material. For example, each gate line GL may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si), but the material of the gate line GL is not limited thereto.

[0071] The cell plug CP may penetrate the stack structure STK. The cell plug CP may include a stem CR, a channel layer CH, a tunnel isolation layer TX, a first charge trap pattern CTLp1, a second charge trap pattern CTLp2, a third charge trap pattern CTLp3, and a blocking pattern BXp.

[0072] The stem column CR may be disposed in a central region of the cell plug CP and may extend along the Z direction. For example, the stem column CR may extend along a central axis AX perpendicular to the XY plane. The stem column CR may be formed of an insulating material or a conductive material. The side surface of the stem column CR may have an uneven structure. For example, in the region where the first material layer M1 is located, the side surface of the stem column CR may protrude from the central axis AX. In the region where the gate line GL is located, the side surface of the stem column CR may be recessed toward the central axis AX. The interface between the recessed portion and the protruding portion of the stem column CR may form a right angle or a curved surface.

[0073] The channel layer CH may surround the side surface of the core column CR. Therefore, a cross section of the channel layer CH taken along the XZ plane may have an uneven structure. The channel layer CH may be formed of polysilicon. Because the channel layer CH is formed along the side surface of the core column CR, the uneven structure of the channel layer CH may be an uneven structure corresponding to the core column CR. For example, a portion of the channel layer CH protruding from the central axis AX may contact a protruding portion of the core column CR, and a portion of the channel layer CH recessed toward the central axis AX may contact a recessed portion of the core column CR.

[0074] The tunnel isolation layer TX may surround the side surface of the channel layer CH. Therefore, the cross section of the tunnel isolation layer TX taken along the XZ plane may have an uneven structure. The tunnel isolation layer TX may be formed of an insulating material. For example, the tunnel isolation layer TX may be formed of an oxide layer. Because the tunnel isolation layer TX is formed along the side surface of the channel layer CH, the uneven structure of the tunnel isolation layer TX may be an uneven structure corresponding to the channel layer CH. For example, a portion of the tunnel isolation layer TX protruding from the central axis AX may contact the protruding portion of the channel layer CH, and a portion of the tunnel isolation layer TX recessed toward the central axis AX may contact the recessed portion of the channel layer CH.

[0075] The first charge trap patterns CTLp1 may be formed along the concave surface of the tunnel isolation layer TX and may be spaced apart from each other along the Z direction. Each of the first charge trap patterns CTLp1 may be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). Each of the first charge trap patterns CTLp1 may be formed along the top surface, the bottom surface, and the side surface of the corresponding concave portion of the tunnel isolation layer TX.

[0076] Each second charge trapping pattern CTLp2 may surround the surface of the corresponding protruding portion of the tunnel isolation layer TX. For example, the second charge trapping pattern CTLp2 may be disposed between the first material layer M1 and the tunnel isolation layer TX. The second charge trapping patterns CTLp2 may be spaced apart from each other along the Z direction. The second charge trapping pattern CTLp2 may be separated from the first charge trapping pattern CTLp1. The second charge trapping pattern CTLp2 may be formed of the same material as the first charge trapping pattern CTLp1. For example, each second charge trapping pattern CTLp2 may be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON).

[0077] The third charge trap patterns CTLp3 may be disposed in a region surrounded by the first charge trap patterns CTLp1 and may be spaced apart from each other along the Z direction.

[0078] The third charge trap patterns CTLp3 may be formed of a material having a higher charge trap density than that of the first charge trap patterns CTLp1. For example, each of the third charge trap patterns CTLp3 may be formed of a silicon nitride layer. In order to have a higher charge trap density than that of the first charge trap patterns CTLp1, each of the third charge trap patterns CTLp3 may be formed of a silicon nitride layer having a lower nitrogen content than that of the first charge trap patterns CTLp1.

[0079] Because the third charge trap pattern CTLp3 is located in the recessed portion of the first charge trap pattern CTLp1, the side surface adjacent to the central axis AX among the side surfaces of the third charge trap pattern CTLp3 and the top and bottom surfaces of the third charge trap pattern CTLp3 may contact the first charge trap pattern CTLp1. The thickness of each third charge trap pattern CTLp3 may be greater than the thickness of each first charge trap pattern CTLp1. Here, the thickness represents the length of each of the third charge trap pattern CTLp3 and the first charge trap pattern CTLp1 in the X direction. For example, assuming that each first charge trap pattern CTLp1 has a first thickness TK1 and each third charge trap pattern CTLp3 has a second thickness TK2, the second thickness TK2 may be greater than the first thickness TK1. Therefore, during the programming operation, electrons may be trapped in the first charge trap pattern CTLp1 and the third charge trap pattern CTLp3. The first charge trap pattern CTLp1 and the third charge trap pattern CTLp3 may be separated from each other by the blocking pattern BXp (61). Because the first and third charge trap patterns CTLp1 and CTLp3 disposed in different layers are spaced apart from each other along the Z direction, a phenomenon in which electrons trapped in the first charge trap pattern CTLp1 move in a downward or upward direction during a programming operation can be mitigated or prevented. Therefore, after the programming operation is terminated, the threshold voltage of the transistor TR can remain unchanged.

[0080] The blocking pattern BXp may contact the side surfaces of the first charge capture pattern CTLp1 and the third charge capture pattern CTLp3 and may be spaced apart from each other along the Z direction. For example, the blocking pattern BXp may surround the side surfaces of the first charge capture pattern CTLp1 and the third charge capture pattern CTLp3. The blocking pattern BXp may be disposed between each of the first charge capture pattern CTLp1 and the third charge capture pattern CTLp3 and the gate line GL. The blocking pattern BXp may be disposed between the second charge capture pattern CTLp2 disposed in a different layer. The blocking pattern BXp may separate the first charge capture pattern CTLp1 and the second charge capture pattern CTLp2 from each other (61). Each blocking pattern BXp may be formed of an insulating material. For example, each blocking pattern BXp may be formed of an oxide layer.

[0081] 7A to 7J is a diagram illustrating a method for manufacturing a memory device according to a second embodiment of the present disclosure.

[0082] Reference Fig. 7A, the first material layer M1 and the second material layer M2 may be alternately stacked on the lower structure (not shown) along the Z direction. The lower structure (not shown) may be, but is not limited to, a substrate or a peripheral circuit. The first material layer M1 may be an oxide layer, and the second material layer M2 may be a layer made of a material having an etching selectivity different from that of the first material layer M1. For example, the second material layer M2 may be a nitride layer.

[0083] Reference Figure 7B , an opening OP for exposing the side surfaces of the first material layer M1 and the second material layer M2 may be formed. The opening OP may be formed by an etching process. For example, the etching process for forming the opening OP may be performed using an anisotropic dry etching method. The opening OP may pass through the first material layer M1 and the second material layer M2. The opening OP may have a third width W3.

[0084] Reference Figure 7C , a sacrificial layer SF may be selectively formed on the side surface of the second material layer M2 exposed by the opening OP. For example, the sacrificial layer SF may be formed of SiOC. Each sacrificial layer SF may have a thickness that prevents the sacrificial layers SF from contacting each other. Therefore, the fourth width W4 between the sacrificial layers SF facing each other in the opening OP may be smaller than the third width W3 between the first material layers M1.

[0085] Reference Fig.7D , the first recessed portion R1 may be formed by removing a portion of the first material layer M1 exposed through the opening OP. For example, the first recessed portion R1 may be formed by performing an anisotropic dry etching process or a wet etching process. Because the first recessed portion R1 is a region formed by removing some portions of the first material layer M1, the width between the first material layers M1 exposed through the opening OP may be a fifth width W5 greater than the third width W3. That is, the side surface of the first material layer M1, some portions of the second material layer M2, and the sacrificial layer SF may be exposed through the first recessed portion R1. Due to the first recessed portion R1, the side surface of the opening OP may have an uneven structure.

[0086] Reference Fig. 7E, a first charge trapping layer CTL1, a tunnel isolation layer TX, a channel layer CH, and a core pillar CR can be sequentially formed along a side surface with an uneven structure of the opening OP. For example, the first charge trapping layer CTL1 can be formed along the surface of the opening OP. The tunnel isolation layer TX can be formed along the inner surface of the first charge trapping layer CTL1, the channel layer CH can be formed along the inner surface of the tunnel isolation layer TX, and the core pillar CR can fill the region surrounded by the channel layer CH. The first charge trapping layer CTL1 can be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). The tunnel isolation layer TX can be formed of an insulating material. For example, the tunnel isolation layer TX can be formed of an oxide layer. The channel layer CH can be formed of polysilicon. The core pillar CR can be formed of an insulating material or a conductive material.

[0087] Referring to Figure 7F , an etching process can be performed to remove a second material layer (e.g., Fig. 7E M2) provided between some portions of the first material layer M1 and the first charge trapping layer (e.g., Fig. 7E CTL1). After performing a first etching process for removing the second material layer M2 provided between the first material layers M1, a second etching process can be performed to remove portions of the first charge trapping layer (e.g., Fig. 7E CTL1) that are exposed as the second material layer M2 is removed. Each of the first etching process and the second etching process can be performed using an anisotropic dry etching method or a wet etching method. The region from which the second material layer M2 and some portions of the first charge trapping layer CTL1 are removed can become a second recess R2. When some portions of the first charge trapping layer CTL1 are removed, the first charge trapping layer CTL1 can be separated into a first charge trapping pattern CTLp1 in contact with the sacrificial layer SF and a second charge trapping pattern CTLp2 in contact with the first material layer M1.

[0088] Referring to Figure 7G , an etching process can be performed to remove the sacrificial layer (e.g., Figure 7F SF) exposed through the second recess R2. The etching process can be performed using an anisotropic dry etching method or a wet etching method.

[0089] Referring to Figure 7H, a third charge trapping pattern CTLp3 may be formed along the first charge trapping pattern CTLp1 and the second charge trapping pattern CTLp2 exposed by the second recess R2. The third charge trapping pattern CTLp3 may be formed by a selective growth method. The third charge trapping pattern CTLp3 may be formed of a material having a higher charge trapping density than that of the first charge trapping pattern CTLp1. For example, each third charge trapping pattern CTLp3 may be formed of a silicon nitride layer. In order to have a higher charge trapping density than that of the first charge trapping pattern CTLp1, each third charge trapping pattern CTLp3 may be formed of a silicon nitride layer having a lower nitrogen content than that of the first charge trapping pattern CTLp1. After forming the third charge trapping pattern CTLp3, the first material layer M1 and the third charge trapping pattern CTLp3 may be exposed by the second recess R2.

[0090] Reference Fig.7I , a blocking pattern BXp may be formed along a surface of the third charge capture pattern CTLp3 exposed through the second recess R2. Each blocking pattern BXp may be formed of an insulating layer. The blocking pattern BXp may be formed by an oxidation method. For example, the blocking pattern BXp may be formed by oxidizing a portion of the third charge capture pattern CTLp3 exposed through the second recess R2. When the side surface of the third charge capture pattern CTLp3 is oxidized, some portions of the third charge capture pattern CTLp3 become the blocking pattern BXp, and thus some portions of the blocking pattern BXp may overlap with some portions of the tunnel isolation layer TX. Therefore, the blocking pattern BXp may be disposed between the first charge capture pattern CTLp1 and the second charge capture pattern CTLp2.

[0091] Reference Figure 7J , a third material layer M3 may be formed in the second recessed portion R2. Figure 7J The gate lines GL indicated as “M3(GL)” in FIG. 1 and FIG. 2 may be formed of a conductive material. For example, each third material layer M3 may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si), but the material of the third material layer M3 is not limited thereto.

[0092] Figure 8 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0093] Reference Figure 8 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0094] The controller 3100 is coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200, or control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In an embodiment, the controller 3100 may include components such as a RAM, a processor, a host interface, a memory interface, and an error correction circuit.

[0095] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. In an embodiment, the controller 3100 can communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), Firewire, a universal flash memory (UFS), WiFi, Bluetooth, and a fast non-volatile memory (NVMe). In an embodiment, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0096] The memory device 3200 may include a plurality of memory cells, and for implementation, may be connected to Figure 1 The illustrated memory device 100 is configured in the same manner.

[0097] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device and then may form a memory card such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), a Universal Flash Storage (UFS), etc.

[0098] Fig. 9 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment of the present disclosure is applied.

[0099] Reference Fig. 9, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0100] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. In an embodiment, the signal may include a signal based on an interface of the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe).

[0101] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells storing data. Figure 1 The illustrated memory device 100 is configured in the same manner. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 through channels CH1 to CHn.

[0102] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may be supplied with a power supply voltage from the host 4100 and may be charged. When power supply from the host 4100 cannot be smoothly performed, the auxiliary power supply 4230 may provide a power supply voltage for the SSD 4200. In an embodiment, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on a mainboard and may also provide an auxiliary power supply for the SSD 4200.

[0103] The buffer memory 4240 is used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0104] For some implementations, the present disclosure may improve the reliability of a memory device.

[0105] CROSS-REFERENCE TO RELATED APPLICATIONS

[0106] This application claims priority to Korean Patent Application No. 10-2023-0164303, filed on November 23, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a channel layer surrounding a central axis and extending in a first direction, the channel layer including a side surface recessed toward the central axis and a side surface protruding from the central axis; a tunnel isolation layer, the tunnel isolation layer surrounding the outer surface of the channel layer; a charge trapping layer, the charge trapping layer surrounding the outer surface of the tunnel isolation layer; charge trap patterns surrounding the recessed portion of the charge trap layer and spaced apart from each other in the first direction; a first blocking pattern surrounding a protruding portion of the charge trap layer; a second blocking pattern, the second blocking pattern surrounding the charge trapping pattern; as well as A gate line surrounds the second barrier pattern.

2. The memory device according to claim 1, wherein: An inner surface of each of the charge trapping patterns contacts the charge trapping layer, An outer side surface of each of the charge trapping patterns contacts the second blocking pattern, and Top and bottom surfaces of each of the charge trap patterns contact the charge trap layer and the first blocking patterns.

3. The memory device according to claim 1, wherein: The charge trap layer is formed of a material having a charge trap density lower than that of the charge trap pattern.

4. The memory device according to claim 1, wherein: The charge trap layer and the charge trap pattern include a silicon nitride layer.

5. The memory device according to claim 4, wherein: Each of the charge trap patterns has a nitrogen content lower than a nitrogen content of the charge trap layer.

6. The memory device according to claim 1, wherein: The charge trapping layer is a silicon oxynitride layer.

7. The memory device according to claim 1, wherein: The charge trap layer has a thickness smaller than a thickness of each of the charge trap patterns.

8. The memory device according to claim 1, wherein: An outer side surface of the charge trap pattern protrudes from the concave portion of the charge trap layer.

9. The memory device according to claim 1, wherein: An outer side surface of the second barrier pattern protrudes from the first barrier pattern.

10. The memory device of claim 1, further comprising: A first material layer is disposed between the gate lines and contacts a side surface of the first barrier pattern.

11. The memory device according to claim 1, wherein: The tunnel isolation layer, the first barrier pattern, and the second barrier pattern include an oxide layer.

12. The memory device according to claim 1, wherein: The channel layer is formed of polysilicon.

13. A method of manufacturing a memory device, the method comprising the steps of: forming an opening through the alternately stacked first material layers and second material layers; modifying a side surface of the opening into an uneven structure by increasing a width between the first material layers exposed through the opening; forming a blocking layer, a charge trapping layer, a tunnel isolation layer, and a channel layer along the side surface of the opening having the uneven structure; exposing a portion of the barrier layer by removing the second material layer; exposing a portion of the charge trapping layer by removing the exposed blocking layer; forming a charge trapping pattern on the exposed charge trapping layer; as well as A blocking pattern is formed on the charge trap pattern.

14. The method according to claim 13, wherein: The first material layer is formed of an oxide layer, and the second material layer is formed of a nitride layer.

15. The method according to claim 13, wherein: The step of modifying the side surface of the opening into the uneven structure comprises the following steps: An anisotropic dry etching process or a wet etching process is performed.

16. The method according to claim 13, wherein: The barrier layer, the barrier pattern, and the tunnel isolation layer are formed of an oxide layer.

17. The method according to claim 13, wherein: The charge trap layer and the charge trap pattern are formed of a silicon nitride layer.

18. The method according to claim 17, wherein: Each of the charge trap patterns has a nitrogen content lower than a nitrogen content of the charge trap layer.

19. The method according to claim 13, wherein: The charge trap layer is formed of a silicon oxynitride layer.

20. The method according to claim 13, wherein: The charge trap pattern is formed along a surface of the charge trap layer.

21. A memory device, the memory device comprising: a channel layer surrounding a central axis and extending in a first direction, the channel layer including a side surface recessed toward the central axis and a side surface protruding from the central axis; a tunnel isolation layer, the tunnel isolation layer surrounding the outer surface of the channel layer; first charge trap patterns contacting a surface of the recessed portion of the tunnel isolation layer and spaced apart from each other in the first direction; second charge trap patterns disposed in the concave portion formed by the first charge trap patterns and spaced apart from each other in the first direction; a blocking pattern contacting a side surface of the second charge trap pattern; as well as A gate line contacts a side surface of the blocking pattern.

22. The memory device of claim 21, wherein: A top surface, a bottom surface, and an inner side surface of each of the second charge trap patterns are in contact with an adjacent first charge trap pattern.

23. The memory device of claim 21, wherein: Each of the first charge trap patterns is formed of a material having a charge trap density lower than that of each of the second charge trap patterns.

24. The memory device of claim 21, wherein: The first charge trap pattern and the second charge trap pattern include a silicon nitride layer.

25. The memory device of claim 24, wherein: Each of the first charge trap patterns has a nitrogen content higher than a nitrogen content of each of the second charge trap patterns.

26. The memory device of claim 21, wherein: The first charge trap pattern includes a silicon oxynitride layer.

27. The memory device of claim 21, wherein: A thickness of each of the first charge trap patterns is smaller than a thickness of each of the second charge trap patterns.

28. The memory device of claim 21, wherein: The first charge trap pattern disposed on top and bottom surfaces of the second charge trap pattern contacts the blocking pattern.

29. The memory device of claim 21, comprising: A third charge trapping pattern is disposed between the first material layer and the tunnel isolation layer.

30. The memory device of claim 29, wherein: The third charge trap pattern is spaced apart from the first charge trap pattern and the second charge trap pattern.

31. The memory device of claim 30, wherein: The third charge trap pattern is spaced apart from the first and second charge trap patterns by the blocking pattern.

32. A method of manufacturing a memory device, the method comprising the steps of: forming an opening through the alternately stacked first material layers and second material layers; forming a sacrificial layer along a surface of the second material layer exposed through the opening; modifying a side surface of the opening into an uneven structure by increasing a width between the first material layers exposed through the opening; forming a charge trapping layer, a tunnel isolation layer, and a channel layer along the side surface of the opening having the uneven structure; exposing a portion of the charge trapping layer by removing the second material layer; exposing the sacrificial layer by removing an exposed portion of the charge trap layer, and forming a first charge trap pattern and a second charge trap pattern separated from each other; exposing the first charge trapping pattern by removing the exposed sacrificial layer; forming a third charge trap pattern in contact with the exposed first charge trap pattern; as well as A blocking pattern is formed on the third charge trap pattern.

33. The method of claim 32, wherein: The first to third charge trap patterns are formed of a silicon nitride layer.

34. The method of claim 33, wherein: Each of the third charge trap patterns has a nitrogen content lower than that of each of the first charge trap patterns.

35. The method of claim 32, wherein: The first charge trap pattern and the second charge trap pattern are formed of a silicon oxynitride layer.

36. The method of claim 32, wherein: The step of forming the blocking pattern comprises the following steps: Portions of the third charge trapping pattern are oxidized.

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