Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, a top of the substrate being formed with a suspended gate layer, a top of the suspended gate layer being formed with a control gate layer; forming a first sidewall layer on sidewalls of the control gate layer; after forming the first sidewall layer, forming a second sidewall layer on the top of the substrate, the second sidewall layer covering sidewalls of the first sidewall layer; using the first sidewall layer and the second sidewall layer as masks, performing a patterning process on the suspended gate layer, and removing the suspended gate layer on the side of the control gate layer. The sidewalls of the first sidewall layer and the second sidewall layer are relatively smooth, which reduces the probability of the first sidewall layer being in an L shape, and makes the morphology of the sidewalls of the suspended gate layer after the patterning process relatively smooth, thereby reducing the probability of the sidewalls of the suspended gate layer being uneven, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: analog circuits, digital circuits, and mixed-signal circuits. Among these, memory devices are an important type of digital circuit. In recent years, flash memory has seen particularly rapid development. The main characteristics of flash memory are its ability to retain stored information for extended periods without power; it also boasts advantages such as high integration density, fast access speed, and ease of erasing and rewriting, thus finding wide application in microcomputers, automation control, and many other fields.

[0003] However, the performance of flash memory still needs to be improved. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of semiconductor devices.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a floating gate layer is formed on the top of the substrate, and a control gate layer protrudes from the top of the floating gate layer; forming a first sidewall layer on the sidewall of the control gate layer; after forming the first sidewall layer, forming a second sidewall layer on the top of the substrate that covers the sidewall of the first sidewall layer; using the first sidewall layer and the second sidewall layer as masks, performing patterning processing on the floating gate layer to remove the floating gate layer on the side of the control gate layer.

[0006] Optionally, the step of forming the control gate layer includes: forming a control gate material layer on top of the floating gate layer; forming a patterned hard mask layer on top of the control gate material layer; using the patterned hard mask layer as a mask to pattern the control gate material layer, thereby forming a raised control gate layer on top of the floating gate layer.

[0007] Optionally, the first sidewall layer includes a first sub-sidewall layer covering the sidewall of the control grid layer, and a second sub-sidewall layer covering the sidewall of the first sub-sidewall layer.

[0008] Optionally, the step of forming the first sidewall layer includes: forming a first sub-sidewall material layer on top of the suspended grid layer exposed by the control grid layer, on top of the control grid layer, and on the sidewall; forming a second sub-sidewall material layer covering the first sub-sidewall material layer; removing the second sub-sidewall material layer on top of the suspended grid layer and the second sub-sidewall material layer on top of the control grid layer, and using the first sub-sidewall material layer located on the sidewall of the control grid layer and the remaining second sub-sidewall material layer as the first sidewall layer; in the step of forming the second sidewall layer, the first sub-sidewall material layer on top of the suspended grid layer and the first sub-sidewall material layer on top of the suspended grid layer are also removed.

[0009] Optionally, the process for removing the second sub-sidewall material layer on top of the levitation gate layer and the second sub-sidewall material layer on top of the control gate layer includes a dry etching process.

[0010] Optionally, the process parameters of the dry etching process include: the process gas includes argon, oxygen and fluoromethane; the chamber pressure range is 60 mTorr to 90 mTorr.

[0011] Optionally, during the process of removing the second sub-sidewall material layer on top of the floating gate layer and the second sub-sidewall material layer on top of the control gate layer, the etching selectivity ratio of the second sub-sidewall material layer to the first sub-sidewall material layer is greater than 10:1.

[0012] Optionally, in the step of forming the first sidewall layer, the thickness of the first sidewall layer is 13 nanometers to 17 nanometers.

[0013] Optionally, the step of forming the second sidewall layer includes: forming a second sidewall material layer on top of the suspended grid layer exposed by the control grid layer, on the sidewall of the first sidewall layer, and on top of the control grid layer; removing the second sidewall material layer on top of the suspended grid layer and the second sidewall material layer on top of the control grid layer, and using the remaining second sidewall material layer located on the sidewall of the control grid layer as the second sidewall layer.

[0014] Optionally, the process for removing the second sidewall material layer on top of the suspending gate layer and the second sidewall material layer on top of the control gate layer includes a dry etching process.

[0015] Optionally, the process parameters of the dry etching process include: the process gas includes argon, oxygen and fluoromethane; the chamber pressure range is 10 mTorr to 20 mTorr.

[0016] Optionally, in the step of forming the second sidewall layer, the thickness of the second sidewall layer is 33 nanometers to 40 nanometers.

[0017] Optionally, the process of patterning the suspended gate layer using the first and second sidewall layers as masks includes a dry etching process.

[0018] Optionally, in the step of providing the substrate, a gate oxide layer is further formed on the top of the substrate, the gate oxide layer being located between the substrate and the levitated gate layer; after removing the levitated gate layer on the side of the control gate layer, the method of forming the semiconductor structure further includes: forming a third sidewall layer on the top of the substrate that covers the sidewalls of the second sidewall layer and the sidewalls of the levitated gate layer; forming an erase gate layer that covers the gate oxide layer and the third sidewall layer between adjacent control gate layers and between adjacent levitated gate layers; and forming a word line structure that covers the gate oxide layer and the third sidewall layer on the side opposite to the adjacent control gate layer and on the side opposite to the adjacent levitated gate layer.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0020] In the semiconductor structure formation method provided by this embodiment of the invention, a first sidewall layer is formed on the sidewall of the control gate layer; after forming the first sidewall layer, a second sidewall layer covering the sidewall of the first sidewall layer is formed on top of the substrate; using the first and second sidewall layers as masks, the floating gate layer is patterned to remove the floating gate layer on the side of the control gate layer. Compared with a scheme where the first and second sidewall layers are formed in the same step, in this embodiment of the invention, the first and second sidewall layers are formed in different steps. During the formation of the first sidewall layer, the process of forming the first sidewall layer consumes part of the sidewall of the first sidewall layer, making the first sidewall layer... The sidewalls of one sidewall layer become smooth, reducing the probability of the first sidewall layer being L-shaped. Correspondingly, during the formation of the second sidewall layer, the process of forming the second sidewall layer consumes part of the sidewall of the second sidewall layer, making its sidewall also smooth. In the subsequent patterning process of the floating gate layer using the first and second sidewall layers as masks, since the first and second sidewall layers serve as etching masks and their sidewalls are relatively smooth, the morphology of the sidewalls of the patterned floating gate layer is also relatively flat and smooth, reducing the probability of unevenness on the sidewalls of the floating gate layer, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0021] Figures 1 to 3 This is a schematic diagram of a method for forming a semiconductor structure.

[0022] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0023] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example.

[0024] Figures 1 to 3 This is a schematic diagram of a method for forming a semiconductor structure.

[0025] refer to Figure 1 A substrate 10 is provided, on the top of which a floating grid layer 12 is formed, and a control grid layer 14 protrudes from the top of the floating grid layer 12. A first sidewall material layer 16 covering the floating grid layer 12 and the control grid layer 14, and a second sidewall material layer 17 covering the first sidewall material layer 16 are formed on the top of the substrate 10.

[0026] refer to Figure 2 Remove the first sidewall material layer 16 and the second sidewall material layer 17 exposed on the top of the floating grid layer 12 of the control grid layer 14, as well as the first sidewall material layer 16 and the second sidewall material layer 17 on the top of the control grid layer 14. The remaining first sidewall material layer 16 serves as the first sidewall layer 20, and the remaining second sidewall layer 17 serves as the second sidewall layer 18.

[0027] refer to Figure 3 Using the first sidewall layer 20 and the second sidewall layer 18 as masks, the floating gate layer 12 on the side of the control gate layer 14 is patterned and then removed.

[0028] Research has revealed that when the first and second sidewall layers are formed using a dry etching process, and these layers are formed in the same step, the first sidewall layer tends to be L-shaped. This means that portions protruding from the sidewalls of the first sidewall layer are more likely to remain (e.g., ...). Figure 2 As shown in the dashed circle, during the subsequent patterning process of the floating gate layer 12 on the side of the control gate layer 14, the sidewall morphology of the second sidewall layer is prone to being uneven. Consequently, during the subsequent patterning process of the floating gate layer 12 on the side of the control gate layer 14 using the first and second sidewall layers as masks, the sidewall morphology of the patterned floating gate layer 12 is prone to being uneven. During the subsequent reliability testing of the semiconductor structure, electrons are prone to escape from the uneven sidewall morphology of the floating gate layer 12, thereby affecting the performance of the semiconductor structure.

[0029] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a floating gate layer is formed on the top of the substrate, and a control gate layer protrudes from the top of the floating gate layer; forming a first sidewall layer on the sidewall of the control gate layer; after forming the first sidewall layer, forming a second sidewall layer on the top of the substrate that covers the sidewall of the first sidewall layer; using the first sidewall layer and the second sidewall layer as masks, performing patterning processing on the floating gate layer to remove the floating gate layer on the side of the control gate layer.

[0030] In the semiconductor structure formation method provided by this embodiment of the invention, a first sidewall layer is formed on the sidewall of the control gate layer; after forming the first sidewall layer, a second sidewall layer covering the sidewall of the first sidewall layer is formed on top of the substrate; using the first and second sidewall layers as masks, the floating gate layer is patterned to remove the floating gate layer on the side of the control gate layer. Compared with a scheme where the first and second sidewall layers are formed in the same step, in this embodiment of the invention, the first and second sidewall layers are formed in different steps. During the formation of the first sidewall layer, the process of forming the first sidewall layer consumes part of the sidewall of the first sidewall layer, making the first sidewall layer... The sidewalls of one sidewall layer become smooth, reducing the probability of the first sidewall layer being L-shaped. Correspondingly, during the formation of the second sidewall layer, the process of forming the second sidewall layer consumes part of the sidewall of the second sidewall layer, making its sidewall also smooth. In the subsequent patterning process of the floating gate layer using the first and second sidewall layers as masks, since the first and second sidewall layers serve as etching masks and their sidewalls are relatively smooth, the morphology of the sidewalls of the patterned floating gate layer is also relatively flat and smooth, reducing the probability of unevenness on the sidewalls of the floating gate layer, thereby improving the performance of the semiconductor structure.

[0031] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] refer to Figures 4 to 11 The diagram shows a schematic diagram of each step in an embodiment of the method for forming a semiconductor structure according to the present invention.

[0033] refer to Figure 4 A substrate 100 is provided, on the top of which a floating gate layer 102 is formed, and a control gate layer 104 protrudes from the top of the floating gate layer 102.

[0034] Substrate 100 provides a process platform for forming Flash memory.

[0035] In this embodiment, the substrate 100 includes a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0036] The floating gate layer 102 is used to store electrons during the operation of the Flash memory, thereby enabling the Flash memory to perform data storage functions.

[0037] In this embodiment, the material of the levitation gate layer 102 is polycrystalline silicon.

[0038] Polysilicon is a commonly used material for the floating gate layer 102 in Flash memory, thus having the advantage of low process cost.

[0039] As an example, in the step of providing the substrate 100, a gate oxide layer 101 is also formed on the top of the substrate 100, and the gate oxide layer 101 is located between the substrate 100 and the floating gate layer 102.

[0040] Specifically, the gate oxide layer 101 is a tunnel oxide layer of the flash memory, used as an insulating layer between the floating gate layer 102 and the substrate 100. When the flash memory is working, electrons can enter the floating gate layer 102 through the gate oxide layer 101 by tunneling effect. Moreover, during data storage, it prevents electrons stored in the floating gate layer 102 from entering the silicon substrate, thereby reducing electron loss. That is, the gate oxide layer 101 is suitable for preventing the loss of data stored in the floating gate layer 102.

[0041] As an example, the gate oxide layer 101 is made of silicon oxide. In other embodiments, the gate oxide layer may also be made of silicon oxynitride.

[0042] It should be noted that the thickness of the gate oxide layer 101 should not be too large or too small. If the thickness of the gate oxide layer 101 is too large, after the formation of the control gate layer 104, the overall height of the Flash memory will be too high, which is not conducive to further miniaturization of the semiconductor structure. If the thickness of the gate oxide layer 101 is too small, during data storage, the probability of electrons stored in the floating gate layer 102 entering the substrate 100 is increased, thereby increasing the probability of electron loss and affecting the storage performance of the Flash memory. Therefore, in this embodiment, the thickness of the gate oxide layer 101 is 7 nanometers to 11 nanometers.

[0043] Specifically, the control gate layer 104 is used to electrically connect with an external circuit structure to control the longitudinal electric field of the levitated gate layer 102.

[0044] As an example, the steps of forming the control gate layer 104 include: forming a control gate material layer (not shown) on top of the floating gate layer 102; forming a patterned hard mask layer 105 on top of the control gate material layer; and using the patterned hard mask layer 105 as a mask to pattern the control gate material layer, thereby forming a raised control gate layer 104 on top of the floating gate layer 102.

[0045] As an example, the process of patterning the control gate material layer using the patterned hard mask layer 105 as a mask includes a dry etching process.

[0046] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching has anisotropic dry etching characteristics, with a longitudinal etching rate greater than a transverse etching rate. The process has high controllability. Using the dry etching process to pattern the control gate material layer can ensure the morphological quality of the control gate layer 104 sidewalls, making the morphology of the control gate layer 104 sidewalls relatively flat and smooth. Correspondingly, in the subsequent formation of the first sidewall layer and the second sidewall layer, the process difficulty of depositing film on the sidewalls of the control gate layer 104 is reduced, and the uniformity of the film thickness can be improved.

[0047] In this embodiment, the material of the control gate layer 104 is polycrystalline silicon.

[0048] Polysilicon is a commonly used material for the floating gate layer 102 in Flash memory, thus having the advantage of low process cost.

[0049] In this embodiment, during the step of providing the substrate 100, a gate insulating layer 103 is also formed between the suspending gate layer 102 and the control gate layer 104.

[0050] The gate insulating layer 103 is used to provide electrical isolation between the floating gate layer 102 and the control gate layer 104.

[0051] As an example, the gate insulating layer 103 is an Oxide-Nitride-Oxide (ONO) structure.

[0052] The ONO structure allows for a reduction in the thickness of the gate insulating layer 103 of the Flash memory while further increasing the dielectric constant of the gate insulating layer 103, thereby enabling the Flash memory to have a higher breakdown electric field and lower leakage current characteristics.

[0053] In other embodiments, the gate insulating layer may also be a single-layer structure, wherein the gate insulating layer is a silicon oxide layer or a silicon nitride layer.

[0054] refer to Figures 5 to 6A first sidewall layer 112 is formed on the sidewall of the control grid layer 104.

[0055] It should be noted that, compared to the scheme where the first sidewall layer 112 and the second sidewall layer are formed in the same step, in this embodiment, the first sidewall layer 112 and the subsequently formed second sidewall layer are formed in different steps. During the formation of the first sidewall layer 112, the process consumes part of the sidewall of the first sidewall layer 112, making the sidewall of the first sidewall layer 112 smooth and reducing the probability of the first sidewall layer being L-shaped. Correspondingly, during the formation of the second sidewall layer, the process consumes part of the second sidewall layer... The partial sidewalls of the sidewall layer make the sidewalls of the second sidewall layer smooth as well. In the subsequent patterning process of the floating gate layer 102 using the first sidewall layer 112 and the second sidewall layer as masks, since the first sidewall layer 112 and the second sidewall layer are used as etching masks and the sidewalls of the first sidewall layer 112 and the second sidewall layer are relatively smooth, the shape of the sidewalls of the patterned floating gate layer 102 is also relatively flat and smooth, reducing the probability of unevenness on the sidewalls of the floating gate layer 102, thereby improving the performance of the semiconductor structure.

[0056] It should also be noted that the first sidewall layer 112 is also used to electrically isolate the floating grid layer 102 from the subsequently formed erase grid layer and word line structure, as well as the control grid layer 104 from the subsequently formed erase grid layer and word line structure.

[0057] In this embodiment, the first sidewall layer 112 includes a first sub-sidewall layer 110 covering the sidewall of the control grid layer 104, and a second sub-sidewall layer 108 covering the sidewall of the first sub-sidewall layer 110.

[0058] Specifically, the first sub-sidewall layer 110 acts as an etching stop layer. During the formation of the second sub-sidewall layer 108, the material forming the first sub-sidewall layer 110 protects the sidewalls and top of the floating gate layer 102 and the sidewalls and top of the control gate layer 104, reducing the probability of damage to the floating gate layer 102 and the control gate layer 104 caused by the process of forming the second sub-sidewall layer 108, thereby improving the performance of the semiconductor structure.

[0059] In this embodiment, the step of forming the first sidewall layer 112 includes: forming a first sub-sidewall material layer 106 on the top of the exposed floating grid layer 102 of the control grid layer 104, the top of the control grid layer 104, and the sidewall; forming a second sub-sidewall material layer 107 covering the first sub-sidewall material layer 106; removing the second sub-sidewall material layer 107 on the top of the exposed floating grid layer 102 of the control grid layer 104 and the second sub-sidewall material layer 107 on the top of the control grid layer 104, using the first sub-sidewall material layer 106 located on the sidewall of the control grid layer 104 as the first sub-sidewall layer 110, and using the remaining second sub-sidewall material layer 107 as the second sub-sidewall layer 108, wherein the first sub-sidewall layer 110 and the second sub-sidewall layer 108 constitute the first sidewall layer 112.

[0060] The first sub-sidewall material layer 106 is used as the material layer forming the first sub-sidewall layer 110.

[0061] During the process of removing the second sub-sidewall material layer 107 exposed on top of the floating gate layer 102 and the second sub-sidewall material layer 107 on top of the control gate layer 104, the first sub-sidewall material layer 106 acts as an etching stop layer. The first sub-sidewall material layer 106 protects the sidewalls and top of the floating gate layer 102 and the control gate layer 104, reducing the probability of damage to the floating gate layer 102 and the control gate layer 104, thereby improving the performance of the semiconductor structure.

[0062] In this embodiment, the process of removing the second sub-sidewall material layer 107 exposed on top of the floating gate layer 102 and the second sub-sidewall material layer 107 on top of the control gate layer 104 includes a dry etching process.

[0063] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching processes possess anisotropic dry etching characteristics, with a longitudinal etching rate greater than a transverse etching rate, resulting in higher process controllability. By using dry etching to remove the second sub-sidewall material layer 107 exposed on top of the floating gate layer 102 and the second sub-sidewall material layer 107 on top of the control gate layer 104, the first sub-sidewall material layer 106 can protect the sidewalls and top of the floating gate layer 102 and the control gate layer 104. During the process of removing the second sub-sidewall material layer 107 exposed on top of the floating gate layer 102 and the second sub-sidewall material layer 107 on top of the control gate layer 104 using a dry etching process, the dry etching process also consumes part of the sidewall of the second sub-sidewall layer 108. Since the longitudinal etching rate of the dry etching process is greater than the transverse etching rate, the sidewall morphology of the second sub-sidewall layer 108 becomes smooth. Correspondingly, this means that the sidewall morphology of the first sidewall layer 112 becomes smooth, thereby improving the sidewall morphology quality of the first sidewall layer 112.

[0064] In this embodiment, the process gas in the dry etching process includes argon, oxygen, and fluoromethane.

[0065] In dry etching processes, oxygen is used as an auxiliary gas to promote the etching reaction, argon is used as a functional auxiliary gas to improve the etching rate, and fluoromethane is used as the etching gas in dry etching processes.

[0066] It should be noted that in dry etching processes, the cavity pressure range should not be too large or too small. If the cavity pressure is too high, the concentration of reactive gas per unit volume will be too high, increasing the probability of collisions between electrons and ions in the plasma. This leads to energy loss in charged reactive particles, thereby reducing the bombardment capability of ions in the dry etching process. Conversely, if the cavity pressure is too low, the mean free path of the plasma will be too long, affecting the etching rate. Therefore, in this embodiment, the cavity pressure range in the dry etching process is 60 mTorr to 90 mTorr.

[0067] It should also be noted that, during the process of removing the second sub-sidewall material layer 107 exposed on top of the floating gate layer 102 and the second sub-sidewall material layer 107 on top of the control gate layer 104, the etching selectivity ratio of the second sub-sidewall material layer 107 and the first sub-sidewall material layer 106 should not be too small. If the etching selectivity ratio between the second sub-sidewall material layer 107 and the first sub-sidewall material layer 106 is too small, the removal of the second sub-sidewall material layer 107 may also lead to the removal of the first sub-sidewall material layer 106, increasing the probability of damage to the floating gate layer 102 and the control gate layer 104. At the same time, it also increases the probability of damage to the surface of the first sub-sidewall material layer 106, resulting in poor surface flatness. This increases the probability of uneven thickness of the second sidewall layer during the subsequent formation of the second sidewall layer, affecting the subsequent patterning of the floating gate layer 102 and causing uneven sidewall morphology of the floating gate layer 102, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, during the process of removing the second sub-sidewall material layer 107 exposed on top of the floating gate layer 102 and the second sub-sidewall material layer 107 on top of the control gate layer 104, the etching selectivity ratio of the second sub-sidewall material layer 107 and the first sub-sidewall material layer 106 is greater than 10:1.

[0068] Specifically, the thickness of the first sidewall layer 112 should not be too large or too small. If the thickness of the first sidewall layer 112 is too large, it can easily affect the size of the semiconductor device. During the formation of the first sidewall layer 112 using a dry etching process, the dry etching process also consumes part of the sidewalls of the first sidewall layer 112. If the thickness of the first sidewall layer 112 is too small, it can easily lead to the complete consumption of the first sidewall layer 112 or to make the remaining thickness of the first sidewall layer 112 even smaller, failing to meet the requirements of Flash memory for the thickness and dielectric constant of the first sidewall layer 112, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the first sidewall layer 112 is 13 nanometers to 17 nanometers.

[0069] refer to Figures 7 to 8 After the first sidewall layer 112 is formed, a second sidewall layer 122 is formed on top of the substrate 100, covering the sidewalls of the first sidewall layer 112.

[0070] It should be noted that during the formation of the second sidewall layer 122, the process of forming the second sidewall layer 122 consumes part of the sidewall of the second sidewall layer 122, making the sidewall of the second sidewall layer 122 smooth as well. In the subsequent patterning process of the floating gate layer 102 using the first sidewall layer 112 and the second sidewall layer 122 as masks, since the first sidewall layer 112 and the second sidewall layer 122 serve as etching masks and their sidewalls are relatively smooth, the shape of the sidewall of the patterned floating gate layer 102 is also relatively flat and smooth. This reduces the probability of unevenness on the sidewall of the floating gate layer 102, improves the flatness of the sidewall of the floating gate layer 102, and thus improves the performance of the semiconductor structure.

[0071] In this embodiment, the step of forming the second sidewall layer 122 includes: forming a second sidewall material layer 123 on the top of the exposed floating grid layer 102 of the control grid layer 104, the sidewall of the first sidewall layer 112, and the top of the control grid layer 104; removing the second sidewall material layer 123 on the top of the floating grid layer 102 and the second sidewall material layer 123 on the top of the control grid layer 104, and using the remaining second sidewall material layer 123 located on the sidewall of the control grid layer 104 as the second sidewall layer 122.

[0072] In this embodiment, the process of removing the second sidewall material layer 123 on top of the floating gate layer 102 and the second sidewall material layer 123 on top of the control gate layer 104 includes a dry etching process.

[0073] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching has anisotropic characteristics, with a longitudinal etching rate greater than the transverse etching rate, resulting in higher process controllability. Using the dry etching process to remove the second sidewall material layer 123 on top of the suspended gate layer 102 and the second sidewall material layer 123 on top of the control gate layer 104 can completely remove the exposed second sidewall material layers 123 on top of the suspended gate layer 102 and the control gate layer 104, while retaining the second sidewall material layer 123 on the sidewall of the control gate layer 104. The first sidewall layer 112 and the second sidewall layer 122 serve as the second sidewall material layer 122. Simultaneously, during the dry etching process to remove the second sidewall material layer 123 exposed on the top of the floating gate layer 102 and the second sidewall material layer 123 on the top of the control gate layer 104, the dry etching process also consumes part of the sidewall of the second sidewall layer 122. Since the longitudinal etching rate of the dry etching process is greater than the transverse etching rate, the sidewall morphology of the second sidewall layer 122 becomes smooth. In the subsequent patterning of the floating gate layer 102, the first sidewall layer 112 and the second sidewall layer 122 serve as etching masks, thereby improving the flatness of the sidewall of the floating gate layer 102.

[0074] In this embodiment, the process gases in the dry etching process include argon, oxygen, and fluoromethane.

[0075] In dry etching processes, oxygen is used as an auxiliary gas to promote the etching reaction, argon is used as a functional auxiliary gas to improve the etching rate, and fluoromethane is used as the etching gas in dry etching processes.

[0076] It should be noted that in dry etching processes, the cavity pressure range should not be too large or too small. If the cavity pressure is too high, the concentration of reactive gas per unit volume will be too high, increasing the probability of collisions between electrons and ions in the plasma. This leads to energy loss in charged reactive particles, thereby reducing the bombardment capability of ions in the dry etching process. Conversely, if the cavity pressure is too low, the mean free path of the plasma will be too long, affecting the etching rate. Therefore, in this embodiment, the cavity pressure range in the dry etching process is 60 mTorr to 90 mTorr.

[0077] It should also be noted that, during the formation of the second sidewall material layer 123, the second sidewall material layer 123 covers the first sub-sidewall material layer 106 located on top of the floating grid layer 102 and the first sub-sidewall material layer 106 located on top of the control grid layer 104.

[0078] In this embodiment, during the step of forming the second sidewall layer 122, the first sub-sidewall material layer 106 on top of the floating grid layer 102 and the first sub-sidewall material layer 106 on top of the floating grid layer 102 are also removed.

[0079] Specifically, in the process of removing the second sidewall material layer 123 on top of the suspended grid layer 102 and the second sidewall material layer 123 on top of the control grid layer 104, the first sub-sidewall material layer 106 on top of the suspended grid layer 102 and the first sub-sidewall material layer 106 on top of the suspended grid layer 102 are also removed. This means that the second sidewall material layer 123 and the first sub-sidewall material layer 106 are removed in the same step, which reduces the number of process steps and lowers the process cost.

[0080] In other embodiments, the first sub-sidewall material layer on top of the floating grid layer and the first sub-sidewall material layer on top of the floating grid layer may be removed after the second sidewall material layer on top of the floating grid layer and the second sidewall material layer on top of the control grid layer are removed.

[0081] It should be noted that the thickness of the second sidewall layer 122 should not be too large or too small. If the thickness of the second sidewall layer 122 is too large, it can easily affect the size of the semiconductor device; if the thickness of the second sidewall layer 122 is too small, during the dry etching process to form the second sidewall layer 122, the dry etching process will also consume part of the sidewalls of the second sidewall layer 122, which may lead to the complete consumption of the second sidewall layer 122 or make the remaining thickness of the second sidewall layer 122 even smaller, failing to meet the thickness and dielectric constant requirements of the Flash memory for the second sidewall layer 122, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the second sidewall layer 122 is 33 nanometers to 40 nanometers.

[0082] refer to Figure 9 Using the first sidewall layer 112 and the second sidewall layer 122 as masks, the floating gate layer 102 is patterned to remove the floating gate layer 102 on the side of the control gate layer 104.

[0083] Specifically, the floating gate layer 102 is graphically processed to remove the floating gate layer 102 on the side of the control gate layer 104, which helps to provide space for the subsequently formed erase gate layer and word line structure.

[0084] In this embodiment, the process of patterning the suspended gate layer 102 using the first sidewall layer 112 and the second sidewall layer 122 as masks includes a dry etching process.

[0085] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching has anisotropic dry etching characteristics, with a longitudinal etching rate greater than a transverse etching rate, resulting in higher process controllability. Since the first sidewall layer 112 and the second sidewall layer 122 serve as etching masks, and the sidewalls of the first sidewall layer 112 and the second sidewall layer 122 are relatively smooth, the morphology of the sidewalls of the patterned floating gate layer 102 is also relatively flat and smooth, reducing the probability of unevenness on the sidewalls of the floating gate layer 102, improving the flatness of the sidewalls of the floating gate layer 102, and thus improving the performance of the semiconductor structure.

[0086] refer to Figures 10 to 11The method of forming the semiconductor structure further includes: forming a third sidewall layer 130 on top of the substrate 100, covering the sidewalls of the second sidewall layer 122 and the sidewalls of the floating gate layer 102; forming an erase gate layer 140 between adjacent control gate layers 104 and between adjacent floating gate layers 102, covering the gate oxide layer 101 and the third sidewall layer 130; and forming a word line (WL) structure covering the gate oxide layer 101 and the third sidewall layer 130 on the side opposite to the adjacent control gate layer 104 and the side opposite to the adjacent floating gate layer 102.

[0087] Specifically, the third sidewall layer 130 is used to achieve electrical isolation between the erase grid layer 140 and the floating grid layer 102, as well as electrical isolation between the word line structure 150 and the floating grid layer 102.

[0088] In this embodiment, the material of the third sidewall layer 130 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0089] The erase gate layer 140 is used to erase signals from the Flash memory.

[0090] Specifically, by applying a high voltage to the erase gate layer 140, a potential difference is formed on the third sidewall layer 130 between the erase gate layer 140 and the floating gate layer 102 due to the coupling capacitance. This difference can pull electrons in the floating gate layer 102 to the erase gate layer 140 through tunneling. As electrons are pulled out of the floating gate layer 102, the potential in the floating gate layer 102 increases, and the potential difference between the floating gate layer 102 and the erase gate layer 140 decreases, weakening the potential difference of the gate insulating layer 103. Finally, the electrons in the floating gate layer 102 are completely pulled out, realizing the signal erasure of the memory.

[0091] In this embodiment, the material used to erase the gate layer 140 includes polysilicon.

[0092] The word line structure 150 is used to control the channel electronics.

[0093] Specifically, a high voltage is applied to the word line structure 150 to open the channel. A high voltage is applied to the control gate layer 104 to create a strong vertical electric field between the floating gate layer 102 and the control gate layer 104. The strong vertical electric field accelerates the channel electrons in the vertical direction, and some electrons are injected into the floating gate layer 102, thus realizing electron injection and signal writing.

[0094] As an example, the material of word line structure 150 is polycrystalline silicon.

[0095] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on top of which a floating gate layer is formed, and on top of the floating gate layer a control gate layer protrudes; A first sidewall layer is formed on the sidewall of the control gate layer; the first sidewall layer includes a first sub-sidewall layer covering the sidewall of the control gate layer, and a second sub-sidewall layer covering the sidewall of the first sub-sidewall layer; The step of forming the first sidewall layer includes: forming a first sub-sidewall material layer on top of the exposed floating grid layer of the control grid layer, on top of the control grid layer, and on the sidewall; forming a second sub-sidewall material layer covering the first sub-sidewall material layer; removing the second sub-sidewall material layer on top of the exposed floating grid layer of the control grid layer and the second sub-sidewall material layer on top of the control grid layer, using the first sub-sidewall material layer located on the sidewall of the control grid layer as the first sub-sidewall layer, and using the remaining second sub-sidewall material layer as the second sub-sidewall layer, wherein the first sub-sidewall layer and the second sub-sidewall layer constitute the first sidewall layer; After the first sidewall layer is formed, a second sidewall layer is formed on top of the substrate to cover the sidewall of the first sidewall layer; in the step of forming the second sidewall layer, the first sub-sidewall material layer on top of the floating grid layer and the first sub-sidewall material layer on top of the floating grid layer are also removed. Using the first and second sidewall layers as masks, the floating grid layer is patterned to remove the floating grid layer on the side of the control grid layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming the control gate layer include: forming a control gate material layer on top of the floating gate layer; forming a patterned hard mask layer on top of the control gate material layer; using the patterned hard mask layer as a mask, performing patterning processing on the control gate material layer to form a raised control gate layer on top of the floating gate layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the second sub-sidewall material layer exposed on top of the floating gate layer and the second sub-sidewall material layer on top of the control gate layer includes a dry etching process.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process parameters of the dry etching process include: process gases including argon, oxygen and fluoromethane; and chamber pressure ranging from 60 mTorr to 90 mTorr.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the process of removing the second sub-sidewall material layer exposed on top of the floating gate layer and the second sub-sidewall material layer on top of the control gate layer, the etching selectivity ratio of the second sub-sidewall material layer to the first sub-sidewall material layer is greater than 10:

1.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the first sidewall layer, the thickness of the first sidewall layer is 13 nanometers to 17 nanometers.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the second sidewall layer includes: forming a second sidewall material layer on top of the suspended grid layer exposed on the control grid layer, on the sidewall of the first sidewall layer, and on top of the control grid layer; removing the second sidewall material layer on top of the suspended grid layer and the second sidewall material layer on top of the control grid layer, and using the remaining second sidewall material layer located on the sidewall of the control grid layer as the second sidewall layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process for removing the second sidewall material layer on top of the floating gate layer and the second sidewall material layer on top of the control gate layer includes a dry etching process.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process parameters of the dry etching process include: process gases including argon, oxygen and fluoromethane; and chamber pressure ranging from 10 mTorr to 20 mTorr.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the second sidewall layer, the thickness of the second sidewall layer is 33 nanometers to 40 nanometers.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of patterning the suspended gate layer using the first and second sidewall layers as masks includes a dry etching process.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a gate oxide layer is further formed on the top of the substrate, and the gate oxide layer is located between the substrate and the suspended gate layer; After removing the floating gate layer on the side of the control gate layer, the method of forming the semiconductor structure further includes: forming a third sidewall layer on top of the substrate that covers the sidewall of the second sidewall layer and the sidewall of the floating gate layer; An eraser gate layer covering the gate oxide layer and the third sidewall layer is formed between adjacent control gate layers and between adjacent floating gate layers. A word line structure covering the gate oxide layer and the third sidewall layer is formed on the side opposite to the adjacent control gate layer and on the side opposite to the adjacent floating gate layer.

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