Semiconductor device

Abstract

A semiconductor device includes a lower electrode, an upper electrode on the lower electrode, and a dielectric layer structure between the lower electrode and the upper electrode. The dielectric layer structure includes a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode. The first dielectric layer, the second dielectric layer, and the third dielectric layer include an antiferroelectric material. The antiferroelectric materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are of the same material type, and a silicon dopant is included in a region adjacent to an interface between the first dielectric layer and the lower electrode and a region adjacent to an interface between the third dielectric layer and the upper electrode.

Description

Technical Field

[0001] The present inventive concept relates to a semiconductor device. More particularly, the present inventive concept relates to a semiconductor device including an antiferroelectric material. Background Art

[0002] With the trend of high integration of semiconductor devices, a single circuit pattern is further refined to realize more semiconductor devices in the same area. That is, as the integration of semiconductor devices increases, the design rules of the components of semiconductor devices are decreasing. Therefore, there is a need for a semiconductor device that can maintain electrical characteristics by overcoming the limitations of design rules. Summary of the invention

[0003] The inventive concept provides a semiconductor device having improved operational reliability.

[0004] According to one aspect of the present invention, a semiconductor device is provided, which includes a lower electrode, an upper electrode on the lower electrode, and a dielectric layer structure between the lower electrode and the upper electrode. The dielectric layer structure includes a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode. The first dielectric layer, the second dielectric layer, and the third dielectric layer include antiferroelectric materials. The antiferroelectric materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are of the same material type, and silicon dopants are included in a region adjacent to an interface between the first dielectric layer and the lower electrode and in a region adjacent to an interface between the third dielectric layer and the upper electrode.

[0005] According to another aspect of the present invention, a semiconductor device is provided, which includes a lower electrode, an upper electrode on the lower electrode, and a dielectric layer structure between the lower electrode and the upper electrode. The dielectric layer structure includes a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode. The second dielectric layer includes a plurality of ferroelectric material layers and a plurality of antiferroelectric material layers stacked alternately, and a silicon dopant is included in at least one of a region adjacent to an interface between the first dielectric layer and the lower electrode and a region adjacent to an interface between the third dielectric layer and the upper electrode.

[0006] According to another aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising a substrate having a plurality of active regions defined by a device isolation layer, a lower structure on the substrate and connected to the plurality of active regions, and a capacitor structure on the lower structure and connected to the lower structure. The capacitor structure comprises a lower electrode, an upper electrode on the lower electrode, and a dielectric layer structure between the lower electrode and the upper electrode. The dielectric layer structure comprises a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode. Each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises HfO 2 and ZrO 2 At least one of the silicon dopants is included in the interior of the first dielectric layer and in the interior of the third dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings:

[0008] Figure 1 is a layout diagram schematically illustrating components of a semiconductor device according to various example embodiments;

[0009] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0010] Figure 3 yes Figure 2 An enlarged cross-sectional view of a region EX;

[0011] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 is shown with Figure 2 An enlarged cross-sectional view of a region corresponding to the region EX shown in FIG.

[0012] Fig. 9 is a layout diagram schematically illustrating components of a semiconductor device according to various example embodiments;

[0013] Fig.10 is along Fig. 9 A cross-sectional view taken along line BB';

[0014] Fig.11 yes Fig.10 An enlarged cross-sectional view of a region EX';

[0015] Fig.12 yes Fig.11 an enlarged cross-sectional view of a region EX"; and

[0016] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F , Figure 13G and Fig.13H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, various exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof are omitted.

[0018] Figure 1 is a layout diagram schematically illustrating components of a semiconductor device 100 according to various example embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 yes Figure 2 An enlarged cross-sectional view of area EX.

[0019] Reference Figure 1 , the semiconductor device 100 may include a plurality of active regions AC arranged to have a long axis in a diagonal direction relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of word lines WL may extend parallel to each other across the plurality of active regions AC in a first direction (X direction). A plurality of bit lines BL may extend parallel to each other along a second horizontal direction (Y direction) on the plurality of word lines WL. Each of the plurality of bit lines BL may be connected to the active region AC by a direct contact DC.

[0020] A plurality of buried contacts BC may be arranged between two bit lines BL adjacent to each other among the plurality of bit lines BL. A plurality of landing pads LP may be arranged on the plurality of buried contacts BC. At least a portion of each of the plurality of landing pads LP may overlap with the buried contact BC in a vertical direction (Z direction). Each of the plurality of lower electrodes LE may be arranged on each of the plurality of landing pads LP to be spaced apart from each other. The plurality of lower electrodes LE may be connected to the plurality of active regions AC through the plurality of buried contacts BC and the plurality of landing pads LP.

[0021] Reference Figure 2 and Figure 3 , the semiconductor device 100 may include: a substrate 110 including a plurality of active areas AC, a lower structure 120 disposed on the substrate 110 , and a plurality of capacitor structures CP disposed on the lower structure 120 .

[0022] The substrate 110 may include a semiconductor element such as Si and Ge or a compound semiconductor such as SiC, GaAs, InAs, and InP. However, example embodiments are not limited thereto. The substrate 110 may include a semiconductor substrate, or a structure including at least one insulating layer or at least one conductive region formed on a semiconductor substrate. The conductive region may include, for example, a well doped with impurities or a structure doped with impurities.

[0023] A device isolation layer 112 defining a plurality of active regions AC may be formed on the substrate 110. The device isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof. In various example embodiments, the device isolation layer 112 may have various structures such as a shallow trench isolation (STI) structure.

[0024] The lower structure 120 may include a plurality of conductive regions 124 and a plurality of insulating structures 122. The plurality of conductive regions 124 may penetrate the lower structure 120 in the vertical direction (Z direction) to be connected to the plurality of active regions AC. The plurality of conductive regions 124 may be insulated from each other by the plurality of insulating structures 122. Each of the plurality of insulating structures 122 may include an insulating layer including a silicon oxide layer, a silicon nitride layer, or a combination thereof. In some other example embodiments, the plurality of insulating structures 122 may each include various conductive regions (e.g., wiring layers, contact plugs, transistors, etc.) and insulating layers that insulate the various conductive regions from each other.

[0025] The plurality of conductive regions 124 may include polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof. However, example embodiments are not limited thereto. The plurality of conductive regions 124 may include reference Figure 1 Each of the plurality of conductive regions 124 may include a reference Figure 1 Describe the buried contact BC and landing pad LP.

[0026] The insulating pattern 126P may be arranged on the lower structure 120. The insulating pattern 126P may have a plurality of openings 126H overlapping the plurality of conductive regions 124 in the vertical direction (Z direction). The insulating pattern 126P may include a silicon nitride (SiN) layer, a silicon carbon nitride (SiCN) layer, a silicon boron nitride (SiBN) layer, or a combination thereof. However, example embodiments are not limited thereto. As used herein, the terms "SiN", "SiCN", and "SiBN" refer to materials including the elements included in each term, rather than chemical formulas representing stoichiometric relationships.

[0027] A plurality of capacitor structures CP may be arranged on the plurality of conductive regions 124. The plurality of capacitor structures CP may include a plurality of lower electrodes LE, a plurality of dielectric layer structures 160, and an upper electrode UE.

[0028] A plurality of lower electrodes LE may be arranged on the plurality of conductive regions 124. Each of the plurality of lower electrodes LE may have a columnar shape penetrating the insulating pattern 126P through each of the plurality of openings 126H and extending lengthwise in a direction away from the substrate 110 in a vertical direction (Z direction). Each of the plurality of lower electrodes LE may have a bottom surface contacting a top surface of one conductive region 124 to be connected to one conductive region 124 selected from among the plurality of conductive regions 124.

[0029] Although Figure 2 It is shown that each of the plurality of lower electrodes LE has a columnar shape, but various exemplary embodiments of the inventive concept are not limited thereto. For example, each of the plurality of lower electrodes LE may have a cross-sectional structure of a cup shape or a cylindrical shape in which a bottom is closed.

[0030] The plurality of lower electrodes LE may be supported by the lower support 142P and the upper support 144P. The plurality of lower electrodes LE and the upper electrode UE may face each other with the dielectric layer structures 160 respectively located therebetween.

[0031] The upper support 144P may surround the top end portion of each of the plurality of lower electrodes LE and may extend in parallel with the substrate 110. A plurality of holes 144H penetrated by the plurality of lower electrodes LE may be formed in the upper support 144P. The inner sidewall of each of the plurality of holes 144H formed in the upper support 144P may contact the sidewall of the lower electrode LE. The top surface of each of the plurality of lower electrodes LE and the top surface of the upper support 144P may be positioned coplanar.

[0032] The lower support 142P may extend parallel to the substrate 110 between the substrate 110 and the upper support 144P. The plurality of holes 142H penetrated by the plurality of lower electrodes LE and the plurality of lower holes LH (see Fig.13E ) may be formed in the lower support 142P. An inner sidewall of each of the plurality of holes 142H formed in the lower support 142P may contact a sidewall of each of the lower electrodes LE.

[0033] The lower support 142P and the upper support 144P may include a silicon nitride (SiN) layer, a silicon carbon nitride (SiCN) layer, a silicon boron nitride (SiBN) layer, or a combination thereof, but example embodiments are not limited thereto. In various example embodiments, the lower support 142P and the upper support 144P may include the same material. For example, each of the lower support 142P and the upper support 144P may include SiCN. In some other example embodiments, the lower support 142P and the upper support 144P may include materials different from each other. For example, the lower support 142P may include SiCN, and the upper support 144P may include SiBN.

[0034] The dielectric layer structure 160 may be arranged between the lower electrode LE and the upper electrode UE. The dielectric layer structure 160 may include a first dielectric layer 161, a second dielectric layer 163, and a third dielectric layer 165, the first dielectric layer 161 may contact the lower electrode LE, the second dielectric layer 163 may be arranged between the first dielectric layer 161 and the third dielectric layer 165, and the third dielectric layer 165 may contact the upper electrode UE.

[0035] Each of the first dielectric layer 161, the second dielectric layer 163, and the third dielectric layer 165 may include a ferroelectric material and an antiferroelectric material. For example, the ferroelectric material may be HfO 2 , the antiferroelectric material can be ZrO 2 In this case, the ratio of the ferroelectric material and the antiferroelectric material included in each of the first dielectric layer 161 , the second dielectric layer 163 , and the third dielectric layer 165 may vary according to the characteristics required for the semiconductor device 100 .

[0036] In various example embodiments, each of the first dielectric layer 161, the second dielectric layer 163, and the third dielectric layer 165 may include the same ferroelectric material and the same antiferroelectric material. For example, the first dielectric layer 161, the second dielectric layer 163, and the third dielectric layer 165 may include HfO 2 As ferroelectric materials and ZrO 2 As antiferroelectric materials.

[0037] In various example embodiments, the first dielectric layer 161 and the third dielectric layer 165 may each include a silicon dopant DP1. In various example embodiments, the silicon dopant DP1 may exist inside each of the first dielectric layer 161 and the third dielectric layer 165. In other example embodiments, the silicon dopant DP1 may exist at an interface where the first dielectric layer 161 and the lower electrode LE contact each other and at an interface where the third dielectric layer 165 and the upper electrode UE contact each other.

[0038] In various example embodiments, the atomic concentration of the silicon dopant DP1 included in the first dielectric layer 161 and the atomic concentration of the silicon dopant DP1 included in the third dielectric layer 165 may be in a range of about 1 atomic concentration % to about 10 atomic concentration %. For example, each of the first dielectric layer 161 and the third dielectric layer 165 may include the silicon dopant DP1 having about 5 atomic concentration %. When the atomic concentration of the silicon dopant DP1 included in the first dielectric layer 161 and the atomic concentration of the silicon dopant DP1 included in the third dielectric layer 165 exceed about 10 atomic concentration %, the crystallinity of the antiferroelectric material included in the first dielectric layer 161 and the antiferroelectric material included in the third dielectric layer 165 may be reduced, thereby deteriorating the performance of the antiferroelectric material and reducing the operational reliability of the semiconductor device 100.

[0039] In various example embodiments, the thickness 160t of the dielectric layer structure 160 may be about to about In various example embodiments, the thickness 161t of the first dielectric layer 161 and the thickness 165t of the third dielectric layer 165 may be within a range of about to about In various example embodiments, the thickness 161t of the first dielectric layer 161 may be the same as the thickness 165t of the third dielectric layer 165. For example, each of the thickness 161t of the first dielectric layer 161 and the thickness 165t of the third dielectric layer 165 may be approximately In various example embodiments, each of the thickness 161t of the first dielectric layer 161 and the thickness 165t of the third dielectric layer 165 may be different from each other. For example, the thickness 161t of the first dielectric layer 161 may be approximately The thickness 165t of the third dielectric layer 165 may be approximately When the thickness 161t of the first dielectric layer 161 and the thickness 165t of the third dielectric layer 165 exceed about When the second dielectric layer 163 and the lower electrode LE may be too far apart from each other, or the second dielectric layer 163 and the upper electrode UE may be too far apart from each other, thereby deteriorating the electrical characteristics of the semiconductor device 100 .

[0040] The upper electrode UE covers the dielectric layer structure 160 , and may be spaced apart from the plurality of lower electrodes LE with the dielectric layer structure 160 therebetween.

[0041] Each of the plurality of lower electrodes LE and the upper electrode UE may include a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal oxynitride, or a combination thereof. In example embodiments, each of the plurality of lower electrodes LE and the upper electrode UE may include Ti, Ti oxide, Ti nitride, Ti oxynitride, Co, Co oxide, Co nitride, Co oxynitride, Nb, Nb oxide, Nb nitride, Nb oxynitride, Sn, Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. For example, the plurality of lower electrodes LE and the upper electrode UE may include TiN, CoN, NbN, SnO 2 or a combination thereof, but the material constituting each of the plurality of lower electrodes LE and the upper electrode UE is not limited thereto.

[0042] The semiconductor device 100 according to various exemplary embodiments of the present inventive concept includes a capacitor structure CP, which includes a lower electrode LE, a dielectric layer structure 160, and an upper electrode UE. The dielectric layer structure 160 may include: a first dielectric layer 161, including a ferroelectric material, an antiferroelectric material, and a silicon dopant DP1; a third dielectric layer 165, including a ferroelectric material, an antiferroelectric material, and a silicon dopant DP1; and a second dielectric layer 163, arranged between the first dielectric layer 161 and the second dielectric layer and including a ferroelectric material and an antiferroelectric material. In this case, the second dielectric layer 163 not including the silicon dopant DP1 may be spaced apart from the lower electrode LE by the first dielectric layer 161 including the silicon dopant DP1, and may be spaced apart from the upper electrode UE by the third dielectric layer 165 including the silicon dopant DP1. Therefore, when the antiferroelectric material (such as ZrO 2 ) but when the dielectric layer not including the silicon dopant DP1 contacts the lower electrode LE and / or the upper electrode UE, during the annealing process for manufacturing the semiconductor device 100, the formation of a secondary phase material such as zirconium silicide or zirconium silicate at the interface where the dielectric layer including the antiferroelectric material and the lower electrode LE and / or the upper electrode UE contact each other can be reduced or prevented. Since the formation of the secondary phase material at the interface is reduced or prevented, the excessive crystallization of the antiferroelectric material can be reduced or prevented, thereby improving the operational reliability of the semiconductor device 100.

[0043] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 is shown with Figure 2 , and is a view for describing semiconductor devices 100a, 100b, 100c, 100d, and 100e according to various example embodiments. Figure 4 , Figure 5 , Figure 6, Figure 7 and Figure 8 The components of the semiconductor devices 100a, 100b, 100c, 100d and 100e shown in FIG. Figures 1 to 3 Components of the semiconductor device 100 shown in FIG. 1 are substantially the same or similar, and thus only differences will be mainly described below.

[0044] Reference Figure 4 , the semiconductor device 100a may have Figure 1 , Figure 2 and Figure 3 The configuration of the semiconductor device 100 shown in FIG. 1 is substantially the same as or similar to that of the semiconductor device 100, except that the dielectric layer structure 160a of the capacitor structure CPa includes a ferroelectric material and an antiferroelectric material, but does not include the silicon dopant DP2, and the silicon dopant DP2 is included at a portion adjacent to an interface at which each of the upper electrode UEa and the lower electrode LEa contacts the dielectric layer structure 160a. That is, the silicon dopant DP2 may be present in a portion of the lower electrode LEa adjacent to an interface at which the dielectric layer structure 160a and the lower electrode LEa contact each other, and in a portion of the upper electrode UEa adjacent to an interface at which the dielectric layer structure 160a and the upper electrode UEa contact each other.

[0045] In various example embodiments, the thickness of the dielectric layer structure 160a may be about to about within the range.

[0046] Reference Figure 5 , the semiconductor device 100b may have Figure 1 , Figure 2 and Figure 3 The configuration of the semiconductor device 100 shown in FIG. 1 is substantially the same as or similar to that of FIG. 1 , except that the silicon dopant DP3 is included at a portion adjacent to an interface of each of the upper electrode UEb and the lower electrode LEb in contact with the dielectric layer structure 160b.

[0047] In this case, the dielectric layer structure 160b of the capacitor structure CPb of the semiconductor device 100b may include a first dielectric layer 161b and a third dielectric layer 165b (which include a ferroelectric material, an antiferroelectric material, and a silicon dopant DP3) and a second dielectric layer 163b (which includes a ferroelectric material and an antiferroelectric material but does not include a silicon dopant DP3). That is, the silicon dopant DP3 may exist in the first dielectric layer 161b, in the third dielectric layer 165b, in a portion of the upper electrode UEb adjacent to an interface where the third dielectric layer 165b and the upper electrode UEb are in contact with each other, and in a portion of the lower electrode LEb adjacent to an interface where the first dielectric layer 161b and the lower electrode LEb are in contact with each other.

[0048] Reference Figure 6 , the semiconductor device 100c may include Figure 1 , Figure 2 and Figure 3 The configuration of the semiconductor device 100 shown in is basically the same or similar to the configuration, except that the dielectric layer structure 160c of the capacitor structure CPc includes ferroelectric material and antiferroelectric material but does not include silicon dopants, the first silicon layer 171 is included between the dielectric layer structure 160c and the lower electrode LEc, and the second silicon layer 173 is included between the dielectric layer structure 160c and the upper electrode UEc.

[0049] The first silicon layer 171 may separate the dielectric layer structure 160c from the lower electrode LEc, and the second silicon layer 173 may separate the dielectric layer structure 160c from the upper electrode UEc. Since the dielectric layer structure 160c is separated from the lower electrode LEc and the upper electrode UEc by the first silicon layer 171 and the second silicon layer 173, during the annealing process, the formation of a secondary phase material such as zirconium silicide at the interface where the dielectric layer structure 160c and the lower electrode LEc contact each other and at the interface where the dielectric layer structure 160c and the upper electrode UEc contact each other may be reduced or prevented.

[0050] In various example embodiments, the thickness 160ct of the dielectric layer structure 160c may be about to about In various example embodiments, the thickness 171t of the first silicon layer 171 and the thickness 173t of the second silicon layer 173 may be within a range of about to about In various example embodiments, the thickness 171t of the first silicon layer 171 may be the same as the thickness 173t of the second silicon layer 173. For example, each of the thickness 171t of the first silicon layer 171 and the thickness 173t of the second silicon layer 173 may be approximately In various example embodiments, the thickness 171t of the first silicon layer 171 may be different from the thickness 173t of the second silicon layer 173. For example, the thickness 171t of the first silicon layer 171 may be approximately The thickness 173t of the second silicon layer 173 may be approximately When the thickness 171t of the first silicon layer 171 and the thickness 173t of the second silicon layer 173 exceed about When the dielectric layer structure 160 c and the lower electrode LE or the dielectric layer structure 160 c and the upper electrode UE are excessively spaced apart from each other, electrical characteristics of the semiconductor device 100 c may be deteriorated.

[0051] Reference Figure 7 , the semiconductor device 100d may have Figure 1 , Figure 2 and Figure 3 The configuration of the semiconductor device 100 shown in is basically the same or similar to the configuration, except that the dielectric layer structure 160d of the capacitor structure CPd includes any one of a ferroelectric material and an antiferroelectric material, a first dielectric layer 161d and a third dielectric layer 165d including a silicon dopant DP4, and a second dielectric layer 163d including a plurality of ferroelectric material layers 163_1 and a plurality of antiferroelectric material layers 163_3.

[0052] In various example embodiments, the first dielectric layer 161d and the third dielectric layer 165d may include materials different from each other. For example, the first dielectric layer 161d may include an antiferroelectric material but may not include a ferroelectric material, and the third dielectric layer 165d may include a ferroelectric material but may not include an antiferroelectric material. In various example embodiments, the first dielectric layer 161d and the third dielectric layer 165d may include the same material. For example, the first dielectric layer 161d and the third dielectric layer 165d may include an antiferroelectric material.

[0053] The plurality of ferroelectric material layers 163_1 may include, for example, HfO 2 The plurality of antiferroelectric material layers 163_3 may include, for example, ZrO 2 .

[0054] In various example embodiments, the second dielectric layer 163d may have a structure in which a plurality of ferroelectric material layers 163_1 and a plurality of antiferroelectric material layers 163_3 are alternately stacked. For example, the first dielectric layer 161d may include a ZrO 2 and a single layer of silicon dopant DP4, the third dielectric layer 165d may include HfO 2 and a single layer of silicon dopant DP4, the second dielectric layer 163d may include a plurality of layers including HfO 2 The plurality of ferroelectric material layers 163_1 and ZrO 2 Multiple antiferroelectric material layers 163_3 are stacked alternately.

[0055] In various example embodiments, the thickness of the dielectric layer structure 160dt may be about to about In various example embodiments, the thickness of the first dielectric layer 161dt and the thickness of the third dielectric layer 165dt may be within a range of about 100 Å to 200 Å. to about within the range.

[0056] In various example embodiments, the thickness 163_1t of the plurality of ferroelectric material layers 163_1 and the thickness 163_3t of the plurality of antiferroelectric material layers 163_3 may be about to about In various example embodiments, the thickness 163_1t of the plurality of ferroelectric material layers 163_1 may be the same as the thickness 163_3t of the plurality of antiferroelectric material layers 163_3. For example, each of the thickness 163_1t of the plurality of ferroelectric material layers 163_1 and the thickness 163_3t of the plurality of antiferroelectric material layers 163_3 may be approximately In various example embodiments, the thickness 163_1t of the plurality of ferroelectric material layers 163_1 may be different from the thickness 163_3t of the plurality of antiferroelectric material layers 163_3. For example, the thickness 163_1t of the plurality of ferroelectric material layers 163_1 may be approximately The thickness 163_3t of the plurality of antiferroelectric material layers 163_3 may be approximately

[0057] Reference Figure 8 , the semiconductor device 100e may have Figure 1 , Figure 2 and Figure 3 The configuration of the semiconductor device 100 shown in is basically the same or similar to the configuration, except that the dielectric layer structure 160e of the capacitor structure CPe includes any one of a ferroelectric material and an antiferroelectric material, a first dielectric layer 161e including a silicon dopant DP5, and a second dielectric layer 163e including a ferroelectric material and an antiferroelectric material (wherein the second dielectric layer 163e includes a plurality of ferroelectric material layers 163_1 and a plurality of antiferroelectric material layers 163_3).

[0058] In various example embodiments, the first dielectric layer 161e may include an antiferroelectric material. For example, the antiferroelectric material may include ZrO 2 .

[0059] The plurality of ferroelectric material layers 163_1 may include, for example, HfO 2 The plurality of antiferroelectric material layers 163_3 may include, for example, ZrO 2 .

[0060] In various example embodiments, the second dielectric layer 163e may have a structure in which a plurality of ferroelectric material layers 163_1 and a plurality of antiferroelectric material layers 163_3 are alternately stacked. For example, the first dielectric layer 161e may include a ZrO 2 and a single layer of silicon dopant DP5, the second dielectric layer 163e may include a plurality of layers including HfO 2 The plurality of ferroelectric material layers 163_1 and ZrO 2 Multiple antiferroelectric material layers 163_3 are stacked alternately.

[0061] Although Figure 8It is shown that the first dielectric layer 161e including the silicon dopant is formed only between the second dielectric layer 163e and the lower electrode LEe, but various exemplary embodiments of the inventive concept are not limited thereto. For example, the dielectric layer including the silicon dopant may be formed only between the second dielectric layer 163e and the upper electrode UEe, and may not be formed between the second dielectric layer 163e and the lower electrode LEe.

[0062] Fig. 9 2 is a layout diagram schematically illustrating components of a semiconductor device according to various example embodiments. Fig.10 is along Fig. 9 A cross-sectional view taken along line BB'. Fig.11 yes Fig.10 An enlarged cross-sectional view of area EX'. Fig.12 yes Fig.11 An enlarged cross-sectional view of area EX" is shown.

[0063] Reference Fig. 9 , Fig.10 , Fig.11 and Fig.12 , the semiconductor device 200 may include a cell array structure CS including a memory cell region MCR and a connection region CON. The memory cell region MCR may be a region in which a vertical channel structure NAND type memory cell array is formed. The connection region CON may be a region in which a rising end portion EP for electrical connection between a memory cell array formed in the memory cell region MCR and a peripheral circuit region (not shown) is arranged.

[0064] The substrate 201 may include semiconductor elements such as Si and Ge or compound semiconductors such as SiC, GaAs, InAs, and InP. However, example embodiments are not limited thereto. The substrate 201 may be provided as a bulk wafer or a wafer on which an epitaxial layer is formed. In other example embodiments, the substrate 201 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0065] The gate stack GS may extend on the substrate 201 in a first horizontal direction (X direction) and a second horizontal direction (Y direction) parallel to the top surface of the substrate 201. The gate stack GS may include a plurality of conductive lines 230 and a plurality of insulating layers 240. The plurality of conductive lines 230 and the plurality of insulating layers 240 may be alternately stacked in a vertical direction (Z direction) perpendicular to the top surface of the substrate 201. An upper insulating layer 250 may be disposed at the uppermost end of the gate stack GS.

[0066] Each of the plurality of conductive lines 230 may include a buried conductive layer 232 and an insulating liner 234 surrounding the top surface, bottom surface, and side surface of the buried conductive layer 232. The buried conductive layer 232 may include, for example, a metal (such as tungsten), a metal silicide (such as tungsten silicide), doped polysilicon, or a combination thereof. However, example embodiments are not limited thereto. In various example embodiments, the insulating liner 234 may include a high-k dielectric material (such as aluminum oxide).

[0067] The plurality of conductive lines 230 may correspond to ground selection lines, word lines WL, and at least one string selection line SSL constituting a memory cell string. For example, the bottom conductive line 230 may be used as a ground selection line, the top conductive line 230 may be used as a string selection line SSL, and the remaining conductive lines 230 except the top conductive line 230 and the bottom conductive line 230 may be used as word lines WL.

[0068] Each of the plurality of word line cuts 270 may extend in a first horizontal direction (X direction) within the word line cut opening WLH. The word line cuts 270 may include an insulating material. The gate stack GS arranged between adjacent word line cuts 270 may constitute a block, and the adjacent word line cuts 170 may limit the width of the gate stack GS in a second horizontal direction (Y direction). A plurality of common source regions CSR may be formed in the substrate 201. The plurality of common source regions CSR may include an impurity region doped with impurities at a high concentration. The word line cuts 270 may have a tapered shape in which the width in the horizontal direction narrows from the bottom surface of the upper insulating layer 250 to the top surface of the substrate 201 in the vertical direction (Z direction).

[0069] A plurality of channel structures 260 may extend from the top surface of the substrate 201 in the vertical direction (Z direction) through the conductive line 230 in the memory cell region MCR. The plurality of channel structures 260 may be arranged to be spaced apart from each other at predetermined intervals in the first horizontal direction (X direction) and the second horizontal direction (Y direction). The plurality of channel structures 260 may be arranged in a zigzag shape or a staggered shape.

[0070] A plurality of channel structures 260 may extend in a vertical direction (Z direction) within a channel hole 260H penetrating the gate stack GS. Each of the plurality of channel structures 260 may include a blocking insulating layer 261 arranged along an inner sidewall of the channel hole 260H, a charge storage layer 263 arranged along an inner sidewall of the blocking insulating layer 261, a channel layer 265 arranged along an inner sidewall of the charge storage layer 263, a buried insulating layer 267 filling a central portion of the channel hole 260H, and a pad pattern 269 arranged to cover a top surface of the buried insulating layer 267.

[0071] Each of the plurality of channel structures 260 may be in contact with the substrate 201. In various example embodiments, the channel layer 265 may be disposed in contact with the top surface of the substrate 201 at the bottom of the channel hole 260H.

[0072] The blocking insulating layer 261 may cover all inner sidewalls of the channel hole 260H. In various example embodiments, the uppermost surface of the blocking insulating layer 261 may have a vertical level higher than the uppermost surface of the charge storage layer 263 and the uppermost surface of the channel layer 265 in the vertical direction (Z direction). That is, the outer sidewall of the blocking insulating layer 261 may be arranged to contact the plurality of conductive lines 230, and the inner sidewall of the blocking insulating layer 261 may be arranged to contact the charge storage layer 263 and the pad pattern 269. The blocking insulating layer 261 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. In various example embodiments, the blocking insulating layer 261 may include a high-k dielectric material.

[0073] The charge storage layer 263 may cover most of the inner sidewall of the blocking insulating layer 261. For example, the charge storage layer (263) may cover the rest of the inner sidewall of the blocking insulating layer 261 except for the upper end portion of the inner sidewall of the blocking insulating layer 261.

[0074] The charge storage layer 263 may include a first dielectric layer 263a, a second dielectric layer 263b, and a third dielectric layer 263c. The first dielectric layer 263a may contact the inner sidewall of the blocking insulating layer 261, the third dielectric layer 263c may contact the sidewall of the channel layer 265, and the second dielectric layer 263b may be arranged between the first dielectric layer 263a and the third dielectric layer 263c.

[0075] The charge storage layer 263 may be Figures 1 to 3 The dielectric layer structure 160 shown in FIG. 1 is substantially the same or similar. That is, the first dielectric layer 263a, the second dielectric layer 263b and the third dielectric layer 263c have the same dielectric layers as those in FIG. Figures 1 to 3 The first dielectric layer 161, the second dielectric layer 163, and the third dielectric layer 165 shown in the figure have substantially the same or similar structures and may include substantially the same or similar materials. For example, the first dielectric layer 263a, the second dielectric layer 263b, and the third dielectric layer 263c may include the same ferroelectric material and the same antiferroelectric material, but the first dielectric layer 263a and the third dielectric layer 263c may also include silicon dopants.

[0076] However, various example embodiments according to the inventive concept are not limited thereto, and the charge storage layer 263 may have Figures 4 to 8The dielectric layer structures 160a, 160b, 160c, 160d, 160e and 160f shown in FIG. 1 are substantially the same or similar structures.

[0077] The channel layer 265 may cover all inner sidewalls of the charge storage layer 263. In various example embodiments, the channel layer 265 may be formed in a ring shape surrounding the buried insulating layer 267 in the channel hole 260H, but example embodiments are not limited thereto. The channel layer 265 may include a semiconductor material layer. For example, the channel layer 265 may include an undoped polysilicon (Si) layer or a polysilicon (Si) layer including p-type or n-type impurities.

[0078] The buried insulating layer 267 may fill the channel hole 260H and may be disposed in a central portion of the channel hole 260H. The buried insulating layer 267 may extend in a vertical direction (Z direction). The buried insulating layer 267 may include silicon oxide or a low-k dielectric material. However, example embodiments are not limited thereto.

[0079] The pad pattern 269 fills an upper portion of the channel hole 260H and may be disposed on the buried insulating layer 267. The pad pattern 269 may include, for example, polysilicon containing p-type or n-type impurities.

[0080] The outer sidewalls of the pad pattern 269 and the outer sidewalls of the charge storage layer 263 may be coplanar and may contact the inner sidewalls of the blocking insulating layer 261 .

[0081] In the connection region CON, the rising end portion EP and the cover insulating layer 220 covering the rising end portion EP may be disposed at the end of the conductive line 230. The rising end portion EP of the conductive line 230 may have an increased thickness compared to other portions of the conductive line 230. That is, the rising end portion EP may have a top surface located at a higher vertical level than other portions of the conductive line 230, but example embodiments are not limited thereto.

[0082] In the connection region CON, the plurality of conductive lines 230 may extend to have a shorter length in the first horizontal direction (X direction) as they are farther in the vertical direction (Z direction) from the top surface of the substrate 201. That is, the plurality of conductive lines 230 may have a stepped structure in the connection region CON.

[0083] In the connection region CON, the contact plug CNT may penetrate the capping insulating layer 220 and may be connected to the rising end portion EP of the conductive line 230. The contact plug CNT may have a tapered column shape having a width narrowing from an upper region to a lower region in a vertical direction (Z direction).

[0084] Although Figures 9 to 12Although not shown in the figure, a plurality of dummy channel structures extending in the vertical direction (Z direction) through the gate stack GS may be arranged in the connection region CON. The dummy channel structures may reduce or prevent bending or warping of the gate stack GS in the manufacturing process of the semiconductor device 200, and may provide improved structural stability.

[0085] The bit line contact BLC may penetrate the upper insulating layer 250 to contact the pad pattern 269 of the channel structure 260 , and the bit line BL contacting the bit line contact BLC may extend in the second horizontal direction (Y direction) on the upper insulating layer 250 .

[0086] In the connection region CON, the conductive line ML may be formed on the upper insulating layer 250. Figures 9 to 12 Although not shown in FIG. 2 , an upper supporting layer may be further formed between the upper insulating layer 250 and the bit line BL and between the upper insulating layer 250 and the conductive line ML.

[0087] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F , Figure 13G and Fig.13H is a cross-sectional view illustrating a method of manufacturing the semiconductor device 100 according to various example embodiments.

[0088] Reference Fig.13A A substrate 110 is provided, in which a plurality of active regions AC are defined by a device isolation layer 112, and a lower structure 120 may be formed on the provided substrate 110, the lower structure 120 including a plurality of insulating structures 122 and a plurality of conductive regions 124 penetrating the plurality of insulating structures 122 and connected to each of the active regions AC. Next, an insulating layer 126 covering the lower structure 120 may be formed.

[0089] The insulating layer 126 may be used as an etch stop layer in the manufacturing process of the semiconductor device 100. The insulating layer 126 may include an insulating material having an etch selectivity relative to the plurality of insulating structures 122. In various example embodiments, the insulating layer 126 may include a silicon nitride (SiN) layer, a silicon carbon nitride (SiCN) layer, a silicon boron nitride (SiBN) layer, or a combination thereof. However, example embodiments are not limited thereto.

[0090] Reference Fig. 13B , a mold structure MST may be formed on the insulating layer 126. The mold structure MST may include a first mold layer 132, a lower support layer 142, a second mold layer 134, and an upper support layer 144 sequentially stacked on the insulating layer 126. Each of the first mold layer 132 and the second mold layer 134 may include a mold layer including ammonium fluoride (NH4 F), hydrofluoric acid (HF) and water etchants have a relatively high etching rate. In various example embodiments, each of the first mold layer 132 and the second mold layer 134 may include an oxide layer, a nitride layer, or a combination thereof. For example, the first mold layer 132 may be made of a borophosphosilicate glass (BPSG) layer, and the second mold layer 134 may include a multi-insulating layer in which relatively thin silicon oxide layers and silicon nitride layers are alternately stacked multiple times, or a silicon nitride layer. However, the constituent materials of the first mold layer 132 and the second mold layer 134 are not limited thereto.

[0091] The lower support member 142 and the upper support member 144 may include a silicon nitride (SiN) layer, a silicon carbon nitride (SiCN) layer, a silicon boron nitride (SiBN) layer, or a combination thereof. However, example embodiments are not limited thereto. In various example embodiments, the lower support member 142 and the upper support member 144 may include the same material. In some other example embodiments, the lower support member 142 and the upper support member 144 may include materials different from each other.

[0092] Reference Fig. 13C ,exist Fig. 13B After forming a mask pattern MP on the mold structure MST in the resultant, a mold structure pattern MSP having a plurality of holes BH may be formed by etching the mold structure MST using the mask pattern MP as an etching mask and using the insulating layer 126 as an etching stop layer. The mold structure pattern MSP may include a first mold pattern 132P, a lower support 142P, a second mold pattern 134P, and an upper support 144P.

[0093] The mask pattern MP may include a nitride layer, an oxide layer, a polysilicon layer, a photoresist layer, or a combination thereof. However, example embodiments are not limited thereto.

[0094] The process of forming the plurality of holes BH may further include etching the mold structure MST and wet-treating the etched mold structure MST. During the wet-treating process, a portion of the insulating layer 126 may be etched to obtain an insulating pattern 126P having a plurality of openings 126H exposing the plurality of conductive regions 124. The wet-treating process may use, for example, an etchant including a diluted sulfuric acid peroxide (DSP) solution, but example embodiments are not limited thereto.

[0095] In the mold structure pattern MSP, a plurality of holes 142H constituting a portion of the plurality of holes BH may be formed in the lower support 142P, and a plurality of holes 144H constituting a portion of the plurality of holes BH may be formed in the upper support 144P.

[0096] Reference Fig.13D , in from Fig. 13CAfter removing the mask pattern MP as a result of the removal of the mask pattern MP, the lower electrodes LE filling the plurality of holes BH may be formed.

[0097] In order to form the lower electrode LE, a conductive layer covering the top surface of the upper support 144P while filling the plurality of holes BH may be formed. The process of forming the conductive layer may include, for example, CVD, PECVD, metal organic CVD (MOCVD), or atomic layer deposition (ALD) processes. However, example embodiments are not limited thereto. After forming the conductive layer, a portion of the conductive layer may be removed using an etch-back process or a chemical mechanical polishing (CMP) process to expose the top surface of the upper support 144P.

[0098] Reference Fig.13E , in from Fig.13D After removing a portion of the upper support 144P to form a plurality of upper holes UH as a result of removing the portion of the lower support 142P exposed through the plurality of upper holes UH to form a plurality of lower holes LH, the second mold pattern 134P may be removed through the plurality of upper holes UH. Next, after removing a portion of the lower support 142P exposed through the plurality of upper holes UH to form a plurality of lower holes LH, the first mold pattern 132P may be removed through the plurality of lower holes LH. Each of the plurality of upper holes UH and each of the plurality of lower holes LH may be connected to each other, and the top surface of the insulating pattern 126P may be exposed through the plurality of upper holes UH and the plurality of lower holes LH. In addition, the first mold pattern 132P and the second mold pattern 134P may be removed so that the sidewalls of the plurality of lower electrodes LE may be exposed.

[0099] In various example embodiments, the second mold pattern 134P and the first mold pattern 132P may be removed in a wet manner. The wet removal process may use, for example, a material including ammonium fluoride (NH 4 F), an etchant of hydrofluoric acid (HF), and water, but example embodiments are not limited thereto.

[0100] Reference Fig.13F , a dielectric material layer 160S may be formed to cover the sidewalls of the plurality of exposed lower electrodes LE, some surfaces of the lower support 142P and the upper support 144P, and some surfaces of the insulating pattern 126P. The dielectric material layer 160S may be formed by using a CVD, MOCVD, PVD, or ALD process. However, example embodiments are not limited thereto. In various example embodiments, the dielectric material layer 160S may include a single layer including a ferroelectric material (such as HfO 2 ) and antiferroelectric materials (such as ZrO 2 ). In various example embodiments, the dielectric material layer 160S may be formed by alternately stacking ferroelectric material layers and antiferroelectric material layers. In this case, when performing the later reference FIG. 13E to FIG. 13G The process described can produce Figure 7 The semiconductor device 100d or Figure 8 The semiconductor device 100e is shown in FIG.

[0101] In various example embodiments, when executing reference Fig.13E After the described processes, a first silicon layer 171 (see FIG. 1 ) may be formed to cover sidewalls of the plurality of exposed lower electrodes LE, some surfaces of the lower support 142P and the upper support 144P, and some surfaces of the insulating pattern 126P. Figure 6 ), a dielectric material layer 160S may be formed, and a second silicon layer 173 covering the dielectric material layer 160S may be formed (see Figure 6 ), as referenced Fig.13F In this case, the later reference may be omitted. Figure 13G The implantation process of the silicon dopant described above, and after forming the second silicon layer 173, an annealing process and a subsequent step may be performed. Fig.13H The process of forming the upper electrode UE is described to manufacture Figure 6 The semiconductor device 100c is shown in FIG.

[0102] Reference Figure 13G , silicon dopants may be implanted into the dielectric material layer 160S (see Fig.13F ) of the region adjacent to the lower electrode LE and the dielectric material layer 160S (see Fig.13F ) of the dielectric material layer 160S adjacent to the exposed surface. The silicon dopant may be, for example, Si. After performing the implantation process, the dielectric material layer 160S (see Fig.13F ) including the silicon dopant and adjacent to the lower electrode LE may be defined as a first dielectric layer 161, a dielectric material layer 160S (see Fig.13F ) including a silicon dopant and a dielectric material layer 160S (see Fig.13F ) can be defined as a third dielectric layer 165, a dielectric material layer 160S (see Fig.13F ) where the silicon dopant is not implanted can be defined as a second dielectric layer 163.

[0103] In various example embodiments, when executing reference Fig.13E After the process described above, silicon dopants are implanted on the exposed surface of the lower electrode LE, as shown in FIG. Figure 13G The dielectric material layer 160S is formed, and the reference Figure 13G In this case, the implantation process of the silicon dopant described in the following can be performed. Fig.13H The process described is to manufacture Figure 3 The semiconductor device 100a is shown in FIG.

[0104] In various example embodiments, when executing reference Fig.13E After the process described above, silicon dopants are implanted on the exposed surface of the lower electrode LE, as shown in FIG. Figure 13G The dielectric material layer 160S is formed and the reference Figure 13G In this case, the implantation process of the silicon dopant described in the following can be performed. Fig.13H The process described is to manufacture Figure 4 The semiconductor device 100b shown in FIG.

[0105] Reference Fig.13H , an upper electrode UE covering the dielectric layer structure 160 may be formed. In various example embodiments, the upper electrode UE may be formed using a CVD, MOCVD, PVD, or ALD process. However, example embodiments are not limited thereto.

[0106] Next, an annealing process of the first dielectric layer 161, the second dielectric layer 163, and the third dielectric layer 165 may be performed. In various example embodiments, the annealing process may be performed at a temperature of about 200° C. to about 700° C. The crystallinity of each of the first dielectric layer 161, the second dielectric layer 163, and the third dielectric layer 165 may be improved by the annealing process. In addition, since the second dielectric layer 163 (which includes a ferroelectric material and an antiferroelectric material but does not include a silicon dopant) is separated from the lower electrode LE and the upper electrode UE and is located between the first dielectric layer 161 and the third dielectric layer 165, during the annealing process, the formation of a secondary phase material such as zirconium silicide at the interface where the dielectric layer (which does not include a silicon dopant) and the lower electrode LE and the upper electrode UE contact each other may be reduced or prevented.

[0107] The annealing process may be performed to produce Figure 1 , Figure 2 and Figure 3 The semiconductor device 100 is shown in FIG.

[0108] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but the freedom of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween in increments such as 0.1%.

[0109] While the inventive concept has been particularly shown and described with reference to various example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0110] This application is based on and claims the priority benefit of Korean Patent Application No. 10-2023-0162718 filed in the Korean Intellectual Property Office on November 21, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Lower electrode; an upper electrode on the lower electrode; as well as a dielectric layer structure between the lower electrode and the upper electrode; as well as The dielectric layer structure comprises a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer comprise antiferroelectric materials, and wherein the antiferroelectric materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are of the same material type, and Silicon dopants are included in a region adjacent to an interface between the first dielectric layer and the lower electrode and in a region adjacent to an interface between the third dielectric layer and the upper electrode. 2 . The semiconductor device according to claim 1 , wherein each of an atomic concentration of the silicon dopant of the first dielectric layer and an atomic concentration of the silicon dopant of the third dielectric layer is in a range of 1 atomic % to 10 atomic %.

3. The semiconductor device according to claim 1, wherein the thickness of the dielectric layer structure is to In the range of to within the range. 4 . The semiconductor device according to claim 3 , wherein the thickness of the first dielectric layer is the same as the thickness of the third dielectric layer. 5 . The semiconductor device according to claim 3 , wherein the thickness of the first dielectric layer is different from the thickness of the third dielectric layer. 6 . The semiconductor device of claim 1 , wherein the silicon dopant is present in the first dielectric layer and in the third dielectric layer.

7. The semiconductor device according to claim 1, wherein the silicon dopant is present in at least a portion of the lower electrode adjacent to an interface between the first dielectric layer and the lower electrode, and The silicon dopant is present in at least a portion of the upper electrode adjacent to an interface between the third dielectric layer and the upper electrode.

8. The semiconductor device of claim 1 , wherein the silicon dopant is present in the first dielectric layer, in the third dielectric layer, in at least a portion of the lower electrode adjacent to an interface between the first dielectric layer and the lower electrode, and in at least a portion of the upper electrode adjacent to an interface between the third dielectric layer and the upper electrode.

9. The semiconductor device according to claim 1, wherein the silicon dopant is present at an interface between the first dielectric layer and the lower electrode, and The silicon dopant is present at an interface between the third dielectric layer and the upper electrode.

10. A semiconductor device comprising: Lower electrode; an upper electrode on the lower electrode; as well as a dielectric layer structure between the lower electrode and the upper electrode, and The dielectric layer structure comprises a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode, The second dielectric layer comprises A plurality of ferroelectric material layers and a plurality of antiferroelectric material layers are alternately stacked, and A silicon dopant is included in at least one of a region adjacent to an interface between the first dielectric layer and the lower electrode and a region adjacent to an interface between the third dielectric layer and the upper electrode. 11 . The semiconductor device according to claim 10 , wherein one of the first dielectric layer and the third dielectric layer comprises an antiferroelectric material, and the other of the first dielectric layer and the third dielectric layer comprises a ferroelectric material. 12 . The semiconductor device of claim 11 , wherein the silicon dopant is present in at least one of the third dielectric layer and the first dielectric layer including an antiferroelectric material. 13 . The semiconductor device according to claim 11 , wherein the silicon dopant is present in at least one of the interface between the first dielectric layer and the lower electrode and the interface between the third dielectric layer and the upper electrode. 14 . The semiconductor device according to claim 10 , wherein each of the first dielectric layer and the third dielectric layer comprises an antiferroelectric material. 15 . The semiconductor device of claim 14 , wherein the silicon dopant is present in each of the first dielectric layer and the third dielectric layer. 16 . The semiconductor device of claim 14 , wherein the silicon dopant is present at an interface between the first dielectric layer and the lower electrode and at an interface between the third dielectric layer and the upper electrode.

17. The semiconductor device according to claim 10, wherein the thickness of the dielectric layer structure is to within the scope of The thickness of each of the plurality of ferroelectric material layers and the thickness of each of the plurality of antiferroelectric material layers are within a range of to within the range.

18. The semiconductor device according to claim 10, wherein each of the first dielectric layer and the second dielectric layer has to The thickness is within the range of .

19. A semiconductor device comprising: a substrate having a plurality of active regions defined by a device isolation layer; a lower structure on the substrate and connected to the plurality of active regions; as well as a capacitor structure on and connected to the substructure, The capacitor structure comprises Lower electrode, an upper electrode on the lower electrode, and a dielectric layer structure between the lower electrode and the upper electrode, The dielectric layer structure comprises a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode, wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises at least one of HfO2 and ZrO2, and Silicon dopants are included inside the first dielectric layer and inside the third dielectric layer. 20 . The semiconductor device of claim 19 , wherein each of an atomic concentration of the silicon dopant of the first dielectric layer and an atomic concentration of the silicon dopant of the third dielectric layer is in a range of 1 atomic % to 10 atomic %.

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