Vertical heterojunction bipolar transistor

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure comprises: a sub-collector region; a collector region over the sub-collector region; an internal base over the collector region; an emitter over the internal base region; and an outer base on the inner base and adjacent to the emitter, where the collector region includes an undercut profile including a lower inwardly tapering sidewall and an upper inwardly tapering sidewall extending to a narrow portion between the sub-collector region and the base region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to vertical heterojunction bipolar transistors and methods of fabrication. Background Art

[0002] A heterojunction bipolar transistor is a bipolar junction transistor that uses different semiconductor materials in the emitter and base regions to form a heterojunction. Heterojunction bipolar transistors can handle very high frequency signals up to several hundred GHz. Heterojunction bipolar transistors can be used in modern ultrafast circuits including radio frequency (RF) systems, and in applications requiring high power efficiency, such as RF power amplifiers in cellular phones. Summary of the invention

[0003] In one aspect of the present disclosure, a structure includes: a subcollector region; a collector region located above the subcollector region; an internal base located above the collector region; an emitter located above the internal base region; and an external base located on the internal base and adjacent to the emitter, wherein the collector region includes an undercut profile including a lower inwardly tapered sidewall and an upper inwardly tapered sidewall extending to a narrow portion between the subcollector region and the base region.

[0004] In one aspect of the present disclosure, a structure includes: a subcollector region comprising a first semiconductor material; an intrinsic base; an emitter; an extrinsic base located on the intrinsic base and adjacent to the emitter; and a collector including an undercut profile including a lower inwardly tapered sidewall and an upper inwardly tapered sidewall extending to a narrow portion between the subcollector region and the intrinsic base.

[0005] In one aspect of the present disclosure, a method includes: forming a subcollector region; forming a collector above the subcollector region; forming an intrinsic base above the collector region; forming an emitter above the intrinsic base region; forming an extrinsic base on and adjacent to the intrinsic base; and forming an undercut in the collector region, the undercut including a lower inwardly tapered sidewall and an upper inwardly tapered sidewall extending to a narrow portion between the subcollector region and the extrinsic base. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0007] Figure 1 The structure and corresponding manufacturing process according to some aspects of the present disclosure are shown.

[0008] Figure 2Structures and corresponding manufacturing processes according to additional aspects of the present disclosure are shown.

[0009] Figure 3 The structure and corresponding manufacturing process according to other aspects of the present disclosure are shown.

[0010] Figures 4A-4F Various collector profiles are shown in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION

[0011] The present disclosure relates to semiconductor structures, and more particularly, to vertical heterojunction bipolar transistors and methods of fabrication. More particularly, the present disclosure relates to vertical heterojunction bipolar transistors and methods of fabrication having sidewall undercuts (e.g., undercut profiles). Advantageously, the present disclosure provides the ability to control and modify recessed structures to achieve high performance devices.

[0012] In an embodiment, the high-performance device described herein may be a vertical heterojunction bipolar transistor with different collector profiles. The vertical heterojunction bipolar transistor may include, for example, an N+Si / SiGe sub-collector, an n-type Si collector, a p-SiGe base, and an n+Si emitter; however, other materials are also considered herein. For example, although the high-performance device is described with respect to an NPN transistor structure, it should be understood by those skilled in the art that by reversing the doping scheme, the high-performance device may also be a PNP transistor structure. The undercut profile may be provided in the collector between the base and the sub-collector. The lateral width of the collector is smaller than the sub-collector and the base.

[0013] The vertical heterojunction bipolar transistor of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer-scale dimensions. Methods (i.e., techniques) for manufacturing the vertical heterojunction bipolar transistor of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on the top of the wafer by means of a photolithography process. Specifically, the manufacture of the vertical heterojunction bipolar transistor uses three basic building blocks: (i) depositing or growing a material film on a substrate; (ii) applying a patterned mask on the top of the film by photolithography imaging; and (iii) selectively etching the film to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0014] Figure 1 The structure and corresponding manufacturing process according to some aspects of the present disclosure are shown. Specifically, Figure 1The structure 10 shows a collector 14 having an undercut region (e.g., outline) 14a. The collector 14 may be disposed between the sub-collectors 16, 18, the extrinsic base 20, and the emitter 22. The undercut region 14a may be filled with an interlayer dielectric material 24 formed by a conventional deposition process (e.g., chemical vapor deposition (CVD)). An optional deep trench isolation structure 25 may be provided to isolate the device.

[0015] More specifically, in Figure 1 In the structure 10, the subcollectors 16 and 18 may preferably include Si material, and more preferably include N+ doped Si material. For example, the subcollector 16 may be doped with phosphorus (e.g., SiP). The subcollector 16 may also be a single crystalline semiconductor material having a suitable crystal orientation (e.g., (100), (110), (111) or (001) crystal orientation). Those skilled in the art should understand that the subcollector 16 may be formed on a p-type substrate 17 as is well known in the art, so that no further explanation is required to fully understand the present invention.

[0016] The semiconductor material 18 can be another type of semiconductor material, such as SiGe. In a preferred embodiment, the semiconductor material 18 can be an N+SiGe material epitaxially grown on the subcollector 16. For example, as an example, the SiGe material can be in-situ doped with phosphorus (SiGeP). Alternatively, the SiGe material can be implanted or doped by outward diffusion from the surrounding area. In an embodiment, the subcollector 16 may include N-type Si as well as N-type SiGe. That is, the entire subcollector region can be SiGe, or it can be just a thin layer of SiGe with N-type Si above and below. It should also be recognized that, as described herein, at least one layer of N-type SiGe that may be located in the collector or subcollector region will be used as an etch stop layer for the undercut recess (e.g., the undercut profile 14a described herein).

[0017] The collector 14 may be the same material as the semiconductor substrate 16. For example, the collector 14 may be an n-doped Si material. In an embodiment, the lateral width of the collector 14 is less than the length (or less than the width, depending on the perspective) of the sub-collector material 18 and the intrinsic base 26 or the extrinsic base 20, and the undercut profile 14a is located between the sub-collector 18 and the intrinsic base 26 or the extrinsic base 20.

[0018] The undercut profile (e.g., region) 14a of the collector 14 may include a narrow region or undercut area, e.g., a narrow profile portion, which is filled with and surrounded by the interlayer dielectric material 24. The interlayer dielectric material 24 may also be located above the semiconductor substrates 16, 18 and surround the collector 14, the intrinsic base 26, the extrinsic base 20, and the emitter 22. In an embodiment, the interlayer dielectric material 24 may be an oxide, a nitride, or a combination thereof.

[0019] In this embodiment, the undercut region 14a may include a narrow middle portion and wider upper and lower portions. In a more specific embodiment, the undercut region 14a may include an inwardly tapered sidewall profile from the top to the middle portion and from the bottom to the middle portion, resulting in the middle portion having the narrowest cross-section along the vertical axis; however, as described with respect to Figures 4A-4F The various embodiments shown are further described, and other configurations are also contemplated herein. The undercut region 14a can be formed by etching the material of the collector 14 by wet or dry etching using selective chemistry. It will be appreciated by those skilled in the art that the term "tapered" can be applied to both faceted and rounded recessed shapes or combinations thereof.

[0020] Still reference Figure 1 , an internal base 26 may be formed above the collector 14. In an embodiment, the internal base 26 may be a p-doped semiconductor material. In a more specific embodiment, the internal base 26 may be SiGe. For example, the internal base 26 may be epitaxially grown from the collector 14 using an in-situ p-type dopant, followed by a conventional patterning process such as photolithography and etching (a reactive ion etching (RIE) process). In a preferred embodiment, the p-type dopant includes boron to produce SiGeB. The internal base 26 should be a different material from the collector 14 so that an undercut can be provided by a selective etching process.

[0021] The external base 20 may be formed above the internal base 26, around the side of the emitter 22, or on the side of the emitter 22. The emitter 22 may be formed on the internal base 26 and may be isolated from the external base 20 by a sidewall spacer 22a. The sidewall spacer 22a may be a nitride and / or oxide material formed by a conventional deposition process (e.g., CVD) and then subjected to an anisotropic etching process. The emitter 22 may include an n-doped semiconductor material. For example, the dopant may be phosphorus (producing SiP) or arsenic (producing SiAs). The emitter 22 may be formed by a conventional epitaxial growth process using an in-situ doping process as is known in the art. In an embodiment, the emitter 22 may be formed after the external base 20. For example, as is known in the art, the material of the emitter 22 may be deposited in a trench etched through the external base 20.

[0022] After the emitter 22 is formed, an extrinsic base 20 may be formed adjacent to the sides of the sidewall spacers 22a. In an embodiment, the extrinsic base 20 may be formed by a conventional epitaxial growth process using an in-situ doping process known in the art. The extrinsic base 20 may be epitaxially grown on the collector 14 using a p-type dopant. In a preferred embodiment, for example, the p-type dopant includes boron producing SiB or SiGeB. Other examples of suitable semiconductor materials for the collector 14, sub-collectors 16, 18, emitter 22, and base 20, 26 may be SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors, noting that selectivity should still exist for the collector 14.

[0023] Figure 1 Also shown are contacts 28 (e.g., wiring structures or interconnect structures) and silicide contacts 30. Contacts 28 and silicide contacts 30 may be in direct contact with subcollector 18, emitter 22, and extrinsic base 20. In an embodiment, contacts 28 may be formed through interlayer dielectric material 24 by conventional photolithography, etching, and deposition methods known to those skilled in the art.

[0024] For example, the resist formed above the interlayer dielectric material 24 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), is used to transfer the pattern from the photoresist layer to the interlayer dielectric material 24 to form one or more trenches in the interlayer dielectric material 24 through the openings of the resist. After the resist is removed by a conventional oxygen ashing process or other known strippers, a conductive material, such as W, Al, Cu with a TiN or TaN liner, can be deposited by any conventional deposition process, such as a CVD process. Any residual material on the surface of the insulator interlayer dielectric material 24 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0025] In addition, it should be understood by those skilled in the art that the silicide process begins by depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor device (e.g., subcollector 16, emitter 22, and extrinsic base 20). After the material is deposited, the structure is heated, allowing the transition metal to react with the exposed silicon (or other semiconductor materials described herein) in the active region of the semiconductor device (e.g., subcollector 16, emitter 22, and extrinsic base 20) to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 30 in the active region of the device.

[0026] Figure 2Another structure 10a according to additional aspects of the present disclosure is shown. Figure 2 In the structure 10a of FIG. 1 , the collector 14 includes an undercut region 14a surrounded by an air gap 15 formed in the interlayer dielectric material 24. The air gap 15 preferably extends to the sidewalls of the collector 14. In an embodiment, the air gap 15 can be formed by a conventional pinch-off process, as is known in the art, and the air gap is formed during the deposition process of the interlayer dielectric material 24. The remaining features of the structure 10a are similar to those of FIG. Figure 1 10, and therefore no further explanation is required to fully understand the present disclosure.

[0027] Figure 3 Another structure 10b is shown according to additional aspects of the present disclosure. Figure 3 In the structure 10b of FIG. 1 , the undercut region 14a includes a straight portion 14b and a tapered portion 14c. The tapered portion 14c includes an inwardly tapered profile from the top to the straight portion 14b (near the middle) and from the bottom to the straight portion 14b (near the middle). It should be understood by those skilled in the art that the recessed profile may include circular and / or asymmetric embodiments. In this embodiment and other embodiments described herein, the collector 14 and the undercut region 14a may be surrounded by an interlayer dielectric material 24 or an air gap formed in the interlayer dielectric material 24. The remaining features of the structure 10b are similar to those of FIG. Figure 1 The structure 10 of FIG. 10 is shown in FIG. 1 , so that no further explanation is needed to fully understand the present disclosure.

[0028] Figures 4A-4F Various profiles of collectors according to some aspects of the present disclosure are shown. For example, Figure 4A The collector 14 is shown having two recessed portions 14a, 14a1 separated along a vertical axis by a layer of semiconductor material 32. In an embodiment, the layer of semiconductor material 32 will extend across the wider portion of the collector 14. Additionally, in an embodiment, each of the recessed portions 14a, 14a1 includes inwardly tapered sidewalls as already described herein.

[0029] For about Figures 4A-4F In each of the described undercut profiles, the layer 32 of semiconductor material can be a semiconductor material that is selectively etched with respect to the semiconductor material of the collector 14. In an embodiment, the layer 32 of semiconductor material can be the same material as the semiconductor material used for the subcollector 18 and the extrinsic base 28. For example, the layer 32 of semiconductor material can be SiGe; and the collector 14 can be Si. Furthermore, it should be understood by those skilled in the art that by including one or more SiGe layers having a lower or higher percentage of Ge material, by varying the spacing, Ge percentage, or thickness of the layer 32, the undercut profile can be precisely adjusted to achieve any desired shape. For example, in Figure 4A In embodiments of the present invention, a higher percentage of Ge may be utilized to provide a desired profile.

[0030] Figure 4B The collector 14 is shown having a recessed portion 14a having inwardly tapered sidewalls, as indicated in structures 10, 10a, 10b. However, in this embodiment, the layer 32 of semiconductor material may extend through a narrow region of the collector 14 approximately at the center along the vertical axis. Furthermore, as should now be understood, Figure 4B The undercut profile 14a shown in the embodiment of can be precisely adjusted by providing a lower percentage of Ge to obtain the desired shape. In this way, a higher percentage of Ge will be used to obtain a wider area of ​​the undercut profile compared to a lower percentage of Ge in a narrower portion of the undercut profile.

[0031] Figure 4C and 4D A collector electrode 14 is shown having a plurality of recessed portions separated along a vertical axis by one or more layers 32 of semiconductor material. Figure 4C In FIG. 1 , the collector 14 comprises three recessed portions 14a, 14a1, 14a2, each of which is separated from each other by a layer 32 of semiconductor material along a vertical axis. Figure 4D , the collector 14 includes four recessed portions 14a, 14a1, 14a2, 14a3, each of which is separated from each other along the vertical axis by a layer of semiconductor material 32. It should be understood by those skilled in the art that the present disclosure may also consider more recessed portions (and corresponding layers of semiconductor material 32), or layers with different thicknesses, spacings and / or compositions.

[0032] Figure 4E and 4F The collector electrode 14 is shown having a plurality of recessed portions asymmetrically positioned along a vertical axis and separated in the vertical direction by a layer 32 of semiconductor material. Figure 4E and 4F In FIG. 1 , the undercut region 14a is smaller than the undercut region 14d1. Figure 4E In the embodiment, the undercut region 14a1 is closer to the external base 26, and in Figure 4F , the undercut region 14a1 is closer to the sub-collector 18. The spacing and positioning of the undercut regions 14a, 14a1 along the vertical axis can be adjusted by adjusting the position of the layer 32 of semiconductor material within the collector 14.

[0033] These structures can be exploited in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0034] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip is installed in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having surface interconnects or buried interconnects, or both surface interconnects and buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0035] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: sub-collector region; a collector region located above the sub-collector region; an intrinsic base located above the collector region; an emitter located above the intrinsic base region; as well as an external base located on the intrinsic base and adjacent to the emitter, The collector region includes an undercut profile, the undercut profile including a lower inwardly tapered sidewall and an upper inwardly tapered sidewall extending to a narrow portion between the sub-collector region and the base region.

2. The structure according to claim 1, wherein: The sub-collector region and the intrinsic base include a semiconductor material different from a semiconductor material of the collector.

3. The structure according to claim 2, wherein: The semiconductor material of the subcollector includes at least n-type SiGe, the intrinsic base includes p-type SiGe, and the collector includes n-type Si.

4. The structure according to claim 1, wherein: The undercut profile includes lower and upper inwardly tapered sidewalls extending to a narrow section between the subcollector region and the extrinsic base.

5. The structure according to claim 4, wherein: The narrow section includes a straight sidewall profile.

6. The structure of claim 4 further comprising a layer of semiconductor material extending across the narrow region of the collector and different from the semiconductor material of the collector region.

7. The structure according to claim 1, wherein: The undercut profile comprises two recessed portions separated along a vertical axis by a layer of semiconductor material different from the semiconductor material of the collector.

8. The structure according to claim 7, wherein: The layer of semiconductor material extends across a wider portion of the undercut profile of the collector.

9. The structure according to claim 7, wherein: The layer of semiconductor material is the same semiconductor material as the sub-collector.

10. The structure according to claim 1, wherein: The undercut profile includes a plurality of recessed portions.

11. The structure according to claim 10, wherein: Each of the plurality of recessed portions is separated along a vertical axis by a semiconductor material different from a semiconductor material of the collector.

12. The structure according to claim 10, wherein: Each of the plurality of recessed portions is asymmetrically positioned along the vertical axis.

13. The structure of claim 4 further comprising an air gap extending to the upper and lower inwardly tapered sidewalls and also surrounding the undercut profile.

14. A structure comprising: a sub-collector region comprising a first semiconductor material; Internal base; emitter; an external base located on the intrinsic base and adjacent to the emitter; as well as A collector includes an undercut profile including lower and upper inwardly tapered sidewalls extending to a narrow section between the sub-collector region and the intrinsic base.

15. The structure according to claim 14, wherein: The first semiconductor material comprises SiGe, the intrinsic base comprises p-type doped SiGe, the sub-collector region comprises n-type doped SiGe, and the semiconductor material of the collector comprises Si.

16. The structure of claim 14, wherein: The narrow section includes a straight sidewall profile.

17. The structure of claim 14, wherein: The undercut profile includes a plurality of recessed portions, each of the plurality of recessed portions being separated along a vertical axis by a layer of a semiconductor material different from a semiconductor material of the collector.

18. The structure of claim 14, further comprising an air gap surrounding the undercut profile.

19. The structure of claim 14, wherein: The sub-collector region includes both Si material and SiGe material, wherein the SiGe material is an etching stop layer.

20. A method comprising: forming a sub-collector region; forming a collector electrode above the sub-collector region; forming an intrinsic base above the collector region; forming an emitter over the intrinsic base region; forming an extrinsic base on the intrinsic base and adjacent to the emitter; as well as An undercut is formed in the collector region, the undercut including lower and upper inwardly tapered sidewalls extending to a narrow section between the sub-collector region and the extrinsic base.

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