Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface and a second surface; the device further comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is of a first conductive type and located on the first surface, the channel layer is of the first conductive type and located on the first surface, and the well region is of a second conductive type and located on the side, away from the first surface, of the first region and the channel layer; the gate structure is located on the first surface and covers at least part of the channel layer; the drain is located on the second surface; the source electrode is located on the first surface and covers at least part of the first area. The depletion type semiconductor device is in a conducting state in a normal state, negative voltage needs to be applied between the grid electrode and the source electrode to cut off a channel in a cut-off state, response can be made faster, current circulation can be controlled, conduction loss is small, and the depletion type semiconductor device is more suitable for a high-frequency circuit and a switching circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in the prior art is an enhancement-mode device, which is normally non-conductive. If it is conductive, a positive voltage needs to be applied between the gate and the source. However, the enhancement-mode device has a high conduction loss and a slow response speed. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the conduction loss of the semiconductor device and improve the response speed.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, the channel layer is set to the first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region and the channel layer away from the first surface;

[0007] A gate structure, located on the first surface and covering at least a portion of the channel layer;

[0008] a drain electrode, located on the second surface;

[0009] The source is located on the first surface and covers at least a portion of the first region.

[0010] Optionally, the thickness of the channel layer is smaller than the thickness of the first region.

[0011] Optionally, the ion concentration of the channel layer is less than the ion concentration of the first region.

[0012] Optionally, the semiconductor body further includes a second region, the second region is set to the second conductivity type and is located on the first surface; the second region is connected to the first region.

[0013] Optionally, the semiconductor body also includes a third region, which is set to the first conductivity type and is located on the first surface; the doping concentration of the third region is greater than the doping concentration of the semiconductor body, and the third region and the well region have no overlap in the orthographic projection of the semiconductor body.

[0014] Optionally, the gate structure includes a gate insulating layer and a gate;

[0015] The gate insulating layer is located on the first surface;

[0016] The gate is located on a side of the gate insulating layer away from the first surface.

[0017] Optionally, the semiconductor device further includes an interlayer insulating layer and a gate electrode;

[0018] The interlayer insulating layer is located on a side of the gate away from the gate insulating layer;

[0019] The interlayer insulating layer is provided with a first through hole and a second through hole;

[0020] The source electrode passes through the first through hole to reach the first region;

[0021] The gate electrode passes through the second through hole to reach the gate.

[0022] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0023] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0024] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first area and a channel layer, the first area and the channel layer are in contact with each other, the first area is set to a first conductivity type and is located on the first surface, the channel layer is set to the first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first area and the channel layer away from the first surface;

[0025] forming a gate structure on the first surface, wherein the gate structure covers at least a portion of the channel layer;

[0026] forming a drain electrode on the second surface;

[0027] A source electrode is formed on the first surface, and the source electrode covers at least a portion of the first region.

[0028] Optionally, providing a semiconductor body includes:

[0029] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other;

[0030] forming a first mask layer on the first surface, wherein the first mask layer is provided with a third through hole;

[0031] forming a transition well region on the first surface exposed by the third through hole, wherein the transition well region is set to a second conductivity type;

[0032] A transition channel region is formed on one side of the transition well region close to the first surface, and the transition channel region is set to be of a first conductivity type;

[0033] forming a second mask layer on at least one sidewall of the third through hole, wherein the material of the second mask layer is different from the material of the first mask layer;

[0034] A first region is formed on a side of the transition channel region away from the first surface exposed by the third through hole, the first region is set to be of a first conductivity type, the ion concentration of the first region is greater than the ion concentration of the transition channel region, and the transition channel region retained after the first region is formed serves as a channel layer;

[0035] removing the second mask layer;

[0036] The first mask layer is removed.

[0037] Optionally, forming a second mask layer on at least one sidewall of the third through hole includes:

[0038] forming a second mask layer on two oppositely disposed side walls of the third through hole;

[0039] After removing the first mask layer, the method further includes:

[0040] A second region is formed on the first surface, and the second region is set to a second conductivity type; the second region is connected to the first region and the transition well region; and the transition well region retained after forming the channel layer, the first region and the second region is used as a well region.

[0041] Optionally, after removing the first mask layer and before forming the second region on the first surface, the method further includes:

[0042] A third mask layer is formed on the first surface. The third mask layer is provided with a fourth through hole. The bottom of the fourth through hole exposes a portion of the first area.

[0043] Optionally, after removing the first mask layer, the method further includes:

[0044] forming a fourth mask layer on the first surface, wherein the fourth mask layer is provided with a fifth through hole;

[0045] A third region is formed on the first surface exposed by the fifth through hole. The third region is set to the first conductivity type. The doping concentration of the third region is greater than the doping concentration of the semiconductor body. The third region and the well region have no overlap in the orthographic projection on the semiconductor body.

[0046] Optionally, forming a gate structure on the first surface includes:

[0047] forming a gate insulating layer on the first surface;

[0048] A gate is formed on a side of the gate insulating layer away from the first surface, and the gate covers at least a portion of the channel layer.

[0049] Optionally, after forming a gate on a side of the gate insulating layer away from the first surface, the method further includes:

[0050] An interlayer insulating layer is formed on a side of the gate away from the gate insulating layer; the interlayer insulating layer is provided with a first through hole and a second through hole;

[0051] forming a gate electrode; the gate electrode passes through the second through hole to reach the gate;

[0052] Before forming a source electrode on the first surface, the method further comprises:

[0053] A first through hole is formed in the interlayer insulating layer, and the source electrode passes through the interlayer insulating layer to reach the first region.

[0054] Optionally, providing a semiconductor body includes:

[0055] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0056] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used for carrying the semiconductor device.

[0057] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0058] The power conversion circuit comprises a circuit board and at least one of the semiconductor devices mentioned above, and the semiconductor device is electrically connected to the circuit board.

[0059] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0060] The technical solution of the embodiment of the present invention is to set a channel layer of the opposite conductivity type to the well region on the side of the well region away from the second surface. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-type semiconductor device. Under normal conditions, it is in the on state, and in the off state, a negative gate-source voltage is required to cut off the channel. Compared with the enhancement-type semiconductor device, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the current flow, and is more suitable for high-frequency circuits and switching circuits.

[0061] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0063] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0064] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0065] Figure 3-Figure 4 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0066] Figure 5 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0067] Figure 6-Figure 20 It is a cross-sectional view corresponding to each step of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0070] Figure 1 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103, a first region 104 and a channel layer 105, the first region 104 and the channel layer 105 are in contact with each other, and the first region 104 is set to the first conductivity type and is located on the first surface 101, the channel layer 105 is set to the first conductivity type and is located on the first surface 101, the well region 103 is set to the second conductivity type and is located on a side of the first region 104 and the channel layer 105 away from the first surface 101; a gate structure 200, located on the first surface 101 and covering at least a portion of the channel layer 105; a source 400, located on the first surface 101 and covering at least a portion of the first region 104; and a drain 300, located on the second surface 102.

[0071] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0072] For example, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0073] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0074] The technical solution of the embodiment of the present invention is to set a channel layer 105 of the opposite conductivity type to the well region 103 on the side of the well region 103 away from the second surface 102. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-type semiconductor device. Under normal conditions, it is in the on state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared with the enhancement-type semiconductor device, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the current flow, and is more suitable for high-frequency circuits and switching circuits.

[0075] In other optional embodiments of the present invention, the thickness of the channel layer 105 is smaller than the thickness of the first region 104 .

[0076] Specifically, the thickness of the channel layer 105 does not need to be set too thick, and the thickness of the channel layer 105 is less than the thickness of the first region 104, which can meet the requirements of serving as a channel.

[0077] In other optional embodiments of the present invention, the ion concentration of the channel layer 105 is less than the ion concentration of the first region 104 .

[0078] Specifically, the ion implantation concentration of the channel layer 105 is 10 16 cm -3 -10 17 cm -3 The ion implantation concentration of the channel layer 105 is lower than the ion implantation concentration of the first region 104, which can reduce the manufacturing cost of the semiconductor device.

[0079] In other optional embodiments of the present invention, the semiconductor body 100 further includes a second region 106 , which is configured as a second conductivity type and is located on the first surface 101 ; the second region 106 is connected to the first region 104 .

[0080] The conductivity type of the second region 106 is the same as that of the well region 103 , and both are set to the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region, and its doping concentration is greater than that of the well region 103 , and can form a good ohmic contact with the source 400 .

[0081] In other optional embodiments of the present invention, the semiconductor body 100 further includes a third region 107, which is set to the first conductivity type and is located on the first surface 101; the doping concentration of the third region 107 is greater than the doping concentration of the semiconductor body 100, and the third region 107 and the well region 103 have no overlap in the orthographic projection of the semiconductor body 100. The provision of the third region 107 reduces the resistance of the junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the MOSFET device.

[0082] In other optional embodiments of the present invention, the gate structure 200 includes a gate insulating layer 201 and a gate 202 ; the gate insulating layer 201 is located on the first surface 101 ; and the gate 202 is located on a side of the gate insulating layer 201 away from the first surface 101 .

[0083] The gate insulating layer 201 may be a gate oxide layer, and the gate 202 may be made of polysilicon.

[0084] In other optional embodiments of the present invention, the semiconductor device also includes an interlayer insulating layer 500 and a gate electrode 600; the interlayer insulating layer 500 is located on the side of the gate 202 away from the gate insulating layer 201; the interlayer insulating layer 500 is provided with a first through hole 501 and a second through hole 502; the source 400 passes through the first through hole 501 to reach the first region 105; the gate electrode 600 passes through the second through hole 502 to reach the gate 202.

[0085] The interlayer insulating layer 500 is used to insulate the gate electrode 202 and the source electrode 400. The interlayer insulating layer 500 is provided with a first through hole 501, and the source electrode 400 passes through the interlayer insulating layer 500 to reach the first region 105. The interlayer insulating layer 500 is also provided with a second through hole 502, and the gate electrode 600 can pass through the second through hole 502 to directly connect with the gate electrode 202, so as to provide an electrical signal to the gate electrode 202.

[0086] In other optional embodiments of the present invention, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0087] The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0088] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0089] Figure 2 The flowchart of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention is shown in FIG.

[0090] like Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0091] S110. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body also comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, and the first region is set to a first conductivity type and is located on the first surface, the channel layer is set to the first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region and the channel layer away from the first surface.

[0092] refer to Figure 3 , a semiconductor body 100 is provided, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103, a first region 104 and a channel layer 105, the first region 104 and the channel layer 105 are in contact with each other, and the first region 104 is set to a first conductivity type and is located on the first surface 101, the channel layer 105 is set to the first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 and the channel layer 105 away from the first surface 101.

[0093] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0094] For example, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0095] In other optional embodiments of the present invention, the semiconductor body 100 further includes a second region 106, which is set to the second conductivity type and is located on the first surface 101; the second region 106 is connected to the first region 104. The conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region, and its doping concentration is greater than the doping concentration of the well region 103.

[0096] In other optional embodiments of the present invention, the semiconductor body 100 also includes a third region 107, which is set to the first conductivity type and is located on the first surface 101; the doping concentration of the third region 107 is greater than the doping concentration of the semiconductor body 100, and the third region 107 and the well region 103 have no overlap in the orthographic projection of the semiconductor body 100.

[0097] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0098] S120 , forming a gate structure on the first surface, wherein the gate structure covers at least a portion of the channel layer.

[0099] refer to Figure 4 A gate insulating layer 201 is formed on the first surface 101 of the semiconductor body 100 by a high temperature oxidation or deposition process. A gate 202 is formed on the gate insulating layer 201 by a polysilicon thin film deposition process. The gate insulating layer 201 and the gate 202 together constitute a gate structure 200 .

[0100] S130, forming a source electrode on the first surface, wherein the source electrode covers at least a portion of the first region.

[0101] refer to Figure 1An interlayer insulating layer 500 is formed above the gate structure 200 to insulate and isolate the gate 202. A first through hole 501 and a second through hole 502 are formed by etching the interlayer insulating layer 500. A metal is deposited on the first surface 101 of the semiconductor body 100 to form a source 400, and the source 400 reaches the first region 104 through the first through hole 501. The gate electrode 600 can be directly connected to the gate 202 through the second through hole 502.

[0102] S140, forming a drain on the second surface.

[0103] refer to Figure 1 , a drain 300 is formed on the second surface 102 of the semiconductor body 100 .

[0104] The technical solution of the embodiment of the present invention forms a channel layer 105 of the opposite conductivity type to the well region 103 on the side of the well region 103 away from the second surface 102. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-type semiconductor device. Under normal conditions, it is in the on state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared with the enhancement-type semiconductor device, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the current flow, and is more suitable for high-frequency circuits and switching circuits.

[0105] Figure 5 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the method for manufacturing the semiconductor device includes:

[0106] S210 , providing a semiconductor body, wherein the semiconductor body includes a first surface and a second surface that are oppositely disposed.

[0107] refer to Figure 6 , a semiconductor body 100 is provided, wherein the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. Figure 6 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0108] S211 , forming a first mask layer on the first surface, wherein the first mask layer is provided with a third through hole.

[0109] refer to Figure 7 , a hard mask (HM) process is applied to form a first mask layer 30 on the first surface 101 of the semiconductor body 100. SiO can also be deposited by plasma enhanced chemical vapor deposition (PECVD). 2 The first mask layer 30 is formed. The first mask layer 30 is patterned by photolithography. The photolithography process is an important step in the semiconductor device manufacturing process. In this step, a geometric structure is depicted on a photoresist layer by exposure and development, and then the pattern of the photoresist layer is transferred to the first mask layer 30 by an etching process to achieve patterning of the first mask layer 100. Figure 7 As shown, the third through hole 503 is formed by a photolithography process.

[0110] S212, forming a transition well region on the first surface exposed by the third through hole, wherein the transition well region is set to be of the second conductivity type.

[0111] refer to Figure 8 Based on the patterned first mask layer 30, second conductive type ion implantation is performed at the first surface 101 exposed by the third through hole 503 to form a transition well region 108. The transition well region 108 is a doped region formed by implanting second conductive type ions into the surface of the epitaxial layer 20 after forming the semiconductor epitaxial layer 20.

[0112] S213, forming a transition channel region on a side of the transition well region close to the first surface, wherein the transition channel region is set to be of the first conductivity type.

[0113] refer to Fig. 9 , first conductivity type ion implantation is performed in the first surface 101 of the transition well region 108 exposed near the third through hole 503 to form a transition channel region 109 .

[0114] S214 , forming a second mask layer on at least one sidewall of the third through hole, wherein the material of the second mask layer is different from that of the first mask layer.

[0115] refer to Fig.10 In an optional embodiment of the present invention, a second mask layer 40 is formed on two oppositely disposed side walls of the third through hole 503. Silicon nitride (SiN) is deposited on the side walls of the third through hole 503 to form the second mask layer 40. The material of the second mask layer 40 is different from that of the first mask layer 30. Exemplarily, the material of the first mask layer 30 is SiO 2The material of the second mask layer 40 is SiN. The material of the second mask layer 40 is distinguished from the material of the first mask layer 30 to prevent the first mask layer 30 from being affected when the second mask layer 40 is removed later, thereby improving the manufacturing accuracy of the semiconductor device.

[0116] S215, forming a first region on a side of the transition channel region away from the first surface exposed by the third through hole, wherein the first region is set to be of the first conductivity type, and the ion concentration of the first region is greater than the ion concentration of the transition channel region, and the transition channel region retained after the first region is formed serves as a channel layer.

[0117] refer to Fig.11 , a first conductive type ion implantation is performed on a side of the transition channel region 109 away from the first surface 101 exposed by the third through hole 503 to form a first region 104. The ion concentration of the first region 104 is greater than the ion concentration of the transition channel region 109. After the first region 104 is formed, the transition channel region 109 retained is used as the channel layer 105. The thickness of the first region 104 is greater than the thickness of the channel layer 105.

[0118] S216, removing the second mask layer.

[0119] refer to Fig.12 , first remove the second mask layer 40. The material of the second mask layer 40 is SiN, and the second mask layer 40 made of SiN material can be etched away by using a hydrofluoric acid solution.

[0120] S217, removing the first mask layer.

[0121] refer to Fig.13 , and then remove the first mask layer 30. The material of the first mask layer 30 is SiO 2 , hydrofluoric acid solution can also be used to etch away SiO 2 A first mask layer 30 of material.

[0122] S218, forming a third mask layer on the first surface, wherein the third mask layer is provided with a fourth through hole, and the bottom of the fourth through hole exposes a portion of the first area.

[0123] Optionally, after S217, removing the first mask layer, and before forming the second region on the first surface, the method further includes: referring to Fig.14 , using HM process or PECVD deposition of SiO 2 The third mask layer 50 is formed. The third mask layer 50 is patterned by a photolithography process. Fig.14As shown, the fourth through hole 504 is formed by a photolithography process. The bottom of the fourth through hole 504 exposes a portion of the first region 104, thereby preventing disconnection from the first region 104 when the second region is subsequently formed, thereby enhancing the reliability of the semiconductor device. In an optional embodiment of the present invention, the width of the first region 104 exposed at the bottom of the fourth through hole 504 is greater than or equal to 0.1 microns and less than or equal to 0.2 microns.

[0124] S219, forming a second region on the first surface, the second region being set to a second conductivity type; connecting the second region to the first region and the transition well region; and after forming the channel layer, the first region and the second region, the transition well region retained is used as a well region.

[0125] refer to Fig.15 , the second conductive type ions are implanted into the first surface 101 exposed at the bottom of the fourth through hole 504 to form the second region 106. After the channel layer 105, the first region 104 and the second region 106 are formed, the transition well region retained is used as the well region 103.

[0126] After the second region 106 is formed, the third mask layer 50 is etched away using a hydrofluoric acid solution.

[0127] S220 , forming a fourth mask layer on the first surface, wherein the fourth mask layer is provided with a fifth through hole.

[0128] Optionally, after S217, removing the first mask layer, the method further includes: referring to Fig.16 , a fourth mask layer 60 is formed on the first surface 101 of the semiconductor body 100 , and a fifth through hole 505 is formed in the fourth mask layer 60 by a photolithography process.

[0129] S221. Form a third region on the first surface exposed by the fifth through hole, wherein the third region is set to be of the first conductivity type, wherein the doping concentration of the third region is greater than the doping concentration of the semiconductor body, and wherein the third region and the well region have no overlap in the orthographic projection of the semiconductor body.

[0130] refer to Fig.17 , ions of the first conductivity type are implanted into the first surface 101 exposed by the fifth through hole 505 to form a third region 107. The provision of the third region 107 reduces the resistance of the JFET region, thereby reducing the on-resistance of the MOSFET device.

[0131] After the third region 107 is formed, the fourth mask layer 60 is etched away using a hydrofluoric acid solution.

[0132] S222, forming a gate insulating layer on the first surface;

[0133] refer to Fig.18On the first surface 101 of the semiconductor body 100 , a gate insulating layer 201 is formed by carbon film deposition and high temperature annealing. The gate insulating layer 201 includes a gate oxide layer.

[0134] S223, forming a gate on a side of the gate insulating layer away from the first surface, wherein the gate covers at least a portion of the channel layer.

[0135] refer to Fig.18 On the side of the gate insulating layer 201 away from the first surface 101 , a gate 202 is formed by polysilicon deposition and etching. The gate insulating layer 201 and the gate 202 together constitute a gate structure 200 .

[0136] S224, forming an interlayer insulating layer on a side of the gate away from the gate insulating layer; the interlayer insulating layer is provided with a first through hole and a second through hole.

[0137] refer to Fig.19 An interlayer insulating layer 500 is formed on a side of the gate 202 away from the gate insulating layer 201 ; the interlayer insulating layer 500 is provided with a first through hole 501 and a second through hole 502 .

[0138] S225, forming a gate electrode; the gate electrode passes through the second through hole to reach the gate; forming a first through hole in the interlayer insulating layer, and the source electrode passes through the first through hole to reach the first region.

[0139] refer to Fig. 20 , forming a gate electrode 600. The gate electrode 600 passes through the second through hole 502 to connect with the gate 202. The source 400 passes through the first through hole 501 to reach the first region 104.

[0140] S226, forming a source on the first surface and covering at least a portion of the first region.

[0141] refer to Figure 1 , metal is deposited on the first surface 101 of the semiconductor body 100 to form a source 400 , and the source 400 reaches the first region 104 through the first through hole 501 .

[0142] S227, forming a drain on the second surface.

[0143] refer to Figure 1 , metal titanium (Ti) or aluminum (Al) is deposited on the second surface 102 to form a drain 300 .

[0144] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0145] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0146] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0147] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0148] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of the present invention will not be repeated here.

[0149] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0150] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, the channel layer is set to the first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region and the channel layer away from the first surface; A gate structure, located on the first surface and covering at least a portion of the channel layer; a drain electrode, located on the second surface; The source is located on the first surface and covers at least a portion of the first region.

2. The semiconductor device according to claim 1, wherein: The thickness of the channel layer is smaller than the thickness of the first region.

3. The semiconductor device according to claim 1, wherein: The ion concentration of the channel layer is lower than the ion concentration of the first region.

4. The semiconductor device according to claim 1, wherein: The semiconductor body further includes a second region, which is set to a second conductivity type and is located on the first surface; the second region is connected to the first region.

5. The semiconductor device according to claim 1, wherein: The semiconductor body also includes a third region, which is set to the first conductivity type and is located on the first surface; the doping concentration of the third region is greater than the doping concentration of the semiconductor body, and the third region and the well region have no overlap in the orthographic projection of the semiconductor body.

6. The semiconductor device according to claim 1, wherein: The gate structure includes a gate insulating layer and a gate; The gate insulating layer is located on the first surface; The gate is located at a side of the gate insulating layer away from the first surface.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises an interlayer insulating layer and a gate electrode; The interlayer insulating layer is located on a side of the gate away from the gate insulating layer; The interlayer insulating layer is provided with a first through hole and a second through hole; The source electrode passes through the first through hole to reach the first region; The gate electrode passes through the second through hole to reach the gate.

8. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

9. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, the channel layer is set to the first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region and the channel layer away from the first surface; forming a gate structure on the first surface, wherein the gate structure covers at least a portion of the channel layer; forming a drain electrode on the second surface; A source electrode is formed on the first surface, and the source electrode covers at least a portion of the first region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; forming a first mask layer on the first surface, wherein the first mask layer is provided with a third through hole; forming a transition well region on the first surface exposed by the third through hole, wherein the transition well region is set to a second conductivity type; forming a transition channel region on a side of the transition well region close to the first surface, wherein the transition channel region is set to be of a first conductivity type; forming a second mask layer on at least one sidewall of the third through hole, wherein a material of the second mask layer is different from a material of the first mask layer; A first region is formed on a side of the transition channel region away from the first surface exposed by the third through hole, the first region is set to be of a first conductivity type, the ion concentration of the first region is greater than the ion concentration of the transition channel region, and the transition channel region retained after the first region is formed serves as a channel layer; removing the second mask layer; The first mask layer is removed.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Forming a second mask layer on at least one sidewall of the third through hole comprises: forming a second mask layer on two oppositely disposed side walls of the third through hole; After removing the first mask layer, the method further includes: A second region is formed on the first surface, and the second region is set to a second conductivity type; the second region is connected to the first region and the transition well region; and the transition well region retained after forming the channel layer, the first region and the second region is used as a well region.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: After removing the first mask layer and before forming the second area on the first surface, the method further includes: A third mask layer is formed on the first surface, wherein the third mask layer is provided with a fourth through hole, and a bottom of the fourth through hole exposes a portion of the first region.

13. The method for manufacturing a semiconductor device according to claim 10, wherein: After removing the first mask layer, the method further includes: forming a fourth mask layer on the first surface, wherein the fourth mask layer is provided with a fifth through hole; A third region is formed on the first surface exposed by the fifth through hole, the third region is set to the first conductivity type, the doping concentration of the third region is greater than the doping concentration of the semiconductor body, and the third region and the well region have no overlap in the orthographic projection of the semiconductor body.

14. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a gate structure on the first surface includes: forming a gate insulating layer on the first surface; A gate is formed on a side of the gate insulating layer away from the first surface, and the gate covers at least a portion of the channel layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: After forming a gate on a side of the gate insulating layer away from the first surface, the method further comprises: An interlayer insulating layer is formed on a side of the gate away from the gate insulating layer; the interlayer insulating layer is provided with a first through hole and a second through hole; forming a gate electrode; the gate electrode passes through the second through hole to reach the gate; Before forming a source electrode on the first surface, the method further comprises: A first through hole is formed in the interlayer insulating layer, and the source electrode passes through the interlayer insulating layer to reach the first region.

16. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

17. A power module, characterized in that: It comprises a substrate and the semiconductor device according to any one of claims 1 to 8, wherein the substrate is used to carry the semiconductor device.

18. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

19. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 18, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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