Display panel and electronic device including the same

Abstract

A display panel according to an embodiment and an electronic device including the same are disclosed. The display panel includes: a plurality of metal layers formed on each of first, second, and third sub-pixels; a first insulating layer covering the plurality of metal layers; a first reflective layer formed on an upper portion of the first insulating layer of the first sub-pixel; a second insulating layer covering the first reflective layer; a second reflective layer formed on the second insulating layer of the second sub-pixel; a third insulating layer covering the second reflective layer; a third reflective layer formed on the third insulating layer of the third sub-pixel; a plurality of first electrodes formed on the third insulating layer of each of the first, second, and third sub-pixels, in which a plurality of holes are formed penetrating the first, second, and third insulating layers of each of the first, second, and third sub-pixels, the metal layer of each of the first, second, and third sub-pixels is electrically connected to the first electrode of each of the first, second, and third sub-pixels via each hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0161956, filed on November 21, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display panel and an electronic device comprising the display panel. Background Art

[0004] Recently, there has been an increasing interest in high-definition organic light-emitting display devices for augmented reality (AR) and virtual reality (VR) electronic devices. Since AR / VR electronic devices require a higher frame rate and a shorter duty cycle ratio for vivid description, they require operating characteristics with high brightness in a short time.

[0005] Therefore, an organic light emitting display device having an OLED on silicon (OLEDoS) structure is being applied to AR / VR electronic devices. The organic light emitting display device having the OLEDoS structure may be implemented by forming an organic light emitting element on a substrate using a silicon wafer. Summary of the invention

[0006] In the process of manufacturing OLEDoS for these AR / VR electronic devices, the metal stack used as a reflector is a structure used to amplify the specific wavelength of each R, G, and B pixel, but the increase in the number of layers added to improve brightness leads to increased wafer and mask costs and increased process tact time, so process simplification is necessary.

[0007] The present invention is directed to solving all of the above needs and problems.

[0008] The invention provides a display panel and an electronic device comprising the display panel.

[0009] It should be noted that the objects of the present invention are not limited to the above objects, and other objects of the present invention will be clear to those skilled in the art from the following description.

[0010] A display panel according to an embodiment of the present invention may include: a plurality of metal layers formed on each of a first sub-pixel, a second sub-pixel, and a third sub-pixel; a first insulating layer covering the plurality of metal layers; a first reflective layer, the first reflective layer being formed on an upper portion of the first insulating layer of the first sub-pixel; a second insulating layer covering the first reflective layer; a second reflective layer formed on the second insulating layer of the second sub-pixel; a third insulating layer covering the second reflective layer; a third reflective layer formed on the third insulating layer of the third sub-pixel; and a plurality of first electrodes, the first electrodes being formed on the third insulating layer of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, wherein a plurality of holes are formed, the holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the metal layer of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel being electrically connected to the first electrode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel via each hole.

[0011] According to an embodiment of the present invention, a display panel may include: a metal layer; a first insulating layer covering the metal layer; a first reflective layer formed on an upper portion of the first insulating layer; a second insulating layer covering the first reflective layer; a second reflective layer formed on an upper portion of the second insulating layer; a third insulating layer covering the second reflective layer; a third reflective layer formed on an upper portion of the third insulating layer; and a first electrode formed on an upper portion of the third insulating layer, wherein a hole is formed penetrating the first insulating layer, the second insulating layer, and the third insulating layer, and the metal layer is electrically connected to the first electrode via the hole.

[0012] According to the present invention, by sequentially stacking a plurality of reflective layers and insulating layers and then forming a via for electrically connecting the plurality of reflective layers, processes for forming the via can be reduced.

[0013] Since the via process is reduced to shorten the process tact time, the development schedule can be shortened.

[0014] By reducing the number of masks and wafers used in the via process, manufacturing costs can be reduced.

[0015] The process for forming the vias can be simplified, allowing process optimization.

[0016] The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art through exemplary embodiments described in detail with reference to the accompanying drawings, in which:

[0018] Figure 1 is a plan view illustrating a pixel of a display panel according to an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram showing that in a top-emitting display panel, Figure 1 A cross-sectional view of an example of a cross-sectional structure of a pixel taken along line II';

[0020] Figure 3 is a schematic diagram showing that in a bottom emission type display panel, Figure 1 A cross-sectional view of an example of a cross-sectional structure of a pixel taken along line II';

[0021] Figure 4 It is illustrated in Figure 1 A diagram of a circuit of a sub-pixel included in the display panel shown;

[0022] Figure 5 The diagram includes Figure 4 A cross-sectional view of a display panel of a sub-pixel shown;

[0023] Figure 6 is a diagram illustrating the structure of a circuit layer according to a first embodiment of the present invention;

[0024] Figure 7 It is used to illustrate Figure 6 A diagram showing the structure and function of the residual reflective layer;

[0025] Figure 8 It is a graphic Figure 6 A diagram of a modified embodiment of the circuit layer shown;

[0026] Fig. 9 It is used to illustrate Figure 6 A diagram showing the connection principle between the reflective layers shown;

[0027] Fig.10 is a diagram illustrating the structure of a circuit layer according to a second embodiment of the present invention;

[0028] Fig.11 It is used to illustrate Fig.10 A diagram showing the connection principle between the reflective layers shown;

[0029] Fig.12 is a diagram illustrating the structure of a circuit layer according to a third embodiment of the present invention;

[0030] Fig.13 It is used to illustrate Fig.12A diagram showing the connection principle between the reflective layers shown;

[0031] Fig.14 is a diagram illustrating a circuit layer structure according to a fourth embodiment of the present invention;

[0032] Fig.15 It is used to illustrate Fig.14 A diagram showing the connection principle between the reflective layers shown;

[0033] Fig.16 is a diagram illustrating an appearance example of an HMD-type personal immersive device;

[0034] Fig.17 is a block diagram illustrating an example of a display device that may be applied to a personal immersive device. DETAILED DESCRIPTION

[0035] The advantages and features of the present invention and the methods for implementing the same will become clear through the preferred embodiments described in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described below, but can be implemented in different forms, which are provided only to make the disclosure of the present invention complete and to fully convey the scope of the present invention to ordinary technicians in the field, and the present invention is defined by the disclosed claims.

[0036] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present invention are merely examples, and the present invention is not limited thereto. Throughout this specification, similar reference numerals generally refer to similar elements. In addition, when describing the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

[0037] When “including,” “having,” “comprising,” etc. are used in the present invention, other components may be added unless “only” is used. The case where a component is expressed in the singular includes the plural form unless it is clearly stated otherwise.

[0038] When interpreting the elements, it should be understood that the error range is included even if there is no separate explicit description.

[0039] In the case of describing a positional relationship, for example, when the positional relationship of two parts is described as "on", "upper", "lower", "after", etc., one or more other parts may be set between the two parts, unless "immediately" or "directly" is used.

[0040] Although the first, second, etc. are used to describe each element, these elements are not limited by these terms. These terms are only used to distinguish an element from other elements. Therefore, within the technical spirit of the present invention, the first element mentioned below can also be the second element.

[0041] Like reference numerals may refer to substantially like elements throughout the present disclosure.

[0042] The following embodiments may be combined or combined with each other in part or in whole, and may be technically connected and operated in various ways. The embodiments may be implemented independently of each other, or in association with each other.

[0043] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a plan view illustrating a pixel of a display panel according to an embodiment of the present invention. Figure 2 is a schematic diagram showing that in a top-emitting display panel, Figure 1 A cross-sectional view showing an example of a cross-sectional structure of a pixel taken along line II'. Figure 3 is a schematic diagram showing that in a bottom emission type display panel, Figure 1 A cross-sectional view showing an example of a cross-sectional structure of a pixel taken along line II'.

[0045] Reference Figures 1 to 3 , the display panel according to the embodiment of the present invention has a length (X), a width (Y) and a thickness (Z). When viewed in a plan view, the display panel may be rectangular, or the display panel may have a variant shape including at least a portion that is curved or ovalized.

[0046] The substrate 10 of the display panel may be made of glass, plastic or silicon wafer. The substrate 10 may be interpreted as a backplane.

[0047] A plurality of pixels PIX are arranged on the display panel. Each pixel PIX may include a red (R) sub-pixel SP1, a green (G) sub-pixel SP2, and a blue (B) sub-pixel SP3 for realizing color. Each pixel may further include a white (W) sub-pixel. The size or shape of each sub-pixel SP1, SP2, and SP3 may be modified in various ways. A recessed groove T may be arranged between adjacent sub-pixels SP1, SP2, and SP3. The groove T blocks current from flowing between adjacent sub-pixels. The groove T may block leakage current flowing to the sub-pixel by extending the current path between adjacent sub-pixels SP1, SP2, and SP3.

[0048] The circuit layer 20 , the light emitting element layer 30 , and the encapsulation layer 40 may be stacked on the substrate 10 .

[0049] The circuit layer 20 includes a pixel circuit that drives the light-emitting elements of the sub-pixels SP1, SP2, and SP3 based on the pixel data of the input image. The circuit layer 20 may further include a gate driving circuit that provides a gate signal to the pixel circuit. The pixel circuit may include: a driving transistor that provides a current to the light-emitting element based on its gate-source voltage; a switching transistor that applies a data voltage of the pixel data to the gate or source of the driving transistor; a storage capacitor that maintains the gate-source voltage of the driving transistor; a plurality of insulating layers that insulate the metal patterns of these circuit elements; and the like.

[0050] The light emitting element layer 30 includes a light emitting element, which is disposed in each of the sub-pixels SP1, SP2, and SP3 and driven by a pixel circuit. The light emitting element may be a white light emitting element that is commonly disposed in the sub-pixels SP1, SP2, and SP3 to generate white light. In another embodiment, a red light emitting element that generates red light may be disposed in the red sub-pixel SP1, and a green light emitting element that generates green light may be disposed in the green sub-pixel SP2. A blue light emitting element that generates blue light may be disposed in the blue sub-pixel SP3.

[0051] When white light emitting elements are provided in the sub-pixels SP1, SP2, and SP3, the color filter 50 may be provided to selectively transmit the wavelength of each color. The light emitting elements of the light emitting element layer 30 may be covered by a plurality of passivation layers including organic and inorganic layers.

[0052] The light emitting element may be implemented as an organic light emitting element or an inorganic light emitting element. For example, the light emitting element may be implemented using an organic light emitting diode (OLED) or an inorganic LED. The light emitting element may include a first electrode 32, a second electrode 34, and a light emitting layer formed between the first electrode 32 and the second electrode 34. The first electrode 32 may be an anode of the light emitting element separated for each sub-pixel. The second electrode 34 may be a common electrode shared by the sub-pixels. The second electrode 34 may be a cathode of the light emitting element.

[0053] The encapsulation layer 40 covers the light emitting element layer 30 to seal the circuit layer 20 and the light emitting element layer 30. The encapsulation layer 40 may have a multi-insulating layer structure in which organic layers and inorganic layers are alternately stacked. The inorganic layer blocks the penetration of moisture or oxygen. The organic layer flattens the surface of the inorganic layer. When the organic layer and the inorganic layer are stacked into multiple layers, the movement path of moisture or oxygen becomes longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect the light emitting element layer 30.

[0054] The display panel may have Figure 2 The top-emitting structure shown or Figure 3 The bottom emission structure shown.

[0055] In a top-emitting display panel, such as Figure 2 As shown, light from the light emitting element layer 30 is emitted to the outside via the second electrode 34, the encapsulation layer 40 and the color filter 50. In a top emission type display panel, the first electrode 32 may also be used as a reflective layer to improve light efficiency, and the second electrode 34 may be implemented as a transparent or translucent electrode. In a top emission type display panel, the distance between the first electrode 32 and the second electrode 34 may be set to be different for each color of the sub-pixels SP1, SP2 and SP3 to achieve a microcavity effect. When a microcavity is adopted, light reflected between the electrodes 32 and 34 undergoes constructive interference, which increases the wavelength amplitude of the light, thereby increasing the amount of light emitted to the outside in the top emission type.

[0056] In bottom-emitting display panels, such as Figure 3 As shown, light from the light emitting element layer 30 is emitted to the outside via the first electrode 32, the color filter 50, the circuit layer 20 and the substrate 10. In a bottom emission type display panel, the second electrode 34 can also be used as a reflective layer to improve light efficiency, and the first electrode 32 can be implemented as a transparent or semi-transparent electrode.

[0057] Figure 4 It is illustrated in Figure 1 A diagram of a circuit of a sub-pixel included in a display panel shown.

[0058] Reference Figure 4 The sub-pixel includes a light emitting element EL, a driving transistor DT for supplying current to the light emitting element EL, a plurality of switching transistors T1 and T2, and a storage capacitor Cst. The driving transistor DT and the switching transistors T1 and T2 may be implemented as n-channel transistors, but are not necessarily limited thereto, and may be implemented as p-channel transistors.

[0059] The transistor may be an oxide thin film transistor (TFT) including an oxide semiconductor, or a low temperature polycrystalline silicon (LTPS) TFT including low temperature polycrystalline silicon (LTPS).

[0060] A transistor is a three-electrode element having a gate, a source, and a drain. The source is an electrode for providing carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is an electrode from which carriers exit the transistor externally. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, which allows electrons to flow from the source to the drain. In an n-channel transistor, the direction of flow of current is from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, which allows holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present invention is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor are referred to as a first electrode and a second electrode.

[0061] The pixel driving voltage as the high potential voltage ELVDD is applied to the drain of the driving element DT via the high potential voltage line PL. The driving transistor DT provides a current to the light emitting element EL according to the gate-source voltage Vgs to drive the light emitting element EL. When the forward voltage between the anode and the cathode is greater than the threshold voltage, the light emitting element EL is turned on and emits light. The low potential voltage ELVSS is applied to the cathode of the light emitting element EL.

[0062] The storage capacitor Cst is connected between the first node n1 and the second node n2 to maintain the gate-source voltage Vgs of the driving transistor DT.

[0063] The first switching transistor T1 is turned on according to a gate-on voltage of a scan pulse SCAN applied from a gate line to connect the data line DL to the first node n1.

[0064] The second switching transistor T2 applies a reference voltage Vref in response to a scan pulse SCAN applied from the gate line RL. The reference voltage Vref is applied to the second node n2 via the reference voltage line RL.

[0065] The second switching transistor T2 may be controlled to sense a voltage of the second node through the sensing line in response to a scan pulse SCAN applied from the gate line.

[0066] The light emitting element EL may be implemented as an organic light emitting diode (OLED). The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto.

[0067] Figure 5 The diagram includes Figure 4 A cross-sectional view of a display panel of a sub-pixel is shown. Figure 5 In the figure, the substrate, encapsulation layer, color filter, etc. are omitted. Figure 5 The illustrated display panel provides a microcavity effect in each of the sub-pixels SP1, SP2, and SP3.

[0068] Reference Figure 5 , showing the driving transistor DT and the storage capacitor Cst included in the red sub-pixel SP1, the green sub-pixel SP2, and the blue sub-pixel SP3.

[0069] The driving transistor may be formed on a substrate SUB. The drain DE and source SE of the driving transistor may be formed on a substrate SUBS. The substrate SUB may be a silicon substrate. The drain DE and source SE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, but is not limited thereto.

[0070] The gate insulating layer GI may be formed on the substrate SUB. The gate insulating layer GI may be formed between the substrate SUB and the gate GE of the driving transistor. The gate GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, but is not limited thereto.

[0071] The gate GE may be formed on the gate insulating layer GI, and the first intermediate insulating layer ILD1 may be formed to cover the gate GE.

[0072] The first metal layer M1 may be formed on an upper portion of the first intermediate insulating layer ILD1 , and the second intermediate insulating layer ILD2 may be formed to cover the first metal layer M1 .

[0073] The second metal layer M2 may be formed on an upper portion of the second intermediate insulating layer ILD2 , and the third intermediate insulating layer ILD3 may be formed to cover the second metal layer M2 .

[0074] The third metal layer M3 may be formed on an upper portion of the third intermediate insulating layer ILD3 , and the fourth intermediate insulating layer ILD4 may be formed to cover the third metal layer M3 .

[0075] A fourth metal layer M4 may be formed on an upper portion of the fourth intermediate insulating layer ILD4 .

[0076] Here, the storage capacitor Cst may include a first electrode CE1 electrically connected to the first node n1 and a second electrode CE2 electrically connected to the second node n2.

[0077] In this case, the first intermediate insulating layer ILD1, the second intermediate insulating layer ILD2, the third intermediate insulating layer ILD3 and the fourth intermediate insulating layer ILD4 may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon dioxide (SiO 2 ) etc., but not limited thereto.

[0078] In addition, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 disposed in different layers may be electrically connected via vias V1, V2, V3, V4 and V5. For example, the vias may be formed of a material such as tungsten (W), but are not limited thereto.

[0079] A first insulating layer 22 covering the fourth metal layer M4 may be formed on an upper portion of the fourth intermediate insulating layer ILD4 .

[0080] The first reflective layer 35 may be formed on an upper portion of the first insulating layer 22 of the first sub-pixel, for example, the red sub-pixel SP1 , and the second insulating layer 24 may be formed to cover the first reflective layer 35 .

[0081] The second reflective layer 36 may be formed on an upper portion of the second insulating layer 24 of the second sub-pixel, for example, the green sub-pixel SP2 , and the third insulating layer 26 may be formed to cover the second reflective layer 36 .

[0082] The third reflective layer 37 may be formed on an upper portion of the third insulating layer 26 of the third sub-pixel, for example, the blue sub-pixel SP3.

[0083] The first electrode 32 may be formed on an upper portion of the third insulating layer 26. The first electrode 32 may be formed of a thin metal material such as aluminum (Al) so as to transmit light.

[0084] In this case, the first insulating layer 22, the second insulating layer 24, and the third insulating layer 26 may be made of a material such as silicon nitride (SiNx) or silicon dioxide (SiO 2 ). In addition, the first reflective layer 35, the second reflective layer 36, and the third reflective layer 37 provided in different layers may be formed of a high reflectivity material such as titanium (Ti), aluminum (Al), and titanium nitride (TiN), but are not limited thereto.

[0085] In order to increase the amount of light of each color in each sub-pixel SP1, SP2 and SP3 by utilizing the microcavity effect, the thickness of the insulating layer between the first electrode 32 and the reflective layer 35, 36, 37 may be different for each sub-pixel. For example, the insulating layers 24 and 26 between the first electrode 32 and the reflective layer 35 of the red sub-pixel SP1 are thicker than the insulating layer 26 between the first electrode 32 and the reflective layer 36 of the green sub-pixel SP2. In the blue sub-pixel SP3, the first electrode 32 and the reflective layer 37 may be in contact without a gap. The reflective layers 35, 36 and 37 of each sub-pixel SP1, SP2 and SP3 may be formed of the same or different stacked structures and / or materials.

[0086] This allows embodiments to improve efficiency by utilizing the microcavity effect, which amplifies the peak of a certain wavelength for each R, G, and B pixel while suppressing the transmission of light at other wavelengths.

[0087] Figure 6 is a diagram illustrating the structure of a circuit layer according to a first embodiment of the present invention, Figure 7 It is used to illustrate Figure 6 Diagram of the structure and function of the residual reflective layer shown.

[0088] Reference Figure 6 , the circuit layer 20 according to the first embodiment may include: a first insulating layer 22 covering the fourth metal layer M4; a second insulating layer 24 disposed on an upper portion of the first insulating layer 22; and a third insulating layer 26 disposed on an upper portion of the second insulating layer 24.

[0089] The first reflective layer 35, the second reflective layer 36, and the third reflective layer 37 may be formed in different layers of each sub-pixel. In addition to the reflective layer, a residual reflective layer may be formed in each sub-pixel. The residual reflective layer may be formed on an insulating layer different from a layer on which the reflective layer is formed.

[0090] Figure 5 The source SE of the driving transistor, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 are electrically connected via different paths V1, V2, V3 and V4, respectively, but the fourth metal layer M4 and the 3a residual reflective layer 37a, the fourth metal layer M4 and the 3b residual reflective layer 37b, and each group of the fourth metal layer M4 and the third reflective layer 37 can be electrically connected via one path V5.

[0091] Instead of the fourth metal layer M4 and the 3a residual reflective layer 37a, the fourth metal layer M4 and the 3b residual reflective layer 37b, and the fourth metal layer M4 and the third reflective layer 37 being electrically connected to each other via a plurality of vias, when the fourth metal layer M4 is electrically connected to the 3a residual reflective layer 37a, the fourth metal layer M4 is electrically connected to the 3b residual reflective layer 37b, and the fourth metal layer M4 is electrically connected to the third reflective layer 37 via one via at a time, the process for forming the via can be reduced from three times to one time. This process simplification can not only reduce the process tact time and thus shorten the development arrangement time, but also reduce the manufacturing cost by reducing the number of via masks.

[0092] The first reflective layer 35 may be formed on an upper portion of the first insulating layer 22 of the red sub-pixel SP1. The first reflective layer 35 may be formed to have the same size or area as the first electrode 32. The 1a-th residual reflective layer 35a may be formed on an upper portion of the first insulating layer 22 of the green sub-pixel SP2. The 1b-th residual reflective layer 35b may be formed on an upper portion of the first insulating layer 22 of the blue sub-pixel SP3. In this case, each of the 1a-th residual reflective layer 35a and the 1b-th residual reflective layer 35b may be formed to be smaller in size or area than the first reflective layer 35.

[0093] The second reflective layer 36 may be formed on an upper portion of the second insulating layer 24 of the green sub-pixel SP2. The second reflective layer 36 may be formed to have the same size or area as the first electrode 32. The 2a-th residual reflective layer 36a may be formed on an upper portion of the second insulating layer 24 of the red sub-pixel SP1. The 2b-th residual reflective layer 36b may be formed on an upper portion of the second insulating layer 24 of the blue sub-pixel SP3. In this case, the 2a-th residual reflective layer 36a and the 2b-th residual reflective layer 36b may be formed to be smaller in size or area than the second reflective layer 36.

[0094] The third reflective layer 37 may be formed on an upper portion of the third insulating layer 26 of the blue sub-pixel SP3. The third reflective layer 37 may be formed to have the same size or area as the first electrode 32. The 3a-th residual reflective layer 37a may be formed on an upper portion of the third insulating layer 26 of the red sub-pixel SP1. The 3b-th residual reflective layer 37b may be formed on an upper portion of the third insulating layer 26 of the green sub-pixel SP2. In this case, the 3a-th residual reflective layer 37a and the 3b-th residual reflective layer 37b may be formed to be smaller in size or area than the third reflective layer 37.

[0095] In this case, the residual reflective layer is formed to a predetermined size, but may be changed according to the wavelength band of the reflected light. For example, when light of a relatively short wavelength band is reflected, the size of the residual reflective layer is formed to be smaller; and when light of a relatively long wavelength band is reflected, the size of the residual reflective layer is formed to be larger. However, it is not necessarily limited thereto.

[0096] For example, if there is light incident at a predetermined angle rather than perpendicularly on the first reflective layer 35 of the red sub-pixel SP1, as Figure 7 shown, the light can be trapped within the circuit layer and canceled out by the 2a residual reflective layer 36a and the 3a residual reflective layer 37a.

[0097] In this way, the color purity of the red sub-pixel SP1 can be increased by canceling out the light incident at an unwanted angle other than the light incident at the desired angle.

[0098] As another example, when there is light incident obliquely at a predetermined angle rather than perpendicularly on the second reflective layer 36 of the green sub-pixel SP2, as Figure 7 shown, the light path can be changed in different directions by the 2b residual reflective layer 36b and the 3b residual reflective layer 37b.

[0099] In this way, the color purity of the green sub-pixel SP2 can be increased by changing the path of the light incident at an unwanted angle to different directions in addition to the light incident at the desired angle.

[0100] In addition, the residual reflective layer can also be used to support the vias in each sub-pixel.

[0101] Figure 8 is a diagrammatic Figure 6 view of a modified embodiment of the circuit layer shown.

[0102] Referring to Figure 8 , the circuit layer 20 according to the modified embodiment may include: a first insulating layer 22 covering the fourth metal layer M4; a second insulating layer 24 disposed on the upper portion of the first insulating layer 22; and a third insulating layer 26 disposed on the upper portion of the second insulating layer 24.

[0103] The first reflective layer 35, the second reflective layer 36, and the third reflective layer 37 may be formed in different layers of each sub-pixel and may form Figure 6 only at least a part of the residual reflective layer formed.

[0104] Not all of the residual reflective layers are used to cancel out the light incident at an unwanted angle as Figure 7 shown, or redirect it to other light paths. That is, in Figure 7 , the 2a residual reflective layer 36a and the 3a residual reflective layer 37a are used in the red sub-pixel, the 3b residual reflective layer 37b is used in the green sub-pixel, but the other residual reflective layers are not used.

[0105] Therefore, in modified embodiments, it is intended to select and form only the residual reflective layer required to counteract light incident at an unwanted angle or to redirect light to other light paths.

[0106] That is, in a modified embodiment, only the residual reflective layer located on the upper portion of each of the first reflective layer 35, the second reflective layer 36 and the third reflective layer 37 in each sub-pixel, that is, the 2a residual reflective layer 36a, the 3a residual reflective layer 37a and the 3b residual reflective layer 37b may be selectively formed.

[0107] This modified embodiment is merely an example and is not limited thereto, and various modifications are possible.

[0108] Fig. 9 It is used to illustrate Figure 6 A diagram showing the connection principle between the reflective layers.

[0109] Reference Fig. 9 In the case of the red sub-pixel, the first reflective layer 35, the second insulating layer 24, the 2a-th residual reflective layer 36a and the third insulating layer 26 are stacked in sequence on the first insulating layer 22 covering the fourth metal layer M4.

[0110] After forming a hole (or via hole) H penetrating the first insulating layer 22, the first reflective layer 35, the second insulating layer 24, the 2a residual reflective layer 36a and the third insulating layer 26, and then forming a via V5 in the hole H, the 3a residual reflective layer 37a and the first electrode 32 are stacked in this order.

[0111] In this case, the hole H may be formed to have a fixed diameter, but is not necessarily limited thereto, and the hole H may be formed in various shapes. For example, an upper portion of the hole H may be wider than a lower portion.

[0112] The fourth metal layer M4 is electrically connected to the 3a-th residual reflective layer 37a via a via V5. Since the first electrode 32 is formed on the upper portion of the 3a-th residual reflective layer 37a, there may be an electrical connection from the fourth metal layer M4 to the first electrode 32.

[0113] In addition, the green sub-pixel and the blue sub-pixel may be formed through the same process.

[0114] Fig.10 is a diagram illustrating the structure of a circuit layer according to a second embodiment of the present invention.

[0115] Reference Fig.10 , the circuit layer 20 according to the second embodiment may include: a first insulating layer 22 covering the fourth metal layer M4; a second insulating layer 24 disposed on an upper portion of the first insulating layer 22; and a third insulating layer 26 disposed on an upper portion of the second insulating layer 24.

[0116] The first reflective layer 35 - 1 , the second reflective layer 36 - 1 , and the third reflective layer 37 - 1 may be formed in different layers for each sub-pixel.

[0117] In contrast to the first embodiment, in the second embodiment, each group of the fourth metal layer M4 and the first reflective layer 35-1, the fourth metal layer M4 and the 1a residual reflective layer 35a-1, and the fourth metal layer M4 and the 1b residual reflective layer 35b-1 can be electrically connected via one path V5a; the first reflective layer 35-1 and the 3a residual reflective layer 37a-1, the 1a residual reflective layer 35a-1 and the 3b residual reflective layer 37b-1, and the 1b residual reflective layer 35b-1 and the third reflective layer 37-1 can be electrically connected via another path V5b.

[0118] Instead of electrically connecting the fourth metal layer M4 and the 3a residual reflective layer 37a-1, the fourth metal layer M4 and the 3b residual reflective layer 37b-1, and the fourth metal layer M4 and the third reflective layer 37-1 to each other via multiple vias, when the fourth metal layer M4 is electrically connected to the first reflective layer 35-1, the fourth metal layer M4 is electrically connected to the 1a residual reflective layer 35a-1, and the fourth metal layer M4 is electrically connected to the 1b residual reflective layer 35b-1 via one via V5a at a time; and when the first reflective layer 35-1 is electrically connected to the 3a residual reflective layer 37a-1, the 1a residual reflective layer 35a-1 is electrically connected to the 3b residual reflective layer 37b-1, and the 1b residual reflective layer 35b-1 is electrically connected to the third reflective layer 37-1 via another via V5b at a time, the process for forming the vias can be reduced from three times to two times. Since one process is reduced, this process simplification can not only reduce the process tact time and thus shorten the development schedule time, but also reduce the manufacturing cost by reducing the number of via masks.

[0119] Fig.11 It is used to illustrate Fig.10 A diagram showing the connection principle between the reflective layers.

[0120] Reference Fig.11 In the case of a red sub-pixel, after forming a hole (or via hole) Ha penetrating the first insulating layer 22 covering the fourth metal layer M4 and then forming a via V5a in the hole Ha, the first reflective layer 35-1, the second insulating layer 24, the 2a residual reflective layer 36a-1 and the third insulating layer 26 are stacked in sequence.

[0121] After forming a hole (or via hole) Hb penetrating the second insulating layer 24, the 2a residual reflective layer 36a-1, and the third insulating layer 26, and then forming a via V5b in the hole Hb, the 3a residual reflective layer 37a-1 and the first electrode 32 are stacked in this order.

[0122] The fourth metal layer M4 and the first reflective layer 35-1 are connected via one via V5a, and the first reflective layer 35-1 is electrically connected to the 3a-th residual reflective layer 37a-1 via another via V5b. Since the first electrode 32 is formed on the upper portion of the 3a-th residual reflective layer 37a-1, there may be an electrical connection from the fourth metal layer M4 to the first electrode 32.

[0123] In addition, the green sub-pixel and the blue sub-pixel may be formed through the same process.

[0124] The hole may not be formed with a fixed-size diameter and may be formed to have a larger upper portion. The reason for forming two vias as in the second embodiment is that when the fourth metal layer M4 and the third reflective layer 37-1 are connected via the first embodiment, Figure 8 When one via is shown to be electrically connected to each other, a portion where the via is formed is relatively deep, thereby increasing an upper diameter of a hole where the via is formed; due to the upper diameter of the hole, an opening reduction may occur.

[0125] Fig.12 is a diagram illustrating the structure of a circuit layer according to a third embodiment of the present invention.

[0126] Reference Fig.12 , the circuit layer 20 according to the third embodiment may include: a first insulating layer 22 covering the fourth metal layer M4; a second insulating layer 24 disposed on an upper portion of the first insulating layer 22; and a third insulating layer 26 disposed on an upper portion of the second insulating layer 24.

[0127] The first reflective layer 35-2, the second reflective layer 36-2, and the third reflective layer 37-2 may be formed in different layers of each sub-pixel. Here, the third reflective layer 37-2 may be configured to function as a via.

[0128] A hole (or contact hole) H may be formed by penetrating the first insulating layer 22, the second insulating layer 24, and the third insulating layer 26 covering the fourth metal layer M4. The hole H may be formed to expose the upper surface of the fourth metal layer M4.

[0129] The 3a residual reflective layer 37a-2, the 3b residual reflective layer 37b-2, and the third reflective layer 37-2 may be formed on the upper portion of the third insulating layer 26 formed with the hole H. Each of the 3a residual reflective layer 37a-2, the 3b residual reflective layer 37b-2, and the third reflective layer 37-2 is formed along the hole H so that the upper surface formed on the upper portion of the third insulating layer 26 contacts the first electrode 32, and the lower surface of the portion formed along the hole contacts the fourth metal layer M4, whereby the first electrode 32 and the fourth metal layer M4 may be electrically connected. The residual reflective layers (37a-2 and 37b-2) of the red sub-pixel SP1 and the green sub-pixel SP2 and the third reflective layer 37-2 of the blue sub-pixel SP3 may have: an upper surface of a portion formed in the third insulating layer 26 in contact with the first electrode 32; and a lower surface of a portion formed along each hole H in contact with each metal layer M4.

[0130] The 3a-th residual reflective layer 37a-2 of the red sub-pixel SP1 may be formed on an upper portion of the third insulating layer 26 along the hole H. The 3a-th residual reflective layer 37a-2 may be formed along side and bottom surfaces of the hole to be electrically connected to the fourth metal layer M4 via the bottom surface of the hole H and to the first reflective layer 35-2 and the 2a-th residual reflective layer 36a-2 via the side surface of the hole H.

[0131] The 3b-th residual reflective layer 37b-2 of the green sub-pixel SP2 may be formed on an upper portion of the third insulating layer 26 along the hole H. The 3b-th residual reflective layer 37b-2 may be formed along side and bottom surfaces of the hole to be electrically connected to the fourth metal layer M4 via the bottom surface of the hole H and to the 1a-th residual reflective layer 35a-2 and the second reflective layer 36-2 via the side surface of the hole H.

[0132] The third reflective layer 37-2 of the blue sub-pixel SP3 is formed on the upper portion of the third insulating layer 26 along the hole H. The third reflective layer 37-2 may be formed along the side and bottom surfaces of the hole to be electrically connected to the fourth metal layer M4 via the bottom surface of the hole H and to the 1b-th residual reflective layer 35b-2 and the 2b-th residual reflective layer 36b-2 via the side surface of the hole H.

[0133] The first electrode 32 may be formed on an upper portion of the third insulating layer 26 on which each of the 3a-th residual reflective layer 37a-2, the 3b-th residual reflective layer 37b-2, and the third reflective layer 37-2 is formed.

[0134] In contrast to the first and second embodiments, in the third embodiment, the fourth metal layer M4 and the first electrode 32 can be electrically connected to each other via the 3a residual reflective layer 37a-2, the 3b residual reflective layer 37b-2 and the third reflective layer 37-2 formed along the hole H without forming a path.

[0135] Instead of the fourth metal layer M4 and the 3a residual reflective layer 37a-2, the fourth metal layer M4 and the 3b residual reflective layer 37b-2, and the fourth metal layer M4 and the third reflective layer 37-2 being electrically connected to each other via a plurality of vias, when the fourth metal layer M4 and the 3a residual reflective layer 37a-2, the fourth metal layer M4 and the 3b residual reflective layer 37b-2, and the fourth metal layer M4 and the third reflective layer 37-2 are electrically connected to each other once via one hole H, the process for forming the via can be reduced from three times to one time. Since two processes are reduced, this process simplification can not only reduce the process tact time and thus shorten the development arrangement time, but also reduce the manufacturing cost by reducing the number of via masks.

[0136] Fig.13 It is used to illustrate Fig.12 A diagram showing the connection principle between the reflective layers.

[0137] Reference Fig.13 In the case of a red sub-pixel, the first reflective layer 35-2, the second insulating layer 24, the 2a-th residual reflective layer 36a-2 and the third insulating layer 26 are sequentially stacked on the first insulating layer 22 covering the fourth metal layer M4.

[0138] After forming a hole (or via hole) H that penetrates the first insulating layer 22, the first reflective layer 35-2, the second insulating layer 24, the 2a residual reflective layer 36a-2 and the third insulating layer 26, and then forming the 3a residual reflective layer 37a-2 along the hole H, the first electrode 32 is formed on the upper portion of the 3a residual reflective layer 37a-2.

[0139] In this case, the hole H may be formed to have a fixed diameter, but is not necessarily limited thereto, and the hole H may be formed in various shapes. For example, an upper portion of the hole H may be wider than a lower portion.

[0140] The fourth metal layer M4 and the 3a-th residual reflective layer 37a-2 are electrically connected to each other via one hole H, that is, via the 3a-th residual reflective layer 37a-2 formed along one hole H. Since the first electrode 32 is formed on the upper portion of the 3a-th residual reflective layer 37a-2, the fourth metal layer M4 and the first electrode 32 may be electrically connected to each other.

[0141] In addition, the green sub-pixel and the blue sub-pixel may be formed by the same process.

[0142] Fig.14 is a diagram illustrating a circuit layer structure according to a fourth embodiment of the present invention.

[0143] Reference Fig.14, the circuit layer 20 according to the fourth embodiment may include: a first insulating layer 22 covering the fourth metal layer M4; a second insulating layer 24 disposed on an upper portion of the first insulating layer 22; and a third insulating layer 26 disposed on an upper portion of the second insulating layer 24.

[0144] The first reflective layer 35-3, the second reflective layer 36-3, and the third reflective layer 37-3 may be formed in different layers of each sub-pixel. Here, the third reflective layer 37-3 may be configured to function as a via.

[0145] The fourth metal layer M4 and the first reflective layer 35-3, the fourth metal layer M4 and the 1a residual reflective layer 35a-3, and the fourth metal layer M4 and the 1b residual reflective layer 35b-3 can be electrically connected to each other via the path V5a, and the first reflective layer 35-3 and the first electrode 32, the 1a residual reflective layer 35a-3 and the first electrode, and the 1b residual reflective layer 35b-3 and the first electrode 32 can be electrically connected to each other via the 3a residual reflective layer 37a-3, the 3b residual reflective layer 37b-3 and the third reflective layer 37-3 formed along the hole H.

[0146] The hole H may be formed by penetrating the second insulating layer 24 and the third insulating layer 26. The hole H may be formed to expose upper surfaces of the first reflective layer 35-3, the 1a-th residual reflective layer 35a-3, and the 1b-th residual reflective layer 35b-3.

[0147] The 3a-th residual reflective layer 37a-3, the 3b-th residual reflective layer 37b-3, and the third reflective layer 37-3 may be formed on the upper portion of the third insulating layer 26 in which the hole H is formed. Each of the 3a-th residual reflective layer 37a-3, the 3b-th residual reflective layer 37b-3, and the third reflective layer 37-3 is formed along the hole H so that the upper surface formed on the upper portion of the third insulating layer 26 contacts the first electrode 32, and the lower surface of the portion formed along the hole contacts the first reflective layer 35-3, the 1a-th residual reflective layer 35a-3, and the 1b-th residual reflective layer 35b-3, whereby the first electrode 32 and the fourth metal layer M4 are electrically connected to each other.

[0148] The 3a-th residual reflective layer 37a-3 of the red sub-pixel SP1 may be formed on an upper portion of the third insulating layer 26 along the hole H. The 3a-th residual reflective layer 37a-3 may be formed along side and bottom surfaces of the hole so as to be electrically connected to the first reflective layer 35-3 via the bottom surface of the hole H and to the 2a-th residual reflective layer 36a-3 via the side surface of the hole H.

[0149] The 3b-th residual reflective layer 37b-3 of the green sub-pixel SP2 may be formed on an upper portion of the third insulating layer 26 along the hole H. The 3b-th residual reflective layer 37b-3 may be formed along side and bottom surfaces of the hole so as to be electrically connected to the 1a-th residual reflective layer 35a-3 via the bottom surface of the hole H and to the second reflective layer 36-3 via the side surface of the hole H.

[0150] The third reflective layer 37-3 of the blue sub-pixel SP3 is formed on an upper portion of the third insulating layer 26 along the hole H. The third reflective layer 37-3 may be formed along side and bottom surfaces of the hole so as to be electrically connected to the 1b-th residual reflective layer 35b-3 via the bottom surface of the hole H and to the 2b-th residual reflective layer 36b-3 via the side surface of the hole H.

[0151] The first electrode 32 may be formed on an upper portion of the third insulating layer 26 on which the 3a-th residual reflective layer 37a-3, the 3b-th residual reflective layer 37b-3, and the third reflective layer 37-3 are formed.

[0152] In contrast to the third embodiment, in the fourth embodiment, the fourth metal layer M4 and the first reflective layer 35-3, the fourth metal layer M4 and the 1a residual reflective layer 35a-3, and the fourth metal layer M4 and the 1b residual reflective layer 35b-3 can be electrically connected to each other via a path V5a, and the first reflective layer 35-3 and the first electrode 32, the 1a residual reflective layer 35a-3 and the first electrode 32, and the 1b residual reflective layer 35b-3 and the first electrode 32 can be electrically connected to each other via the 3a residual reflective layer 37a-3, the 3b residual reflective layer 37b-3 and the third reflective layer 37-3 formed along the hole H.

[0153] Instead of electrically connecting the fourth metal layer M4 and the 3a residual reflective layer 37a-3, the fourth metal layer M4 and the 3b residual reflective layer 37b-3, and the fourth metal layer M4 and the third reflective layer 37-3 to each other via multiple vias, when the fourth metal layer M4 and the first reflective layer 35-3, the fourth metal layer M4 and the 1a residual reflective layer 35a-3, and the fourth metal layer M4 and the 1b residual reflective layer 35b-3 are electrically connected to each other via the via V5a, and the first reflective layer 35-3 and the first electrode 32, the 1a residual reflective layer 35a-3 and the first electrode 32, and the 1b residual reflective layer 35b-3 and the first electrode 32 are electrically connected to each other once via each of the 3a residual reflective layer 37a-3, the 3b residual reflective layer 37b-3, and the third reflective layer 37-3 formed along the hole H, the process for forming the via can be reduced from three times to two times. This process simplification not only reduces the process tact time and thus shortens the development schedule time, but also reduces manufacturing costs by reducing the number of via masks.

[0154] Fig.15 It is used to illustrate Fig.14 A diagram showing the connection principle between the reflective layers.

[0155] Reference Fig.15 In the case of a red sub-pixel, after forming a hole (or via hole) Ha penetrating the first insulating layer 22 covering the fourth metal layer M4 and then forming a via V5a in the hole Ha, the first reflective layer 35-3, the second insulating layer 24, the 2a residual reflective layer 36a-3 and the third insulating layer 26 are stacked in sequence.

[0156] After forming a hole (or via hole) Hb penetrating the second insulating layer 24, the 2a residual reflective layer 36a-3 and the third insulating layer 26, and then forming the 3a residual reflective layer 37a-3 along the hole Hb, the first electrode 32 is formed on the upper portion of the 3a residual reflective layer 37a-3.

[0157] The fourth metal layer M4 and the first reflective layer 35-3 are connected to each other via one via V5a, and the first reflective layer 35-3 is electrically connected to the 3a residual reflective layer 37a-3 via one hole Hb, that is, via the 3a residual reflective layer 37a-3 formed along one hole Hb. Since the first electrode 32 is formed on the upper portion of the 3a residual reflective layer 37a-3, the fourth metal layer M4 and the first electrode 32 can be electrically connected to each other.

[0158] In addition, the green sub-pixel and the blue sub-pixel may be formed by the same process.

[0159] The display panel of the above-described embodiment can realize a left-eye screen and a right-eye screen of a personal immersive device.

[0160] Fig.16 FIG. 1 is a diagram illustrating an example of the appearance of a personal immersive device. The appearance of the personal immersive device is not limited to Fig.16 .

[0161] Reference Fig.16 The personal immersive device may be manufactured as an HMD type appearance design including a main body 1000 and a head-mounted band 1100 .

[0162] The main body 1000 may include the display panel of the above-mentioned embodiment, a lens disposed opposite to the screen of the display panel, a display panel driver, a system controller, a plurality of sensors, etc. The main body 1000 may further include a camera. The lens may include an eyepiece or a fisheye lens. The display panel driver receives pixel data of an input image and drives pixels to display the input image on the pixels of the display panel.

[0163] The system controller may include: an external device interface connected to a sensor, a camera, etc. and connected to a memory or an external video source; a user interface for receiving user commands; and one or more processors connected to a power supply for generating power. The sensor includes various sensors such as a gyro sensor and an acceleration sensor. The sensor transmits its output to the system controller. The system controller may receive the output of the sensor, move the pixel data of the image displayed on the pixel of the display panel in synchronization with the movement of the user, and execute a foveated rendering algorithm that follows the user's gaze.

[0164] The personal immersive device can be implemented using a mobile terminal system such as a smart phone. In this case, the left eye image and the right eye image can be displayed together on the display panel of the mobile terminal system. The smart phone supports the VR mode as an example of a partial mode. In the VR mode of the smart phone, the left eye image and the right eye image can be displayed together on a single display panel in a separated manner. In this case, Fig.15 The structure of the main body 1000 is simplified, and the mobile terminal system supporting the VR mode is detachably mounted on the main body 1000.

[0165] Fig.17 is a block diagram illustrating an example of a display device that may be applied to a personal immersive device.

[0166] Reference Fig.17 , the display device may include: a first display panel 100A, on which a left-eye image is displayed; and a second display panel 100B, on which a right-eye image is displayed.

[0167] The display panels 100A and 100B include data lines DL, gate lines GL, and pixels PIX. The screens of the display panels 100A and 100B include a pixel array on which an image is displayed. The pixel array includes pixel rows L1 to Ln, wherein pixel data is written to the pixel rows L1 to Ln by sequentially scanning via a scanning pulse shifted along a scanning direction.

[0168] The display panel driver may include data drivers 111 and 112, gate drivers 121 and 122, a controller 130, etc. The data drivers 111 and 112 and the gate drivers 121 and 122 may be separated for each of the display panels 100A and 100B, and the controller 130 may be shared.

[0169] The data drivers 111 and 112 convert pixel data input from the controller 130 into voltage or current to provide data signals to pixels.

[0170] The gate drivers 121 and 122 sequentially output scan pulses synchronized with the data signals output from the data drivers 111 and 112 under the control of the controller 130.

[0171] Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not limited thereto, and the present invention can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided for illustrative purposes only, and these embodiments are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present invention.

Claims

1. A display panel, comprising: forming a plurality of metal layers on each of the first sub-pixel, the second sub-pixel, and the third sub-pixel; a first insulating layer covering the plurality of metal layers; a first reflective layer formed on an upper portion of the first insulating layer of the first sub-pixel; a second insulating layer covering the first reflective layer; a second reflective layer formed on the second insulating layer of the second sub-pixel; a third insulating layer covering the second reflective layer; a third reflective layer formed on the third insulating layer of the third sub-pixel; and a plurality of first electrodes, wherein the first electrodes are formed on the third insulating layer of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, A plurality of holes are formed therein, the holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, The metal layer of each of the first subpixel, the second subpixel, and the third subpixel is electrically connected to the first electrode of each of the first subpixel, the second subpixel, and the third subpixel via each hole.

2. The display panel according to claim 1, further comprising: a first residual reflective layer formed on an upper portion of the first insulating layer of each of the second sub-pixel and the third sub-pixel; a second residual reflective layer formed on an upper portion of the second insulating layer of each of the first sub-pixel and the third sub-pixel; as well as A third residual reflective layer is formed on an upper portion of the third insulating layer of each of the first sub-pixel and the second sub-pixel. 3 . The display panel of claim 2 , wherein each of the first, second, and third residual reflective layers is formed to have a size smaller than that of each of the first, second, and third reflective layers. 4 . The display panel of claim 3 , wherein the first residual reflective layer, the second residual reflective layer, and the third residual reflective layer are formed to have different sizes according to a wavelength band of light.

5. The display panel according to claim 1, wherein a passage is formed in each of the plurality of holes, The metal layer is electrically connected to the first electrode via the formed via.

6. The display panel according to claim 2, wherein the third residual reflective layer formed on the upper portion of the third insulating layer of each of the first sub-pixel and the second sub-pixel and each of the third reflective layers formed on the upper portion of the third insulating layer of the third sub-pixel have: an upper surface in contact with the first electrode; and a lower surface electrically connected to the metal layer via a path formed in each hole.

7. The display panel according to claim 2, wherein each of the plurality of holes comprises a first hole and a second hole, The first hole penetrates the first insulating layer, The second hole penetrates the second insulating layer and the third insulating layer.

8. The display panel according to claim 7, wherein the first reflective layer of the first sub-pixel and the first residual reflective layers of the second sub-pixel and the third sub-pixel are electrically connected to the metal layer via a via formed in the first hole, and are electrically connected to the first electrode via a via formed in the second hole. 9 . The display panel of claim 2 , wherein the third residual reflective layers of the first and second sub-pixels and the third reflective layer of the third sub-pixel extend along one hole to be electrically connected to each metal layer.

10. The display panel according to claim 9, wherein the third residual reflective layer of the first sub-pixel and the second sub-pixel and the third reflective layer of the third sub-pixel have: an upper surface that is in contact with the first electrode and is formed in a portion of the third insulating layer; and a lower surface that is in contact with each metal layer and is formed along a portion of each hole.

11. The display panel according to claim 9, wherein each of the plurality of holes comprises a first hole and a second hole, The first hole penetrates the first insulating layer, The second hole penetrates the second insulating layer and the third insulating layer.

12. The display panel according to claim 11, wherein the first reflective layer of the first sub-pixel and the first residual reflective layers of the second sub-pixel and the third sub-pixel are electrically connected to the metal layer via a path formed in the first hole, and are electrically connected to each first electrode via the third residual reflective layer of the first sub-pixel and the second sub-pixel and the third reflective layer of the third sub-pixel formed along the second hole.

13. The display panel according to claim 1, further comprising: a second residual reflective layer formed on an upper portion of the second insulating layer of the first sub-pixel; as well as A third residual reflective layer is formed on an upper portion of the third insulating layer of each of the first sub-pixel and the second sub-pixel. 14 . The display panel according to claim 1 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. 15 . The display panel of claim 14 , wherein an insulating layer between the first electrode of the red sub-pixel and the first reflective layer is thicker than an insulating layer between the first electrode of the green sub-pixel and the second reflective layer. 16 . The display panel according to claim 15 , wherein the first electrode of the blue sub-pixel contacts the third reflective layer.

17. The display panel according to claim 1, further comprising a residual reflective layer formed in each sub-pixel, Wherein in each sub-pixel, the residual reflective layer is formed on an insulating layer different from a layer on which a corresponding reflective layer is formed.

18. A display panel, comprising: Metal layer; a first insulating layer covering the metal layer; a first reflective layer formed on an upper portion of the first insulating layer; a second insulating layer covering the first reflective layer; a second reflective layer formed on an upper portion of the second insulating layer; a third insulating layer covering the second reflective layer; a third reflective layer formed on an upper portion of the third insulating layer; as well as a first electrode formed on an upper portion of the third insulating layer, A hole is formed therein, penetrating the first insulating layer, the second insulating layer, and the third insulating layer, and the metal layer is electrically connected to the first electrode via the hole.

19. The display panel according to claim 18, wherein One of the first reflective layer, the second reflective layer, and the third reflective layer is formed to have the same size as the first electrode according to the color of the sub-pixel, Each of the remaining two reflective layers is formed to have a size smaller than that of the first electrode.

20. The display panel according to claim 18, wherein the metal layer is formed on each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, The display panel further comprises a residual reflective layer formed in each sub-pixel, Wherein in each sub-pixel, the residual reflective layer is formed on an insulating layer different from a layer on which a corresponding reflective layer is formed. 21 . The display panel according to claim 20 , wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. 22 . The display panel of claim 21 , wherein an insulating layer between the first electrode of the red sub-pixel and the first reflective layer is thicker than an insulating layer between the first electrode of the green sub-pixel and the second reflective layer. 23 . The display panel according to claim 22 , wherein the first electrode of the blue sub-pixel contacts the third reflective layer.

24. An electronic device comprising: The display panel according to claim 1 or 18; as well as A display panel driver is used to drive the display panel.

Images