Piezoelectric composite substrate for reducing wafer warping and preparation method and application thereof

Abstract

The invention belongs to the technical field of semiconductor preparation, and particularly relates to a piezoelectric composite substrate capable of reducing wafer warping and a preparation method and application of the piezoelectric composite substrate. The preparation method comprises the following steps: carrying out ion implantation on a piezoelectric wafer in sequence to obtain a first wafer implantation sheet which sequentially comprises a thin film layer, an implantation layer and a residual layer; soaking the first wafer injection sheet in mixed acid liquor containing hydrofluoric acid and inorganic oxyacid to obtain a second wafer injection sheet; bonding the thin film layer of the second wafer injection sheet with the supporting substrate to obtain a bonding body; and annealing the bonding body, and removing the injection layer and the residual layer to obtain the piezoelectric composite substrate. According to the method, the piezoelectric wafer after ion implantation is placed in the mixed acid solution to be soaked, on one hand, thermal stress in the piezoelectric wafer can be effectively released, on the other hand, particle pollution on the surface of the implanted wafer can be removed, and bubbles caused by particles in the bonding process can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor preparation, and in particular relates to a piezoelectric composite substrate capable of reducing wafer warpage, and a preparation method and application thereof. Background Art

[0002] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention, and should not necessarily be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art.

[0003] As people pursue the increasing data transmission speed, performance and power consumption of telecommunication equipment, people need to provide acoustic filters that work at higher frequencies and larger bandwidths to achieve higher data transmission. In recent years, filters based on piezoelectric composite substrates with piezoelectric single crystal films can effectively improve the center frequency and bandwidth of the filter, reduce power consumption and reduce heat dissipation.

[0004] The general preparation method of piezoelectric composite substrate is to transfer the piezoelectric single crystal material to the required substrate using an ion beam stripping method. However, during the ion implantation process, a large amount of thermal effects will be generated during the implantation process, resulting in obvious warping of the piezoelectric wafer after implantation, which will have an adverse effect on the subsequent process, easily causing the composite film to break, and increasing the production cost of the composite film. In order to improve the wafer warping, the prior art suppresses the warping of the wafer by designing a special structure or offsets the warping of both sides by ion implantation or etching on the other side. CN117597008A performs wafer bonding twice on the piezoelectric wafer with the first supporting substrate and the second supporting substrate in sequence to obtain a composite bonding structure with rigidity, which can effectively suppress the uneven thermal expansion of the piezoelectric wafer. CN105702564B deposits a stress film on the wafer first, then patterns the wafer through a photolithography process, protects the stress film in a specific area with a photoresist, and then performs an ion implantation process on the wafer, so that the stress in a specific direction can be released, thereby being able to make targeted adjustments to the warping degree in a specific direction of the wafer. CN113053747B forms a first back doping region corresponding to the front doping region on the back of the wafer, so that the stresses generated by the back ion implantation and the front ion implantation can offset each other. Although the above prior art can reduce the warping degree of the wafer, it requires the use of complex bonding structures, photolithography patterns and other structures or the use of multi-faceted ion implantation, which increases the production cost. Summary of the invention

[0005] In order to solve the deficiencies of the prior art, the present invention provides a piezoelectric composite substrate with reduced wafer warpage, and a preparation method and application thereof. The present invention can effectively release the thermal stress in the piezoelectric wafer and reduce the wafer warpage by placing the piezoelectric wafer after ion implantation in a mixed acid solution for immersion, thereby obtaining a piezoelectric composite substrate with reduced wafer warpage.

[0006] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0007] In a first aspect, the present invention provides a method for preparing a piezoelectric composite substrate with reduced wafer warpage, comprising the following steps:

[0008] Performing ion implantation on the piezoelectric wafer in sequence to obtain a first wafer implantation sheet including a thin film layer, an implantation layer and a residual layer in sequence;

[0009] Soaking the first wafer implantation sheet in a mixed acid solution containing hydrofluoric acid and an inorganic oxygen-containing acid to obtain a second wafer implantation sheet;

[0010] bonding the thin film layer of the second wafer implantation sheet to the support substrate to obtain a bonded body;

[0011] The bonded body is annealed to remove the implanted layer and the residual layer, thus obtaining a piezoelectric composite substrate.

[0012] Preferably, the piezoelectric wafer comprises one of lithium niobate, lithium tantalate, quartz, lithium tetraborate and lanthanum gallium silicate, the diameter of the piezoelectric wafer is 4 to 12 inches, and the thickness of the piezoelectric wafer is 100 to 1000 μm.

[0013] Preferably, the ions implanted include at least one of hydrogen ions and helium ions, the energy of the ion implantation is 50 to 500 KeV, and the dose of the ion implantation is 3×10 15 ~5×10 18 ions / cm 2 , the thickness of the thin film layer is 50 to 1000 nm.

[0014] Preferably, the inorganic oxygen-containing acid includes sulfuric acid or nitric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:(1-3), the volume ratio of hydrofluoric acid to nitric acid is 1:(1-5), and the soaking time is 5-1200 min.

[0015] Preferably, the material of the support substrate includes at least one of sapphire, silicon, silicon carbide, quartz, diamond, gallium nitride and gallium arsenide, the diameter of the support substrate is 4 to 12 inches, and the thickness of the support substrate is 100 to 1000 μm.

[0016] Preferably, an intermediate layer is arranged on the supporting substrate, the intermediate layer is a single-layer structure, the thin film layer of the second wafer injection piece is bonded to the intermediate layer of the supporting substrate, the material of the intermediate layer includes at least one of silicon dioxide, silicon nitride, aluminum oxide and aluminum nitride, and the thickness of the intermediate layer is 50 to 5000 nm.

[0017] Preferably, an intermediate layer is arranged on the supporting substrate, and the intermediate layer comprises a defect layer and an isolation layer which are sequentially stacked on the supporting substrate, and the thin film layer of the second wafer injection piece is bonded to the isolation layer of the supporting substrate, and the material of the defect layer comprises at least one of polycrystalline silicon, amorphous silicon and polycrystalline germanium, and the material of the isolation layer comprises at least one of silicon dioxide, silicon nitride, aluminum oxide and aluminum nitride, and the thickness of the defect layer is 100 to 3000 nm.

[0018] Preferably, the annealing temperature is 80° C. to 800° C., and the annealing time is 0.5 to 60 hours.

[0019] In a second aspect, the present invention provides a piezoelectric composite substrate with reduced wafer warpage, which is obtained by the preparation method described in the first aspect.

[0020] In a third aspect, the present invention provides use of the piezoelectric composite substrate according to the second aspect in preparing a semiconductor device including an acoustic filter.

[0021] The beneficial effects achieved by one or more technical solutions of the present invention are as follows:

[0022] The present invention places the piezoelectric wafer after ion implantation in a mixed acid solution for immersion, which can effectively release the thermal stress in the piezoelectric wafer on the one hand, and remove the particle contamination on the surface of the implanted wafer on the other hand, which is beneficial to reduce the bubbles caused by particles during the bonding process. The preparation method can effectively reduce the wafer warpage, is beneficial to the development of subsequent processes, improves the yield rate of piezoelectric single crystal thin films, and reduces the production cost of piezoelectric composite substrates.

[0023] The immersion process in the mixed acid solution of the present invention does not affect the implementation of other processes, and there is no need to design a special structure or change process parameters. The mixed acid solution can be recycled, has low cost and can be applied to the preparation process of different piezoelectric single crystal films or piezoelectric composite substrates.

[0024] The piezoelectric composite substrate obtained by the present invention has low deformation degree and high yield rate, and can effectively improve the center frequency and bandwidth of the filter when applied to the acoustic filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0026] Figure 1 The process flow chart of the method for preparing a piezoelectric composite substrate with reduced wafer warpage in the present invention;

[0027] Figure 2 It is a schematic structural flow diagram of a method for preparing a piezoelectric composite substrate for reducing wafer warpage in the present invention;

[0028] Figure 3 A schematic diagram of the structural flow of a method for preparing a supporting substrate provided with an intermediate layer in the present invention;

[0029] Figure 4 A schematic diagram of the structural process of preparing a support substrate provided with an intermediate layer including a defect layer and an isolation layer in the present invention;

[0030] In the accompanying drawings, the numbers correspond to: 100-piezoelectric wafer, 110-first wafer injection piece, 1101-thin film layer, 1102-injection layer, 1103-residual layer, 120-second wafer injection piece, 130-support substrate, 140-bonding body, 150-intermediate layer, 1501-defect layer, 1502-isolation layer. DETAILED DESCRIPTION

[0031] As described in the background technology, a large amount of thermal effect will be generated during the ion implantation process, resulting in obvious warping of the piezoelectric wafer after implantation. Although the existing technology can reduce the degree of wafer warping, it requires the use of complex bonding structures, photolithography patterns and other structures or the use of multi-faceted ion implantation and etching, which increases production costs.

[0032] In order to solve the above problems, an embodiment of the present invention provides a piezoelectric composite substrate with reduced wafer warpage, a preparation method and an application thereof.

[0033] Specifically, a method for preparing a piezoelectric composite substrate with reduced wafer warpage is as follows: Figure 1 and Figure 2 As shown, the following steps are included:

[0034] S1, performing ion implantation on the piezoelectric wafer 100 in sequence to obtain a first wafer implantation sheet 110 which includes a thin film layer 1101, an implantation layer 1102 and a residual layer 1103 in sequence;

[0035] S2, soaking the first wafer implantation sheet 110 in a mixed acid solution containing hydrofluoric acid and an inorganic oxygen-containing acid to obtain a second wafer implantation sheet 120;

[0036] S3, bonding the thin film layer 1101 of the second wafer implantation sheet 120 to the support substrate 130 to obtain a bonded body 140;

[0037] S4, annealing the bonded body 140, removing the implanted layer 1102 and the residual layer 1103, and obtaining a piezoelectric composite substrate.

[0038] In an embodiment of the present invention, the piezoelectric wafer 100 includes one of lithium niobate, lithium tantalate, quartz, lithium tetraborate and lanthanum gallium silicate, the diameter of the piezoelectric wafer 100 is 4 to 12 inches, and the thickness of the piezoelectric wafer is 100 to 1000 μm.

[0039] In an embodiment of the present invention, the ions implanted include at least one of hydrogen ions and helium ions, the energy of the ion implantation is 50 to 500 KeV, and the dose of the ion implantation is 3×10 15 ~5×10 18 ions / cm 2 , the thickness of the thin film layer 1101 is 50 to 1000 nm.

[0040] The present invention does not specifically limit the method of ion implantation, and any ion implantation method in the prior art can be used, and the implanted ions can be ions that can generate gas through heat treatment. The thickness of the thin film layer 1101 is adjusted by adjusting the energy of the ion implantation. Specifically, the greater the energy of the ion implantation, the greater the thickness of the prepared thin film layer 1101; conversely, the smaller the energy of the ion implantation, the smaller the thickness of the prepared thin film layer 1101. At the same time, the depth of the implanted layer 1102 is adjusted by adjusting the ion implantation energy. Specifically, the greater the energy of the ion implantation, the deeper the depth of the implanted layer 1102; conversely, the smaller the energy of the ion implantation, the shallower the depth of the implanted layer 1102. The implantation time is controlled according to the thickness of the thin film layer 1101.

[0041] In an embodiment of the present invention, the inorganic oxygen-containing acid includes sulfuric acid or nitric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:(1-3), the volume ratio of hydrofluoric acid to nitric acid is 1:(1-5), and the immersion time is 5-1200 min.

[0042] The first wafer implantation sheet 110 is immersed in the mixed acid solution, which can effectively release the thermal stress in the piezoelectric wafer and reduce the wafer warpage; at the same time, the particle contamination on the surface of the implantation sheet is removed, which is conducive to reducing the bubbles caused by particles during the bonding process. Immersing in the mixed acid solution does not affect the progress of the previous and next processes, and there is no need to adjust the parameters of the previous and next processes. In addition, the mixed acid solution can be recycled, which reduces the cost.

[0043] In an embodiment of the present invention, the material of the support substrate 130 includes at least one of sapphire, silicon, silicon carbide, quartz, diamond, gallium nitride and gallium arsenide, the diameter of the support substrate 130 is 4 to 12 inches, and the thickness of the support substrate 130 is 100 to 1000 μm.

[0044] In an embodiment of the present invention, before bonding the thin film layer 1101 of the second wafer implantation sheet 120 to the support substrate 130, the surfaces to be bonded of the thin film layer 1101 and the support substrate 130 are cleaned. The cleaning method is not particularly limited, and any one of the prior art can be used. The bonding method is not particularly limited, and any one of the prior art can be used, such as plasma bonding and surface activation bonding. The surface activation method is not particularly limited, and any one of the prior art can be used, such as plasma activation or chemical solution activation.

[0045] In an embodiment of the present invention, an intermediate layer 150 is arranged on the supporting substrate 130, and the intermediate layer 150 is a single-layer structure. The thin film layer 1101 of the second wafer injection piece 120 is bonded to the intermediate layer 150 of the supporting substrate 130. The material of the intermediate layer 150 includes at least one of silicon dioxide, silicon nitride, aluminum oxide and aluminum nitride, and the thickness of the intermediate layer 150 is 50 to 5000 nm.

[0046] like Figure 3 As shown, the intermediate layer 150 is disposed on the support substrate 130 by deposition, and the deposition method is not particularly limited, and may be chemical vapor deposition (CVD), physical vapor deposition (PVD) or magnetron sputtering.

[0047] In an embodiment of the present invention, an intermediate layer 150 is arranged on the supporting substrate 130, and the intermediate layer 150 includes a defect layer 1501 and an isolation layer 1502 which are sequentially stacked on the supporting substrate. The thin film layer 1101 of the second wafer injection piece 120 is bonded to the isolation layer 1502 of the supporting substrate 130. The material of the defect layer 1501 includes at least one of polycrystalline silicon, amorphous silicon and polycrystalline germanium. The material of the isolation layer 1502 includes at least one of silicon dioxide, silicon nitride, aluminum oxide and aluminum nitride. The thickness of the defect layer 1501 is 100 to 3000 nm.

[0048] When the active layer composed of insulating material is in direct contact with the insulating layer composed of semiconductor material, there will be many defect energy levels in the insulating layer at the interface, and the defect energy levels can attract carriers. The carriers in the semiconductor substrate layer are attracted to the vicinity of the interface between the two by the defect energy levels in the insulating layer, thereby generating a parasitic surface conductivity effect (PSC) in the semiconductor substrate layer. This greatly reduces the effective resistivity of the substrate near the interface by more than one order of magnitude, which has a bad impact on the final performance of the components prepared by the thin film structure material based on the insulator substrate, and limits the ability of the substrate to meet the next generation performance requirements. There is a certain density of lattice defects in the defect layer 1501, which can capture the carriers existing between the isolation layer 1502 and the supporting substrate 130, and prevent these carriers from causing carrier aggregation at the isolation layer 1502 and the supporting substrate 130, thereby suppressing PSC and reducing the loss of the composite film.

[0049] like Figure 4 As shown, a defect layer 1501 is first prepared on a supporting substrate 130, and then an isolation layer 1502 is prepared on the defect layer 1501. Both the defect layer 1501 and the isolation layer 1502 are prepared by deposition, and the deposition method is not particularly limited, and can be chemical vapor deposition (CVD), physical vapor deposition (PVD) or magnetron sputtering.

[0050] In the embodiment of the present invention, the annealing temperature is 80°C to 800°C, and the annealing time is 0.5 to 60 hours. During the annealing process, the ions in the injection layer 1102 form bubbles, such as hydrogen ions forming hydrogen gas. The long-term annealing and heat preservation make the bubbles in the injection layer 1102 connected into one piece, and finally the injection layer 1102 is broken, and the residual layer 1103 is separated from the film layer 1101.

[0051] In an embodiment of the present invention, the thin film layer 1103 is polished and thinned.

[0052] In order to enable those skilled in the art to more clearly understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below in combination with specific embodiments and comparative examples.

[0053] Example 1

[0054] A 4-inch lithium tantalate wafer and a silicon carbide wafer are provided, and the two wafers are cleaned by semiconductor-level RCA so that they have clean surfaces. The lithium tantalate wafer is used as the piezoelectric wafer 100 , and the silicon carbide wafer is used as the supporting substrate 130 .

[0055] Ion implantation is performed on the piezoelectric wafer 100, with an implantation dose of 3×10 16 ions / cm 2The implantation energy is 150 KeV, forming a first implanted wafer 110 having a thin film layer 1101 , an implanted layer 1102 and a residual layer 1103 .

[0056] The first implanted wafer 110 is immersed in a solution of hydrofluoric acid and nitric acid, the volume ratio of hydrofluoric acid to nitric acid is 1:2, and the immersion time is 2 hours to obtain a second implanted wafer 120. The second implanted wafer 120 is cleaned at the semiconductor level to obtain a clean surface.

[0057] The thin film layer 1101 of the second injection wafer 120 and the surface to be bonded of the support substrate 130 are subjected to surface activation treatment, and the activated thin film layer 1101 of the second injection wafer 120 and the surface to be bonded of the support substrate 130 are bonded at room temperature to obtain a bonded body 140 .

[0058] The bonded body 140 is annealed at a temperature of 300° C. for 2 hours, and the injection layer 1102 is broken to separate the thin film layer 1101 from the residual layer 1103 to obtain a piezoelectric composite substrate.

[0059] The piezoelectric composite substrate is fixed on a porous ceramic chuck of a polishing device, then subjected to chemical mechanical polishing, and finally to RCA cleaning.

[0060] Example 2

[0061] A 6-inch lithium tantalate wafer and a silicon wafer are provided, and the two wafers are cleaned by semiconductor-level RCA so as to have a clean surface. The lithium tantalate wafer is used as the piezoelectric wafer 100 , and the silicon wafer is used as the supporting substrate 130 .

[0062] The piezoelectric wafer 100 is implanted with hydrogen ions, and the implantation dose is 7×10 16 ions / cm 2 The implantation energy is 200 KeV, forming a first implanted wafer 110 having a thin film layer 1101 , an implanted layer 1102 and a residual layer 1103 .

[0063] The first implanted wafer 110 is immersed in a solution of hydrofluoric acid and sulfuric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:1.5, and the immersion time is 5 hours to obtain a second implanted wafer 120. Then, the second implanted wafer 120 is cleaned at the semiconductor level to obtain a clean surface.

[0064] Polysilicon is deposited on the support substrate 130 by using the LPCVD process to form a defect layer 1501. The deposition temperature is 600°C, and the thickness of the deposited defect layer 1501 is 500nm.

[0065] Silicon dioxide is deposited on the defective layer 1501 by PECVD to form an isolation layer 1502 with a deposition thickness of 600 nm. Chemical mechanical polishing is then performed to obtain a smooth surface, and finally RCA cleaning is performed to obtain a clean surface.

[0066] The thin film layer 1101 of the second wafer implantation sheet 120 and the isolation layer 1502 of the support substrate 130 are subjected to surface activation treatment, and the activated thin film layer 1101 and the isolation layer 1502 are directly contacted and bonded together at room temperature to form a bonding body 140 .

[0067] The bonded body 140 is annealed at a temperature of 240° C. for 8 hours to separate the thin film layer 1101 from the residual layer 1103 to obtain a piezoelectric composite substrate.

[0068] The piezoelectric composite substrate is fixed on a porous ceramic chuck of a polishing device, then subjected to chemical mechanical polishing, and finally to RCA cleaning.

[0069] Example 3

[0070] A 6-inch lithium niobate wafer and a silicon wafer are provided, and the two wafers are cleaned by semiconductor-level RCA so as to have a clean surface. The lithium tantalate wafer is used as the piezoelectric wafer 100 , and the silicon wafer is used as the supporting substrate 130 .

[0071] The piezoelectric wafer 100 is implanted with hydrogen ions at a dose of 2×10 16 ions / cm 2 The implantation energy is 120 KeV, forming a first implanted wafer 110 having a thin film layer 1101 , an implanted layer 1102 and a residual layer 1103 .

[0072] The first implanted wafer 110 is immersed in a solution of hydrofluoric acid and sulfuric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:3, and the immersion time is 1 hour to obtain a second implanted wafer 120. Then, the second implanted wafer 120 is cleaned at the semiconductor level to obtain a clean surface.

[0073] Silicon dioxide is deposited on the cleaned support substrate 130 by using a PECVD process to form an intermediate layer 150, and the deposited intermediate layer 150 has a thickness of 1000 nm. Chemical mechanical polishing is then performed to obtain a smooth surface, and finally RCA cleaning is performed to obtain a clean surface.

[0074] The thin film layer 1101 and the intermediate layer 150 are subjected to surface activation treatment, and the activated thin film layer 1101 and the intermediate layer 150 are directly contacted and bonded together at room temperature to form a bonding body 140 .

[0075] The bonded body 140 is annealed at a temperature of 320° C. for 6 hours to separate the thin film layer 1101 from the residual layer 1103 to obtain a piezoelectric composite substrate.

[0076] The piezoelectric composite substrate is fixed on a porous ceramic chuck of a polishing device, then subjected to chemical mechanical polishing, and finally to RCA cleaning.

[0077] Example 4

[0078] A 6-inch lithium tantalate wafer and a silicon wafer are provided, and the two wafers are cleaned by semiconductor-level RCA so as to have a clean surface. The lithium tantalate wafer is used as the piezoelectric wafer 100 , and the silicon wafer is used as the supporting substrate 130 .

[0079] The piezoelectric wafer 100 is implanted with hydrogen ions, and the implantation dose is 3×10 15 ions / cm 2 The implantation energy is 50 KeV, forming a first implanted wafer 110 having a thin film layer 1101 , an implanted layer 1102 and a residual layer 1103 .

[0080] The first implanted wafer 110 is immersed in a solution of hydrofluoric acid and sulfuric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:1, and the immersion time is 5 minutes to obtain a second implanted wafer 120. Then, the second implanted wafer 120 is cleaned at the semiconductor level to obtain a clean surface.

[0081] Polysilicon is deposited on the support substrate 130 by using the LPCVD process to form a defect layer 1501. The deposition temperature is 600°C, and the thickness of the deposited defect layer 1501 is 100 nm.

[0082] Silicon dioxide is deposited on the defective layer 1501 by PECVD to form an isolation layer 1502 with a deposition thickness of 50 nm, and then chemical mechanical polishing is performed to obtain a smooth surface, and finally RCA cleaning is performed to obtain a clean surface.

[0083] The thin film layer 1101 of the second wafer implantation sheet 120 and the isolation layer 1502 of the support substrate 130 are subjected to surface activation treatment, and the activated thin film layer 1101 and the isolation layer 1502 are directly contacted and bonded together at room temperature to form a bonding body 140 .

[0084] The bonded body 140 is annealed at a temperature of 80° C. for 60 hours to separate the thin film layer 1101 from the residual layer 1103 to obtain a piezoelectric composite substrate.

[0085] The piezoelectric composite substrate is fixed on a porous ceramic chuck of a polishing device, then subjected to chemical mechanical polishing, and finally to RCA cleaning.

[0086] Example 5

[0087] A 6-inch lithium tantalate wafer and a silicon wafer are provided, and the two wafers are cleaned by semiconductor-level RCA so as to have a clean surface. The lithium tantalate wafer is used as the piezoelectric wafer 100 , and the silicon wafer is used as the supporting substrate 130 .

[0088] The piezoelectric wafer 100 is implanted with hydrogen ions, and the implantation dose is 5×10 18 ions / cm 2 The implantation energy is 500 KeV, forming a first implanted wafer 110 having a thin film layer 1101 , an implanted layer 1102 and a residual layer 1103 .

[0089] The first implanted wafer 110 is immersed in a solution of hydrofluoric acid and sulfuric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:5, and the immersion time is 60 hours to obtain a second implanted wafer 120. Then, the second implanted wafer 120 is cleaned at the semiconductor level to obtain a clean surface.

[0090] Polysilicon is deposited on the support substrate 130 by using the LPCVD process to form a defect layer 1501. The deposition temperature is 600°C, and the thickness of the deposited defect layer 1501 is 3000nm.

[0091] Silicon dioxide is deposited on the defective layer 1501 by PECVD to form an isolation layer 1502 with a deposition thickness of 2000 nm. Chemical mechanical polishing is then performed to obtain a smooth surface, and finally RCA cleaning is performed to obtain a clean surface.

[0092] The thin film layer 1101 of the second wafer implantation sheet 120 and the isolation layer 1502 of the support substrate 130 are subjected to surface activation treatment, and the activated thin film layer 1101 and the isolation layer 1502 are directly contacted and bonded together at room temperature to form a bonding body 140 .

[0093] The bonded body 140 is annealed at a temperature of 800° C. for a holding time of 0.5 h to separate the thin film layer 1101 from the residual layer 1103 to obtain a piezoelectric composite substrate.

[0094] The piezoelectric composite substrate is fixed on a porous ceramic chuck of a polishing device, then subjected to chemical mechanical polishing, and finally to RCA cleaning.

[0095] Comparative Example 1

[0096] Different from the first embodiment, the first implanted wafer 110 is not immersed in the solution of hydrofluoric acid and nitric acid.

[0097] Comparative Example 2

[0098] Different from the second embodiment, the first implanted wafer 110 is not immersed in the solution of hydrofluoric acid and nitric acid.

[0099] Comparative Example 3

[0100] Different from the third embodiment, the first implanted wafer 110 is not immersed in the solution of hydrofluoric acid and nitric acid.

[0101] The warpage and bending tests were performed on the piezoelectric composite substrates obtained in Examples 1 to 5 and Comparative Examples 1 to 3. The results are shown in Table 1.

[0102] Table 1 Warpage and curvature of piezoelectric composite substrate

[0103] Experiment number Warpage(um) Curvature(um) Example 1 11.881 -4.525 Example 2 9.002 6.924 Example 3 13.919 11.791 Example 4 10.251 8.421 Example 5 10.201 -0.591 Comparative Example 1 40.929 44.022 Comparative Example 2 56.620 13.878 Comparative Example 3 42.167 46.315

[0104] The deformation degrees of the thin film layer 1101 in the piezoelectric composite substrates obtained in Example 1 and Comparative Example 1, Example 2 and Comparative Example 2, and Example 3 and Comparative Example 3 were compared respectively. Since the thermal stress in the piezoelectric wafer was effectively released by immersing the piezoelectric wafer after ion implantation in a mixed acid solution in the embodiments, the warping and curvature of the piezoelectric composite substrate were significantly reduced, indicating that the wafer warping was effectively suppressed.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a piezoelectric composite substrate with reduced wafer warpage, characterized in that: The following steps are involved: Performing ion implantation on the piezoelectric wafer in sequence to obtain a first wafer implantation sheet including a thin film layer, an implantation layer and a residual layer in sequence; Soaking the first wafer implantation sheet in a mixed acid solution containing hydrofluoric acid and an inorganic oxygen-containing acid to obtain a second wafer implantation sheet; bonding the thin film layer of the second wafer implantation sheet to the support substrate to obtain a bonded body; The bonded body is annealed to remove the implanted layer and the residual layer, thus obtaining a piezoelectric composite substrate.

2. The preparation method according to claim 1, characterized in that The piezoelectric wafer comprises one of lithium niobate, lithium tantalate, quartz, lithium tetraborate and lanthanum gallium silicate. The diameter of the piezoelectric wafer is 4 to 12 inches, and the thickness of the piezoelectric wafer is 100 to 1000 μm.

3. The preparation method according to claim 1, characterized in that: The ions implanted include at least one of hydrogen ions and helium ions. The energy of the ion implantation is 50 to 500 KeV, and the dose of the ion implantation is 3×10 15 ~5×10 18 ions / cm 2 , the thickness of the thin film layer is 50 to 1000 nm.

4. The preparation method according to claim 1, characterized in that: The inorganic oxygen-containing acid includes sulfuric acid or nitric acid, the volume ratio of hydrofluoric acid to sulfuric acid is 1:(1-3), the volume ratio of hydrofluoric acid to nitric acid is 1:(1-5), and the soaking time is 5-1200 minutes.

5. The preparation method according to claim 1, characterized in that: The material of the support substrate includes at least one of sapphire, silicon, silicon carbide, quartz, diamond, gallium nitride and gallium arsenide. The diameter of the support substrate is 4 to 12 inches, and the thickness of the support substrate is 100 to 1000 μm.

6. The preparation method according to claim 1, characterized in that: An intermediate layer is arranged on the supporting substrate, and the intermediate layer is a single-layer structure. The thin film layer of the second wafer injection piece is bonded to the intermediate layer of the supporting substrate. The material of the intermediate layer includes at least one of silicon dioxide, silicon nitride, aluminum oxide and aluminum nitride. The thickness of the intermediate layer is 50 to 5000 nm.

7. The preparation method according to claim 1, characterized in that: An intermediate layer is arranged on the supporting substrate, and the intermediate layer includes a defect layer and an isolation layer stacked in sequence on the supporting substrate. The thin film layer of the second wafer injection piece is bonded to the isolation layer of the supporting substrate. The material of the defect layer includes at least one of polycrystalline silicon, amorphous silicon and polycrystalline germanium. The material of the isolation layer includes at least one of silicon dioxide, silicon nitride, aluminum oxide and aluminum nitride. The thickness of the defect layer is 100 to 3000 nm.

8. The preparation method according to claim 1, characterized in that: The annealing temperature is 80°C to 800°C, and the annealing time is 0.5 to 60 hours.

9. A piezoelectric composite substrate for reducing wafer warpage, characterized in that: The method is obtained by the preparation method according to any one of claims 1 to 8.

10. Use of the piezoelectric composite substrate according to claim 9 in preparing a semiconductor device including an acoustic filter.

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