Gelatin-starch composite membrane, synaptic transistor and preparation method and application of gelatin-starch composite membrane and synaptic transistor

Abstract

The invention belongs to the technical field of electronic devices, and particularly relates to a gelatin-starch composite film, a synaptic transistor and a preparation method and application of the gelatin-starch composite film and the synaptic transistor. The gelatin-starch composite film is prepared by innovatively combining gelatin and starch, and the synaptic transistor is constructed based on the gelatin-starch composite film. The transistor structure comprises a substrate, an active layer, a gelatin-starch composite film serving as a gate dielectric layer, and a source electrode and a drain electrode which are sequentially stacked, wherein the source electrode and the drain electrode are arranged on the two sides of the gate dielectric layer. The ingenious design of the gate dielectric layer not only improves the dielectric property of single gelatin, but also solves the problem that starch is difficult to form a film independently. Through intermolecular hydrogen bond combination, the mechanical strength and the structural stability of the composite film are enhanced, the current regulation and control capability of the transistor is optimized, the post-synaptic current response sensitivity is remarkably improved, and the high stability of a device is ensured. Benefited from the combination of the materials, the synaptic transistor shows excellent synaptic plasticity, which indicates that the synaptic transistor is significantly improved in electrical properties.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic devices. More specifically, it relates to a gelatin-starch composite film, a synaptic transistor, and their preparation methods and applications. Background Art

[0002] Synaptic transistors, as the core devices for simulating neuron and synapse functions, have shown great application potential in the fields of neuromorphic computing and artificial intelligence. The key performance of such devices, including the current regulation range, response speed, and stability, is crucial for achieving low-power and high-efficiency computing tasks. To further improve the performance of synaptic transistors, researchers are exploring them in depth from different perspectives. Among them, the selection of materials has become the top priority of the research.

[0003] At the level of material exploration, researchers are constantly searching for and testing new materials, aiming to discover ideal materials that can significantly improve the performance of synaptic transistors. Factors such as the conductivity, stability, and mechanical strength of the materials, as well as their compatibility with other parts of the transistor, all have a profound impact on the device performance. For example, Vivek et al. (Raghuwanshi V, Saxena P, Rahi S, et al. Solution-processed flexible organic field-effect transistors with biodegradable gelatin as the dielectric layer: an approach toward biodegradable systems [J]. ACS Applied Electronic Materials, 2020, 2(10): 3373-3379.) prepared a flexible transistor using gelatin as the dielectric layer, and this device exhibited a high field-effect mobility close to zero threshold voltage. However, the specific capacitance of single gelatin was only 9.1 nF / cm at low frequency (1 kHz) 2 , which is much lower than that of conventional ion gel dielectric materials of μF / cm 2Magnitude, thus restricting high-density charge accumulation and being unfavorable for the full play of dielectric properties. Shao et al. (Shao F, Cai M L, Gu X F, et al. Starch as ion-based gatedielectric for oxide thin film transistors[J]. Organic Electronics, 2017, 45:203-208.) used starch as the dielectric layer to fabricate oxide thin film transistors and emphasized that the performance of the transistors is closely related to the specific capacitance and ionic conductivity of the starch medium. In particular, potato starch exhibited a high on / off ratio and field mobility, but the film-forming ability of single starch is poor and it is difficult to meet the requirements of the device for the mechanical stability of the dielectric layer. Therefore, scientific researchers began to focus on the development of composite materials. For example, Chen Xinli et al. (Chen Xinli, Li Yan, Wang Weisheng, et al. Gelatin / carboxylated chitosan gated oxide neuromorphic transistors[J]. Journal of Inorganic Materials, 2023, 38(04):421-430.) innovatively used a gelatin / carboxylated chitosan composite electrolyte membrane as the gate dielectric layer to fabricate oxide neuromorphic transistors and successfully mimicked synaptic response behaviors under different humidities, such as excitatory postsynaptic current and paired-pulse facilitation. However, despite this innovation bringing progress, the peak value of the postsynaptic current of this device and the increment of the excitatory postsynaptic current under different pulse stimulations are limited to the nA level, which means there is still great room for improvement in simulating the synaptic plasticity of the brain.

[0004] Therefore, developing new materials with high specific capacitance, high mechanical stability, and excellent synaptic plasticity simulation ability remains the focus and difficulty of current research. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the limitations of single materials such as gelatin and starch in the gate dielectric layer of existing transistors in terms of specific capacitance, mechanical stability, etc., which are difficult to meet the requirements of high-performance devices; while the synaptic plasticity of composite materials such as gelatin / carboxylated chitosan still needs to be improved, and to provide a preparation method of a gelatin-starch composite film.

[0006] Another object of the present invention is to provide a gelatin-starch composite film prepared by the above preparation method.

[0007] Another object of the present invention is to provide the application of the above gelatin-starch composite film in the preparation of a gate dielectric layer.

[0008] Another object of the present invention is to provide the application of the above gelatin-starch composite film in the preparation of synaptic transistors.

[0009] Another object of the present invention is to provide a synaptic transistor.

[0010] Another object of the present invention is to provide a method for preparing the above synaptic transistor.

[0011] Another object of the present invention is to provide the use of the above-mentioned gelatin-starch composite film or the above-mentioned synaptic transistor in the preparation of bionic sensing devices, neuromorphic memory or brain-like computing chips.

[0012] The above-mentioned purpose of the present invention is achieved through the following technical solutions:

[0013] The present invention provides a method for preparing a gelatin-starch composite film, comprising the following steps:

[0014] S1. Mix gelatin, starch, water and plasticizer thoroughly to obtain a gelatin-starch mixture;

[0015] S2. injecting the gelatin-starch mixture obtained in step S1 into a mold, and performing annealing treatment (referred to as pre-annealing treatment) at 50 to 70° C. to obtain a gelatin-starch composite film;

[0016] Wherein, in step S1, the mass volume ratio of the gelatin, starch and plasticizer is 1:(0.2-1):(0.2-1) g / mL.

[0017] The present invention proposes a simple and easy-to-operate method for preparing a gelatin-starch composite film. By optimizing the preparation process, the obtained composite film successfully integrates the complementary performance advantages of gelatin and starch within a specific ratio range, and achieves an excellent balance of material film-forming property, mechanical property, dielectric property and ion conductivity of the gate dielectric layer. Specifically, gelatin, as a protein material, has relatively weak dielectric properties, but it exhibits excellent flexibility and excellent film-forming property by virtue of its rich polar groups; starch, as a polysaccharide, has limitations in film-forming ability and mechanical properties, but has high ionic conductivity and high specific capacitance, which adds unique electrical properties to the composite material. When gelatin and starch are composited after annealing treatment, gelatin effectively improves the overall electrical properties of the composite material by adjusting the polar environment; and starch provides additional advantages for the composite material with its high ionic conductivity. In addition, the hydrogen bonds formed between the molecules of the two not only significantly enhance the mechanical strength and structural stability of the composite film, but also further optimize its performance. In order to further improve the performance of the composite film, the addition of an appropriate amount of plasticizer not only improves its plasticizing effect, but also enhances its moisture retention performance. Therefore, the composite film has achieved significant improvements in ionic conductivity, dielectric constant and overall electrical properties, which greatly enhances the ability of thin-film transistors in current regulation and significantly improves the sensitivity of postsynaptic current response, thereby ensuring the high stability of the device. The high efficiency and practicality of this preparation method make the composite film have broad application prospects and huge development potential in electronic devices such as synaptic transistors.

[0018] Further, in step S1, the plasticizer includes one or more of glycerol, polyethylene glycol, and sorbitol.

[0019] Preferably, in step S1, the plasticizer is glycerol. As a plasticizer, glycerol can effectively reduce the intermolecular forces between polymer chains. This reduction enables the polymer chains to move more freely, thereby enhancing the flexibility and ductility of the material. In addition, glycerol also has a moisturizing function and can lock an appropriate amount of moisture inside the material, which is beneficial for maintaining the softness of the material and a suitable humidity environment.

[0020] Further, in step S1, the starch includes one or more of corn starch, potato starch, and sweet potato starch. The basic chemical compositions of these starches are similar, and they are all composed of amylose and amylopectin, which can provide the required dielectric properties and ion conduction channels. Therefore, using one or a combination of the above starches can effectively improve the performance of the gate dielectric layer.

[0021] Preferably, in step S1, the mixing ratio of the gelatin, starch, and plasticizer is 1 g : (0.3 - 0.8) g : (0.3 - 0.9) mL.

[0022] More preferably, in step S1, the mixing ratio of the gelatin, starch, and plasticizer is 1 g : (0.4 - 0.6) : (0.5 - 0.8) mL. Within this ratio range, it can greatly promote the uniform fusion and interaction between components, thereby significantly enhancing the overall performance of the composite film.

[0023] Further, in step S1, the mass - volume ratio of the gelatin to water is 1 : (10 - 40) g / mL.

[0024] Preferably, the time for sufficient mixing is 0.5 - 1.5 h.

[0025] Further, the mixing is stirring mixing.

[0026] Further, the rotation speed of the stirring mixing is 800 - 1500 rpm.

[0027] Preferably, in step S1, the time for mixing is 0.5 - 2 h.

[0028] Preferably, in step S2, the time for the annealing treatment is 0.5 - 1 h.

[0029] The present invention protects the gelatin - starch composite film prepared by the above - mentioned preparation method.

[0030] The present invention protects the application of the above - mentioned gelatin - starch composite film in the preparation of a gate dielectric layer.

[0031] The present invention protects the application of the above-mentioned gelatin-starch composite film in the preparation of synaptic transistors.

[0032] The present invention protects a synaptic transistor, which includes a substrate, an active layer, a gate dielectric layer, and a source electrode and a drain electrode disposed on both sides of the gate dielectric layer, which are stacked in sequence;

[0033] Wherein, the gate dielectric layer is the aforementioned gelatin-starch composite film.

[0034] The synaptic transistor structure of the present invention includes a substrate, an active layer, a gelatin-starch composite film as the gate dielectric layer, and source and drain electrodes disposed on both sides of the gate dielectric layer, which are stacked in sequence. The ingenious design of this gate dielectric layer not only strengthens the dielectric properties of single gelatin, but also successfully overcomes the problem of starch forming a film alone. Thanks to the strengthened connection of intermolecular hydrogen bonds, the composite film exhibits excellent mechanical strength and structural stability, thereby optimizing the current regulation efficiency of the transistor and greatly improving the response sensitivity of the postsynaptic current, ensuring the long-term stability of the device. This innovative design lays a solid foundation for the application of synaptic transistors in the preparation of bionic sensing devices, neuromorphic memories or brain-like computing chips, highlighting its excellent product competitiveness.

[0035] Specifically, in the synaptic transistor of the present invention, the gate dielectric layer not only covers the channel region between the source and drain electrodes, but also extends to the source and drain electrodes, forming a full-coverage structure. This design significantly enhances the storage capacity of the device because it can more effectively regulate the charge distribution in the channel. At the same time, the full-coverage gate dielectric layer also optimizes the uniformity of the electric field distribution, effectively reducing the electric field concentration and edge effect, thereby further improving the reliability and service life of the device.

[0036] Furthermore, the substrate includes any one of silicon dioxide, glass, and polyimide substrates.

[0037] Preferably, the thickness of the substrate is 50-200 μm. The substrate within this range has better mechanical stability and processing feasibility, thus ensuring that it can reliably carry the device without directly affecting the device performance.

[0038] Furthermore, the active layer is an indium tin zinc oxide (ITZO) thin film.

[0039] Preferably, the thickness of the active layer is 20-40 nm.

[0040] Furthermore, the materials of the source electrode and the drain electrode are the same; the source electrode and the drain electrode are silver or gold.

[0041] Preferably, the thickness of the source electrode and the drain electrode is 30 - 90 nm. The source and drain electrodes within this thickness range can effectively reduce the contact resistance, enhance the carrier injection efficiency, and ensure the mechanical stability of the device.

[0042] More preferably, the thickness of the source electrode and the drain electrode is 50 - 70 nm.

[0043] Preferably, the thickness of the gate dielectric layer is 10 - 25 μm. The gate dielectric layer within this range has good stripping performance, facilitating subsequent process operations and being beneficial to improving the reliability of the device.

[0044] More preferably, the thickness of the gate dielectric layer is 11 - 20 μm.

[0045] The present invention protects the preparation method of the above synaptic transistor, which includes the following steps:

[0046] Si. Prepare an active layer on the substrate;

[0047] Sii. Attach a mask plate to the active layer obtained in step Si, and then evaporate the source and drain electrodes;

[0048] Siii. Remove the mask plate described in step Sii, attach the aforementioned gelatin - starch composite film as the gate dielectric layer, and perform an optional annealing treatment (referred to as post - annealing treatment) at 50 - 70 °C to obtain the synaptic transistor based on the gelatin - starch composite film.

[0049] By constructing a gelatin - starch composite film as the gate dielectric layer and combining with an efficient evaporation process of the active layer and the source and drain electrodes, the present invention not only realizes the simplification of the process and the convenience of operation, but also provides an optional annealing treatment step to meet the requirements of diverse application scenarios. This strategy significantly improves the electrical performance and stability of the synaptic transistor, especially showing excellent performance in precise current regulation and postsynaptic current response, providing a high - performance and reliable preparation scheme for synaptic transistors in cutting - edge technology fields such as bionic sensing devices, neuromorphic memories, or brain - like computing chips.

[0050] Furthermore, in step Si, the use of the substrate includes pre - treatment.

[0051] Even further, as a preferred method, the pre - treatment includes the following steps:

[0052] Ultrasonically clean the substrate with water and isopropyl alcohol solution in sequence for 15 - 30 min, and then dry it with nitrogen to obtain the pre - treated substrate.

[0053] Furthermore, in step Si, the preparation method of the active layer specifically includes the following steps:

[0054] In an Ar and O 2 atmosphere, indium tin oxide (ITO) and zinc oxide (ZnO) targets are used to prepare an ITZO thin film, and the obtained ITZO thin film is annealed to obtain an ITZO active layer.

[0055] Preferably, in step Si, the gas flow rate of Ar:O 2 is (5 - 15):(3 - 9) sccm.

[0056] More preferably, the gas flow rate of Ar:O 2 is fixed at 10:6 sccm.

[0057] Furthermore, the molar ratio of indium tin oxide to zinc oxide is 1:(0.25 - 10).

[0058] Preferably, the power of the ITO target is 90 - 110 W.

[0059] Preferably, the power of the ZnO target is 120 - 140 W.

[0060] Furthermore, the temperature of the annealing treatment is 300 - 350 °C.

[0061] Preferably, the time of the annealing treatment is 2 - 3 h.

[0062] Preferably, in step Si, the thickness of the active layer is 10 - 50 nm. Within this thickness range, the active layer can not only ensure the carrier transport efficiency but also enhance the overall stability of the device, thus achieving a more ideal balance among conductivity, on-off ratio, and stability.

[0063] Furthermore, in step Sii, the evaporation rate is

[0064] Furthermore, in step Siii, the optional annealing treatment includes the following two cases: (1) If annealing treatment is selected, the gelatin - starch composite film undergoes a front - and - back annealing process combining front annealing and back annealing; (2) If annealing treatment is not selected, the gelatin - starch composite film only undergoes the front annealing process.

[0065] Specifically, the front - and - back annealing process is to attach the gelatin - starch composite thin film obtained after front annealing to the active layer region as the gate dielectric layer, and then place the device at 50 - 70 °C for back annealing to obtain a synaptic transistor based on the gelatin - starch composite film that has undergone front - and - back annealing treatment.

[0066] Specifically, the pre-annealing process is to attach the gelatin-starch composite film obtained by pre-annealing treatment to the active layer region as the gate dielectric layer, so as to obtain a synaptic transistor based on the gelatin-starch composite film that only undergoes pre-annealing treatment.

[0067] The present invention protects the application of the above-mentioned gelatin-starch composite film or the above-mentioned synaptic transistor in the preparation of bionic sensing devices, neuromorphic memories or brain-like computing chips.

[0068] Compared with the prior art, the present invention has the following beneficial effects:

[0069] The present invention innovatively combines gelatin and starch to prepare a gelatin-starch composite film, and constructs a synaptic transistor based on this. The transistor structure includes a substrate, an active layer, a gelatin-starch composite film as the gate dielectric layer, and source and drain electrodes arranged on both sides of the gate dielectric layer, which are stacked in sequence. The ingenious design of the gate dielectric layer not only improves the dielectric properties of single gelatin, but also solves the problem that starch is difficult to form a film alone. Through hydrogen bonding between molecules, the mechanical strength and structural stability of the composite film are enhanced, the current regulation ability of the transistor is optimized, and the sensitivity of the postsynaptic current response is significantly improved, ensuring the high stability of the device. Thanks to the combination of the above materials, the synaptic transistor exhibits excellent synaptic plasticity, marking a significant improvement in electrical performance. Description of the Drawings

[0070] Figure 1 It is a schematic structural diagram of the synaptic transistor in Examples 1-2 and Comparative Examples 1-7; the schematic diagram mainly focuses on expressing the structural relationship, rather than accurately reflecting the actual thickness of each layer.

[0071] Figure 2 It is an excitatory postsynaptic current diagram of the synaptic transistor based on the gelatin-starch composite film in Example 1 under single-pulse stimulation in the pre-annealing process.

[0072] Figure 3 It is an excitatory postsynaptic current diagram of the synaptic transistor based on the gelatin-starch composite film in Example 2 under single-pulse stimulation in the pre- and post-annealing processes.

[0073] Figure 4 It is an excitatory postsynaptic current diagram of the synaptic transistor based on the gelatin-starch composite film in Comparative Example 1 under single-pulse stimulation in the post-annealing process.

[0074] Figure 5 It is an excitatory postsynaptic current diagram of the synaptic transistor based on the gelatin film in Comparative Example 2 under single-pulse stimulation in the pre-annealing process.

[0075] Figure 6Excitatory postsynaptic current diagram of the gelatin film-based synaptic transistor in Comparative Example 3 under single-pulse stimulation during the post-annealing process.

[0076] Figure 7 Excitatory postsynaptic current diagram of the gelatin film-based synaptic transistor in Comparative Example 4 under single-pulse stimulation during the pre- and post-annealing processes.

[0077] Figure 8 Excitatory postsynaptic current diagram of the starch film-based synaptic transistor in Comparative Example 7 under single-pulse stimulation during the post-annealing process.

[0078] Figure 9 Excitatory postsynaptic current diagram of the gelatin-starch composite film-based synaptic transistor in Example 1 under 6 groups of different numbers of pulse stimulations during the pre-annealing process.

[0079] Figure 10 Excitatory postsynaptic current diagram of the gelatin-starch composite film-based synaptic transistor in Example 2 under 6 groups of different numbers of pulse stimulations during the pre- and post-annealing processes.

[0080] Figure 11 Excitatory postsynaptic current diagram of the gelatin-starch composite film-based synaptic transistor in Comparative Example 1 under 6 groups of different numbers of pulse stimulations during the post-annealing process.

[0081] Figure 12 Excitatory postsynaptic current diagram of the gelatin film-based synaptic transistor in Comparative Example 2 under 6 groups of different numbers of pulse stimulations during the pre-annealing process.

[0082] Figure 13 Excitatory postsynaptic current diagram of the gelatin film-based synaptic transistor in Comparative Example 3 under 6 groups of different numbers of pulse stimulations during the post-annealing process.

[0083] Figure 14 Excitatory postsynaptic current diagram of the gelatin film-based synaptic transistor in Comparative Example 4 under 6 groups of different numbers of pulse stimulations during the pre- and post-annealing processes.

[0084] Figure 15 Excitatory postsynaptic current diagram of the starch film-based synaptic transistor in Comparative Example 7 under 6 groups of different numbers of pulse stimulations during the post-annealing process.

[0085] Figure 16 Excitatory postsynaptic current diagram generated by applying electrical pulse signals in the Morse code format representing the four letters G, D, U, and T to the gelatin-starch composite film-based synaptic transistor in Example 2. Detailed implementation mode

[0086] The present invention is further described below in conjunction with the accompanying drawings and specific examples, but the examples do not limit the present invention in any form. Unless otherwise specified, the reagents, methods and equipment used in the present invention are conventional reagents, methods and equipment in the art.

[0087] Unless otherwise specified, the reagents and materials used in the following examples are commercially available.

[0088] Figure 1 (a) Figure 1 In Figure (a), Figure 1 (b) Figure 1 The order of the other figures is similar.

[0089] Example 1 A synaptic transistor and a method for manufacturing the same

[0090] 1. A synaptic transistor (schematic diagram as shown in Figure 1 (a)), comprising a rigid substrate-SiO 2 , active layer-ITZO film, gate dielectric layer-gelatin-starch composite film, and also includes a source electrode-Ag and a drain electrode-Ag arranged on both sides of the gate dielectric layer.

[0091] 2. The method for preparing the synaptic transistor comprises the following steps:

[0092] S1. Pretreatment of substrate:

[0093] SiO 2 The substrate was placed in deionized water and isopropanol solution in turn, ultrasonically cleaned for 15 min respectively, and then dried with nitrogen to obtain a pretreated SiO 2 Substrate.

[0094] S2. Preparation of active layer:

[0095] The pre-treated SiO obtained in step S1 2 On the substrate, the ITZO active layer was deposited by magnetron co-sputtering at room temperature using ITO target and ZnO target. During the sputtering process, the power of ITO target and ZnO target was 100W and 130W, the gas pressure in the chamber was 0.5Pa, and the Ar:O 2 The gas flow rate is fixed at 10:6 sccm. In an air environment, the film is annealed at 350°C for 3 hours to obtain an ITZO film with a thickness of 30 nm, which is the active layer.

[0096] S3. Evaporation electrode:

[0097] The mask is attached to the surface of the active layer prepared in step S2, and then placed in a coating machine at a evaporation rate of Under the condition of , Ag with a thickness of 60 nm is evaporated and deposited as the source electrode and the drain electrode.

[0098] S4. Preparation of the gate dielectric layer:

[0099] S4-1. Dissolve 1 g of gelatin powder in 15 mL of deionized water, and stir at a speed of 1200 rpm for 50 min at 70 °C. Subsequently, add 0.5 g of corn starch and 800 μL of glycerol to the solution, and continue heating and stirring for 50 min to obtain a uniform gelatin-starch solution;

[0100] S4-2. Pour the gelatin-starch solution prepared in step S4-1 evenly into a petri dish, and anneal it in an environment of 60 °C for 1 h (pre-annealing treatment) to form a peelable gelatin-starch composite film with a thickness of 16 μm;

[0101] S4-3. Remove the mask plate in step S3, and then laminate the gelatin-starch composite film obtained in step S4-2 as the gate dielectric layer to obtain the synaptic transistor.

[0102] Example 2 A synaptic transistor and its manufacturing method

[0103] The difference from Example 1 is that in step S4-3 of the manufacturing method of the synaptic transistor, a post-annealing step is added. The structural schematic diagram is as Figure 1 (b) shown.

[0104] 1. A synaptic transistor, including a rigid substrate - SiO 2 , an active layer - ITZO thin film, a gate dielectric layer - gelatin-starch composite film, and further including a source electrode - Ag and a drain electrode - Ag disposed on both sides of the gate dielectric layer.

[0105] 2. The manufacturing method of the above-mentioned synaptic transistor includes the following steps:

[0106] S1. Pretreatment of the substrate:

[0107] Put the SiO 2 substrate into deionized water and isopropyl alcohol solution in sequence, ultrasonically clean for 15 min respectively, and then dry with nitrogen to obtain the pretreated SiO 2 substrate.

[0108] S2. Preparation of the active layer:

[0109] On the pretreated SiO 2 substrate obtained in step S1, deposit the ITZO active layer by magnetron co-sputtering method at room temperature using ITO target and ZnO target. During the sputtering process, the powers of the ITO target and ZnO target are 100 W and 130 W respectively, the air pressure in the cavity is 0.5 Pa, Ar:O2 The gas flow rate was fixed at 10:6 sccm. In an air environment, annealing treatment was carried out at 350 °C for 3 h to obtain an ITZO thin film with a thickness of 30 nm.

[0110] S3. Evaporating electrodes:

[0111] The mask plate was attached to the surface of the active layer prepared in step S2, and then placed in a coating machine. Under the condition of an evaporation rate of Ag with a thickness of 60 nm was evaporated as the source electrode and the drain electrode.

[0112] S4. Preparation of the gate dielectric layer:

[0113] S4-1. Dissolve 1 g of gelatin powder in 15 mL of deionized water, and stir at a speed of 1200 rpm at 70 °C for 50 min. Subsequently, add 0.5 g of corn starch and 800 μL of glycerol to the solution, and continue heating and stirring for 50 min to obtain a uniform gelatin-starch solution;

[0114] S4-2. Pour the gelatin-starch solution prepared in step S4-1 evenly into a petri dish, and anneal in an environment of 60 °C for 1 h (pre-annealing treatment) to form a peelable ion gel film with a thickness of 16 μm;

[0115] S4-3. Remove the mask plate in step S3, and then attach the ion gel film obtained in step S4-2 as the gate dielectric layer. Place the device in an environment of 60 °C for 1 h of secondary annealing (post-annealing treatment) to obtain the synaptic transistor.

[0116] Example 3 A synaptic transistor and its preparation method

[0117] The difference from Example 1 is that in step S4-1 of the preparation method of the synaptic transistor, the input amount of corn starch was changed from 0.5 g to 0.2 g, so that the mass ratio of gelatin to starch is 5:1.

[0118] Other steps and conditions are the same as those in Example 1.

[0119] Comparative Example 1 A synaptic transistor and its preparation method

[0120] The difference from Example 2 is that in step S4-2 of the preparation method of the synaptic transistor, the pre-annealing step is not carried out, that is, it is in the state of a gelatin-starch solution. The structural schematic diagram is as shown in Figure 1 (c).

[0121] 1. A synaptic transistor, comprising a rigid substrate - SiO 2 , an active layer - ITZO thin film, a gate dielectric layer - gelatin-starch composite film, and further comprising a source electrode - Ag and a drain electrode - Ag disposed on both sides of the gate dielectric layer.

[0122] 2. The preparation method of the above synaptic transistor includes the following steps:

[0123] S1. Pretreatment of the substrate:

[0124] Put the SiO 2 substrate into deionized water and isopropyl alcohol solution in sequence, ultrasonically clean for 15 min respectively, and then dry with nitrogen gas to obtain the pretreated SiO 2 substrate.

[0125] S2. Preparation of the active layer:

[0126] On the pretreated SiO 2 substrate obtained in step S1, deposit the ITZO active layer by magnetron co-sputtering method at room temperature using ITO target and ZnO target. During the sputtering process, the powers of the ITO target and ZnO target are 100 W and 130 W respectively, the air pressure in the cavity is 0.5 Pa, and the Ar:O 2 gas flow rate is fixed at 10:6 sccm. Anneal at 350 °C for 3 h in an air environment to obtain an ITZO thin film with a thickness of 30 nm.

[0127] S3. Evaporation of electrodes:

[0128] Attach the mask plate to the surface of the active layer prepared in step S2, and then place it in the coating machine. Evaporate Ag with a thickness of 60 nm as the source electrode and drain electrode under the condition of evaporation rate of .

[0129] S4. Preparation of the gate dielectric layer:

[0130] S4-1. Dissolve 1 g of gelatin powder in 15 mL of deionized water, stir at 1200 rpm for 50 min at 70 °C. Subsequently, add 0.5 g of corn starch and 800 μL of glycerol to the solution, and continue heating and stirring for 50 min to obtain a uniform gelatin-starch solution;

[0131] S4-2. Remove the mask plate in step S3, and then drop the gelatin-starch solution obtained in step S4-1 onto the ITZO thin film obtained in step S2. Subsequently, place the device in an environment of 60 °C for 1 h annealing (post-annealing treatment). After the annealing treatment, use the gelatin-starch composite film with a thickness of 16 μm as the gate dielectric layer to obtain the synaptic transistor.

[0132] Comparative Example 2 A synaptic transistor and its preparation method

[0133] The difference from Example 1 is that in step S4-1 of the preparation method of the synaptic transistor, corn starch is not added, and a pure gelatin solution is prepared. The structural schematic diagram is asFigure 1 as shown in (d).

[0134] Other steps and conditions are the same as those in Example 1.

[0135] Comparative Example 3 A synaptic transistor and its manufacturing method

[0136] The difference from Example 2 is that in step S4-1 of the manufacturing method of the synaptic transistor, corn starch is not added, and a pure gelatin solution is obtained. The structural schematic diagram is as shown in Figure 1 (e).

[0137] Comparative Example 4 A synaptic transistor and its manufacturing method

[0138] The difference from Example 2 is that in step S4-1 of the manufacturing method of the synaptic transistor, corn starch is not added, and a pure gelatin solution is obtained; in part of step S4-2 of the manufacturing method of the synaptic transistor based on the gelatin-starch composite film, the pre-annealing step is not performed, and it is in the state of the gelatin solution. The structural schematic diagram is as shown in Figure 1 (f).

[0139] 1. A synaptic transistor, comprising a rigid substrate - SiO 2 , an active layer - ITZO thin film, a gate dielectric layer - gelatin film, and further comprising a source electrode - Ag and a drain electrode - Ag disposed on both sides of the gate dielectric layer.

[0140] 2. The manufacturing method of the above-mentioned synaptic transistor comprises the following steps:

[0141] S1. Pretreatment of the substrate:

[0142] Put the SiO 2 substrate into deionized water and isopropyl alcohol solution in sequence, ultrasonically clean for 15 minutes respectively, and then blow dry with nitrogen to obtain the pretreated SiO 2 substrate.

[0143] S2. Preparation of the active layer:

[0144] On the pretreated SiO 2 substrate obtained in step S1, deposit the ITZO active layer by magnetron co-sputtering method at room temperature using ITO target and ZnO target. During the sputtering process, the powers of the ITO target and ZnO target are 100W and 130W respectively, the air pressure in the cavity is 0.5Pa, and the gas flow rate of Ar:O 2 is fixed at 10:6 sccm. Anneal at 350°C for 3 hours in an air environment to obtain an ITZO thin film with a thickness of 30nm.

[0145] S3. Evaporation of electrodes:

[0146] Attach the mask plate to the surface of the active layer prepared in step S2, and then place it in a coating machine. Under the condition that the evaporation rate is , evaporate Ag with a thickness of 60 nm as the source electrode and the drain electrode.

[0147] S4. Preparation of the gate dielectric layer:

[0148] S4-1. Dissolve 1 g of gelatin powder in 15 mL of deionized water, stir at 1200 rpm for 50 min at 70 °C to obtain a uniform gelatin solution;

[0149] S4-2. Remove the mask plate in step S3, and then drop the gelatin solution obtained in step S4-1 onto the ITZO thin film obtained in step S2. Subsequently, place the device in an environment of 60 °C for 1 h annealing (post-annealing). After the annealing treatment, use the gelatin film with a thickness of 16 μm as the gate dielectric layer, and thus obtain the synaptic transistor.

[0150] Comparative Example 5 A synaptic transistor and its preparation method

[0151] The difference from Example 1 is that in step S4-1 of the preparation method of the synaptic transistor, no gelatin powder is added, that is, a pure starch solution is prepared. The structural schematic diagram is as shown in Figure 1 (g).

[0152] Other steps and conditions are the same as those in Example 1.

[0153] Comparative Example 6 A synaptic transistor and its preparation method

[0154] The difference from Example 2 is that in step S4-1 of the preparation method of the synaptic transistor, no gelatin powder is added, that is, a pure starch solution is prepared. The structural schematic diagram is as shown in Figure 1 (h).

[0155] Comparative Example 7 A synaptic transistor and its preparation method

[0156] The difference from Example 2 is that in step S4-1 of the preparation method of the synaptic transistor, no gelatin powder is added, that is, a pure starch solution is prepared; in step S4-2 of the preparation method of the synaptic transistor, the pre-annealing step is not performed, that is, it is in the state of a starch solution. The structural schematic diagram is as shown in Figure 1 (i).

[0157] 1. A synaptic transistor includes a rigid substrate - SiO 2 , an active layer - ITZO thin film, a gate dielectric layer - starch film, and also includes a source electrode - Ag and a drain electrode - Ag arranged on both sides of the gate dielectric layer.

[0158] 2. The preparation method of the above-mentioned synaptic transistor includes the following steps:

[0159] S1. Pretreatment of the substrate:

[0160] Put the SiO 2 substrate into deionized water and isopropyl alcohol solution in sequence, ultrasonically clean for 15 min respectively, and then blow dry with nitrogen to obtain the pretreated SiO 2 substrate.

[0161] S2. Preparation of the active layer:

[0162] On the pretreated SiO 2 substrate obtained in step S1, deposit the ITZO active layer by magnetron co-sputtering method using ITO target and ZnO target at room temperature. During the sputtering process, the powers of the ITO target and ZnO target are 100 W and 130 W respectively, the air pressure in the cavity is 0.5 Pa, and the Ar:O 2 gas flow rate is fixed at 10:6 sccm. Under the air environment, anneal at 350 °C for 3 h to obtain an ITZO thin film with a thickness of 30 nm.

[0163] S3. Evaporation of electrodes:

[0164] Attach the mask plate to the surface of the active layer prepared in step S2, and then place it in the coating machine. Under the condition of evaporation rate of evaporate Ag with a thickness of 60 nm as the source electrode and drain electrode.

[0165] S4. Preparation of the gate dielectric layer:

[0166] S4-1. Dissolve 0.5 g of corn starch and 800 μL of glycerol in 15 mL of deionized water, stir at 70 °C at a speed of 1200 rpm for 50 min to obtain a uniform starch solution;

[0167] S4-2. Remove the mask plate in step S3, and then drop the starch solution obtained in step S4-1 onto the ITZO thin film obtained in step S2. Subsequently, place the device in an environment of 60 °C for 1 h annealing (post-annealing). After the annealing treatment, use the starch film with a thickness of 16 μm as the gate dielectric layer to obtain the synaptic transistor.

[0168] Experimental Example 1 Performance test of excitatory postsynaptic current of synaptic transistor under single-pulse stimulation

[0169] 1. Experimental method

[0170] The synaptic transistors prepared in Examples 1-2 and Comparative Examples 1-7 were used as test samples and tested using a Keithley 4200-SCS semiconductor characterization analyzer. Test procedure: Connect the probe of electrode SUM1 to the source electrode - Ag, the probe of electrode SUM2 to the gate dielectric layer as the top electrode, and the probe of electrode SUM3 to the drain electrode - Ag. Then continuously apply a reading voltage of 0.5 mV to SUM1, and apply a single pre-synaptic spike with an amplitude of 4 V and a duration of 0.1 s to SUM2. The excitatory postsynaptic current diagram of the tested synaptic transistor under a single 0.1 s negative pulse stimulation is as shown in Figures 2 - 8 shown.

[0171] 2. Experimental results

[0172] As can be seen from the data in the figure, the postsynaptic current of the synaptic transistor prepared by the pre-annealing process based on the gelatin-starch composite film in Example 1 is 0.7955 μA ( Figure 2 shown), and further, the postsynaptic current of the synaptic transistor prepared by the pre- and post-annealing processes based on the gelatin-starch composite film in Example 2 is 1.3339 μA ( Figure 3 shown). In contrast, the postsynaptic currents of Comparative Example 2 and Comparative Example 3 corresponding to the synaptic transistors prepared by the pre-annealing process and the pre- and post-annealing processes based on the gelatin film are significantly reduced, being 0.1369 μA ( Figure 5 shown) and 0.2287 μA ( Figure 6 shown), respectively. During the process of using the starch film to prepare the gate dielectric layer by the pre-annealing (Comparative Example 5) and pre- and post-annealing (Comparative Example 6) processes, since the starch material becomes viscous during the pre-annealing and pre- and post-annealing processes, a stable thin film cannot be formed and the process of transferring it to the device cannot be completed. In addition, the postsynaptic current of the synaptic transistor prepared by the post-annealing process based on the gelatin-starch composite film in Comparative Example 1 is 0.9499 μA ( Figure 4 shown), and the postsynaptic current of the synaptic transistor prepared by the post-annealing process based on the gelatin film in Comparative Example 4 is 0.2961 μA ( Figure 7 shown). It is worth noting that the postsynaptic current of the synaptic transistor prepared by the post-annealing process based on the starch film in Comparative Example 7 is extremely low, only 0.0038 μA ( Figure 8 shown). The change in postsynaptic current is an important indicator for evaluating the strength of synaptic plasticity. In the facilitatory synaptic plasticity (such as long-term potentiation) concerned in this application, the greater the increase in postsynaptic current, the stronger the synaptic plasticity usually indicates. This means that in this application, the synaptic transistors based on the gelatin-starch composite film obtained by pre-annealing or pre- and post-annealing show higher flexibility and adaptability when simulating the information processing of the nervous system.

[0173] Experimental Example 2: Excitatory Postsynaptic Current Performance Test of Synaptic Transistors under Different Numbers of Presynaptic Spikes

[0174] 1. Experimental Method

[0175] Use the synaptic transistors prepared in Examples 1 - 2, Comparative Examples 1 - 4, and Comparative Example 7 as test samples. Connect the probe of electrode SUM1 to the source electrode - Ag, the probe of electrode SUM2 to the gate dielectric layer as the top electrode, and the probe of electrode SUM3 to the drain electrode - Ag. Test method: Continuously apply a reading voltage of 5 mV to electrode SUM1 using a Keithley 4200 - SCS semiconductor characterization analyzer, and apply a single signal with a duration of 0.1 s and an amplitude of 4 V to electrode SUM2 as the presynaptic spike to obtain the excitatory postsynaptic current graph under a single 0.1 s positive pulse stimulation. Replace the single pulse with 5, 10, 20, 30, 50, and 100 pulses respectively to obtain the excitatory postsynaptic current graphs under different numbers of presynaptic spikes.

[0176] 2. Experimental Results

[0177] In the experimental results of Examples 1 - 2, Comparative Examples 1 - 4, and Comparative Example 7, it can be observed that the postsynaptic current of the synaptic transistors all shows a gradually increasing trend with the increase in the number of input spikes. Specifically, when the number of spikes of the synaptic transistors based on the gelatin - starch composite film (Examples 1 - 2) increases from 5 to 100, the maximum postsynaptic current of Example 1 increases from 2.6893 μA to 37.5584 μA, and the regulation range is 34.8691 μA( Figure 9 ); for Example 2, it significantly increases from 4.5644 μA to 55.4417 μA, and the regulation range reaches 50.8773 μA( Figure 10 ). In contrast, the regulation ranges of the comparative examples using pure gelatin films (Comparative Examples 2 and 3) are significantly smaller: the postsynaptic current of Comparative Example 2 increases from 0.6059 μA to 3.2263 μA, and the regulation range is only 2.6204 μA( Figure 12 ); for Comparative Example 3, it increases from 0.3243 μA to 1.7250 μA, and the regulation range is only 1.4007 μA( Figure 13 ). In addition, for the comparative examples using the post - annealing process (Comparative Examples 1, 4, and 7), the postsynaptic current of Comparative Example 1 increases from 1.2622 μA to 3.7827 μA, and the regulation range is 2.5205 μA( Figure 11 ); Comparative Example 4 also uses the post - annealing process, but its regulation range is more limited, only increasing from 1.2833 μA to 2.0447 μA, and the regulation range is 0.7614 μA( Figure 14);The regulation range of Comparative Example 7 is the smallest, with its postsynaptic current increasing from 0.01 μA to 0.17 μA, and the regulation range is only 0.16 μA( Figure 15 )。Among them, for Example 1 based on the gelatin-starch composite film and using the pre-annealing process, the regulation range of its postsynaptic current is 13.3 times that of Comparative Example 2 based on the gelatin film and using the pre-annealing process; while for Example 2 using the gelatin-starch composite film and combining the pre- and post-annealing processes, the regulation range of its postsynaptic current is 36.3 times that of Comparative Example 3 based on the gelatin film and using the pre- and post-annealing processes. These results strongly indicate that by combining the addition of starch in gelatin with appropriate annealing processes (pre-annealing or pre- and post-annealing processes), the performance of synaptic transistors can be significantly improved, endowing them with high sensitivity. As the number of spikes continuously increases, the response intensity of the postsynaptic current of these two types of synaptic transistors also increases significantly. This characteristic not only indicates the high dependence of the device on the number of spikes but also further highlights its enhanced plasticity.

[0178] Experimental Example 3 Performance Test of Excitatory Postsynaptic Current of Synaptic Transistors Simulating Morse Code under Different Signals

[0179] 1. Experimental Method

[0180] The synaptic transistor prepared in Example 2 was used as the test sample. The probe of electrode SUM1 was connected to the source electrode - Ag, the probe of electrode SUM2 was connected to the gate dielectric layer as the top electrode, and the probe of electrode SUM3 was connected to the drain electrode - Ag. Test method: Use a Keithley 4200-SCS semiconductor characterization analyzer for testing. During the process, a reading voltage of 0.1 mV was continuously applied to electrode SUM1. At the same time, a signal was applied to electrode SUM2 to simulate Morse code: A single signal with a duration of 0.1 s and an amplitude (pulse voltage) of 0.1 V represents a short signal (denoted by "·"); a single signal with a duration of 0.2 s and an amplitude of 0.1 V represents a long signal (denoted by "-"). Through this method, excitatory postsynaptic current diagrams representing the letters G (long / long / short), D (long / short / short), U (short / short / long), and T (long) were obtained.

[0181] 2. Experimental Results

[0182] According to Figure 16It can be seen that in the experiment of Morse coding of the four letters G, D, U, or T using the synaptic transistor with the gelatin-starch composite film prepared in Example 2 as the gate dielectric layer, under short pulse signals, the excitatory postsynaptic current ranges from 0.46 to 0.60 nA, and its floating rate ((upper limit value of current - average value) / average value × 100%) is approximately 13.21%; under long pulse signals, the excitatory postsynaptic current ranges from 0.98 to 1.38 nA, and the floating rate is approximately 16.95%. The fault tolerance margin between the long signal and the short signal (the minimum difference between the excitatory postsynaptic current ranges of the long signal and the short signal) is 0.38 nA. These results indicate that although under low-power conditions (read voltage < 0.1 V, pulse voltage < 0.5 V), the device can still accurately identify the changes in the presynaptic spike morphology and output corresponding current signals. The above experimental results further verify the stability and reliability of the device under low voltage.

[0183] When only changing the ratio of gelatin to starch, it mainly affects the microstructure and conductivity of the material, but the two still maintain similar basic properties in the composite film. Even when the ratio changes, gelatin and starch can still cooperate with each other to maintain the structural stability and electrical conductivity of the film. Therefore, the semiconductor characteristics of the synaptic transistor based on the gelatin-starch composite film prepared in Example 3 are basically the same as those in Example 1, and will not be elaborated here.

[0184] The above embodiments are the preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A method for preparing a gelatin-starch composite film, characterized in that: The following steps are involved: S1. Mix gelatin, starch, water and plasticizer thoroughly to obtain a gelatin-starch mixture; S2. injecting the gelatin-starch mixture obtained in step S1 into a mold and annealing at 50 to 70° C. to obtain a gelatin-starch composite film; Wherein, in step S1, the mixing ratio of gelatin, starch and plasticizer is 1g: (0.2-1)g: (0.2-1)mL.

2. The preparation method according to claim 1, characterized in that: The plasticizer includes one or more of glycerol, polyethylene glycol, and sorbitol.

3. The gelatin-starch composite film prepared by the preparation method according to claim 1 or 2.

4. Use of the gelatin-starch composite film according to claim 3 in preparing a gate dielectric layer.

5. Use of the gelatin-starch composite film according to claim 3 in the preparation of synaptic transistors.

6. A synaptic transistor, characterized in that: It includes a substrate, an active layer, a gate dielectric layer, and a source electrode and a drain electrode arranged on both sides of the gate dielectric layer. Wherein, the gate dielectric layer is the gelatin-starch composite film as described in claim 3.

7. The synaptic transistor according to claim 6, characterized in that: The active layer is an indium tin zinc oxide film.

8. The synaptic transistor according to claim 6, characterized in that: The thickness of the gate dielectric layer is 10-25 μm.

9. The method for preparing a synaptic transistor according to any one of claims 6 to 8, characterized in that: The following steps are involved: Si. Preparing an active layer on a substrate; Sii. The mask is attached to the active layer obtained in step Si, and then the source and drain electrodes are evaporated; Siii. Remove the mask described in step Sii, and adhere the gelatin-starch composite film described in claim 3 as a gate dielectric layer, and perform an optional annealing treatment at 50 to 70° C. to obtain a synaptic transistor.

10. Use of the gelatin-starch composite film according to claim 3 or the synaptic transistor according to any one of claims 6 to 8 in the preparation of bionic sensor devices, neuromorphic memories or brain-like computing chips.

Images