Laser projection equipment

Abstract

A laser projection apparatus includes a light source, a ray machine, a lens, and circuitry. The circuitry is configured to control the light source to emit light beams of at least N colors, N being an integer greater than 3. The circuit system comprises a display control circuit and a light source driving circuit. The display control circuit is configured to generate N PWM signals and three enable signals. The light source driving circuit is electrically connected with the display control circuit and is configured to receive the N PWM signals and the three enable signals so as to drive the laser chips of the corresponding colors to emit the light beams of the at least N colors.

Description

Technical Field

[0001] This application belongs to the field of laser projection display, and particularly relates to a laser projection device. Background Art

[0002] Laser projection devices such as laser TVs and laser projectors are widely used in the display field due to their advantages of high color purity, large color gamut, and high brightness. Laser projection devices use laser light sources, which have advantages such as good monochromaticity, high brightness, and long lifespan, and are relatively ideal light sources. The laser light source provides an illumination beam containing three primary colors of light, and the laser projection device then converts this illumination beam into a projection beam according to the image signal, thereby projecting an image on a screen or wall. Summary of the Invention

[0003] The present disclosure provides a laser projection device. The laser projection device includes: a light source, an optical engine, a lens, and a circuit system. Among them, the light source is configured to provide an illumination beam, and the light source includes laser chips encapsulated with N primary colors, where N is an integer greater than 3. The optical engine is configured to modulate the illumination beam using an image signal to obtain a projection beam. The lens is configured to project the projection beam to form an image. The circuit system is configured to control the light source to emit at least N colors of light beams.

[0004] The circuit system includes: a display control circuit and a laser chip driving circuit.

[0005] The display control circuit is configured to generate N pulse width modulation (PWM) signals corresponding to the laser chips of N primary colors based on the N primary color components of the image to be displayed, and generate three enable signals based on a preset ratio of the lighting duration of the laser chips of N primary colors within one driving cycle. Each PWM signal is configured to control the brightness of the light beam emitted by the laser chip of the corresponding color among the laser chips of N primary colors. Each enable signal is configured to control the lighting duration of the laser chip of the corresponding color among the laser chips of N primary colors within one driving cycle.

[0006] The light source driving circuit is electrically connected to the laser chips of N primary colors. The light source driving circuit is electrically connected to the display control circuit and is configured to receive N PWM signals and three enable signals, so that when at least one of the three enable signals is at an effective potential, drive the laser chips of N primary colors to emit at least N colors of light beams according to the N PWM signals, realizing the illumination of multiple primary color lasers and providing a display with a wide color gamut and multiple color gamut modes for the projection screen. Description of the Drawings

[0007] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the accompanying drawings required for use in some embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, the actual timings of the signals, etc.

[0008] Figure 1 Structural diagram of a laser projection device according to some embodiments; Figure 2 Schematic diagram of the hardware control system architecture of a laser projection device according to some embodiments; Figures 3 - 5 Top view of three different internal structures of the laser component in the light source according to some embodiments; Figure 6 Schematic diagram of the structure of the first laser chip drive circuit according to some embodiments; Figure 7 For Figure 6 Specific structural diagram of the first laser chip drive circuit in Figure 8 For Figure 6 Structural diagram of the drive chip in Figure 9 Schematic diagram of the structure of the second laser chip drive circuit according to some embodiments; Figure 10 Schematic diagram of the structure of the third laser chip drive circuit according to some embodiments; Figures 11 - 13 Another three different circuit system diagrams of a laser projection device according to some embodiments; Figure 14 Another different circuit system diagram of a laser projection device according to some embodiments; Figure 15 Another timing diagram of the enable signal output by the display control circuit according to some embodiments; Figure 16 Schematic diagram of the structure of the fourth laser chip drive circuit according to some embodiments; Figure 17 Schematic diagram of the structure of the fifth laser chip drive circuit according to some embodiments; Figure 18 Schematic diagram of the structure of the sixth laser chip drive circuit according to some embodiments; Figure 19 Another different circuit system diagram of a laser projection device according to some embodiments; Figure 20 is Figure 19 a schematic structural diagram of a digital-to-analog converter in Figure 21 Another different circuit system diagram of a laser projection device according to some embodiments; Figures 22 - 23 Two more different circuit system diagrams of a laser projection device according to some embodiments.

[0009] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Detailed implementation manners

[0010] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0011] Some embodiments of the present disclosure provide a laser projection device. As Figure 1 shown, the laser projection device 10 includes a whole machine housing 900 ( Figure 1 only a part of the housing 900 is shown), a light source 100, an optical engine 200, and a lens 300 assembled in the whole machine housing 900. The light source 100 is configured to provide an illumination beam (laser beam). The optical engine 200 is configured to modulate the illumination beam provided by the light source 100 using an image signal to obtain a projection beam. The lens 300 is configured to project the projection beam onto a screen or a wall for imaging. In some embodiments, the laser projection device 10 further includes a screen, and the screen is disposed on the light output path of the lens 300, and the projection beam emitted by the lens 300 forms an image on the screen.

[0012] The light source 100, the optical engine 200, and the lens 300 are sequentially connected along the beam propagation direction, and each is wrapped by a corresponding housing.

[0013] The illumination beam emitted by the light source 100 enters the optical engine 200. The light source 100 is a laser light source and can emit laser beams of N primary colors, where N is greater than or equal to 4. For example, the light source 100 includes a red laser, a blue laser, a green laser, and a yellow laser, which emit red laser, blue laser, green laser, and yellow laser respectively. Or, the light source 100 includes a red laser, a blue laser, a green laser, a cyan laser, and a magenta laser, which emit red laser, Blue laser, green laser, cyan laser, and magenta laser. The core component in the optical engine 200 is the optical modulation component. In the embodiments of the present disclosure, a DLP (Digital Light Processing) projection architecture is provided, and the optical modulation component therein is a DMD (Digital Micromirror Device). Its function is to modulate the illumination beam provided by the light source 100 using the image signal, that is, to control the projection beam to display different colors and brightness for different pixels of the image to be displayed, so as to finally form an optical image. Therefore, the DMD is also called an optical modulation device or a light valve. According to whether the optical modulation device (or light valve) transmits or reflects the illumination beam, the optical modulation device (or light valve) can be divided into a transmissive optical modulation device (or light valve) or a reflective optical modulation device (or light valve). The liquid crystal light valve transmits the illumination beam, so it is a transmissive optical modulation device. In addition, according to the number of optical modulation devices (or light valves) used in the optical engine, the optical engine can be divided into a single-chip system, a two-chip system, or a three-chip system.

[0014] Moreover, the lens 300 can be a telephoto lens or a short-focus lens. In some embodiments, the laser projection device is an ultra-short-focus projection device, the lens 300 is an ultra-short-focus projection lens, and the projection ratio of the lens 300 is usually less than 0.3, such as 0.24.

[0015] Reference Figure 3 、 Figure 4 and Figure 5 In, some embodiments of the laser projection device, the light source 100 used may include two laser assemblies 140, and the two laser assemblies 140 are the first laser assembly 140A and the second laser assembly 140B respectively. Both the first laser assembly 140A and the second laser assembly 140B are MCL type assemblies. Among them, the first laser assembly 140A and the second laser assembly 140B can be packaged on the same substrate, or can be independently arranged on different substrates and then spliced for use.

[0016] As Figure 3 shown, each laser assembly 140 (that is, the first laser assembly 140A and the second laser assembly 140B) is packaged with a four-primary-color laser chip. The four-primary-color laser chip includes: a row of red laser chips 103, a row of green laser chips 102 capable of emitting green laser, a row of blue laser chips 103, and a row of yellow laser chips 104 capable of emitting yellow laser.

[0017] Figure 3Each laser component 140 among them includes, in addition to the red laser chip 101, the green laser chip 102, and the blue laser chip 103, a yellow laser chip 104. Therefore, when the light source 100 includes two laser components 140, each laser component 140 can generate an illumination beam containing four primary color lights. Thus, there is no need to provide a fluorescent wheel inside the light source 100. As a result, in some embodiments of the present disclosure, while simplifying the structure of the light source 100 and reducing the volume of the light source 100, not only can the brightness of the illumination beam be improved, but also the color gamut range of the illumination beam can be expanded.

[0018] In actual use, in order to improve the brightness of the illumination beam and expand the color gamut range of the illumination beam, the light source 100 may include at least two (i.e., two or more) laser components 140, and each laser component 140 includes corresponding color laser chips capable of emitting at least four colors of laser light.

[0019] As can be seen from the above, each laser component 140 includes at least four laser chips in order to generate at least three colors of laser light, thereby simplifying the structure of the light source 100. However, since the number of laser colors emitted by each laser component increases, more precise control of each laser component is also required.

[0020] As Figure 4 shown, the first laser component 140A is encapsulated with three-primary-color laser chips. The three-primary-color laser chips include: two rows of blue laser chips 103, one row of green laser chips 102, and one row of yellow laser chips 104. The second laser component 140B is encapsulated with a single-primary-color laser chip. The single-primary-color laser chip includes: two rows of red laser chips 101.

[0021] For example, Figure 4 among the two laser components 140 shown, only one of the laser components includes at least two laser chips, and the at least two laser chips, in addition to including the red laser chip 101, the green laser chip 102, and the blue laser chip 103, further include a yellow laser chip 104, while the other laser component only includes one laser chip. For example, the red laser chip 101 is separately encapsulated in one laser component. Therefore, when the light source 100 includes two laser components 140, one of the two laser components 140 can generate an illumination beam containing three-primary-color lights, and the other of the two laser components 140 can generate an illumination beam containing a fourth primary color light different from the three-primary-color lights. As a result, the two laser components 140 can not only improve the brightness of the illumination beam and expand the color gamut range of the illumination beam, but also enable separate control or cooperative control of the two laser components 140, so as to select an illumination beam of single-primary-color light, three-primary-color light, or four-primary-color light for display according to the actual situation.

[0022] As shown Figure 5 in FIG. 1, the first laser assembly 140A encapsulates four-color laser chips. The four-color laser chips include: a row of cyan laser chips 105 capable of emitting cyan laser light, a row of green laser chips 102, a row of blue laser chips 103, and a row of yellow laser chips 104. The second laser assembly 140B encapsulates single-color laser chips. The single-color laser chips include: two rows of red laser chips 101.

[0023] For example, Figure 5 in the two laser assemblies 140 shown in FIG. 2, only one of the laser assemblies includes at least two types of laser chips, and the at least two types of laser chips include, in addition to red laser chips 101, green laser chips 102, and blue laser chips 103, yellow laser chips 104 and cyan laser chips 105, while the other laser assembly includes only one type of laser chip. For example, the red laser chips 101 are individually encapsulated in one laser assembly. Therefore, when the light source 100 includes two laser assemblies 140, one of the two laser assemblies 140 can generate an illumination beam containing four primary colors of light, and the other laser assembly of the two laser assemblies 140 can generate an illumination beam containing a fifth primary color of light different from the four primary colors of light. As a result, the two laser assemblies 140 can not only improve the brightness of the illumination beam and expand the color gamut range of the illumination beam, but also achieve independent control or coordinated control of the two laser assemblies 140 so as to select an illumination beam of single primary color light, four primary color lights, or five primary color lights for display according to the actual situation.

[0024] In some embodiments, in order to improve the brightness of the illumination beam and expand the color gamut range of the illumination beam, one of the two laser assemblies 140 can encapsulate five-color laser chips. For example, the five-color laser chips include: a row of magenta laser chips capable of emitting magenta laser light, a row of cyan laser chips, a row of green laser chips, a row of blue laser chips, and a row of yellow laser chips. The other laser assembly of the two laser assemblies 140 can encapsulate single-color laser chips. For example, the single-color laser chips include: at least two rows of red laser chips. Therefore, one of the two laser assemblies 140 can also generate an illumination beam containing five primary colors of light, and the other laser assembly of the two laser assemblies 140 can generate an illumination beam containing a sixth primary color of light different from the five primary colors of light. In this way, the two laser assemblies 140 can not only expand the color gamut range of the illumination beam, but also achieve independent control or coordinated control of the two laser assemblies 140 so as to select an illumination beam of single primary color light, five primary color lights, or six primary color lights for display according to the actual situation.

[0025] In actual use, in order to increase the brightness of the illumination beam and expand the color gamut range of the illumination beam, the light source 100 may include at least two (two or more) laser assemblies 140. One or more of the at least two laser assemblies 140 include corresponding color laser chips capable of emitting at least three colors of laser light, and the remaining laser assemblies among the at least two laser assemblies 140 include corresponding color laser chips capable of emitting at least one color of laser light.

[0026] As can be seen from the above, one or more of the at least two laser assemblies 140 include at least three laser chips to generate at least three colors of laser light, and the remaining laser assemblies among the at least two laser assemblies 140 include at least one laser chip to generate at least one color of laser light different from the at least three colors, so that the at least two laser assemblies 140 generate at least four colors of laser light, thereby simplifying the structure of the light source 100. However, since the number of laser colors emitted by each laser assembly increases, more precise control of each laser assembly is also required.

[0027] It should be noted that the present disclosure does not limit the wavelength ranges of the multiple laser colors emitted by the laser assembly 140. For example, in the illumination beam of multi-primary color light emitted by the laser assembly 140, the wavelength range of the main wavelength of the red laser can be 643 nm ± 8 nm, the wavelength range of the main wavelength of the green laser can be 525 nm ± 8 nm, the wavelength range of the main wavelength of the blue laser can be 465 nm ± 8 nm, the wavelength range of the main wavelength of the yellow laser can be 575 nm ± 15 nm, and the wavelength range of the main wavelength of the yellow laser can be 488 nm ± 10 nm. Since magenta is a visually mixed color (for example, a mixture of red and blue) and does not have a single wavelength, the wavelength range of the main wavelength of the magenta laser can be 0 to 700 nm.

[0028] For this reason, as Figure 1 shown, the laser projection device 10 further includes a circuit system (power system architecture) 400, and the circuit system 400 can be a PCBA (Printed Circuit Board Assembly). Figure 1 Only the approximate position of the circuit system 400 is shown, and the specific position of the circuit system 400 can be arranged differently in different laser projection devices 10. The circuit system 400 is a control system circuit for controlling the light source 100 to emit light, and is configured to control the light source 100 to emit an illumination beam of N primary color lights according to the image quality requirements of the laser projection device 10. Here, N is a positive integer. For example, when N = 4, 5, or 6, the circuit system 400 can control the light source 100 to emit illumination beams of four-primary color light, five-primary color light, or six-primary color light, respectively.

[0029] In some embodiments, as Figure 2 shown, the laser projection device 10 further includes: a system main board 500, a display board 600, and a power supply board 700. The power supply board 700 is respectively connected to the system main board 500 and the display board 600, and is configured to supply power to each device or partial unit on the system main board 500 and the display board 600, and is configured to supply power to other functional units in the laser projection device, such as an eye protection unit, a fan, and a wireless-fidelity (WI-FI) unit, etc.

[0030] The system main board 500 is also connected to the display board 600. The system main board 500 is configured to receive the image data of the projection image sent by the front-end device and perform decoding processing on the image data. The system main board 500 may include a system on chip (SOC). The system on chip is configured to decode the image data in different data formats into a normalized format and transmit the image data in the normalized format to the display board 600. For example, the system main board 500 may transmit the image data in the normalized format to the display board 600 through a connector. The system main board may also be referred to as a television (TV) board.

[0031] A circuit system 400 is provided on the display board 600, and a light valve driving circuit 240 may also be provided. The circuit system 400 includes a display control circuit 401 and a light source driving circuit 402. The display control circuit 401 is connected to the system main board 500 and the light valve driving circuit 240, and is configured to receive the projection image to be displayed transmitted by the system main board 500 and convert the projection image signal to be displayed into a light valve driving signal and output it to the light valve. The display control circuit 401 is also connected to the light source driving circuit 402, and is further configured to output a light source driving signal to the light source driving circuit 402 based on the projection image to be displayed. The light source driving circuit 402 is connected to the light source 100, and is configured to receive the light source driving signal and control the light source 100 to emit light based on the light source driving signal. Among them, the light source driving signal may include an image enable signal and a brightness adjustment signal. The image enable signal is configured to control whether the light source 100 emits light (i.e., whether it is lit) to implement control of the light emission timing of the light source 100 that emits illumination beams of N primary colors. The image enable signal may be simply referred to as an enable signal. The brightness adjustment signal may be a pulse width modulation (PWM) signal, which is configured to control the brightness of the beams emitted by the laser chips of N primary colors in the light source 100.

[0032] In some embodiments, the display control circuit 401 includes an algorithm processor. The algorithm processor is connected to the system main board 500 and is configured to process the image data of the input projection screen, such as performing motion estimation and motion compensation (MEMC) frequency doubling processing or image correction processing. In this case, the display control circuit 401 is configured to receive the processed image data of the projection screen and use the processed projection screen as the projection screen to be displayed. The algorithm processor can be a field programmable gate array (FPGA). However, it is not limited thereto. In other embodiments, the algorithm processor can be omitted.

[0033] Wherein, a laser driver component for driving the laser light source to emit light can also be provided on the power supply board. Alternatively, the laser driver component can also be provided independently of the power supply board.

[0034] It should be noted that in different laser projection devices 10, the specific positions of the various components in the circuit system 400 can be arranged differently. In some embodiments, the display control circuit 401 and the algorithm processor in the circuit system 400 can be provided on the display board 600, and the setting position of the light source drive circuit 402 is not limited. For example, the light source drive circuit 402 can be provided on the power supply board 700 or can be provided independently of the power supply board 70 or the display board 600. At this time, only a part of the circuit system 400 is provided on the display board 600. Also, the light valve drive circuit 240 can be provided on the display board 600 or can be integrated into the display control circuit 401 of the display board.

[0035] The light valve drive circuit 240 is electrically connected to the display control circuit 401 and the light valve, and is further configured to generate a modulation drive signal for driving the light valve based on the projection image to be displayed.

[0036] Each laser component of each primary color in the light source 100 receives a corresponding enable signal and brightness adjustment signal, and lights up the laser chip of the corresponding primary color to emit light. Taking the first laser chip drive circuit 402A corresponding to the red laser chip 101 as an example, the structure and principle of the laser chip drive circuit will be described below.

[0037] As Figure 6As shown in the figure, the first laser chip driving circuit 402A includes: a driving chip U2 and an external sub-circuit connected to the driving chip U2. The external sub-circuit includes a positive output terminal LD3+ and a negative output terminal LD3-, which serve as the driving output terminals of the laser chip driving circuit 402A. The positive output terminal LD3+ can be connected to pins 0 and 2 of the red laser chip 101, and the negative output terminal LD3- can be connected to pins 1 and 3 of the red laser chip 101.

[0038] The driving chip U2 is configured to receive a red PWM signal R_PWM and an enable signal R_EN, and when the enable signal R_EN is at an effective potential, output a driving signal to the external sub-circuit according to the red PWM signal R_PWM, so that the external sub-circuit adjusts the output voltages of the positive output terminal LD3+ and the negative output terminal LD3- of the external sub-circuit according to the driving signal, so that the output voltages of the positive output terminal LD3+ and the negative output terminal LD3- meet the driving voltage requirements of the red laser chip 101.

[0039] As Figure 6 and Figure 7 shown in the figure, the driving chip U2 includes an rt pin, a drv pin (i.e., the output terminal of U2), an adim pin (i.e., the first input terminal of U2), a pwm pin (i.e., the second input terminal of U2), and an isen pin (i.e., the third input terminal of U2).

[0040] Figure 8 is the internal circuit diagram of the driving chip U2. As Figure 8 shown in the figure, the driving chip U2 further includes a divider x1, a switching frequency square wave generator hfosc, a voltage limiter max, a comparator lm1, a comparator lm2, a comparator lm3, and a buffer m1.

[0041] The divider x1 is configured to reduce the voltage of the adim pin. The comparator lm1 (i.e., the first comparator) is configured to compare the voltage reduced by the divider x1 with the voltage of the isen pin. The comparator lm3 (i.e., the second comparator) is configured to compare whether the voltage of the pwm pin exceeds 1V. The comparator lm2 (i.e., the third comparator) is configured to, when the voltage of the pwm pin exceeds 1V, compare the square wave signal value of the switching frequency square wave generator hfosc with the output signal value of the comparator lm1 to adjust the duty cycle of the driving signal output by the drv pin, thereby adjusting the voltage of the isen pin through the external sub-circuit.

[0042] It should be understood that when the voltage obtained after the voltage of the adim pin is reduced by the divider x1 is substantially equal to the voltage of the isen pin, the duty cycle of the drive signal output by the drv pin tends to be stable, thereby stabilizing the voltage of the isen pin. The first laser chip drive circuit 402A outputs a stable drive voltage through the positive output terminal LD3+ and the negative output terminal LD3-. In addition, in order to prevent the drive voltage output by the first laser chip drive circuit 402A from being too large and damaging the red laser chip 101, the stable voltage of the isen pin can be limited by the voltage limiter max in the drive chip U2.

[0043] As Figure 6 and Figure 7 shown, the adim pin of the drive chip U2 is configured to receive the red PWM signal R_PWM. In order to enable the red PWM signal R_PWM to match the rated voltage of the adim pin of the drive chip U2, the adim pin can be connected to the R_PWM output terminal of the display control circuit 401 through a voltage dividing resistor, so as to divide the received red PWM signal R_PWM through the voltage dividing resistor. The voltage dividing resistor can include resistor R10, resistor R11, and resistor R12. The adim pin can be connected to the R_PWM output terminal of the display control circuit 401 through the series-connected resistor R11 and resistor R12. The adim pin is also grounded through resistor R10.

[0044] In this way, the voltage U adim of the adim pin of the drive chip U2 can satisfy:

[0045] U R_PWM is the voltage of the red PWM signal R_PWM received by the laser chip drive circuit 402A, in millivolts.

[0046] As described above, when the voltage of the isen pin is stable, the voltage of the isen pin is equal to the voltage of the adim pin after being reduced by the divider x1. Therefore, the voltage U isen of the isen pin can satisfy

[0047] k is the reduction coefficient of the divider x1 in the drive chip U2.

[0048] In order to ensure the stability of the R_PWM signal, the connection end of the resistor R12 to the R_PWM output terminal of the display control circuit 401 is also connected to a pull-down resistor R13. In order to filter and shape the red PWM signal R_PWM, the adim pin can also be grounded through a capacitor C9.

[0049] The pwm pin of the driving chip U2 is connected to the R_EN output terminal of the display control circuit 401 and is configured to receive the enable signal R_EN corresponding to the red laser chip 101. In order to filter and shape the enable signal R_EN, as Figure 6 shown, the pwm pin is connected to the R_EN output terminal of the display control circuit 401 through the resistor R22 and is grounded through the parallel-connected capacitor C13 and resistor R23.

[0050] The drv pin of the driving chip U2 is configured to output a driving signal to an external sub-circuit, so that the external sub-circuit adjusts the driving voltage output to the external sub-circuit and the voltage of the isen pin according to the duty cycle of the driving signal.

[0051] The isen pin of the driving chip U2 is configured to be connected to an external sub-circuit and receive the feedback voltage of the external sub-circuit (i.e., the voltage of the isen pin), so that when the driving chip U2 receives that the enable signal R_EN is at an effective potential, it adjusts the duty cycle of the driving signal output to the external sub-circuit according to the voltage of the isen pin and the voltage of the adim pin.

[0052] As Figure 7 shown, the external sub-circuit includes a power supply VDD2, a transformer L2, a switching field-effect transistor Q1, and a sampling resistor Risen. The power supply VDD2 provides power for the first laser chip driving circuit 402A. One end of the sampling resistor Risen is connected to the isen pin of the driving chip U2 and the source electrode of the switching field-effect transistor Q1, and the other end of the sampling resistor Risen is grounded. The gate of the switching field-effect transistor Q1 is connected to the drv pin of the driving chip U2, and the drain of the switching field-effect transistor is connected to the power supply VDD2. The source electrode of the switching field-effect transistor Q1 is also connected to the negative output terminal LD3- through the transformer L2.

[0053] In this way, when the driving chip U2 receives that the enable signal R_EN is at an effective potential, it adjusts the duty cycle of the driving signal output by the drv pin according to the voltage of the above-mentioned isen pin to control the switching state of the switching field-effect transistor Q1, so that when the switching field-effect transistor Q1 is in the conducting state, it connects the power supply VDD2 and one end of the transformer L2, thereby changing the output voltage of the negative output port LD3- through the transformer L2, and further changing the current on the sampling resistor Risen (i.e., the driving current input to the red laser chip 101) and the voltage of the isen pin.

[0054] When the duty cycle of the driving signal output by the drv pin no longer changes, the driving signal output by the drv pin tends to be stable. At this time, the output voltage of the negative output terminal LD3- and the current on the sampling resistor Risen tend to be stable, and the first laser chip driving circuit 402A outputs a stable driving voltage and a stable driving current to the red laser chip 101.

[0055] It should be understood that the driving current I provided by the first laser chip driving circuit 402A to the red laser chip laser (in milliamperes) can be

[0056] k is the reduction coefficient of the divider x1 in the driving chip U2. R isen is the above-mentioned sampling resistor, in ohms. As Figure 7 shown, the sampling resistor Risen includes resistors R15, R16, R17, and R18 connected in parallel. R in the above formula isen is the resistance value after resistors R15, R16, R17, and R18 are connected in parallel, and can be expressed as R isen = R15 / / R16 / / R17 / / R18, where " / / " represents parallel connection.

[0057] The rt pin of the driving chip U2 can be grounded through the resistor R24. The frequency of the driving signal output by the drv pin in the driving chip U2 is determined by the resistance value of the resistor R24. That is to say, the switching frequency of the switching field-effect transistor Q1 can be determined by the resistance value of the resistor R24.

[0058] In addition, as Figure 7 shown, the drv pin of the driving chip U2 can be connected to the gate of the switching field-effect transistor Q1 through a shaping circuit. The shaping circuit can include a diode D1, a resistor R19, and a resistor R20. The diode D1 is connected in series with the resistor R20 and then in parallel with the resistor R19, and the cathode of the diode is connected to the drv pin. Through this shaping circuit, the slope of the rising edge or the falling edge of the driving signal output by the drv pin can be adjusted to make the slope of the rising edge or the falling edge of the driving signal output by the drv pin smoother.

[0059] Exemplarily, as Figure 7As shown, a diode combination is also provided between the power supply VDD2 and the transformer L2, and this diode combination is also connected between the power supply VDD2 and the drain of the switching field-effect transistor Q1. The diode combination is configured to conduct the power supply VDD2 to the transformer L2 when the switching field-effect transistor Q1 is turned on; and when the switching field-effect transistor Q1 is turned off, discharge the driving current flowing to the transformer L2. The diode combination includes two diodes D2 connected in parallel, and the anode of each diode D2 is connected to the drain of the switching field-effect transistor Q1, and the cathode of each diode D2 is connected to the power supply.

[0060] As Figure 7 shown, a capacitor C16 is also connected between the positive output terminal LD3+ and the negative output terminal LD3-. The capacitor C16 is matched with the capacitance characteristics of the red laser chip 101.

[0061] Exemplarily, as Figure 7 shown, the drive chip U2 also includes a VCC pin, an st pin, a vref pin, and a GND pin.

[0062] The VCC pin of the drive chip U2 is connected to the power supply VDD1. The st pin of the drive chip U2 can be connected to the alarm terminal FLG through the triode B1. For example, the st pin is connected to the base of the triode B1 through the resistor R26, the alarm terminal FLG is connected to the base of the triode B1 through the resistor R27, the emitter of the triode B1 is connected to the alarm terminal FLG, and the collector of the triode B1 is grounded. The alarm terminal FLG is configured to output an alarm signal to the external power supply circuit connected to the power supply pin VCC of the drive chip U2 when an abnormal current occurs in the first laser chip drive circuit 402A, so that the external power supply circuit stops supplying power to the drive chip U2. The vref pin of the drive chip U2 can be grounded through the capacitor C15. The GND pin of the drive chip U2 is grounded.

[0063] According to the above description of the drive chip U2, the enable signal R_EN corresponding to the red laser chip 101 input to the pwm pin of the drive chip U2 is the enable signal of the drive chip U2. When this enable signal R_EN is at an effective potential, the drive chip U2 works normally. The drive chip U2 can adjust the duty cycle of the drive signal output by the drv pin according to the voltage of the R_PWM signal input to the adim pin and the voltage of the isen pin, so as to adjust the output voltage of the negative output port LD3- through an external sub-circuit, and further realize the adjustment of the drive voltage applied to the red laser chip 101, so that the red laser chip 101 works under a constant current. When this enable signal R_EN is at an invalid potential, the drive chip U2 stops working and the red laser chip 101 does not emit light.

[0064] It should be understood that the above Figure 7The structure of the first laser chip driving circuit 402A shown is only an example. During actual implementation, the circuit structure of the first laser chip driving circuit 402A can be adaptively adjusted under the condition of meeting the basic functions. Therefore, the above Figure 7 The circuit structure of the first laser chip driving circuit 402A shown does not limit the structure of the laser chip driving circuit in the embodiments of the present disclosure.

[0065] Figure 9 The structure of the second laser chip driving circuit 402B corresponding to the green laser chip 102 is Figure 9 The positive output terminal LD1+ in it can be connected to pin 4 of the green laser chip 102, and the negative output terminal LD1- can be connected to pin 5 of the green laser chip 102. Figure 10 The structure of the third laser chip driving circuit 402C corresponding to the blue laser chip 103 is Figure 10 The positive output terminal LD2+ in it can be connected to pin 6 of the blue laser chip 103, and the negative output terminal LD2- can be connected to pin 7 of the blue laser chip 103. In some embodiments, the second laser chip driving circuit 402B and the third laser chip driving circuit 402C are the same as the first laser chip driving circuit 402A in terms of structure, connection relationship, and working principle, and will not be elaborated here.

[0066] In some embodiments, taking the light source 100 including at least two laser assemblies 140 as an example, the at least two laser assemblies 140 generate five-primary-color lasers, and the five-primary-color laser chips include a red laser chip 101, a green laser chip 102, a blue laser chip 103, a yellow laser chip 104, and a cyan laser chip 105 for illustration.

[0067] As Figure 11 shown, the light source driving circuit 402 in the circuit system 400 includes laser chip driving circuits 402A, 402B, 402C, 402D, and 402E.

[0068] The first laser chip driving circuit 402A is connected to the red laser chip 101 and is configured to control the red laser chip 101 to emit a red illumination beam. The second laser chip driving circuit 402B is connected to the green laser chip 102 and is configured to control the green laser chip 104 to emit a green illumination beam. The third laser chip driving circuit 402C is connected to the blue laser chip 103 and is configured to control the blue laser chip 103 to emit a blue illumination beam. The fourth laser chip driving circuit 402D is connected to the yellow laser chip 104 and is configured to control the yellow laser chip 104 to emit a yellow illumination beam. The fifth laser chip driving circuit 402E is connected to the cyan laser chip 105 and is configured to control the cyan laser chip 105 to emit a cyan illumination beam.

[0069] The display control circuit 401 in the circuit system 400 is electrically connected to the five laser chip driving circuits 402A, 402B, 402C, 402D, and 402E, and is configured to generate five PWM signals corresponding to the five primary color laser chips (i.e., the red laser chip 101, the green laser chip 102, the blue laser chip 103, the yellow laser chip 104, and the cyan laser chip 105) based on the five primary color components of the image to be displayed, and generate three enable signals based on a preset ratio of the lighting duration of the five primary color laser chips within one driving cycle. The PWM signals are configured to control the brightness of the beams emitted by the corresponding color laser chips among the five primary color laser chips. The enable signals are configured to control the lighting duration of at least two of the five primary color laser chips within one driving cycle.

[0070] As Figure 11 shown, the circuit system 400 further includes a logic circuit 406. The logic circuit 406 is electrically connected to the display control circuit 401 and the five laser chip driving circuits 402A, 402B, 402C, 402D, and 402E. The logic circuit 406 is configured to generate five duty signals based on the three enable signals, and the five duty signals respectively correspond to the five primary color laser chips (i.e., the red laser chip 101, the green laser chip 102, the blue laser chip 103, the yellow laser chip 104, and the cyan laser chip 105). The duty signals are configured to control the lighting duration of the corresponding color laser chips among the five primary color laser chips within one driving cycle.

[0071] In some embodiments, the display control circuit 401 may also be configured to generate five PWM signals corresponding to the five primary color laser chips (i.e., the red laser chip 101, the green laser chip 102, the blue laser chip 103, the yellow laser chip 104, and the cyan laser chip 105) based on the five primary color components in the preset color matching scheme of the laser projection device 10.

[0072] It should be noted that the working principle of the display control circuit 401 configured to generate five PWM signals corresponding to the five-color laser chips based on the five primary color components in the preset color matching scheme of the laser projection device 10 or based on the five primary color components of the image to be displayed is the same as that of the display control circuit 401 in the foregoing embodiments of the present disclosure configured to generate three PWM signals corresponding to the three-color laser chips based on the three primary color components in the preset color matching scheme of the laser projection device 10 or based on the three primary color components of the image to be displayed, and thus will not be elaborated herein.

[0073] In some embodiments, the driving period of the five-color laser chip is also the same as the display period of one frame of color image.

[0074] Exemplarily, the display control circuit 401 may generate a red PWM signal R_PWM (i.e., the first PWM signal) corresponding to the red laser chip 101 based on the red component of the image to be displayed; the display control circuit 401 may further generate a green PWM signal G_PWM (i.e., the second PWM signal) corresponding to the green laser chip 102 based on the green component of the image to be displayed; the display control circuit 401 may further generate a blue PWM signal B_PWM (i.e., the third PWM signal) corresponding to the blue laser chip 103 based on the blue component of the image to be displayed; the display control circuit 401 may further generate a yellow PWM signal Y_PWM (i.e., the fourth PWM signal) corresponding to the yellow laser chip 104 based on the yellow component of the image to be displayed; the display control circuit 401 may further generate a cyan PWM signal C_PWM (i.e., the fifth PWM signal) corresponding to the cyan laser chip 105 based on the cyan component of the image to be displayed.

[0075] The display control circuit 401 may generate a first enable signal R_EN based on the preset ratio of the lighting duration of the red laser chip 101 and the yellow laser chip 104 within one driving period; the display control circuit 401 may further generate a second enable signal G_EN based on the preset ratio of the lighting duration of the green laser chip 102, the yellow laser chip 104, and the cyan laser chip 105 within one driving period; the display control circuit 401 may further generate a third enable signal B_EN based on the preset ratio of the lighting duration of the blue laser chip 103 and the cyan laser chip 105 within one driving period.

[0076] The logic circuit 406 can generate a first duty cycle signal R'_EN (i.e., the duty cycle signal corresponding to the red laser chip 101), a second duty cycle signal G'_EN (i.e., the duty cycle signal corresponding to the green laser chip 102), a third duty cycle signal B'_EN (i.e., the duty cycle signal corresponding to the blue laser chip 103), a fourth duty cycle signal Y'_EN (i.e., the duty cycle signal corresponding to the yellow laser chip 104), and a fifth duty cycle signal C'_EN (i.e., the duty cycle signal corresponding to the cyan laser chip 105) based on the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN.

[0077] As Figure 11 As shown, the above laser chip driving circuits 402A, 402B, 402C, 402D, and 402E are connected to the output terminals of the display control circuit 401 and are configured to receive the PWM signals corresponding to the laser chips of the five primary colors output by the display control circuit 401. The above laser chip driving circuits 402A, 402B, 402C, 402D, and 402E are also connected to the output terminals of the logic circuit 406 and are configured to receive the duty cycle signals corresponding to the laser chips of the five primary colors output by the logic circuit 406, and when the duty cycle signal is at an effective potential (such as a high level or a high potential), output a driving voltage or a driving current according to the PWM signal, so that the laser chips of the five primary colors emit illumination beams under the drive of the driving voltage or the driving current.

[0078] Exemplarily, the display control circuit 401 includes at least eight output terminals, namely an R_PWM output terminal, a G_PWM output terminal, a B_PWM output terminal, a Y_PWM output terminal, a C_PWM output terminal, an R_EN output terminal, a G_EN output terminal, and a B_EN output terminal. The logic circuit 406 includes at least five output terminals, namely an R'_EN output terminal, a G'_EN output terminal, a B'_EN output terminal, a Y'_EN output terminal, and a C'_PWM output terminal.

[0079] The R_EN output terminal is configured to output a first enable signal R_EN, the G_EN output terminal is configured to output a second enable signal G_EN, and the B_EN output terminal is configured to output a third enable signal B_EN. The input terminal of the logic circuit 406 is connected to the R_EN output terminal, the G_EN output terminal, and the B_EN output terminal, and is configured to receive the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN. When at least one of the three received enable signals R_EN, G_EN, and B_EN is at an effective potential (e.g., a high potential, also known as a high level), the logic circuit 406 adjusts the output of the first duty cycle signal R′_EN corresponding to the red laser chip 101, the second duty cycle signal G′_EN corresponding to the green laser chip 102, the third duty cycle signal B′_EN corresponding to the blue laser chip 103, the fourth duty cycle signal Y′_EN corresponding to the yellow laser chip 104, and the fifth duty cycle signal C′_EN corresponding to the cyan laser chip 105.

[0080] The R_PWM output terminal is configured to output a red PWM signal R_PWM; the R′_EN output terminal is configured to output a first duty cycle signal R′_EN. The input terminal of the first laser chip driving circuit 402A is connected to the R_PWM output terminal of the display control circuit 401 and the R′_EN output terminal in the logic circuit 406, and is configured to receive the red PWM signal R_PWM and the first duty cycle signal R′_EN. When the received first duty cycle signal R′_EN is at an effective potential (e.g., a high potential, also known as a high level), according to the voltage of the received PWM signal R_PWM, the first laser chip driving circuit 402A adjusts the output red laser driving voltage and loads the red laser driving voltage onto the pins of the red laser chip 101, so that the red laser chip 101 emits a red light beam (i.e., the first color light beam).

[0081] The G_PWM output terminal is configured to output a green PWM signal G_PWM; the G′_EN output terminal is configured to output a second duty cycle signal G′_EN. The input terminal of the second laser chip driving circuit 402B is connected to the G_PWM output terminal in the display control circuit 401 and the G′_EN output terminal in the logic circuit 406, and is configured to receive the green PWM signal G_PWM and the second duty cycle signal G′_EN. When the received second duty cycle signal G′_EN is at an effective potential (e.g., a high potential, also known as a high level), according to the voltage of the received PWM signal G_PWM, the second laser chip driving circuit 402B adjusts the output green laser driving voltage, loads the green laser driving voltage onto the pins of the green laser chip 102, so that the green laser chip 102 emits a green light beam (i.e., the second color light beam).

[0082] The B_PWM output terminal is configured to output a blue PWM signal B_PWM; the B'_EN output terminal is configured to output a third duty cycle signal B'_EN. The input terminal of the third laser chip driving circuit 402C is connected to the B_PWM output terminal in the display control circuit 401 and the B'_EN output terminal in the logic circuit 406, and is configured to receive the blue PWM signal B_PWM and the third duty cycle signal B'_EN, and when the received third duty cycle signal B'_EN is at an effective potential (for example, a high potential, also known as a high level), according to the voltage of the received PWM signal B_PWM, adjust the blue laser driving voltage output by the third laser chip driving circuit 402C, and load the blue laser driving voltage onto the pins of the blue laser chip 103, so that the blue laser chip 103 emits a blue light beam (i.e., the third color light beam).

[0083] The Y_PWM output terminal is configured to output a yellow PWM signal Y_PWM; the Y'_EN output terminal is configured to output a fourth duty cycle signal Y'_EN. The input terminal of the fourth laser chip driving circuit 402D is connected to the Y_PWM output terminal in the display control circuit 401 and the Y'_EN output terminal in the logic circuit 406, and is configured to receive the yellow PWM signal Y_PWM and the fourth duty cycle signal Y'_EN, and when the received fourth duty cycle signal Y'_EN is at an effective potential (for example, a high potential, also known as a high level), according to the voltage of the received PWM signal Y_PWM, adjust the yellow laser driving voltage output by the fourth laser chip driving circuit 402D, and load the yellow laser driving voltage onto the pins of the yellow laser chip 104, so that the yellow laser chip 104 emits a yellow light beam (i.e., the fourth color light beam).

[0084] The C_PWM output terminal is configured to output a cyan PWM signal C_PWM; the C'_EN output terminal is configured to output a fifth duty cycle signal C'_EN. The input terminal of the fifth laser chip driving circuit 402E is connected to the C_PWM output terminal in the display control circuit 401 and the C'_EN output terminal in the logic circuit 406, and is configured to receive the cyan PWM signal C_PWM and the fifth duty cycle signal C'_EN, and when the received fifth duty cycle signal C'_EN is at an effective potential (for example, a high potential, also known as a high level), according to the voltage of the received PWM signal C_PWM, adjust the cyan laser driving voltage output by the fifth laser chip driving circuit 402D, and load the cyan laser driving voltage onto the pins of the cyan laser chip 105, so that the cyan laser chip 105 emits a cyan light beam (i.e., the fifth color light beam).

[0085] Of course, in some embodiments, the light source 100 includes at least two laser assemblies 140. The at least two laser assemblies 140 generate lasers of four primary colors, and the laser chips of the four primary colors include a red laser chip 101, a green laser chip 102, a blue laser chip 103, and a yellow laser chip 104. At this time, as Figure 12 shown, the light source driving circuit 402 of the circuit system 400 may only include four laser chip driving circuits. The four laser chip driving circuits can be electrically connected to the corresponding pins of the laser chips of the four colors respectively, and are all electrically connected to the display control circuit 401 and the logic circuit 406. The four laser chip driving circuits can be the first laser chip driving circuit 402A, the second laser chip driving circuit 402B, the third laser chip driving circuit 402C, and the fourth laser chip driving circuit 402D respectively. Among them, the structures, connection relationships, and working principles of the first laser chip driving circuit 402A, the second laser chip driving circuit 402B, the third laser chip driving circuit 402C, and the fourth laser chip driving circuit 402D are respectively the same as those of Figure 11 the first laser chip driving circuit 402A, the second laser chip driving circuit 402B, the third laser chip driving circuit 402C, and the fourth laser chip driving circuit 402D in

[0086] and will not be elaborated here. Figure 11 Compared with the circuit system 400 shown in

[0087] Of course, in some embodiments, the light source 100 includes at least two laser assemblies 140 that generate six-primary-color lasers, and the six-primary-color laser chips include a red laser chip 101, a green laser chip 102, a blue laser chip 103, a yellow laser chip 104, a cyan laser chip 105, and a magenta laser chip 106. At this time, as Figure 13 shown, the light source driving circuit 402 of the circuit system 400 may include more (e.g., six) laser chip driving circuits. The six laser chip driving circuits may be electrically connected to the six-color laser chips respectively, for example, through the corresponding pins of the lasers or through the conductive regions on the circuit board welded to the lasers, and are all electrically connected to the display control circuit 401 and the logic circuit 406. The six laser chip driving circuits may be the first laser chip driving circuit 402A, the second laser chip driving circuit 402B, the third laser chip driving circuit 402C, the fourth laser chip driving circuit 402D, the fifth laser chip driving circuit 402E, and the sixth laser chip driving circuit 402F respectively. Among them, the structures, connection relationships, and working principles of the first laser chip driving circuit 402A, the second laser chip driving circuit 402B, the third laser chip driving circuit 402C, the fourth laser chip driving circuit 402D, and the fifth laser chip driving circuit 402E are respectively the same as those of the first laser chip driving circuit 402A, the second laser chip driving circuit 402B, the third laser chip driving circuit 402C, the fourth laser chip driving circuit 402D, and the fifth laser chip driving circuit 402E in Figure 11 , and will not be elaborated here.

[0088] The sixth laser chip driving circuit 402F is connected to the magenta laser chip 106 and is configured to control the magenta laser chip 106 to emit a magenta illumination beam.

[0089] With Figure 11Compared with the circuit system 400 shown, the difference is only that a laser chip driving circuit corresponding to a color (for example, the magenta laser chip driving circuit 402F) is newly added to the light source driving circuit 402 of the circuit system 400. Correspondingly, the display control circuit 401 is electrically connected to six laser chip driving circuits 402A, 402B, 402C, 402D, 402E, and 402F, and is configured to generate six PWM signals corresponding to the six primary color laser chips (i.e., the red laser chip 101, the green laser chip 102, the blue laser chip 103, the yellow laser chip 104, the cyan laser chip 105, and the magenta laser chip 106) based on the six primary color components of the image to be displayed, and generate three enable signals based on the preset ratio of the lighting duration of the six primary color laser chips within one driving cycle. The logic circuit 406 is electrically connected to the display control circuit 401 and the six laser chip driving circuits 402A, 402B, 402C, 402D, 402E, and 402F, and is configured to generate six duty signals based on the three enable signals, and the six duty signals respectively correspond to the six primary color laser chips.

[0090] In some embodiments, the logic circuit 406 includes at least one AND gate and at least one NOT gate. Among them, the AND gate is also called "AND circuit", logical "product" circuit or logical "AND" circuit; the AND gate has multiple input terminals and one output terminal; when all inputs are at high level (logic 1) simultaneously, the output is at high level, otherwise the output is at low level (logic 0). The NOT gate is also called NOT circuit, inverter, phase inverter, logical negation circuit; the NOT gate has one input terminal and one output terminal; when its input terminal is at high level (logic 1), the output terminal is at low level (logic 0), and when its input terminal is at low level, the output terminal is at high level; that is to say, the level states of the input terminal and the output terminal are always opposite.

[0091] Exemplarily, in some embodiments, such as Figure 14As shown, the logic circuit 406 includes five AND gates 4061A, 4061B, 4061C, 4061D, and 4061E, and two NOT gates 4062A and 4062B. The first AND gate 4061A has two input terminals. One input terminal of the first AND gate 4061A is used to receive one of the three enable signals (e.g., the first enable signal R_EN), and the other input terminal of the first AND gate 4061A is connected to the output terminal of the first NOT gate 4062A; the output terminal of the first AND gate 4061A is used to output the first enable signal R_EN or one of the five duty cycle signals (e.g., the first duty cycle signal R′_EN). The second AND gate 4061B has three input terminals. One input terminal of the second AND gate 4061B is used to receive another one of the three enable signals (e.g., the second enable signal G_EN), and the other two input terminals of the second AND gate 4061B are respectively connected to the output terminal of the first NOT gate 4062A and the output terminal of the second NOT gate 4062B; the output terminal of the second AND gate 4061B is used to output the second enable signal G_EN or another one of the five duty cycle signals (e.g., the second duty cycle signal G′_EN). The third AND gate 4061C has two input terminals. One input terminal of the third AND gate 4061C is used to receive one of the three enable signals other than the above two enable signals (e.g., the third enable signal B_EN), and the other input terminal of the third AND gate 4061C is connected to the output terminal of the second NOT gate 406BA; the output terminal of the third AND gate 4061C is used to output the third enable signal B_EN or one of the five duty cycle signals other than the above three duty cycle signals (e.g., the third duty cycle signal B′_EN). The fourth AND gate 4061D has two input terminals. The two input terminals of the fourth AND gate 4061D are respectively connected to the output terminal of the first AND gate 4061A and the output terminal of the second AND gate 4061B, and are used to respectively receive the corresponding two of the three enable signals (i.e., the enable signal R_EN and the enable signal G_EN); the output terminal of the fourth AND gate 4061D is used to output one of the five duty cycle signals other than the above three duty cycle signals (e.g., the fourth duty cycle signal Y′_EN). The input terminal of the first NOT gate 4062A is connected to the output terminal of the fourth AND gate 4061D, and the output terminal of the first NOT gate 4062A is connected to the input terminals of the first AND gate 4061A and the second AND gate 4061B. The output terminal of the fifth AND gate 4061E is used to output one of the five duty cycle signals other than the above four duty cycle signals (e.g., the fifth duty cycle signal C′_EN).The fifth AND gate 4061E has two input terminals. The two input terminals of the fifth AND gate 4061E are respectively connected to the output terminal of the second AND gate 4061B and the output terminal of the third AND gate 4062B, and are used to receive two corresponding enable signals among the three enable signals (i.e., the enable signal G_EN and the enable signal B_EN); the output terminal of the fifth AND gate 4061E is used to output an enable signal other than the above four enable signals among the five duty cycle signals (for example, the fifth duty cycle signal C'_EN). The input terminal of the second NOT gate 4062B is connected to the output terminal of the fifth AND gate 4061E, and the output terminal of the second NOT gate 4062B is connected to the input terminal of the second AND gate 4061B and the input terminal of the third AND gate 4061C.

[0092] It should be noted that Figure 14 Taking the example that one input terminal of the first AND gate 4061A receives the enable signal R_EN, one input terminal of the second AND gate 4061B receives the enable signal G_EN, and one input terminal of the third AND gate 4061A receives the enable signal B_EN for illustration, but the input order of the three enable signals R_EN, G_EN, and B_EN is not limited.

[0093] In this way, through the AND gates and NOT gates of the logic circuit 406, the three enable signals output by the display control circuit 401 can be converted into five duty cycle signals corresponding to the five primary color laser chips.

[0094] Table 1 shows the corresponding relationship between the enable signals generated by the display control circuit 401 and the duty cycle signals generated by the logic circuit 406. Table 1

[0095] In some examples, referring to Table 1, when the potentials of the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN generated by the display control circuit 401 are 1, 0, and 0 respectively, the logic circuit 406 generates a first duty cycle signal R'_EN, and the potential of the first duty cycle signal R'_EN is 1; when the potentials of the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN generated by the display control circuit 401 are 0, 1, and 0 respectively, the logic circuit 406 generates a second duty cycle signal G'_EN, and the potential of the second duty cycle signal G'_EN is 1; when the potentials of the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN generated by the display control circuit 401 are 0, 0, and 1 respectively, the logic circuit 406 generates a third duty cycle signal B'_EN, and the potential of the third duty cycle signal B'_EN is 1; when the potentials of the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN generated by the display control circuit 401 are 1, 1, and 0 respectively, the logic circuit 406 generates a fourth duty cycle signal Y'_EN, and the potential of the fourth duty cycle signal Y'_EN is 1; when the potentials of the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN generated by the display control circuit 401 are 0, 1, and 1 respectively, the logic circuit 406 generates a fifth duty cycle signal C'_EN, and the potential of the fifth duty cycle signal C'_EN is 1; when the potentials of the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN generated by the display control circuit 401 are 0, 0, and 0 respectively, the logic circuit 406 generates a reset period signal, and the potential of the reset period signal is 0.

[0096] Among them, the reset period signal is a signal for turning off the light source 100. The reset period refers to selecting a time period during which at least one laser chip of the light source 100 for a primary color is turned off and does not emit light, and the light valve randomly executes an instruction to flip a plurality of micromirror elements; the purpose is to prevent the corresponding drive structure of the micromirror elements of the light valve from forming mechanical fatigue and performance degradation in some fixed deflection states for a long time. During the off stage of the laser chip, the micromirror elements can randomly vibrate. Exemplarily, the reset period signal can be a general enable signal juxtaposed with the duty cycle signals of multiple primary colors (e.g., five primary colors). During the period when the reset period signal is valid, all laser chips in the light source 100 are turned off, that is, no laser chip emits a light beam. Therefore, the enable signals of the laser chips of various primary colors are all invalid at this time. Alternatively, the reset period signal can also be included within the valid period of the timing enable signal of one primary color. At this time, the reset period signal can only occupy a certain period or a proportion of the period within the valid period of the enable signal of a certain primary color light. For example, during the period when blue laser light emits, a small period of time starting from the starting moment is selected and the blue laser chip is not actually lit, but is lit after a delay. The period of this delay is the reset period. During the reset period, the light source 100 does not emit a laser beam.

[0097] In some embodiments, the reset period signal RESET is not issued by the logic circuit 406, but by the display control circuit 401. For example, the display control circuit 401 is further configured to reserve the reset period signal when generating the first enable signal R_EN, the second enable signal G_EN, and the third enable signal B_EN.

[0098] Exemplarily, in some embodiments, a driving cycle of the light source 100 may include: a timing output stage. During the timing output stage, the light source 100 can sequentially output lights of different colors under the control of the laser chip driving circuits 402A, 402B, 402C, 402D, and 402E. For example, during the timing output stage, the light source 100 sequentially outputs red light, green light, blue light, yellow light, and cyan light.

[0099] In the timing output stage, the time periods during which the five duty cycle signals generated by the logic circuit 406 are at the effective potential do not overlap with each other. For example, in the red light output stage, the first duty cycle signal R'_EN corresponding to the red laser chip 101 generated by the logic circuit 406 is at the effective potential; in the green light output stage, the second duty cycle signal G'_EN corresponding to the green laser chip 102 generated by the logic circuit 406 is at the effective potential; in the blue light output stage, the third duty cycle signal B'_EN corresponding to the blue laser chip 103 generated by the logic circuit 406 is at the effective potential; in the yellow light output stage, the fourth duty cycle signal Y'_EN corresponding to the yellow laser chip 104 generated by the logic circuit 406 is at the effective potential; in the cyan light output stage, the fifth duty cycle signal C'_EN corresponding to the cyan laser chip 105 generated by the logic circuit 406 is at the effective potential.

[0100] During the entire timing output stage, the time periods during which the three enable signals generated by the display control circuit 401 are at the effective potential partially overlap. Among them, in a part of the timing output stage, the time periods during which the three enable signals generated by the display control circuit 401 are at the effective potential do not overlap with each other. For example, in the red light output stage, only the first enable signal R_EN generated by the display control circuit 401 is at the effective potential; in the green light output stage, only the second enable signal G_EN generated by the display control circuit 401 is at the effective potential; in the blue light output stage, only the third enable signal B_EN generated by the display control circuit 401 is at the effective potential.

[0101] In the remaining part of the timing output stage, the time periods during which M enable signals among the three enable signals generated by the display control circuit 401 are at the effective potential overlap, where M is a positive integer greater than 1 and less than three. For example, in the yellow light output stage, both the first enable signal R_EN and the second enable signal G_EN generated by the display control circuit 401 are at the effective potential; in the cyan light output stage, both the enable signal G_EN and the enable signal B_EN generated by the display control circuit 401 are at the effective potential.

[0102] In some embodiments, a driving cycle of the light source 100 may further include: a timing shutdown stage. In the timing shutdown stage, the light source 100 outputs no light beams during the timing shutdown stage.

[0103] Such as Figure 15As shown in the figure, taking the light source 100 as an example, which includes a laser chip with five primary colors, and the laser chip with five primary colors includes a red laser chip 101, a green laser chip 102, a blue laser chip 103, a yellow laser chip 104, and a cyan laser chip 105. During a driving cycle of the light source 100, the ratio of the durations of the effective potentials of the five duty cycle signals satisfies a preset ratio. Assume that when the laser projection device 10 meets the optimal color coordinate requirements, the ratio (i.e., the preset ratio) of the lighting durations of the red laser chip 101, the green laser chip 102, the blue laser chip 103, the yellow laser chip 104, and the cyan laser chip 105 in each driving cycle is 2:2:2:1:1. If a driving cycle T includes a timing output stage, R' represents the duration of the duty cycle signal R'_EN being at the effective potential within a driving cycle; G' represents the duration of the duty cycle signal G'_EN being at the effective potential within a driving cycle; B' represents the duration of the duty cycle signal B'_EN being at the effective potential within a driving cycle; Y' represents the duration of the duty cycle signal Y'_EN being at the effective potential within a driving cycle; C' represents the duration of the duty cycle signal C'_EN being at the effective potential within a driving cycle, then the duration R of the enable signal R_EN being at the effective potential within a driving cycle is R = R' + Y', the duration G of the enable signal G_EN being at the effective potential within a driving cycle is G = G' + Y' + C', and the duration B of the enable signal B_EN being at the effective potential within a driving cycle is B = B' + C'. At this time, the ratio of the durations of the effective potentials of the three enable signals R_EN, G_EN, and B_EN in each driving cycle is R:G:B = 3:4:3. If a driving cycle T further includes a timing shutdown stage, and S represents the duration when all enable signals are at the invalid potential within a driving cycle, then a driving cycle T = R + G + B + S.

[0104] In this way, by adding the yellow laser chip 104 and the cyan laser chip 105, when a driving cycle only includes a timing output stage (i.e., no output stage) except for the timing shutdown stage, not only can the light emitted by the light source 100 meet the brightness requirements of the laser projection device 10, but also the colors in the image displayed by the laser projection device 10 can be made more vivid and have a wider color gamut.

[0105] The above laser chip driving circuits 402A, 402B, 402C, 402D, 402E, and 402F can adopt a boost driving method or a buck driving method to drive the corresponding color laser chips to emit light.

[0106] Figure 16 The structure of the fourth laser chip driving circuit 402D corresponding to the yellow laser chip 104 Figure 16The positive output terminal LD4+ in it can be connected to the positive pin of the yellow laser chip 104, and the negative output terminal LD4- can be connected to the negative pin of the yellow laser chip 104. Figure 17 It is the structure of the fifth laser chip driving circuit 402E corresponding to the cyan laser chip 105. Figure 17 The positive output terminal LD5+ in it can be connected to the positive pin of the cyan laser chip 105, and the negative output terminal LD5- can be connected to the negative pin of the cyan laser chip 105. Figure 18 It is the structure of the sixth laser chip driving circuit 402F corresponding to the magenta laser chip 106. Figure 18 The positive output terminal LD6+ in it can be connected to the positive pin of the magenta laser chip 106, and the negative output terminal LD6- can be connected to the negative pin of the magenta laser chip 106. In some embodiments, the structures, connection relationships, and working principles of the above-mentioned fourth laser chip driving circuit 402D, fifth laser chip driving circuit 402E, and sixth laser chip driving circuit 402F are the same as those of the first laser chip driving circuit 402A, and will not be elaborated here.

[0107] In summary, in the laser projection device provided by some embodiments of the present disclosure, the display control circuit 401 can generate PWM signals corresponding to each color of laser chip, and can transmit the generated PWM signals to the laser chip driving circuits corresponding to the respective colors. The display control circuit 401 can also generate three enable signals, and can transmit the generated enable signals to the logic circuit 406. The logic circuit 406 can generate duty cycle signals corresponding to each color of laser chip, and can transmit the generated duty cycle signals to the laser chip driving circuits corresponding to the respective colors. The laser chip driving circuit corresponding to the respective colors can output a driving voltage according to the received PWM signals and enable signals, and load the driving voltage onto the pins of the laser chips corresponding to the respective colors, thereby driving each color of laser chip to emit light, thus realizing independent control of each color of laser chip. In addition, in the laser projection device provided by some embodiments of the present disclosure, the brightness of the light beams emitted by the five color laser chips can be adjusted according to the components of the five primary colors in each frame of image, which can avoid waste of light sources and reduce the power consumption of the device.

[0108] Still taking the light source 100 including laser chips of five primary colors, and the laser chips of five primary colors including a red laser chip 101, a green laser chip 102, a blue laser chip 103, a yellow laser chip 104, and a cyan laser chip 105 as an example for illustration.

[0109] In some embodiments of the present disclosure, in order to improve the response speed of the laser chip driving circuit and reduce signal and response delays, as Figure 19 shown, with Figure 14The corresponding circuit system 400 may also include: a digital-to-analog converter 403. The input end of the digital-to-analog converter 403 is connected to the display control circuit 401, and the output ends of the digital-to-analog converter 403 are respectively connected to the laser chip driving circuits 402A, 402B, 402C, 402D, and 402E. The digital-to-analog converter 403 is configured to receive the PWM signals generated by the display control circuit 401, convert each received PWM signal into a corresponding analog signal respectively, and transmit the corresponding analog signals to the laser chip driving circuits 402A, 402B, 402C, 402D, and 402E respectively.

[0110] Figure 20 A digital-to-analog converter is provided. As Figure 20 shown, the digital-to-analog converter 403 has at least five input pins (i.e., input ends), which are INA pin, INB pin, INC pin, IND pin, and INE pin respectively; the digital-to-analog converter 403 has at least five output pins (i.e., output ends), which are VOUTA pin, VOUTB pin, VOUTC pin, VOUTD pin, and VOUTE pin respectively.

[0111] The IND pin and the INE pin are also connected to the display control circuit 401, and are respectively configured to receive the yellow PWM signal Y_PWM and the cyan PWM signal C_PWM output by the display control circuit 401. The yellow PWM signal Y_PWM and the cyan PWM signal C_PWM are also both digital signals.

[0112] The VOUTD pin is connected to the laser chip driving circuit 402D, and is configured to output the analog signal Y1_PWM (i.e., the fourth analog PWM signal) converted from the yellow PWM signal Y_PWM (i.e., the fourth PWM signal) to the fourth laser chip driving circuit 402D. The VOUTE pin is connected to the laser chip driving circuit 402E, and is configured to output the analog signal C1_PWM (i.e., the fifth analog PWM signal) converted from the cyan PWM signal C_PWM (i.e., the fifth PWM signal) to the fifth laser chip driving circuit 402E.

[0113] In some embodiments, in order to reduce the power consumption of the laser projection device 10, as Figure 21 shown, the circuit system 400 may further include: selection circuits 404A, 402B, 404C, 404D, and 404E corresponding to the laser chips of five primary colors.

[0114] The two input terminals of the first selection circuit 404A are respectively connected to the output terminal of the digital-to-analog converter 403 and the output terminal of the logic circuit 406, and are configured to receive the analog signal R1_PWM output by the digital-to-analog converter 403 and the duty cycle signal R'_EN output by the logic circuit 406. The output terminal of the first selection circuit 404A is connected to the input terminal of the first laser chip driving circuit 402A, and is configured to transmit the received analog signal R1_PWM to the first laser chip driving circuit 402A when the received duty cycle signal R'_EN is at an effective potential, so that the first laser chip driving circuit 402A loads the driving voltage (or driving current) onto the pins of the red laser chip 101 according to the voltage of the received analog signal R2_PWM (the analog signal R2_PWM and the analog signal R1_PWM are the same signal, and they are only named differently), so that the red laser chip 101 emits a red light beam.

[0115] The two input terminals of the second selection circuit 404B are respectively connected to the output terminal of the digital-to-analog converter 403 and the output terminal of the logic circuit 406, and are configured to receive the analog signal G1_PWM output by the digital-to-analog converter 403 and the duty cycle signal G'_EN output by the logic circuit 406. The output terminal of the second selection circuit 404B is connected to the input terminal of the second laser chip driving circuit 402B, and is configured to transmit the received analog signal G1_PWM to the second laser chip driving circuit 402B when the received duty cycle signal G'_EN is at an effective potential, so that the second laser chip driving circuit 402B loads the driving voltage (or driving current) onto the pins of the green laser chip 102 according to the voltage of the received analog signal G2_PWM (the analog signal G2_PWM and the analog signal G1_PWM are the same signal, and they are only named differently), so that the green laser chip 102 emits a green light beam.

[0116] The two input terminals of the third selection circuit 404C are respectively connected to the output terminal of the digital-to-analog converter 403 and the output terminal of the logic circuit 406, and are configured to receive the analog signal B1_PWM output by the digital-to-analog converter 403 and the duty cycle signal B'_EN output by the logic circuit 406. The output terminal of the third selection circuit 404C is connected to the input terminal of the third laser chip driving circuit 402C, and is configured to transmit the received analog signal B1_PWM to the third laser chip driving circuit 402C when the received duty cycle signal B'_EN is at an effective potential, so that the third laser chip driving circuit 402C loads the driving voltage (or driving current) onto the pins of the blue laser chip 103 according to the voltage of the received analog signal B2_PWM (the analog signal B2_PWM and the analog signal B1_PWM are the same signal, and they are only named differently), so that the blue laser chip 103 emits a blue light beam.

[0117] The two input terminals of the fourth selection circuit 404D are respectively connected to the output terminal of the digital-to-analog converter 403 and the output terminal of the logic circuit 406, and are configured to receive the analog signal Y1_PWM output by the digital-to-analog converter 403 and the duty cycle signal Y'_EN output by the logic circuit 406. The output terminal of the fourth selection circuit 404D is connected to the input terminal of the fourth laser chip driving circuit 402D, and is configured to transmit the received analog signal Y1_PWM to the fourth laser chip driving circuit 402D when the received duty cycle signal Y'_EN is at an effective potential, so that the fourth laser chip driving circuit 402D loads the driving voltage (or driving current) onto the pins of the yellow laser chip 104 according to the voltage of the received analog signal Y2_PWM (the analog signal Y2_PWM and the analog signal Y1_PWM are the same signal, only with different names), so that the yellow laser chip 104 emits a blue light beam.

[0118] The two input terminals of the fifth selection circuit 404E are respectively connected to the output terminal of the digital-to-analog converter 403 and the output terminal of the logic circuit 406, and are configured to receive the analog signal C1_PWM output by the digital-to-analog converter 403 and the duty cycle signal C'_EN output by the logic circuit 406. The output terminal of the fifth selection circuit 404E is connected to the input terminal of the fifth laser chip driving circuit 402E, and is configured to transmit the received analog signal C1_PWM to the fifth laser chip driving circuit 402E when the received duty cycle signal C'_EN is at an effective potential, so that the fifth laser chip driving circuit 402E loads the driving voltage (or driving current) onto the pins of the cyan laser chip 105 according to the voltage of the received analog signal C2_PWM (the analog signal C2_PWM and the analog signal C1_PWM are the same signal, only with different names), so that the cyan laser chip 105 emits a blue light beam.

[0119] In addition, in the circuit system 400 shown above Figure 21 there may also be no digital-to-analog converter 403, that is, on the basis of Figure 21 selection circuits 404A, 404B, 404C, 404D, and 404E corresponding to the laser chip driving circuits 402A, 402B, 402C, 402D, and 402E are added respectively.

[0120] Taking the light source 100 as an example which includes a laser chip with five primary colors, and the laser chip with five primary colors includes a red laser chip 101, a green laser chip 102, a blue laser chip 103, a yellow laser chip 104, and a cyan laser chip 105. In some embodiments, at least one of the five PWM signals corresponding to the laser chip with five primary colors is not generated by the display control circuit 401, but by other components in the circuit system 400 except the display control circuit 401.

[0121] In some embodiments, such as Figure 22 and Figure 23 As shown, the circuit system 400 further includes a microcomputer unit (MCU) 407. The microcontroller 407 is connected to the system main board 500 and is configured to receive the projection image signal to be displayed transmitted by the system main board 500. The microcontroller 407 is also connected to the light source drive circuit 402 and is further configured to output a brightness adjustment signal to the light source drive circuit 402 based on the projection image to be displayed. The microcontroller 407 is also connected to the display control circuit 401 and is configured to notify the display control circuit 401 whether to output a brightness adjustment signal and which primary color laser chip the output brightness adjustment signal corresponds to based on the output brightness adjustment signal.

[0122] Exemplarily, the microcontroller 407 is electrically connected to at least one of the five laser chip drive circuits 402A, 402B, 402C, 402D, and 402E and is configured to generate at least one PWM signal corresponding to at least one primary color laser chip based on the five primary color components of the image to be displayed. The microcontroller 407 is connected to the display control circuit 401 and is configured to notify the display control circuit 401 to output PWM signals corresponding to the laser chips of the other primary colors except the at least one primary color based on the at least one PWM signal. At this time, the display control circuit 401 is configured to generate PWM signals corresponding to the laser chips of the other primary colors in the five primary colors based on the five primary color components of the image to be displayed, and generate three enable signals based on a preset ratio of the lighting duration of the laser chip with five primary colors in one driving cycle. That is, in the application example, the microcontroller 407 is used to output at least one primary color PWM brightness adjustment signal. At this time, the display control circuit 401 is used to output PWM brightness adjustment signals of other primary colors except the above at least one primary color.

[0123] For example, such as Figure 23As shown, the microcontroller 407 is electrically connected to all of the five laser chip driving circuits 402A, 402B, 402C, 402D, and 402E among the five laser chip driving circuits 402A, 402B, 402C, 402D, and 402E, and is configured to generate five PWM signals (i.e., R_PWM, G_PWM, B_PWM, Y_PWM, and C_PWM) corresponding to the laser chips of the five primary colors (i.e., the red laser chip 101, the green laser chip 102, the blue laser chip 103, the yellow laser chip 104, and the cyan laser chip 105) based on the five primary color components of the image to be displayed. The microcontroller 407 is connected to the display control circuit 401 and is configured to notify the display control circuit 401 not to output PWM signals based on the five PWM signals. At this time, the display control circuit 401 is only configured to generate three enable signals based on a preset ratio of the lighting duration of the laser chips of the five primary colors within one driving cycle.

[0124] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the claims. It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A laser projection device, include: A light source configured to provide an illumination beam; wherein the light source comprises N primary color laser chips, where N is an integer greater than 3; An optical machine configured to modulate the illumination light beam using an image signal to obtain a projection light beam; A lens configured to project the projection light beam into an image; and A circuit system is configured to control the light source to emit light beams of at least N colors; wherein, The circuit system comprises: The display control circuit is configured to generate N pulse width modulation (PWM) signals corresponding to the N primary color laser chips based on the N primary color components of the image to be displayed, and generate three enable signals based on a preset proportion of the lighting duration of the N primary color laser chips in one driving cycle; each PWM signal is configured to control the brightness of a light beam emitted by a laser chip of a corresponding color among the N primary color laser chips; each enable signal is configured to control the lighting duration of at least one color laser chip among the N primary color laser chips in one driving cycle; A light source driving circuit electrically connected to the N primary color laser chips; The light source driving circuit is electrically connected to the display control circuit and is configured to receive the N PWM signals and the three enable signals so as to drive the N primary color laser chips to emit light beams of at least N colors according to the N PWM signals when at least one of the three enable signals is at a valid potential.

2. The laser projection device according to claim 1, It is characterized in that The circuit system further comprises: a logic circuit electrically connected to the display control circuit and configured to generate N duty cycle signals based on the three enable signals, wherein the N duty cycle signals correspond to the laser chips of the N primary colors respectively; each duty cycle signal is configured to control the lighting duration of the laser chip of the corresponding color among the laser chips of the N primary colors within a driving cycle; The display control circuit comprises: N PWM output terminals are electrically connected to the light source driving circuit and are configured to transmit the N PWM signals to the light source driving circuit; and three enable output terminals, electrically connected to the logic circuit and configured to transmit the three enable signals to the logic circuit; The light source driving circuit is electrically connected to the display control circuit and is configured to receive the N PWM signals; the light source driving circuit is also electrically connected to the display control circuit through the logic circuit and is configured to receive the N duty cycle signals, so that when one of the N duty cycle signals is at a valid potential, the laser chips of the N primary colors are driven according to the N PWM signals to emit light beams of at least N colors.

3. The laser projection device according to claim 2, It is characterized in that in, In one driving cycle of the light source, a ratio between the durations of the effective potentials of the N duty cycle signals satisfies a preset ratio; A driving cycle of the light source includes a timing output stage; In the timing output stage, the N duty cycle signals are in effective potentials in sequence under the control of the logic circuit, and the time periods in which the N duty cycle signals are in effective potentials do not overlap with each other.

4. The laser projection device according to claim 3, It is characterized in that A driving cycle of the light source also includes a timing closing phase; In the timing closing phase, the N duty cycle signals are all at invalid potentials under the control of the logic circuit.

5. The laser projection device according to claim 2, It is characterized in that The logic circuit comprises: The N duty cycle output terminals are electrically connected to the light source driving circuit and are configured to transmit the N duty cycle signals to the light source driving circuit.

6. The laser projection device according to claim 1, It is characterized in that The circuit system architecture further includes: a logic circuit electrically connected to the display control circuit and configured to generate N duty cycle signals based on the three enable signals; A driving cycle of the light source also includes a timing closing phase; In the timing closing phase, the N duty cycle signals are all at invalid potentials under the control of the logic circuit.

7. The laser projection device according to claim 6, It is characterized in that The circuit system architecture satisfies one of the following: In the timing closing phase, the logic circuit is configured to generate a reset period signal based on the three enable signals being in an invalid potential; or The display control circuit is further configured to reserve the reset period signal when three enable signals are generated.

8. The laser projection device according to claim 7, It is characterized in that The reset period signal satisfies one of the following: The reset period signal is a universal enable signal in parallel with the N duty cycle signals; or, The reset period signal is an enable signal included in the valid period of one duty cycle signal among the N duty cycle signals.

9. A laser projection device, include: A light source configured to provide an illumination beam; wherein the light source comprises N primary color laser chips, where N is an integer greater than 3; An optical machine configured to modulate the illumination light beam using an image signal to obtain a projection light beam; A lens configured to project the projection light beam into an image; and A circuit system is configured to control the light source to emit light beams of at least N colors; wherein, The circuit system comprises: A microcontroller and a display control circuit configured to generate N pulse width modulation (PWM) signals corresponding to the laser chips of the N primary colors based on the N primary color components of the image to be displayed; The microcontroller is connected to the display control circuit and is configured to generate at least one PWM signal corresponding to at least one laser chip of the primary color among the N primary color laser chips; The display control circuit is configured to: output PWM signals corresponding to laser chips of other primary colors among the N primary colors except the at least one primary color, and generate three enable signals based on a preset proportion of the lighting duration of the laser chips of the N primary colors in one driving cycle; Each PWM signal is configured to control the brightness of a light beam emitted by a laser chip of a corresponding color among the N primary color laser chips; each enable signal is configured to control the lighting duration of a laser chip of at least one color among the N primary color laser chips within a driving cycle; A light source driving circuit electrically connected to the N primary color laser chips; The light source driving circuit is electrically connected to the microcontroller and the display control circuit, and is configured to receive the N PWM signals and the three enable signals, so as to drive the N primary color laser chips to emit the light beams of at least N colors according to the N PWM signals when at least one of the three enable signals is at a valid potential.

10. The laser projection device according to claim 9, It is characterized in that The circuit system further comprises: a logic circuit electrically connected to the display control circuit and configured to generate N duty cycle signals based on the three enable signals, wherein the N duty cycle signals correspond to the laser chips of the N primary colors respectively; each duty cycle signal is configured to control the lighting duration of the laser chip of the corresponding color among the laser chips of the N primary colors within a driving cycle; The light source driving circuit is electrically connected to the microcontroller and the display control circuit, and is configured to receive the N PWM signals; the light source driving circuit is also electrically connected to the display control circuit through the logic circuit, and is configured to receive the N duty cycle signals, so that when one of the N duty cycle signals is at a valid potential, the laser chips of the N primary colors are driven according to the N PWM signals to emit light beams of at least N colors.

11. The laser projection device according to claim 9, It is characterized in that The microcontroller is further configured to, based on the at least one PWM signal, notify the display control circuit to output PWM signals corresponding to laser chips of other primary colors among the N primary colors except the at least one primary color.

12. The laser projection device according to claim 9, It is characterized in that In one driving cycle of the light source, a ratio between the durations of the effective potentials of the N duty cycle signals satisfies a preset ratio; A driving cycle of the light source includes a timing output stage; in the timing output stage, the N duty cycle signals are in effective potentials in sequence under the control of the logic circuit, and the time periods in which the N duty cycle signals are in effective potentials do not overlap with each other.

13. The laser projection device according to claim 9, It is characterized in that The circuit system architecture satisfies one of the following: In the timing closing phase, the logic circuit is configured to generate a reset period signal based on the three enable signals being in an invalid potential; or The display control circuit is further configured to reserve the reset period signal when three enable signals are generated.

14. The laser projection device according to claim 13, It is characterized in that The reset period signal satisfies one of the following: The reset period signal is a universal enable signal in parallel with the N duty cycle signals; or, The reset period signal is an enable signal included in the valid period of one duty cycle signal among the N duty cycle signals.

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