Patting and anti-deadlock device and integrated system

Abstract

The invention discloses a beating and deadlock preventing device and an integrated system, and relates to the technical field of SOC systems.The beating and deadlock preventing device comprises a beating module, when a slave module immediately responds to an operation request of a bus matrix, the beating module delays for a preset duration and then outputs a bus release signal, and when the slave module cannot immediately respond to the operation request, the beating module deadlocks the bus release signal; and when the forced release control signal is received, a release bus signal is output after the preparation control signal is delayed for a preset time period, and meanwhile, when the forced release control signal is received, the release bus signal is output after the beating module is delayed for the preset time period. Therefore, the time sequence problem existing when the signal transmitted between the host and the slave cannot arrive in time is prevented, the release bus signal can be output after the preset time period of forcibly releasing the control signal when the control signal needs to be forcibly released, and the time sequence problem of forcibly releasing the control signal is also prevented.

Description

Technical Field

[0001] This application relates to the technical field of SOC systems, and particularly to a beat-taking and deadlock-preventing device and an integrated system. Background Art

[0002] In SOC design, a bus matrix connects each host module and slave module together to form a complete SOC system. The slave module is usually connected to the bus matrix, and the interface connecting the slave module and the bus matrix on the slave module is called a bus slave interface.

[0003] However, if the distance between the host and the slave is long, the signals sent between the host and the slave cannot reach as required, resulting in a timing problem between the host and the slave, and thus there is a metastability problem in the system. Summary of the Invention

[0004] This application provides a beat-taking and deadlock-preventing device and an integrated system to at least solve the timing problem between the host and the slave in the related art.

[0005] This application provides a beat-taking and deadlock-preventing device. The beat-taking and deadlock-preventing device is respectively connected to a bus matrix and a slave. The bus matrix includes: an access signal terminal, and the slave includes: a ready control terminal; The beat-taking and deadlock-preventing device includes: A beat-taking module, which is respectively connected to the ready control terminal, the access signal terminal, and the forced release control terminal, and is used for receiving an access signal and a ready control signal, and after beating the access signal and the ready control signal for a preset time period, controlling the output of an extension request and a bus release signal; The beat-taking module is further used for, when receiving a forced release control signal, delaying a preset time period to output a bus release signal whether or not an access signal and / or a ready control signal is received.

[0006] This application also provides an integrated system, including: a host, a bus matrix, a slave, and the above-mentioned beat-taking and deadlock-preventing device. With this application, when the slave module immediately responds to the operation request of the bus matrix, the release bus signal is output after a preset time delay through the pipelining module. And when the slave module cannot immediately respond to the operation request of the bus matrix, the preparation control signal is output in the slave module, and after the preparation control signal is no longer needed, the release bus signal is output after a preset time delay through the pipelining module. At the same time, when the forced release control signal is received, regardless of whether there is an access signal and / or a preparation control signal currently, the release bus signal is output after a preset time delay through the pipelining module. Thus, when the host outputs access information to the slave, the transmission time of the access information is reserved, and when the slave sends a preparation control signal to the host, the transmission time of the preparation control signal is also reserved. Therefore, the timing problem caused by the signal transmitted between the host and the slave not reaching in time is prevented. At the same time, when the forced release control signal is required, regardless of whether the access signal and / or the preparation control signal is received, the release bus signal can be timely output to the bus matrix, and the release bus signal is output again after the preset time period of the forced release control signal, which also prevents the timing problem of the forced release control signal. The present invention can realize the reserved pipelining time during the normal communication between the slave and the host through the pipelining module, can also release the bus matrix when forced release is needed, and can reserve the pipelining time for the forced release, thereby achieving the effect of integrating the pipelining function and the forced release function. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0008] Figure 1 A pipelining and deadlock prevention device provided by an embodiment of the present application; Figure 2 Another pipelining and deadlock prevention device provided by an embodiment of the present application; Figure 3 A detailed structure diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application; Figure 4 A timing diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application; Figure 5 Another timing diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application; Figure 6 Another timing diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application; Figure 7Another timing diagram of a beat - hitting and dead - lock - preventing device provided by an embodiment of this application. Detailed implementation manners

[0009] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of this application.

[0010] It should be noted that in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0011] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific implementation manners.

[0012] The slave interface needs to return correct response - type signals such as resp / err, rdata, ready, etc. to the bus matrix so that the bus matrix can obtain information about whether the current access is normal / abnormal, the return value, and whether the access is ended. The signal names returned for different buses are slightly different. The slave interface of the slave module may, due to certain defects, cause the slave to dead - lock and never return the information indicating the end of the bus to the bus matrix, resulting in the bus and the host being occupied all the time. At this time, it is necessary to end the dead - lock occupation of the bus according to the timeout signal returned by the bus matrix.

[0013] In common bus matrices such as the ahb bus and apb 3.0 bus of the AMBA bus, when the slave module cannot immediately respond to the operation request of the bus matrix, the ready - related preparation control signal (hready in the ahb protocol of the bus and pready in the apb3.0 protocol of the bus) can be pulled low to notify the bus matrix to extend the time for which the operation request is retained on the bus. When the response ends, the slave module can pull the ready - related preparation control signal high to notify the bus matrix to continue with the next operation request. During this process, if the accessed slave module has an exception and keeps ready low all the time, it will cause the bus matrix to dead - lock, and thus the SOC system to dead - lock.

[0014] Moreover, the long distance between the master and the slave results in the signal sent between the master and the slave not reaching as required, thus causing a timing problem between the master and the slave, and making the system have a metastability problem.

[0015] Embodiments of the present application provide a beating and deadlock prevention device. The beating and deadlock prevention device is respectively connected to a bus matrix and a slave, as Figure 1 shown. The bus matrix includes: an access signal terminal, and the slave includes: a ready control terminal; The beating and deadlock prevention device includes: A beating module 10, which is respectively connected to the ready control terminal, the access signal terminal, and the forced release control terminal, is configured to receive an access signal and a ready control signal, and after beating the access signal and the ready control signal for a preset time period, control the output of an extension request and a bus release signal; The beating module 10 is further configured to, when receiving a forced release control signal, whether receiving an access signal and / or a ready control signal, output a bus release signal after delaying for a preset time period.

[0016] Specifically, the bus matrix is, for example, the ahb bus and the apb 3.0 bus of the AMBA bus, and the ready control terminal is the ready terminal of the slave, which is hready in the bus ahb protocol and pready in the bus apb 3.0 protocol. The slave outputs a ready control signal through the ready control terminal. If the ready control signal is at a high level, it is used to notify the bus matrix to continue with the next operation request. If the ready control signal is at a low level, it is used to notify the bus matrix to extend the operation to request the time reserved on the bus. The access signal terminal is the terminal for the master to send an access signal to the slave based on the bus matrix, and the forced release control terminal is the deadlock prevention port output by the SOC system, which can specifically be a soft reset terminal for controlling the reset of the slave, or a timeout signal. The timeout signal is timeout, and both the slave reset and the timeout signal are used to output a bus release signal to the bus matrix.

[0017] Specifically, based on the beat module 10, the following three scenarios are implemented. First, when the host sends an access signal to the slave based on the bus matrix and the slave can process it in time (that is, when the ready control terminal of the slave does not output a ready signal), the beat module 10 outputs an extension request to the bus matrix and outputs a bus release signal to the bus matrix after beating for a preset time period. Second, when the host sends an access signal to the slave based on the bus matrix and the slave cannot process it in time, the slave outputs a ready control signal. At this time, the beat module 10 outputs an extension request to the bus matrix, and after the extension request ends (that is, when the ready control terminal of the slave outputs a ready completion signal), it beats for a preset time period and then outputs a bus release signal to the bus matrix. Third, even if the beat module 10 does not receive a ready completion signal but receives a forced release control signal, it beats for a preset time period starting from the forced release control signal and then outputs a bus release signal to the bus matrix.

[0018] In summary, the beat module 10 implements the following three functions. When the host sends an access signal to the slave based on the bus matrix, even if the slave does not need to output a ready control signal, it beats for a preset time period for the access signal and then outputs a bus release signal, thus realizing the beating of the reserved time period for the host to send an access signal to the slave. It also realizes that after the slave outputs a ready completion signal, it beats for a preset time period and then outputs a bus release signal, thus realizing the beating of the preset time period for the ready completion signal when the slave sends a ready completion signal to the bus matrix. It also realizes that when receiving a forced release signal, whether receiving an access signal and / or a ready control signal, it beats for a preset time period and then outputs a bus release signal. It should be noted that the priority of the forced release control signal is higher than that of the access signal and / or the ready control signal.

[0019] With this application, when the slave module immediately responds to the operation request of the bus matrix, after a delay of a preset duration through the beat module, a bus release signal is output. And when the slave module cannot immediately respond to the operation request of the bus matrix, a preparation control signal is output at the slave module, and after the preparation control signal is no longer needed, after a delay of a preset time period through the beat module, a bus release signal is output. At the same time, when a forced release control signal is received, regardless of whether there is an access signal and / or a preparation control signal currently, after a delay of a preset time period through the beat module, a bus release signal is output. Thus, when the host outputs access information to the slave, the transmission time of the access information is reserved, and when the slave sends a preparation control signal to the host, the transmission time of the preparation control signal is also reserved. Therefore, the timing problem that occurs when the signals transmitted between the host and the slave cannot reach in time is prevented. At the same time, when forced release is required, regardless of whether an access signal and / or a preparation control signal is received, a bus release signal can be timely output to the bus matrix, and after a preset time period of the forced release control signal, a bus release signal is output again, which also prevents the timing problem of the forced release control signal. The present invention can use the beat module to achieve the reserved beat time during the normal communication between the slave and the host, can release the bus matrix when forced release is needed, and can also reserve the beat time for forced release. Thus, the effect of integrating the beat function and the forced release function is achieved.

[0020] In an exemplary embodiment, as Figure 2 shown, the beat module 10 includes: A first extension unit 11, the first extension unit 11 is respectively connected to the preparation control terminal, the access signal terminal and the forced release control terminal, and is used for, when receiving an access signal, extending a preset time period for the access signal and then outputting a first bus release signal, and is used for, when receiving a forced release control signal, extending a preset time period for the forced release control signal and then outputting a first bus release signal; Specifically, the first extension unit 11 is used for, when not receiving a forced release control signal and as long as receiving an access signal, outputting an extension request starting from the access signal, and outputting a first bus release signal after a preset time period. The first extension unit 11 is further used for, when receiving a forced release control signal, outputting an extension request starting from the forced release control signal access signal and outputting a first bus release signal after a preset time period. Optionally, the first extension unit 11 outputs the first bus release signal in a reset manner.

[0021] The second extension unit 12, the second extension unit 12 is respectively connected to the preparation control terminal and the forced release control terminal, and is used for outputting a second release bus signal after extending a preset time period when the preparation is completed upon receiving a preparation control signal, and is used for outputting a second release bus signal after extending a preset time period for the forced release control signal upon receiving a forced release control signal; Specifically, the second extension unit 12 is used for outputting an extension request starting from the preparation control signal and outputting a second release bus signal after a preset time period when the forced release control signal is not received and as long as the preparation control signal is received. The second extension unit 12 is further used for outputting an extension request starting from the forced release control signal access signal and outputting a second release bus signal after a preset time period when the forced release control signal is received. Optionally, the second extension unit 12 outputs the second release bus signal in a delayed manner.

[0022] The first control unit 13, the first control unit 13 is respectively connected to the first extension unit 11 and the second extension unit 12, and is used for outputting a release bus signal when receiving the first release bus signal and the second release bus signal.

[0023] Specifically, the first control unit 13 outputs a release bus signal only when both the first release bus signal and the second release bus signal are received, and does not output a release bus signal when only the first release bus signal or the second release bus signal is received, or when neither the first release bus signal nor the second release bus signal is received.

[0024] In an exemplary embodiment, as Figure 3 shown, the first extension unit 11 includes: A reset control structure 11a, the reset control structure 11a is connected to the access signal terminal and is used for outputting a reset control signal when receiving an access signal; A reset extension structure 11b, the reset extension structure 11b is connected to the preparation control terminal, the forced release control terminal and the reset control structure, and is used for receiving the reset control signal and extending it for a preset time period.

[0025] Specifically, when the reset control structure 11a receives an access signal, it outputs a reset control signal, so that the reset extension structure 11b resets for a preset time period, thereby outputting a first release bus signal. It should be noted that the reset control signal of the first extension unit 11 extends the preset time period by a reset method, which is different from the reset of the slave device. Optionally, the reset control structure 11a can be a control chip for outputting a reset control signal.

[0026] In an exemplary embodiment, as Figure 3 shown, the beat and deadlock prevention device further includes: Synchronization signal module 20, the input end of the synchronization signal module 20 is connected to the forced release control end, and the output end of the synchronization signal module 20 is respectively connected to the first extension unit 11 and the second extension unit 12, and is used to output the forced release control signal after synchronization with the slave machine.

[0027] Specifically, the synchronization signal module 20 performs data synchronization at a preset level for the forced release control signal. The synchronization signal module 20 is sync_data, the forced release control signal is force_rsp, and the forced release control signal output after synchronization is force_rsp_sync. The synchronization signal module 20 also sends the synchronized forced release control signal to the slave machine to control the reset of the slave machine. Thus, the slave machine reset signal is synchronized with the slave machine, solving the timing problem of the slave machine during reset. The synchronization signal module 20 can perform 3-level synchronization or 2-level synchronization.

[0028] Reference Figure 5 , the synchronization signal module 20 performs 3-level synchronization, that is, extends the forced release control signal for 3 beats. It should be noted that due to the influence of crossing clock domains, the synchronized forced release control signal output by the synchronization signal module 20 may have a one-cycle offset.

[0029] It should be noted that traditional bus management relies on the slave machine to actively release resources, but the system may be completely paralyzed in the case of a deadlock. This design realizes the active intervention of the host through the forced release control signal, breaking the deadlock, which is an innovation in hardware-level fault tolerance. In addition, in some emergency situations, if it is necessary to give high-priority slaves emergency priority to occupy the bus, the currently occupied slave can be released through the forced release control mechanism. In addition, because of the asynchronous reset and reset sequence problems of the slave machine and the host machine, directly resetting the slave machine may transmit metastability to the host machine. The present invention performs synchronization when forcibly switching the bus to avoid metastability. At the same time, technically, there is no need for a complex state machine or an additional arbiter, and fast fault isolation can be achieved only through logic signals, reducing the system complexity and cost. And currently, timing adjustment mostly relies on fixed delay or global clock synchronization, which is difficult to cope with dynamic environments (such as temperature changes, signal attenuation). This design inserts a "beating" mechanism to dynamically compensate for timing deviations at the data link layer, improving communication reliability. Technically, it supports heterogeneous device hybrid networking, can flexibly adapt to different protocols (such as AHB / APB), and has strong scalability.

[0030] The present invention can also be applied to the following scenarios. First, it can achieve fault isolation and troubleshooting. In the case where a large number of low-power devices may be briefly offline due to network fluctuations or power supply problems, the dynamic bus release mechanism can quickly isolate the faulty node, or troubleshoot the faulty module by releasing the bus module by module. Second, it can achieve emergency bus release to ensure high-priority requirements. Key subsystems (such as radars and cameras) require high-priority bus access, and the communication delay must be extremely low. By forcibly releasing the bus, it is ensured that emergency instructions (such as brake signals) are transmitted preferentially. Third, it can achieve improved dynamic stability under environmental (temperature, voltage) deviations. Monitor the environmental conditions, adaptively adjust the number of beats, improve the stability of the system under environmental deviations, adaptively compensate for clock drift and increased delay caused by temperature and voltage changes, reduce the retransmission rate, and improve the system stability.

[0031] Exemplarily, the synchronization signal module 20 synchronizes the forced release control signal at 3 levels or 2 levels.

[0032] In an exemplary embodiment, as Figure 3 shown, the reset control structure 11a includes: A first inverter N1, the input end of the first inverter N1 is connected to the access signal terminal; A first register D1, the input end of the first register D1 is connected to the output end of the first inverter N1, and the output end of the first register D1 is used to output a reset control signal.

[0033] Optionally, the first register D1 is a MUX register.

[0034] Exemplarily, when the first inverter N1 receives the access signal as 1, it outputs 0 after passing through the first inverter N1, and the first register D1 outputs a reset control signal after receiving 0.

[0035] In an exemplary embodiment, as Figure 3 shown, the reset extension structure 11b includes: A second inverter N2, the input end of the second inverter N2 is connected to the forced release control terminal; A first selector M1, the first input end of the first selector M1 is connected to the output end of the second inverter N2, the second input end of the first selector M1 is connected to the preparation control terminal, and the selection end of the first selector M1 is connected to the synchronization signal module 20; X cascaded second registers D2, the input ends of the cascaded second registers D2 are connected to the output end of the first selector M1, the output ends of the cascaded second registers D2 are connected to the first control unit 13, and the reset ends of the second registers D2 are connected to the output end of the first register D1, where X ≥ 1.

[0036] Specifically, when sending an access signal through the access signal terminal without forced release, each second register D2 receives a reset control signal. At this time, the cascaded second registers D2 are reset simultaneously. After the first second register D2 is reset, it outputs 0. The second register D2 receives 0 and outputs 0. The cascaded second registers D2 sequentially absorb it as the first release bus and output it to the first control unit 13. In the case of forced release, the forced release control signal 0 is inverted to 1 by the second inverter N2 and sent to the first selector M1. The first selector M1 outputs 1, and after being delayed by a preset time period through the cascaded second registers D2 respectively, it is output as the first release bus. It should be noted that the number of X represents the number of beats of the preset time period of the access signal.

[0037] That is to say, when the application faces asynchronous forced change conditions such as asynchronous reset, it first synchronizes the asynchronous reset data and then participates in data selection as the selection terminal of the first selector M1. To avoid the slave module's interface changing immediately due to asynchronous reset before switching, it is required that the slave module uses the reset after data synchronization.

[0038] Optionally, the first selector M1 is a MUX (Multiplexer). The second register D2 is a MUX register.

[0039] In an exemplary embodiment, as Figure 3 shown, the second extension unit 12 is used to extend the preparation control signal for a preset time period and output the extended preparation control signal as the second release bus signal.

[0040] Specifically, the second extension unit 12 extends the signal output from the preparation control terminal, that is, extends the preparation control signal and also extends the signal without the preparation control signal. When the slave outputs the preparation control signal, it is 0, and when there is no need to output the preparation control signal, it is 1. When the second extension unit 12 receives the forced release control signal, it extends the forced release control signal for a preset time period and then outputs the second release bus signal.

[0041] In an exemplary embodiment, as Figure 3 shown, the second extension unit 12 includes: A third inverter N3, the input terminal of the third inverter N3 is connected to the forced release control terminal; A second selector M2, the first input terminal of the second selector M2 is connected to the output terminal of the third inverter N3, the second input terminal of the second selector M2 is connected to the preparation control terminal, and the selection terminal of the second selector M2 is connected to the synchronization signal module 20; X cascaded third registers D3, the input end of the cascaded third registers D3 is connected to the output end of the second selector M2, and the output end of the cascaded third registers D3 is connected to the first control unit 13, where X 1.

[0042] Specifically, in the case of no forced release, when a preparation control signal is sent through the preparation control terminal, the cascaded third registers D3 delay the preparation control signal in sequence and then output it as the second release bus. In the case of forced release, the forced release control signal 0 is inverted to 1 by the third inverter N3 and sent to the second selector M2. The second selector M2 outputs 1, and after being delayed by the cascaded third registers D3 for a preset time period respectively, it is output as the second release bus signal. The number of X represents the number of beats of the preset time period of the access signal.

[0043] It should be noted that the number of the cascaded third registers D3 is equal to the number of the cascaded second registers D2.

[0044] In addition, the beating and deadlock prevention device may further include a beating duration control module. The beating duration control module is respectively connected to the input and output paths of each second register D2 and each third register D3, that is, the beating duration control module selects a preset number Y of second registers D2 and a preset number Y of cascaded third registers D3 from the X cascaded second registers D2 and the X cascaded third registers D3. That is, the output end of the Y-th second register D2 is directly connected to the first control unit 13, and the output end of the Y-th third register D3 is directly connected to the first control unit 13. Thus, the preset beating time is controlled. Furthermore, flexible control of the beating duration is achieved.

[0045] Optionally, the second selector M2 is a MUX (Multiplexer, multiplexer). The third register D3 is a MUX register.

[0046] In an exemplary embodiment, as Figure 3 、 Figure 4 and Figure 5 shown, the first control unit 13 includes: A first AND gate AND1, the first input end of the first AND gate AND1 is connected to the output end of the cascaded second register D2, the second input end of the first AND gate is connected to the output end of the cascaded third register D3, and the output end of the first AND gate AND1 is used to output a release bus signal.

[0047] Specifically, when the first AND gate AND1 receives the first release bus signal and the second release bus signal, it outputs the release bus signal. The first AND gate AND1 outputs the no-release bus signal only when the first release bus signal or the second release bus signal is present. When the first AND gate AND1 does not receive the first release bus signal and the second release bus signal, it outputs the no-release bus signal.

[0048] Exemplarily, referring to Figure 4 , the forced release control signal is 0, and the no-forced release control signal is 1. The ready control signal is 0, and the no-ready control signal is 1. The release bus signal is 1, and the no-release bus signal is 0. The access signal is 1, and the no-access signal is 0.

[0049] Referring to Figure 3 and Figure 4 in a, if 3 second registers D2 are cascaded and 3 third registers D3 are cascaded. When there is no need for forced release, the selection signal received by the first selector M1 is 1, that is, the signal at the second input terminal is output by the first selector M1. At this time, if there is no need for preparation, the first selector M1 outputs 0 to the first second register D2. After 0 passes through three second registers D2, 0s for 3 beats are output to the first control unit 13. The selection signal received by the second selector M2 is 1, that is, the signal at the second input terminal is output by the second selector M2. At this time, if there is no need for preparation, the second selector M2 outputs 1 to the first third register D3. After 1 passes through three second registers D2, it is transmitted to the first control unit 13. The first control unit 13 outputs 0s for three beats, that is, the no-release bus signal, and then outputs 1, that is, the release bus signal.

[0050] Referring to Figure 3 and Figure 4 in b, when there is no need for forced release, if preparation is required, that is, the ready control signal is 0, and the first selector M1 outputs 1 to the first second register D2. However, since each second register D2 receives the reset signal at this time, the first second register D2 outputs 0, and the cascaded second registers D2 sequentially output 0s to the first control unit 13. The second selector M2 outputs 0 to the first third register D3. After a delay of three third registers D3, 0s for 4 beats are output to the first control unit 13 in total, that is, the no-release bus signal, and then 1 is output, that is, the release bus signal.

[0051] Referring to Figure 3 and Figure 5, when forced release is required, that is, the forced release control signal is 0, after three - stage synchronization by the synchronization signal module 20, 0 is output. At this time, due to the cross - clock - domain effect, there is a delay of 4 beats. The selection signal received by the first selector M1 is 0, that is, the signal output by the first selector M1 is the signal of the first input terminal. The forced release control signal 0 outputs 1 after passing through the second inverter N2. The first selector M1 outputs 1 to the first second register D2. At this time, the cascaded second register D2 outputs 1 to the first control unit 13. The selection signal received by the second selector M2 is 0, that is, the signal output by the second selector M2 is the signal of the first input terminal. The forced release control signal 0 outputs 1 after passing through the third inverter N3. The second selector M2 outputs 1 to the first third register D3. At this time, the cascaded third register D3 outputs 1 to the first control unit 13. That is to say, the first control unit 13 outputs 1 after a delay of 3 more beats, that is, the release bus signal.

[0052] In an exemplary embodiment, as Figure 3 shown, the clock - beating and dead - lock - prevention device includes: A control module 30, which is respectively connected to the clock - beating control terminal, the clock - beating module 10 and the preparation control terminal, is used to receive the clock - beating control signal, and control whether the clock - beating module 10 delays the access signal and the preparation control signal, and is also used to output a release bus signal that delays the forced release control signal by a preset time period when receiving the forced release control signal.

[0053] Specifically, the control module 30 is used to control whether the function of the clock - beating module 10 is turned on. It should be noted that when the function of the clock - beating module 10 is not turned on, if the forced release control signal is received, the clock - beating is still extended for a preset time period. Thus, the timing problem during reset is ensured, and the situation where the system is in a metastable state is prevented.

[0054] In an exemplary embodiment, as Figure 3 shown, the control module 30 includes: A second control unit 31, the first input terminal of the second control unit 31 is connected to the clock - beating control terminal, and the second input terminal of the second control unit 31 is connected to the output terminal of the synchronization signal module 20, and is used to output a clock - beating signal when receiving the clock - beating control signal and / or the forced release signal; A routing control unit 32, the first input terminal of the routing control unit 32 is connected to the output terminal of the clock - beating module 10, the second input terminal of the routing control unit 32 is connected to the preparation control terminal, the output terminal of the selection terminal of the routing control unit is connected to the bus matrix, and the selection terminal of the routing control unit 32 is connected to the output terminal of the second control unit 31, and is used to output the release bus signal transmitted by the clock - beating module 10 to the bus matrix when receiving the clock - beating signal.

[0055] Specifically, when the second control unit 31 receives a no-beat control signal and a no-forced release signal, it controls the routing control unit 32 to output the ready control signal as a release bus signal to the bus matrix. When the second control unit 31 receives a beat signal and a no-forced release signal, it controls the routing control unit 32 to output the release bus signal sent by the beat module 10 to the bus matrix. When the second control unit 31 receives a no-beat control signal and a forced release control signal, it controls the routing control unit 32 to output the release bus signal sent by the beat module 10 to the bus matrix.

[0056] In an exemplary embodiment, as Figure 3 shown, the second control unit 31 includes: A second AND gate AND2, where the first input terminal of the second AND gate AND2 is connected to the beat control terminal, the second input terminal of the second AND gate AND2 is connected to the output terminal of the synchronization signal module 20, and the output terminal of the second AND gate AND2 is connected to the routing control unit 32.

[0057] Specifically, the no-beat control signal is 1, and the beat control signal is 0. The no-forced release signal is 1, and the forced release signal is 0. When the second AND gate AND2 receives a no-beat control signal and a no-forced release signal, that is, when it receives 1 and 1, it outputs 1. When the second AND gate AND2 receives a beat control signal and a no-forced release signal, that is, when it receives 0 and 1, it outputs 0. When the second AND gate AND2 receives a no-beat control signal and a forced release signal, that is, when it receives 1 and 0, it outputs 0. When the second AND gate AND2 receives a beat control signal and a forced release signal, that is, when it receives 0 and 0, it outputs 0.

[0058] In an exemplary embodiment, as Figure 3 and Figure 5 shown, the routing control unit 32 includes: A third selector M3, where the first input terminal of the third selector M3 is connected to the output terminal of the beat module 10, the second input terminal of the third selector M3 is connected to the ready control terminal, the output terminal of the third selector M3 is connected to the bus matrix, and the selection terminal of the third selector M3 is connected to the output terminal of the second control unit 31.

[0059] Specifically, when the third selector M3 receives a selection terminal of 0, it outputs the signal output by the beat module 10 to the bus matrix. When the third selector M3 receives a selection terminal of 1, it outputs the ready control signal to the bus matrix.

[0060] Exemplarily, referring to Figure 5, when the beat control signal is not required to be 1 and the slave device deadlocks and never releases the bus, the bus is forcibly released through the forced release control signal 0. That is, when the forced release control signal is 0, the synchronization signal outputs 0 after 3 delays. The synchronized signal has a one-cycle offset due to the cross-clock domain effect, and then after 3 beat times of the beat module 10, the bus release signal is output. Because the synchronized signal has a one-cycle offset due to the cross-clock domain effect, the bus release signal also has a one-cycle offset.

[0061] In one exemplary embodiment, as Figure 3 , Figure 6 and Figure 7 shown, the beat and deadlock prevention device includes: An access identification module 40, which is respectively connected to the bus matrix and the access signal terminal, and is used to receive the access signal and output the access signal when the access signal is detected to be valid.

[0062] Specifically, the access identification module 40 detects the validity of the access signal and only outputs it as the access signal when it is detected to be valid. Thus, the validity of the transmitted access signal is improved.

[0063] Refer to Figure 6 , in the AHB protocol, the address / control command channel is AHB A / C CH, and the control signals it contains are such as hsel, htrans, etc. The ready control signal is hreadyin. That is, when the address / control instruction is 1 and the control signal is 1, it is judged as a valid access signal active_s.

[0064] Refer to Figure 7 , under the APB3.0 protocol, the address / control command channel is psel, and the control signals it contains are such as penable, etc. The valid access signal is active_s. That is, when the address / control instruction is 1 and the control signal is 0, it is detected as a valid access signal. The ready control signal is pready.

[0065] Embodiments of the present application further provide an integrated system, which includes a host, a bus matrix, a slave, and a beating and deadlock prevention device. Thus, when the host outputs access information to the slave, the transmission time of the access information is reserved, and when the slave sends a preparation control signal to the host, the transmission time of the preparation control signal is also reserved. Therefore, the timing problem caused by the signal transmitted between the host and the slave not reaching in time is prevented. At the same time, when it is necessary to forcibly release the control signal, regardless of whether the access signal and / or the preparation control signal is received, a bus release signal can be output to the bus matrix in time, and the bus release signal is output again after a preset time period for forcibly releasing the control signal, which also prevents the timing problem of forcibly releasing the control signal. The present invention can achieve the reserved beating time during the normal communication between the slave and the host through the beating module, can release the bus matrix when forced release is required, and can also reserve the beating time for forced release. Thus, the effect of integrating the beating function and the forced release function is achieved.

[0066] The above has introduced in detail a beating and deadlock prevention device and an integrated system provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A beating and anti-deadlocking device, characterized in that: The beat and anti-deadlock device is connected to the bus matrix and the slave respectively, the bus matrix includes: an access signal terminal, and the slave includes: a ready control terminal; The beating and anti-deadlocking device comprises: A beat module, the beat module is connected to the preparation control end, the access signal end, and the forced release control end respectively, and is used to receive the access signal and the preparation control signal, and after beating the access signal and the preparation control signal for a preset time period, control the output of the extension request and the release bus signal; The beat module is also used to output a release bus signal after a preset time period when receiving a forced release control signal.

2. The beating and anti-deadlocking device according to claim 1, characterized in that: The beat module comprises: a first extension unit, the first extension unit being connected to the preparation control end, the access signal end and the forced release control end respectively, and being used for outputting a first release bus signal after extending a preset time period for the access signal upon receiving the access signal, and being used for outputting a first release bus signal after extending a preset time period for the forced release control signal upon receiving the forced release control signal; a second extension unit, the second extension unit being connected to the preparation control end and the forced release control end respectively, and being used for outputting a second release bus signal after extending the preset time period after the preparation is completed upon receiving the preparation control signal, and being used for outputting a second release bus signal after extending the preset time period for the forced release control signal upon receiving the forced release control signal; The first control unit is connected to the first extension unit and the second extension unit respectively, and is used to output a release bus signal when receiving the first release bus signal and the second release bus signal.

3. The beating and anti-deadlocking device according to claim 2, characterized in that: The first extension unit comprises: A reset control structure, the reset control structure being connected to the access signal terminal and configured to output a reset control signal upon receiving an access signal; A reset extension structure, the reset extension structure is connected to the preparation control end, the forced release control end and the reset control structure, and is used to receive a reset control signal and extend a preset time period.

4. The beating and anti-deadlocking device according to claim 3, characterized in that: The beating and anti-deadlocking device also includes: A synchronization signal module, wherein the input end of the synchronization signal module is connected to the forced release control end, and the output end of the synchronization signal module is respectively connected to the first extension unit and the second extension unit, and is used to synchronize the forced release control signal with the slave and then output it.

5. The beating and anti-deadlocking device according to claim 4, characterized in that: The reset control structure comprises: A first inverter, wherein an input terminal of the first inverter is connected to the access signal terminal; A first register, wherein an input end of the first register is connected to an output end of the first inverter, and an output end of the first register is used to output a reset control signal.

6. The beating and anti-deadlocking device according to claim 5, characterized in that: The resetting extension structure comprises: A second inverter, wherein an input terminal of the second inverter is connected to a forced release control terminal; A first selector, wherein a first input terminal of the first selector is connected to the output terminal of the second inverter, a second input terminal of the first selector is connected to the preparation control terminal, and a selection terminal of the first selector is connected to the synchronization signal module; X cascaded second registers, the input end of the cascaded second registers is connected to the output end of the first selector, the output end of the cascaded second registers is connected to the first control unit, and the reset end of each second register is connected to the output end of the first register, wherein X 1.

7. The beating and anti-deadlocking device according to claim 4, characterized in that: The second extension unit is used to extend the prepared control signal by a preset time period, and output the extended prepared control signal as the second release bus signal.

8. The beating and anti-deadlocking device according to claim 7, characterized in that: The second extension unit comprises: A third inverter, wherein an input terminal of the third inverter is connected to the forced release control terminal; A second selector, wherein a first input terminal of the second selector is connected to the output terminal of the third inverter, a second input terminal of the second selector is connected to the preparation control terminal, and a selection terminal of the second selector is connected to the synchronization signal module; X cascaded third registers, the input end of the cascaded third registers is connected to the output end of the second selector, and the output end of the cascaded third registers is connected to the first control unit, wherein X 1.

9. The beating and anti-deadlocking device according to claim 2, characterized in that: The first control unit comprises: A first AND gate, wherein a first input end of the first AND gate is connected to an output end of a second cascaded register, a second input end of the first AND gate is connected to an output end of a third cascaded register, and an output end of the first AND gate is used to output a release bus signal.

10. The beating and anti-deadlocking device according to claim 1, characterized in that: The beating and anti-deadlocking device comprises: A control module, wherein the control module is respectively connected to the beat control end, the beat module and the preparation control end, and is used to receive a beat control signal, and control whether the beat module delays the access signal and the preparation control signal, and is also used to output a release bus signal that delays the forced release control signal for a preset time period when a forced release control signal is received.

11. The beating and anti-deadlocking device according to claim 10, characterized in that: The control module comprises: A second control unit, wherein a first input end of the second control unit is connected to the beat control end, and a second input end of the second control unit is connected to the output end of the synchronization signal module, and is used for outputting a beat signal when receiving a beat control signal and / or a forced release control signal; A routing control unit, wherein a first input terminal of the routing control unit is connected to an output terminal of the beat module, a second input terminal of the routing control unit is connected to the preparation control terminal, an output terminal of a selection terminal of the routing control unit is connected to a bus matrix, and a selection terminal of the routing control unit is connected to an output terminal of the second control unit, for outputting a release bus signal transmitted by the beat module to the bus matrix upon receiving a beat signal.

12. The beating and anti-deadlocking device according to claim 11, characterized in that: The second control unit comprises: A second AND gate, wherein the first input end of the second AND gate is connected to the beat control end, the second input end of the second AND gate is connected to the output end of the synchronization signal module, and the output end of the second AND gate is connected to the routing control unit.

13. The beating and anti-deadlocking device according to claim 12, characterized in that: The routing control unit comprises: A third selector, wherein the first input end of the third selector is connected to the output end of the beat module, the second input end of the third selector is connected to the preparation control end, the output end of the third selector is connected to the bus matrix, and the selection end of the third selector is connected to the output end of the second control unit.

14. The beating and anti-deadlocking device according to claim 1, characterized in that: The beating and anti-deadlocking device comprises: The access identification module is connected to the bus matrix and the access signal terminal respectively, and is used to receive the access signal and output when detecting that the access signal is valid.

15. An integrated system, characterized in that: The integrated system comprises a host, a bus matrix, a slave and a beat and anti-deadlock device as claimed in any one of claims 1 to 14.

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