Fault injection method and device, equipment and storage medium

Abstract

The invention discloses a fault injection method and device, equipment and a storage medium, and relates to the field of data processing, and the method comprises the steps: carrying out the iterative graph processing based on a graph processing program of a graph calculation task, and determining a task processing result; determining a target iteration round to be subjected to fault injection from the iteration rounds through the task processing result and a predetermined fault elastic exploration result, and analyzing an active vertex set corresponding to the target iteration round to determine a target vertex to be subjected to fault injection based on an obtained set analysis result; performing fault injection result marking on a corresponding bit in a dynamic instruction corresponding to the graph processing program based on the fault elastic exploration result to obtain a marked program; and performing simulation injection of the hardware fault by utilizing the target iteration round, the target vertex and the marked program, and performing injection result statistics by adopting each preset granularity to obtain a fault injection result. The fault injection frequency can be reduced, and the efficiency of a fault-tolerant strategy for subsequent guidance graph processing is improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and particularly to a fault injection method, device, equipment and storage medium. Background Art

[0002] In order to improve the processing efficiency of graph computing tasks, acceleration is usually carried out on general-purpose graphics processors and customized domain-specific hardware. As the integration degree of these platforms gradually increases and the circuit has developed to the nanometer level, in such a case, the probability of hardware faults caused by factors such as is rising. Common fault resolution measures are instruction re-execution, hardware double backup, etc. However, undifferentiated redundant backup will cause relatively large energy consumption and time overhead.

[0003] Currently, in order to analyze the parts that need to be protected in a graph processing system under the influence of hardware faults, traditional solutions usually rely on random fault injection into the program fault space, which often requires a large number of injection times. However, since the program fault space is often very large and the data scale of graph processing is increasing day by day, a large number of fault injections will consume unacceptable time and energy consumption overhead. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a fault injection method, device, equipment and storage medium, which can reduce the number of fault injections under the conditions of ensuring effectiveness and reliability, thereby reducing energy consumption and time overhead, and further improving the efficiency of the subsequent fault tolerance strategy guiding graph processing. The specific solutions are as follows:

[0005] In the first aspect, the present application provides a fault injection method, including:

[0006] Performing iterative graph processing based on a graph processing program corresponding to a graph computing task to determine and record corresponding task processing results;

[0007] Determining a target iteration round for fault injection from each iteration round through the task processing results and a pre-determined fault resilience exploration result, and analyzing an active vertex set corresponding to the target iteration round to determine a target vertex for fault injection based on the obtained set analysis result;

[0008] Marking the corresponding bit positions in the dynamic instructions corresponding to the graph processing program based on the fault resilience exploration result to obtain a marked program;

[0009] Performing simulated injection of hardware faults using the target iteration round, the target vertex and the marked program, and respectively performing injection result statistics at each preset granularity to obtain corresponding fault injection results.

[0010] Optionally, performing iterative graph processing based on the graph processing program corresponding to the graph computing task to determine and record the corresponding task processing results, including:

[0011] By executing the graph processing program corresponding to the graph computing task, to complete the corresponding iterative graph processing operation, and record the corresponding program output information, the dynamic instructions and register information corresponding to the graph processing program, and the set of active vertices for each iteration round.

[0012] Optionally, determining the target iteration round for fault injection from each iteration round based on the task processing results and the pre-determined fault resilience exploration results, including:

[0013] Analyzing the coincidence degree of the active vertices in each iteration round based on the task processing results and the pre-determined fault resilience exploration results to obtain the corresponding iteration round analysis results;

[0014] Determining multiple iteration groups based on the iteration round analysis results, and screening out the target iteration round for fault injection from each of the iteration groups.

[0015] Optionally, analyzing the set of active vertices corresponding to the target iteration round to determine the target vertex for fault injection based on the obtained set analysis results, including:

[0016] Performing neighbor set similarity analysis between the vertices in each set of active vertices corresponding to the target iteration round based on the task processing results and the fault resilience exploration results to obtain the corresponding first set analysis result;

[0017] Using the first set analysis result to screen out the target vertex for fault injection from each of the sets of active vertices.

[0018] Optionally, analyzing the set of active vertices corresponding to the target iteration round to determine the target vertex for fault injection based on the obtained set analysis results, including:

[0019] Calculating the clustering coefficient between the vertices in each set of active vertices corresponding to the target iteration round based on the task processing results and the fault resilience exploration results to obtain the corresponding second set analysis result;

[0020] Using the second set analysis result to screen out the target vertex for fault injection from each of the sets of active vertices.

[0021] Optionally, marking the corresponding bit positions in the dynamic instructions corresponding to the graph processing program with fault injection results based on the fault resilience exploration results, including:

[0022] Divide the dynamic instructions corresponding to the graph processing program based on the instruction type to obtain the corresponding instruction division result;

[0023] Based on the fault resilience exploration result, trigger the corresponding first fault injection result marking operation and second fault injection result marking operation on the corresponding bit positions in the numerical calculation instructions and address calculation instructions in the instruction division result respectively, to obtain the marked program.

[0024] Optionally, the method of simulating and injecting hardware faults by using the target iteration round, the target vertex, and the marked program, and respectively performing injection result statistics for each preset granularity includes:

[0025] After simulating and injecting hardware faults into the marked program, for any preset granularity, by monitoring the program output, and using the task processing result and the preset fault injection result type to perform injection result analysis and statistics on the marked area and the fault injection area in the marked program respectively, to obtain the fault injection result corresponding to the current preset granularity.

[0026] In a second aspect, the present application provides a fault injection device, including:

[0027] A program execution module, configured to perform iterative graph processing based on a graph processing program corresponding to a graph calculation task, to determine and record the corresponding task processing result;

[0028] An injection exploration module, configured to determine a target iteration round to be fault-injected from each iteration round through the task processing result and a pre-determined fault resilience exploration result, and analyze the active vertex set corresponding to the target iteration round, to determine a target vertex to be fault-injected based on the obtained set analysis result;

[0029] An instruction marking module, configured to perform fault injection result marking on the corresponding bit positions in the dynamic instructions corresponding to the graph processing program based on the fault resilience exploration result, to obtain the marked program;

[0030] A fault injection module, configured to use the target iteration round, the target vertex, and the marked program to perform simulation injection of hardware faults, and respectively perform injection result statistics for each preset granularity, to obtain the corresponding fault injection result.

[0031] In a third aspect, the present application provides an electronic device, including:

[0032] A memory, configured to store a computer program;

[0033] A processor, configured to execute the computer program to implement the steps of the foregoing fault injection method.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the foregoing fault injection method.

[0035] It can be seen that in the present application, iterative graph processing is performed based on a graph processing program corresponding to a graph computing task to determine and record corresponding task processing results; a target iteration round for fault injection is determined from each iteration round through the task processing results and pre-determined fault resilience exploration results, and the active vertex set corresponding to the target iteration round is analyzed to determine a target vertex for fault injection based on the obtained set analysis result; corresponding bits in the dynamic instructions corresponding to the graph processing program are marked with fault injection results based on the fault resilience exploration results to obtain a marked program; the target iteration round, the target vertex, and the marked program are used to simulate and inject hardware faults, and the injection results are statistically analyzed at each preset granularity to obtain corresponding fault injection results. That is to say, the present application first obtains task processing results corresponding to a graph computing task, then determines a target iteration round and a target vertex for fault injection by using the task processing results and pre-determined fault resilience exploration results, marks the corresponding bits in the graph processing program with fault injection results, then performs fault injection based on the marked program, the target iteration round, and the target vertex, and statistically analyzes the injection results at different preset granularities to determine the fault injection results. In this way, under the conditions of ensuring effectiveness and reliability, the number of fault injections can be reduced, thereby reducing energy consumption and time overhead, and further improving the efficiency of the subsequent fault tolerance strategy for guiding graph processing. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0037] Figure 1 It is a flowchart of a fault injection method provided by the present application;

[0038] Figure 2 It is a schematic diagram for exploring the fault resilience law from the iterative perspective provided by the present application;

[0039] Figure 3 It is a schematic diagram for exploring the fault resilience law from the graph topology perspective provided by the present application;

[0040] Figure 4Schematic diagram of fault injection results for different bit positions of an address calculation instruction provided by this application;

[0041] Figure 5 Schematic diagram of fault injection results for different bit positions of a numerical calculation instruction provided by this application;

[0042] Figure 6 Schematic diagram of the structure of a fault injection device provided by this application;

[0043] Figure 7 Structural diagram of an electronic device provided by this application. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0045] To analyze the parts that need to be protected in the graph processing system under the influence of hardware faults, traditional solutions usually rely on random fault injection into the program fault space, which often requires a large number of injection times. However, since the program fault space is often extremely large and the data scale of graph processing is increasing day by day, a large number of fault injections will consume unacceptable time and energy consumption overheads. For this reason, this application provides a fault injection scheme that can reduce the number of fault injections under the conditions of ensuring effectiveness and reliability, thereby reducing energy consumption and time overheads, and further improving the efficiency of the subsequent fault tolerance strategy for guiding graph processing.

[0046] See Figure 1 As shown, an embodiment of the present invention discloses a fault injection method, including:

[0047] Step S11: Perform iterative graph processing based on a graph processing program corresponding to a graph calculation task to determine and record the corresponding task processing results.

[0048] In this embodiment, first, the program is executed and analyzed, that is, the graph processing program corresponding to the graph calculation task is executed to complete the corresponding iterative graph processing operation, and record the corresponding program output information (as a standard for comparing the correctness of the fault injection results later), the dynamic instruction and register information corresponding to the graph processing program, and the active vertex set of each iterative round.

[0049] Step S12: Determine the target iteration round for fault injection from each iteration round based on the task processing result and the pre-determined fault resilience exploration result, and analyze the set of active vertices corresponding to the target iteration round to determine the target vertex for fault injection based on the obtained set analysis result.

[0050] It should be understood that in this embodiment, the fault resilience law is explored through some experiments. Starting from the execution mode of graph processing (i.e., the iterative perspective) and the graph topology perspective respectively, the fault resilience characteristics are gradually identified, so that only representative fault points can be selected for fault injection, or the performance of some fault points under hardware faults can be predicted in advance, thereby reducing the number of fault injection times.

[0051] Regarding the exploration of the fault resilience law from the iterative perspective, combined with Figure 2 As shown, it is found that: during the iterative process of graph processing, the set of active vertices in different iteration rounds is constantly changing. Through experiments, it is found that the iterations with highly overlapping active vertex sets have similar performances under faults. It can be found that the number of active vertices in the 9th to 19th iterations is basically the same (after inspection, their active vertex sets are also very similar), and their SC and BC probabilities (the red broken line and the green broken line in Figure 2 respectively) also show similarity. That is, through exploration, it is known that for the iteration set with highly overlapping active vertex sets, only one iteration round needs to be selected for representative fault injection to represent the fault resilience of this iteration set.

[0052] Regarding the exploration of the fault resilience law from the graph topology perspective, it is found that: in the graph topology (that is, the input of graph processing), (1) if the neighbor sets of different vertices are similar, then the distribution of the wrong program output results caused by faults occurring on these vertices is also similar; (2) if different vertices are highly clustered, that is, the edges between vertices are very dense, then the distribution of the wrong program output results caused by faults occurring on these vertices is also similar. This is because the execution modes and error propagation modes of the vertices that meet these conditions are very similar. Specifically, please refer to Figure 3 As shown, Figure 3 shows the performance of the vertex sets with similar neighbors and high clustering (each black box) under faults. It can be seen that the error distributions of the vertices within each box are similar. That is, through exploration, it is known that by identifying the vertex sets with high neighbor similarity and high clustering degree, representative vertices can be selected for fault injection in each set.

[0053] In addition, regarding the predictability of the fault results during the execution process, it is found that: specifically for the instructions in the program execution, they can generally be divided into numerical calculation instructions and address calculation instructions. Figure 4It is a display of the fault injection results for different bit positions of the address calculation instruction. The Detected errors in the program are basically caused by errors in the address calculation instruction. An error in the high bits (bits 28 to 63) of the address calculation instruction may cause the program to access an address beyond the allocated address, and an error in the low two bits of the address calculation may cause the program to access an illegal address. Both of these situations will cause the program to crash. Moreover, for numerical calculation instructions, the binary data storage in the computer is similar to the decimal system, and the data in the high bits often has a greater weight. In numerical calculation instructions, if a fault occurs in the low bits, it means that the initial deviation caused by the fault is relatively low and it is difficult to have a serious impact on the final result of the program, just like Figure 5 the bits 0 to 16 in

[0054] According to the above findings, the corresponding fault resilience exploration results can be determined and applied to guide fault injection. In this way, pruning of the fault space can be carried out from the iteration rounds to the vertices to the instruction bit positions. The pruned space is greatly reduced compared to the original fault space, so the efficiency of fault injection can be improved. Specifically, first, based on the task processing results and the pre-determined fault resilience exploration results, analyze the coincidence degree of active vertices in each iteration round to obtain the corresponding iteration round analysis results; determine multiple iteration groups based on the iteration round analysis results, and screen out the target iteration rounds to be fault-injected from each of the iteration groups. Then, based on the task processing results and the fault resilience exploration results, conduct neighbor set similarity analysis among the vertices in each active vertex set corresponding to the target iteration round to obtain the corresponding first set analysis results; use the first set analysis results to screen out the target vertices to be fault-injected from each of the active vertex sets. Then, based on the task processing results and the fault resilience exploration results, calculate the clustering coefficient among the vertices in each active vertex set corresponding to the target iteration round to obtain the corresponding second set analysis results; use the second set analysis results to screen out the target vertices to be fault-injected from each of the active vertex sets. That is, in this embodiment, by calculating the coincidence degree of active vertices in different iterations and selecting the iterations with similar active vertices as an elastic similarity iteration group. Select one iteration from each iteration group for representative fault injection. By calculating the neighbor similarity of different vertices and identifying the neighbor similar vertex sets, in each vertex set, there are similar neighbors between every two vertices, and select one vertex from each vertex set for representative fault injection; by calculating the clustering coefficient of different vertices and identifying the highly clustered vertex sets, each vertex set represents a subgraph with a highly connected relationship, and select one vertex from each vertex set for representative fault injection.

[0055] Step S13: Based on the fault resilience exploration results, mark the fault injection results for the corresponding bit positions in the dynamic instructions corresponding to the graph processing program to obtain the marked program.

[0056] In this embodiment, after completing the pruning of the fault space from the iteration round to the vertex, it is also necessary to perform pruning of the fault space of the instruction bit positions. The dynamic instructions are distinguished into numerical calculation instructions and address calculation instructions. For numerical calculation instructions, the fault results of their low bits are directly marked as BC and do not require fault injection (for example, for the IEEE 754 data format, its low 16 bits can be marked as BC); for address calculation instructions, according to the address space allocated to the program, the fault results of the high bits of the instruction are directly marked as Detected and do not require fault injection. That is, first, the dynamic instructions corresponding to the graph processing program are divided based on the instruction type to obtain the corresponding instruction division result; then, based on the fault resilience exploration result, the corresponding first fault injection result marking operation and the second fault injection result marking operation are triggered for the corresponding bit positions in the numerical calculation instructions and the address calculation instructions in the instruction division result respectively to obtain the marked program.

[0057] Step S14: Use the target iteration round, the target vertex, and the marked program to perform simulated injection of hardware faults, and perform injection result statistics for each preset granularity respectively to obtain the corresponding fault injection results.

[0058] In this embodiment, after completing the pruning of the fault space, only perform fault injection on the remaining fault space. And after performing fault injection, result statistics are performed for different preset granularities of the graph processing system (which can be at the assembly instruction level, vertex level, subgraph level, kernel function level, or other granularities or combinations of granularities can be selected or customized according to actual needs).

[0059] Furthermore, regarding result statistics. In this embodiment, after performing simulated injection of hardware faults on the marked program, for any preset granularity, by monitoring the program output, and using the task processing result and the preset fault injection result type to perform injection result analysis and statistics on the marked area and the fault injection area in the marked program respectively to obtain the fault injection result corresponding to the current preset granularity. Specifically, for each preset granularity, the following are calculated respectively: for the area with a known result of BC, the proportion of the area in the total fault area, BC probability, SC probability, and Detected probability are (a, 1, 0, 0); for the area with a known result of Detected, the proportion of the area in the total fault area, BC probability, SC probability, and Detected probability are (b, 0, 0, 1); for the fault injection area, the proportion of the area in the total fault area, BC probability, SC probability, and Detected probability are (c, x, y, z), where . The calculation of the fault injection result distribution of this granularity can be shown as follows:

[0060] ;

[0061] In the formula, is the probability of benign error; is the probability of severe error; is the probability of detectable error. In this way, the fault injection results at all preset granularities can be obtained. Then, the hardware fault-sensitive parts in the graph processing system can be found according to the determined fault injection results for selective protection, that is, the parts that are likely to cause damage to the graph processing results after being interfered by hardware faults.

[0062] In summary, in this embodiment, for the hardware fault problem in the large-scale graph processing system, an efficient fault injection method for graph computing tasks is designed. Specifically, the fault injection space is reduced according to the execution characteristics of the graph processing process. Compared with the traditional random fault injection method, the number of fault injections and the overhead are reduced on the premise of ensuring the correctness of the system reliability evaluation of the graph processing system. In addition, this embodiment also supports multi-dimensional analysis of the reliability of the graph processing system, which is of great significance for efficiently reducing the overhead of the program fault tolerance strategy.

[0063] It can be seen that in the embodiment of the present application, iterative graph processing is performed based on the graph processing program corresponding to the graph computing task to determine and record the corresponding task processing results; the target iteration round to be fault-injected is determined from each iteration round through the task processing results and the pre-determined fault resilience exploration results, and the active vertex set corresponding to the target iteration round is analyzed to determine the target vertex to be fault-injected based on the obtained set analysis results; the corresponding bit positions in the dynamic instructions corresponding to the graph processing program are marked with fault injection results based on the fault resilience exploration results to obtain the marked program; the target iteration round, the target vertex, and the marked program are used to simulate the injection of hardware faults, and the injection results are statistically analyzed using each preset granularity to obtain the corresponding fault injection results. That is, the present application first obtains the task processing results corresponding to the graph computing task, then uses the task processing results and the pre-determined fault resilience exploration results to determine the target iteration round and target vertex to be fault-injected, and marks the corresponding bit positions in the graph processing program with fault injection results, and then performs fault injection based on the marked program, target iteration round, and target vertex, and statistically analyzes the injection results using different preset granularities to determine the fault injection results. In this way, under the condition of ensuring effectiveness and reliability, the number of fault injections can be reduced, thereby reducing energy consumption and time overhead, and further improving the efficiency of the subsequent fault tolerance strategy for guiding graph processing.

[0064] See Figure 6 As shown, the embodiment of the present application also correspondingly discloses a fault injection device, including:

[0065] A program execution module 11, configured to perform iterative graph processing based on a graph processing program corresponding to a graph computing task, so as to determine and record corresponding task processing results;

[0066] An injection exploration module 12, configured to determine a target iteration round to be fault-injected from each iteration round according to the task processing results and pre-determined fault resilience exploration results, and analyze an active vertex set corresponding to the target iteration round, so as to determine a target vertex to be fault-injected according to the obtained set analysis results;

[0067] An instruction marking module 13, configured to mark corresponding bit positions in dynamic instructions corresponding to the graph processing program based on the fault resilience exploration results, so as to obtain a marked program;

[0068] A fault injection module 14, configured to perform simulated injection of hardware faults by using the target iteration round, the target vertex, and the marked program, and respectively perform statistics on injection results in each preset granularity, so as to obtain corresponding fault injection results.

[0069] Wherein, for the more specific working processes of the above-mentioned various modules, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0070] Thus, the present application first obtains task processing results corresponding to a graph computing task, then determines a target iteration round and a target vertex to be fault-injected by using the task processing results and pre-determined fault resilience exploration results, marks corresponding bit positions in the graph processing program with fault injection results, then performs fault injection based on the marked program, the target iteration round, and the target vertex, and statistically analyzes injection results in different preset granularities to determine fault injection results. In this way, under the conditions of ensuring effectiveness and reliability, the number of fault injections can be reduced, thereby reducing energy consumption and time overhead, and further improving the efficiency of subsequent fault tolerance strategies for guiding graph processing.

[0071] In some specific embodiments, the program execution module 11 may specifically be configured to complete corresponding iterative graph processing operations by executing a graph processing program corresponding to a graph computing task, and record corresponding program output information, dynamic instructions and register information corresponding to the graph processing program, and an active vertex set of each iteration round.

[0072] In some specific embodiments, the injection exploration module 12 may be specifically configured to analyze the coincidence degree of active vertices in each iteration round based on the task processing result and the pre-determined fault resilience exploration result, so as to obtain the corresponding iteration round analysis result; determine a plurality of iteration groups based on the iteration round analysis result, and screen out the target iteration rounds to be fault-injected from each of the iteration groups.

[0073] In some specific embodiments, the injection exploration module 12 may be specifically configured to perform neighbor set similarity analysis on vertices in each active vertex set corresponding to the target iteration round based on the task processing result and the fault resilience exploration result, so as to obtain the corresponding first set analysis result; use the first set analysis result to screen out the target vertices to be fault-injected from each of the active vertex sets.

[0074] In some specific embodiments, the injection exploration module 12 may be specifically configured to calculate the clustering coefficient between vertices in each active vertex set corresponding to the target iteration round based on the task processing result and the fault resilience exploration result, so as to obtain the corresponding second set analysis result; use the second set analysis result to screen out the target vertices to be fault-injected from each of the active vertex sets.

[0075] In some specific embodiments, the instruction marking module 13 may be specifically configured to divide the dynamic instructions corresponding to the graph processing program based on the instruction type, so as to obtain the corresponding instruction division result; respectively trigger the corresponding first fault injection result marking operation and the second fault injection result marking operation on the corresponding bit positions in the numerical calculation instructions and the address calculation instructions in the instruction division result based on the fault resilience exploration result, so as to obtain the marked program.

[0076] In some specific embodiments, the fault injection module 14 may be specifically configured to, after simulating and injecting hardware faults into the marked program, for any preset granularity, monitor the program output, and perform injection result analysis and statistics on the marked area and the fault injection area in the marked program by using the task processing result and the preset fault injection result type respectively, so as to obtain the fault injection result corresponding to the current preset granularity.

[0077] Furthermore, the embodiment of the present application also discloses an electronic device. Figure 7 It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment, and the content in the figure should not be considered as any limitation on the scope of use of the present application.

[0078] Figure 7Schematic diagram of the structure of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the fault injection method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0079] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed thereon here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0080] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a disk, or an optical disc, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0081] Among them, the operating system 221 is used to manage and control each hardware device on the electronic device 20 and the computer program 222, and it may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the fault injection method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs that can be used to complete other specific tasks.

[0082] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the fault injection method disclosed above is implemented. For the specific steps of this method, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

[0083] In the present specification, the various embodiments are described in a progressive manner, and the key points of each embodiment are the differences from other embodiments. The same or similar parts among the various embodiments may be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and reference may be made to the description of the method part for related parts.

[0084] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0085] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0086] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of another identical element in the process, method, article or device comprising the element.

[0087] The technical solutions provided in this application have been introduced in detail above. Specific examples are used herein to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A fault injection method, characterized in that: include: Perform iterative graph processing based on the graph processing program corresponding to the graph computing task to determine and record the corresponding task processing results; Determine a target iteration round to be injected with faults from each iteration round by using the task processing result and the predetermined fault resilience exploration result, and analyze the active vertex set corresponding to the target iteration round to determine the target vertex to be injected with faults based on the obtained set analysis result; Based on the fault resilience exploration result, marking the corresponding bits in the dynamic instructions corresponding to the graph processing program with fault injection results to obtain a marked program; The target iteration round, the target vertex and the marked program are used to perform simulated injection of hardware faults, and injection result statistics are performed using each preset granularity to obtain corresponding fault injection results.

2. The fault injection method according to claim 1, characterized in that: The iterative graph processing is performed based on the graph processing program corresponding to the graph computing task to determine and record the corresponding task processing result, including: The corresponding iterative graph processing operation is completed by executing the graph processing program corresponding to the graph computing task, and the corresponding program output information, the dynamic instructions and register information corresponding to the graph processing program, and the active vertex set of each iteration round are recorded.

3. The fault injection method according to claim 1, characterized in that: The step of determining a target iteration round to be injected with faults from each iteration round by using the task processing result and a predetermined fault resilience exploration result includes: Analyze the overlap degree of active vertices in each iteration round based on the task processing result and the predetermined fault resilience exploration result to obtain the corresponding iteration round analysis result; Based on the iteration round analysis result, a plurality of iteration groups are determined, and a target iteration round to be injected with a fault is screened out from each of the iteration groups.

4. The fault injection method according to claim 1, characterized in that: The step of analyzing the active vertex set corresponding to the target iteration round to determine the target vertex to be injected with the fault based on the obtained set analysis result includes: Based on the task processing result and the fault resilience exploration result, a neighbor set similarity analysis is performed between vertices in each active vertex set corresponding to the target iteration round to obtain a corresponding first set analysis result; The target vertices to be injected with faults are screened out from each of the active vertex sets using the first set analysis result.

5. The fault injection method according to claim 1, characterized in that: The step of analyzing the active vertex set corresponding to the target iteration round to determine the target vertex to be injected with the fault based on the obtained set analysis result includes: Based on the task processing result and the fault resilience exploration result, a clustering coefficient is calculated between vertices in each active vertex set corresponding to the target iteration round to obtain a corresponding second set analysis result; The target vertices to be injected with faults are screened out from each of the active vertex sets using the analysis result of the second set.

6. The fault injection method according to claim 1, characterized in that: The marking of the fault injection result of the corresponding bit in the dynamic instruction corresponding to the graph processing program based on the fault resilience exploration result includes: Dividing the dynamic instructions corresponding to the graph processing program based on instruction types to obtain corresponding instruction division results; Based on the fault resilience exploration result, corresponding bits in the numerical calculation instruction and the address calculation instruction in the instruction partitioning result are respectively triggered to correspondingly perform a first fault injection result marking operation and a second fault injection result marking operation to obtain a marked program.

7. The fault injection method according to any one of claims 1 to 6, characterized in that: The use of the target iteration round, the target vertex, and the marked program to simulate the injection of hardware faults, and the use of each preset granularity to perform injection result statistics, includes: After the hardware fault is simulated and injected into the marked program, for any preset granularity, the program output is monitored, and the injection result analysis and statistics are performed on the marked area and the fault injection area in the marked program respectively using the task processing result and the preset fault injection result type, so as to obtain the fault injection result corresponding to the current preset granularity.

8. A fault injection device, characterized in that: include: A program execution module, used to perform iterative graph processing based on a graph processing program corresponding to the graph computing task, so as to determine and record corresponding task processing results; An injection exploration module, used to determine a target iteration round to be injected with faults from each iteration round by using the task processing result and a predetermined fault resilience exploration result, and to analyze the active vertex set corresponding to the target iteration round to determine the target vertex to be injected with faults based on the obtained set analysis result; An instruction marking module, used for marking the corresponding bits in the dynamic instructions corresponding to the graph processing program with fault injection results based on the fault resilience exploration result, so as to obtain a marked program; The fault injection module is used to perform a simulated injection of a hardware fault using the target iteration round, the target vertex and the marked program, and perform injection result statistics using each preset granularity to obtain a corresponding fault injection result.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the fault injection method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the fault injection method according to any one of claims 1 to 7.

Images