DRAM (Dynamic Random Access Memory) and end-side equipment

Abstract

The invention provides a DRAM (Dynamic Random Access Memory) and an end side device, and the DRAM comprises a plurality of memory blocks which are used for storing data; the plurality of memory block controllers are arranged corresponding to the plurality of memory blocks, and each memory block controller can control the corresponding memory block to write or read data; the ONFI interface controller is respectively connected with the plurality of memory block controllers and can send instructions to the plurality of memory block controllers so as to control the operation of the plurality of memory blocks; and the IO interface is connected with the ONFI interface controller and is configured to be used for being connected with a main control circuit, receiving a control signal of the main control circuit and sending the control signal to the ONFI interface controller. According to the invention, the ONFI protocol is utilized to control the DRAM memory, and the technologies of three-dimensional packaging, CE Reduction mechanism and the like are combined, so that the cost, the power consumption and the chip area are reduced, the storage density, the data access efficiency and the system flexibility are improved, and diversified application requirements are met.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to a DRAM memory and an edge device. Background Art

[0002] With the increasing richness of the functions of System on Chip (SOC) hosts, the storage requirements for different types of data continue to grow. In the selection of storage media, it is mainly divided into two types: flash memory (FLASH) and dynamic random access memory (DRAM).

[0003] Flash memory (FLASH) is mainly used to store data that needs to be preserved after power-off. Among them, large-capacity NAND FLASH is the most widely used. SOC chips usually connect to an external storage system through the Universal Flash Storage (UFS) or embedded MultiMediaCard (eMMC) protocol. Inside the external storage system, the storage system control chip connects to multiple FLASH dies through the Open NAND Flash Interface (ONFI) protocol.

[0004] Dynamic random access memory (DRAM) is mainly used for intermediate data that needs to be stored during the operation of the system. SOC chips need to be connected to DRAM through the Double Data Rate (DDR) interface protocol.

[0005] However, the above storage solutions have the following problems:

[0006] Complex interface: SOC chips need different interfaces (such as UFS / eMMC, DDR) to connect to different storage media, resulting in a large chip area overhead, especially the physical layer (PHY) part of DDR.

[0007] Increased power consumption: Different interfaces and memory types increase the power consumption of the system.

[0008] System bloat: The existence of multiple memories and interfaces makes the system structure complex and appears bloated.

[0009] In view of the above problems, there is an urgent need in the art for a new storage solution to reduce the chip area overhead of SOC chips, reduce power consumption, and simplify the system structure. Summary of the Invention

[0010] In view of the above problems, the present invention provides a DRAM memory, which is characterized by including:

[0011] A plurality of memory blocks for storing data;

[0012] A plurality of memory block controllers, arranged corresponding to the plurality of memory blocks, each memory block controller being capable of controlling the corresponding memory block to write or read data;

[0013] An ONFI interface controller, respectively connected to the plurality of memory block controllers, capable of sending instructions to the plurality of memory block controllers to control the operation of the plurality of memory blocks; and

[0014] An IO interface, connected to the ONFI interface controller, and configured to be connected to a main control circuit, receive control signals from the main control circuit and send them to the ONFI interface controller.

[0015] For the DRAM memory provided by the present invention, the IO interface is used for the input / output conversion of the ONFI signal of the main control circuit (host chip / SoC chip); the ONFI interface controller is used to name the received bus protocol and distribute data to each memory block, receive the data read from each memory block and strobe and output it, and can also process the status of the DRAM memory and perform calibration. Since the ONFI protocol is simpler than the DDR protocol, the circuit structure of its controller is also simpler and the power consumption is lower. In addition, the ONFI protocol controls fewer pins, which can save more pins of the main control circuit.

[0016] Optionally, the ONFI interface controller is configured to refresh the plurality of memory blocks using its refresh instruction.

[0017] The main function of the memory block controller is to control the reading and writing of each memory block and control the refresh strategy of the internal storage array circuit of the memory block. Specifically, since the ONFI protocol instruction set itself contains an erase instruction originally used to clear data in the FLASH memory, in this embodiment, this instruction is used to control the refresh strategy of the DRAM memory. Designed in this way, without the need to additionally introduce hardware resources, the existing instructions of the ONFI protocol are used to implement the refresh control of the DRAM memory. Compared with the existing DRAM memory that requires a dedicated refresh signal generation circuit, space and cost are saved.

[0018] Optionally, the plurality of memory blocks and the plurality of memory block controllers are integrated into at least one DRAM storage chip, and the IO interface and the ONFI interface controller are integrated into a control chip.

[0019] In the present invention, the circuits with storage functions and the circuits with interface functions are separately arranged on different chips. With such an arrangement, on the one hand, the circuits with interface functions and the circuits with storage functions can be manufactured using different processes respectively, so that the DRAM storage chip has a higher storage density. On the other hand, when multiple DRAM storage chips are configured, the space of the DRAM memory can be saved and the cost can be reduced by sharing the same control chip.

[0020] Optionally, the at least one DRAM storage chip and the control chip are connected by a three-dimensional packaging process.

[0021] With such an arrangement, the following technical effects are achieved:

[0022] Reduce chip area: Through three-dimensional packaging, the DRAM storage chip and the control chip are stacked together, thus reducing the area they occupy on the plane. This is particularly important for SOC chips with limited area.

[0023] Improve storage density: Three-dimensional packaging can effectively improve the storage density and integrate more storage capacity in a limited space.

[0024] Shorten the interconnection distance: The DRAM storage chip and the control chip are connected by means of TSV (Through-Silicon Via) or Hybrid bonding, etc., shortening the interconnection distance between them, thus reducing the signal transmission delay and power consumption.

[0025] Improve data transmission rate: Due to the shortened interconnection distance, the data transmission rate can be increased, thus improving the overall performance of the system.

[0026] To achieve the above-mentioned invention purpose, the present invention provides an edge device, which applies the DRAM memory described above and includes:

[0027] A main control circuit; and

[0028] At least one DRAM target, which is connected to the main control circuit and can operate based on the instructions of the main control circuit;

[0029] Wherein, each DRAM target includes a plurality of the DRAM memories that can synchronously receive control signals.

[0030] Optionally, the multiple DRAM memories included in each DRAM target share the same address.

[0031] Optionally, the external network interfaces and external nodes of adjacent DRAM memories are interconnected to form a daisy chain.

[0032] Optionally, the main control circuit accesses and controls the corresponding DRAM target based on the CE Reduction mechanism and address of the ONFI protocol.

[0033] The technical effects of such a setting are as follows:

[0034] Expand the DRAM storage capacity: Through the CE Reduction mechanism, multiple DLUNs can be connected together without adding extra pins. In this way, with the same number of pins, the main control circuit (host / SoC chip) can connect more DRAM storage chips, thus expanding the DRAM storage capacity.

[0035] Share channel signals: Multiple DRAM Targets can share one channel signal of the host, and different DRAM Targets are distinguished by different CE signals. This method can effectively utilize channel resources and improve data transmission efficiency.

[0036] Flexible topology structure: The main control circuit can be provided with multiple channels, and the required DRAM storage size can be topologically arranged flexibly according to actual needs. This solution can flexibly configure the DRAM storage capacity according to different application scenarios to meet different requirements.

[0037] Optionally, the edge device further includes a FLASH memory and an external storage control chip. The DRAM memory and the FLASH memory are connected to the external storage control chip based on the ONFI protocol, and the external storage control chip is connected to the main control circuit.

[0038] Optionally, the main control circuit is an SoC chip, and the external storage control chip is connected to the SoC chip by the UFS protocol, SD protocol or emmc protocol.

[0039] The core of the present invention lies in using the ONFI protocol to replace the traditional DDR protocol to control the DRAM memory, and a series of optimizations and expansions are carried out on this basis. Its main technical effects can be summarized as the following points:

[0040] Reduce the area and power consumption of the main control chip: Since the ONFI protocol is simpler than the DDR protocol, its controller circuit structure is also simpler, occupying less chip area and having lower power consumption.

[0041] Reduce the number of pins of the main control chip: The ONFI protocol requires fewer pins, which can save the pin resources of the main control chip and enable them to be used for other functions.

[0042] Simplified DRAM Memory Control: The ONFI interface controller can uniformly manage multiple memory blocks, simplifying the control of the DRAM memory by the host chip.

[0043] Implementation of DRAM Memory Refresh Control: By utilizing the existing refresh instructions of the ONFI protocol, the refresh control of the DRAM memory can be achieved without the need to introduce additional hardware resources, saving space and cost.

[0044] Improvement of Storage Density: By separately arranging the circuits for storage functions and interface functions on different chips and adopting a three-dimensional packaging process, the storage density of the DRAM memory can be increased.

[0045] Flexible Storage Configuration: Different types and capacities of memories can be flexibly configured according to actual needs to meet different application scenarios.

[0046] Improvement of Data Access Efficiency: The external storage control chip can optimize the transmission and management of data between the DRAM memory and the FLASH memory, improving data access efficiency.

[0047] Easy to Expand: This solution is easy to expand, and the number and type of memories can be increased according to needs to meet the requirements of future applications.

[0048] Simplification of Control Logic: By forming a DRAM target from multiple DLUNs, the host only needs to control one CE signal and one address to access all DLUNs within the target, simplifying the control logic.

[0049] Improvement of Bandwidth: Since multiple DLUNs can be accessed simultaneously, this architecture can improve the bandwidth of the storage system.

[0050] Logical Unity: Combining multiple DLUNs into a DRAM target can make the storage system more unified logically, facilitating management and use.

[0051] In summary, the present invention controls the DRAM memory by utilizing the ONFI protocol and combines technologies such as three-dimensional packaging and the CEReduction mechanism, reducing costs, power consumption, and chip area while increasing storage density, data access efficiency, and system flexibility, meeting diverse application requirements. Brief Description of the Drawings

[0052] Figure 1 It is a schematic structural diagram of the DRAM memory and the end-side device provided by the embodiment of the present invention.

[0053] Figure 2 It is a schematic structural diagram of the DRAM memory and the end-side device provided by the embodiment of the present invention.

[0054] Figure 3 It is a schematic structural diagram of a DRAM memory and an edge device provided by an embodiment of the present invention.

[0055] Figure 4 It is a schematic structural diagram of a DRAM target provided by an embodiment of the present invention.

[0056] Figure 5 It is a schematic structural diagram of an edge device provided by an embodiment of the present invention.

[0057] Figure 6 It is a schematic structural diagram of an edge device provided by an embodiment of the present invention. Specific Embodiments

[0058] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0059] As Figure 1 shown, this embodiment provides a DRAM memory 100, including: a plurality of memory blocks 10 for storing data; a plurality of memory block controllers 20, provided corresponding to the plurality of memory blocks 10, capable of controlling the corresponding memory blocks 10 to write or read data; an ONFI interface controller 30, respectively connected to the plurality of memory block controllers 20, capable of sending instructions to the plurality of memory block controllers 20 to control the operation of the plurality of memory blocks 10; an IO interface 40, connected to the ONFI interface controller 30 and configured to be connected to the main control circuit 200, receive the control signal of the main control circuit 200 and send it to the ONFI interface controller 30.

[0060] For the DRAM memory 100 provided in this embodiment, the IO interface 40 is used for the input / output conversion of the ONFI signal of the main control circuit 200 (host chip / SoC chip); the ONFI interface controller 30 is used to name the received bus protocol and distribute the data to each memory block 10, receive the data read from each memory block 10 and strobe and output it, and at the same time can process the state of the DRAM memory 100 and perform calibration. Since the ONFI protocol is simpler than the DDR protocol, the circuit structure of its controller is also simpler and the power is lower. In addition, the ONFI protocol controls fewer pins, which can save more pins of the main control circuit 200.

[0061] Optionally, the ONFI interface controller 30 is configured to refresh the plurality of memory blocks using its refresh instruction.

[0062] The main function of the memory block controller 20 is to control the read and write of each memory block 10 and to control the refresh strategy of the internal storage array circuit of the memory block 10. Specifically, since the ONFI protocol instruction set itself includes an erase instruction originally used to clear data in the FLASH memory, in this embodiment, this instruction is used to control the refresh strategy of the DRAM memory 100. Designed in this way, without the need to introduce new instructions additionally, the existing instructions of the ONFI protocol are used to implement the refresh control of the DRAM memory 100. Compared with the existing DRAM memory that requires a dedicated refresh signal generation circuit, space and cost are saved.

[0063] In addition, since the ONFI protocol is simpler than the DDR protocol, the structure of its interface controller is simpler, resulting in lower power consumption of the DRAM memory 100. At the same time, since there are fewer pins controlled by the ONFI protocol, the host chip / SoC system chip connected to the DRAM memory 100 can use fewer pins to control the DRAM memory 100.

[0064] Optionally, as Figure 2 shown, in another embodiment, the DRAM memory includes at least one DRAM storage chip 110 and a control chip 120. The control chip 120 includes an IO interface 40 and an ONFI interface controller 30. The DRAM storage chip 110 includes a plurality of memory blocks 10 and a plurality of memory block controllers 20 corresponding to the plurality of memory blocks 10. In this embodiment, the circuits with storage functions and the circuits with interface functions are separately arranged on different chips. Arranged in this way, on the one hand, it can enable the circuits with interface functions and the circuits with storage functions to be manufactured using different processes respectively. The interface circuit / control circuit that occupies a larger chip size is arranged on the control chip 120, so that the DRAM storage chip 110 has more space to arrange the storage array, thereby enabling the DRAM storage chip 110 to have a higher storage density. On the other hand, when there are multiple DRAM storage chips 110, the space of the DRAM memory can be saved and the cost can be reduced by sharing the same control chip 120.

[0065] Specifically, at least one DRAM storage chip 110 and the control chip 120 are connected by a three-dimensional packaging process. As Figure 3 shown, when the number of DRAM storage chips 110 is multiple, each DRAM storage chip 110 is connected to the control chip 120 by means of TSV, Hybridbonding, etc.

[0066] With such a setting, the following technical effects are achieved:

[0067] Reduce chip area: Through 3D packaging, the DRAM memory chip and the control chip are stacked together, thus reducing the area they occupy on the plane. This is particularly important for SOC chips with limited area.

[0068] Improve storage density: 3D packaging can effectively improve storage density and integrate more storage capacity in a limited space.

[0069] Shorten the interconnection distance: The DRAM memory chip and the control chip are connected through TSV (Through-Silicon Via) or Hybrid bonding, etc., shortening the interconnection distance between them, thus reducing signal transmission delay and power consumption.

[0070] Improve data transmission rate: Since the interconnection distance is shortened, the data transmission rate can be increased, thus enhancing the overall performance of the system.

[0071] Reduce power consumption: Shortening the interconnection distance can reduce the energy loss during signal transmission, thus reducing power consumption.

[0072] Optionally, Figures 1 to 3 Each DRAM memory shown in is a DLUN (DRAM logic unit). In this embodiment, referring to Figure 4 , multiple DLUNs are combined into a DRAM target, and the control signals (such as the CE signal) of all DLUNs inside this DRAM target are connected together. This means that when the host accesses this DRAM target, all DLUNs that make up this target will be activated simultaneously.

[0073] ONFI CE Reduction mechanism: The connection between DLUNs still follows the CE Reduction mechanism of the ONFI protocol, that is, the Eni (External Network Interface) and Eno (External Node) signals of adjacent DLUNs are interconnected to form a daisy chain.

[0074] Unified addressing: Each DRAM target will be assigned a unique address when powered on. The host accesses this DRAM target through this address. Since the control signals of multiple DLUNs inside a DRAM target are connected together and share the same address, the host can access them as if accessing a single storage unit.

[0075] Different from the traditional architecture where each DLUN corresponds to one or more DRAM targets, the architecture provided in this embodiment combines multiple DLUNs into a logically single DRAM target. The advantages of this approach are as follows:

[0076] Simplified control: Since the DLUNs within a single DRAM target share control signals, in this embodiment, the host only needs to control one CE signal and one address to access all the DLUNs within that target, simplifying the control logic.

[0077] Increased bandwidth: Since multiple DLUNs can be accessed simultaneously, this architecture may be able to increase the bandwidth of the storage system.

[0078] Logical unity: Combining multiple DLUNs into a single DRAM target can make the storage system more logically unified, facilitating management and use.

[0079] In addition, multiple DLUNs can be connected together through the CE Reduction mechanism of the ONFI protocol without adding any additional pins; thus, with the same number of pins, taking the main control circuit 200 as the host / SoC chip as an example, the main control circuit 200 can expand to a larger DRAM storage capacity.

[0080] Optionally, this embodiment provides an end-side device, such as Figure 5 shown, which includes a main control circuit 200 and at least one DRAM target 300. When the number of DRAM targets 300 is more than one, each DRAM target 300 is assigned an address, and multiple DRAM Targets 300 can share the signals of one channel of the host. Different DRAM Targets 300 are distinguished by different CE signals; the main control circuit 200 can be provided with multiple channels and can topology the required DRAM storage size according to actual needs.

[0081] The technical effects of such a setting are as follows:

[0082] Expanded DRAM storage capacity: Through the CE Reduction mechanism, multiple DLUNs can be connected together without adding extra pins. In this way, with the same number of pins, the main control circuit (host / SoC chip) can connect more DRAM storage chips, thereby expanding the DRAM storage capacity.

[0083] Shared channel signal: Multiple DRAM Targets can share one channel signal of the host, and different DRAM Targets are distinguished by different CE signals. This method can effectively utilize channel resources and improve data transfer efficiency.

[0084] Flexible topology structure: The main control circuit can be provided with multiple channels, and the required DRAM storage size can be topologically arranged flexibly according to actual needs. This solution can flexibly configure the DRAM storage capacity according to different application scenarios to meet different requirements.

[0085] This technical solution connects multiple DLUNs through the CE Reduction mechanism of the ONFI protocol, achieving the purpose of expanding the DRAM storage capacity with the same number of pins. At the same time, multiple DRAM Targets share the channel signal and the flexible topology structure, improving the utilization rate of storage resources and the flexibility of configuration. This solution can effectively solve the problems of limited SOC chip area and increased power consumption, and meet the requirements of different application scenarios for DRAM storage capacity.

[0086] Optionally, this embodiment also provides an end-side device, such as Figure 6 shown, including a main control circuit 200, an external storage control chip 400, and a memory. The memory includes a DRAM memory 100 and a FLASH memory 500. Among them, the DRAM memory 100 and the FLASH memory 500 are connected to the external storage control chip 400 through the ONFI protocol. Taking the main control circuit 200 as an SoC chip as an example, the SoC chip is connected to the external storage control chip through a UFS protocol, an SD protocol, or an emmc protocol, etc.

[0087] The technical effect of such a setting is:

[0088] Unified storage interface: Through the ONFI protocol, both the DRAM memory and the FLASH memory are connected to the external storage control chip. This enables the main control circuit (SoC chip) to only communicate with the external storage control chip without directly managing different types of memory interfaces, thus simplifying the design of the main control circuit and reducing its area overhead and power consumption.

[0089] Flexible storage configuration: Since the external storage control chip uniformly manages the DRAM memory and the FLASH memory, different types and capacities of memories can be flexibly configured according to actual needs to meet different application scenarios.

[0090] Efficient data access: The external storage control chip can optimize the transfer and management of data between the DRAM memory and the FLASH memory, improving data access efficiency.

[0091] Scalability: This solution is easy to expand. The number and type of memories can be increased as needed to meet the requirements of future applications.

[0092] So far, the technical solution of the present invention has been described with reference to the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to the above specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.

Claims

1. A DRAM memory, characterized in that: include: a plurality of memory blocks for storing data; A plurality of memory block controllers are arranged corresponding to the plurality of memory blocks, each memory block controller can control the corresponding memory block to write or read data; An ONFI interface controller, connected to the plurality of memory block controllers respectively, capable of sending instructions to the plurality of memory block controllers to control the operation of the plurality of memory blocks; as well as The IO interface is connected to the ONFI interface controller and is configured to be connected to the main control circuit, receive the control signal of the main control circuit and send it to the ONFI interface controller.

2. The DRAM memory according to claim 1, characterized in that: The ONFI interface controller is configured to refresh the plurality of memory blocks using refresh instructions thereof.

3. The DRAM memory according to claim 1 or 2, characterized in that: The plurality of memory blocks and the plurality of memory block controllers are integrated into at least one DRAM memory chip, and the IO interface and the ONFI interface controller are integrated into a control chip.

4. The DRAM memory according to claim 3, characterized in that: The at least one DRAM memory chip and the control chip are connected using a three-dimensional packaging process.

5. A terminal side device, characterized in that: A DRAM memory according to any one of claims 1 to 4, comprising: main control circuit; and at least one DRAM target, connected to the main control circuit and capable of operating based on instructions of the main control circuit; Each DRAM target includes a plurality of DRAM memories capable of synchronously receiving control signals.

6. The terminal side device according to claim 5, characterized in that: The multiple DRAM memories included in each DRAM target share the same address.

7. The terminal side device according to claim 5, characterized in that: The external network interfaces and external nodes of adjacent DRAM memories are interconnected to form a daisy chain.

8. The terminal side device according to claim 6, characterized in that: The main control circuit accesses and controls the corresponding DRAM target based on the CEReduction mechanism and address of the ONFI protocol.

9. The terminal side device according to any one of claims 5 to 8, characterized in that: It also includes a FLASH memory and an external storage control chip. The DRAM memory and the FLASH memory are connected to the external storage control chip based on the ONFI protocol, and the external storage control chip is connected to the main control circuit.

10. The terminal side device according to claim 9, characterized in that: The main control circuit is a SoC chip, and the external storage control chip is connected to the SoC chip using a UFS protocol, a SD protocol, or an emmc protocol.

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