PCIe automatic branching method and system
By establishing a correspondence between backplane identifiers and transmission bus numbers in the processor, and using the BMC to determine the channel splitting configuration information of the PCIe interface, the problem of BIOS setting errors was solved, automatic branching was achieved, and the stability and maintenance efficiency of the system were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANECHIPS TECH CO LTD
- Filing Date
- 2023-11-14
- Publication Date
- 2026-07-28
AI Technical Summary
In the existing technology, incorrect PCIe bridging settings in the BIOS can cause system function and performance problems. Furthermore, when facing new application scenarios, new versions of the BIOS need to be released, which increases the difficulty of BIOS maintenance.
By setting the correspondence between backplane identifiers and transmission bus numbers in the processor, the Baseboard Management Controller (BMC) determines the channel splitting configuration information of the PCIe interface and stores it in memory for use by the BIOS. This avoids the BIOS directly setting incorrect mapping tables and enables automatic branching.
It improves the accuracy of BIOS settings for PCIe interface branch modes, reduces the difficulty of system and BIOS maintenance, and avoids the possibility of devices becoming unusable or running at reduced speed due to configuration errors.
Smart Images
Figure CN120045494B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computers, and more specifically, to an automatic branching method and system for PCIe. Background Technology
[0002] In server equipment, the processor and peripheral devices are connected via the Peripheral Component Interconnect Express (PCIe). A processor typically has multiple standard PCIe interfaces, which are used to connect different devices, such as solid-state drives (SSDs), graphics cards, network cards, and data processing units (DPUs).
[0003] A standard PCIe interface typically has 16 lanes, which can be used to connect different PCIe devices simultaneously. To achieve this functionality, the PCIe interface's lane splitting information (PCIe bridging) needs to be configured through the Basic Input / Output System (BIOS) to divide the 16 lanes of the PCIe interface into different communication channels for connecting different PCIe devices.
[0004] In existing technology, a single BIOS firmware image is used to support different computer systems. This image stores the PCIe Bifurcation configurations for different systems to accommodate the hardware design associated with each system. Typically, a mapping table is provided in the BIOS, which records the PCIe Bifurcation configurations corresponding to different systems. When the BIOS powers on, it detects the system type and sets the correct PCIe Bifurcation according to the mapping table. If the BIOS sets an incorrect PCIe Bifurcation, it may prevent the system from using PCIe devices installed on the system, or cause PCIe devices to operate at reduced speed.
[0005] When a server processor is used in two different application scenarios and connected to different PCIe devices, it can be considered as two separate systems. To ensure proper system operation, it's necessary to first identify the current system and provide the correct PCIe bridging settings accordingly. In more complex scenarios, this process may result in incorrect PCIe bridging configurations in the BIOS, negatively impacting system functionality and performance. Furthermore, each time a new application scenario emerges, a new BIOS version needs to be released to support changes in PCIe bridging. These potential changes increase the maintenance complexity of both the system and the BIOS itself.
[0006] No solutions have yet been proposed for the problems of PCIe Bifurcation due to BIOS settings errors in related technologies, and the increased difficulty of BIOS maintenance caused by the need to release new BIOS versions when facing new application scenarios. Summary of the Invention
[0007] This invention provides an automatic branching method and system for the PCIe peripheral interconnect expansion bus, which at least solves the problems of PCIe Bifurcation due to BIOS settings errors in related technologies, as well as the increased difficulty of BIOS maintenance caused by the need to release new versions of BIOS when facing new application scenarios.
[0008] According to one embodiment of the present invention, an automatic branching system for the PCIe peripheral interconnect expansion bus is provided, comprising:
[0009] The processor is provided with one or more PCIe interfaces, through which it connects to one or more PCIe devices; one or more backplanes, each of which is configured with a backplane identifier and used to identify the maximum link width supported by the PCIe devices plugged into the backplane, and each of which PCIe devices is plugged into a corresponding backplane.
[0010] The Baseboard Management Controller (BMC) is connected to the backplane to which the PCIe devices are plugged in via a transmission bus. Each transmission bus is numbered and connected to a corresponding backplane. There is a preset correspondence between the number of each transmission bus and the PCIe interface to which the PCIe device plugged into the corresponding backplane is connected. The BMC obtains the backplane identifier of the backplane to which the PCIe devices are plugged in and the number of the transmission bus used. Based on the obtained backplane identifier and the number of the transmission bus, it determines the channel splitting configuration (Bifurcation) information for each PCIe interface for use by the Basic Input / Output System (BIOS).
[0011] In one exemplary embodiment, determining the channel splitting configuration (Bifurcation) information for each PCIe interface based on the acquired backplane identifier and the transmission bus number includes:
[0012] For each backplane connected to the BMC and the transmission bus used, the BMC determines the maximum link width supported by the PCIe device plugged into the backplane based on the obtained backplane identifier, and determines the PCIe interface to which the PCIe device is connected based on the obtained transmission bus number and the preset correspondence between the transmission bus number and the PCIe interface.
[0013] The bridging information for each PCIe interface is determined based on the maximum link width supported by each PCIe device connected to each PCIe interface.
[0014] In one exemplary embodiment, the system further includes:
[0015] The memory is used to store the bridging information of each PCIe interface set by the BMC;
[0016] The BIOS, connected to the processor, is used to read the Bifurcation information from the memory and set the branch mode of the PCIe interface in the processor according to the Bifurcation information.
[0017] In one exemplary embodiment, the processor is one of the following: a central processing unit (CPU), a data processing unit (DPU), and a graphics processing unit (GPU).
[0018] In one exemplary embodiment, the transmission bus is one of the following: serial bidirectional communication interface bus I2C, serial peripheral interface bus SPI, and universal asynchronous transceiver bus URAT.
[0019] According to another embodiment of the present invention, an automatic branching method for a peripheral device interconnect expansion bus PCIe is provided, applicable to any of the above-mentioned automatic branching system embodiments, comprising:
[0020] For each backplane connected to the BMC and the transmission bus used, obtain the backplane identifier of the backplane where each PCIe device is located and the number of the transmission bus used.
[0021] The BIFU (Bifurcation) information for each PCIe interface is determined based on the obtained backplane identifier and the transmission bus number for use by the BIOS (Basic Input / Output System).
[0022] In one exemplary embodiment, after determining the bridging information of each PCIe interface based on the acquired backplane identifier and the transmission bus number, the method further includes:
[0023] Store the Bifurcation information in a memory;
[0024] The BIOS reads the Bifurcation information from the memory and sets the branch mode of each PCIe interface in the processor according to the Bifurcation information.
[0025] In one exemplary embodiment, determining the bridging information for each PCIe interface based on the acquired backplane identifier and the transmission bus number includes:
[0026] The maximum link width supported by the PCIe device plugged into each backplane is determined based on the obtained backplane identifier. The PCIe interface to which the PCIe device is connected is determined based on the obtained transmission bus number and the preset correspondence between the transmission bus number and each PCIe interface.
[0027] The bridging information for each PCIe interface is determined based on the maximum link width supported by each PCIe device connected to each PCIe interface.
[0028] In one exemplary embodiment, before obtaining the number of the transport bus used by each PCIe device, the method further includes:
[0029] Establish the correspondence between the PCIe interface and the number of the transmission bus.
[0030] In one exemplary embodiment, before obtaining the backplane identifier of the backplane where each PCIe device is located, the method further includes:
[0031] Configure the correspondence between the maximum link width supported by the PCIe device and the backplane identifier.
[0032] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.
[0033] In the above embodiments of the present invention, by establishing a correspondence between the backplane ID and the type of PCIe device plugged into the CPU's PCIe interface, and establishing a correspondence between the transmission bus number of the PCIe device and the plugged PCIe interface, the BMC can correctly configure the CPU's PCIe interface for PCIe Bifurcation based on the plugged PCIe device. This avoids the problems in related technologies where setting a mapping table in the BIOS and setting PCIe Bifurcation according to the mapping table may lead to BIOS setting errors, and the increased difficulty of BIOS maintenance due to the need to release a new version of the BIOS when facing new application scenarios. This improves the correctness of BIOS setting the branch mode of the PCIe interface and reduces the difficulty of system and BIOS maintenance. Attached Figure Description
[0034] Figure 1 This is a block diagram of an automatic branching system for a peripheral device interconnect expansion bus PCIe according to an embodiment of the present invention;
[0035] Figure 2 This is a flowchart of an automatic branching method for a peripheral device interconnect expansion bus PCIe according to an embodiment of the present invention;
[0036] Figure 3 This is a flowchart illustrating the specific execution process of an automatic branching system for a peripheral device interconnection expansion bus (PCIe) according to an embodiment of the present invention. Detailed Implementation
[0037] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.
[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0039] In existing server equipment, the CPU and peripheral devices are connected via PCIe. A CPU typically has multiple standard PCIe interfaces for connecting devices such as SSDs, graphics cards, network cards, and DPUs. A standard PCIe interface usually has 16 lanes. A standard PCIe interface may be used to connect different PCIe devices simultaneously. This requires configuring PCIeBifurcation in the BIOS to divide the 16 PCIe lanes into different communication channels to connect different PCIe devices.
[0040] To address the issue of incorrect PCIe Bifurcation configurations in BIOS settings during complex scenarios, this invention provides an implementation of automatic PCIe branching in the following embodiments.
[0041] Example 1
[0042] According to one embodiment of the present invention, an automatic branching system for the PCIe peripheral interconnect expansion bus is provided. Figure 1 This is a block diagram of an automatic branching system for the PCIe peripheral interconnect expansion bus according to an embodiment of the present invention, such as... Figure 1 As shown, it includes:
[0043] Processor 101, setting one or more ( Figure 1 Only two PCIe interfaces (108a and 108b are shown in the image), through which PCIe interface 108b connects to one or more (… Figure 1 Only two are shown in the image) PCIe devices 102a and 102b are connected ( Figure 1 (Only one PCIe interface is shown connected to two PCIe devices).
[0044] One or more backplates Figure 1 Only two backplanes (103a and 103b) are shown. These backplanes 103a and 103b have markings (e.g., markings 1 and 0) to indicate the maximum link width supported by the PCIe devices plugged into them. PCIe devices 102a and 102b are plugged into backplanes 103a and 103b. The markings of backplanes 103a and 103b and the numbers of transmission buses 104a and 104b are obtained. Based on these markings, the channel splitting configuration information of PCIe interface 108b is determined, and this information is stored in memory 109 for use by BIOS 107. Memory 109 is connected to both BMC 106 and BIOS 107.
[0045] In this embodiment, by establishing a correspondence between the backplane ID and the type of PCIe device plugged into the CPU's PCIe interface, and by establishing a correspondence between the transmission bus number of the PCIe device and the plugged PCIe interface, the BMC can perform the correct PCIe Bifurcation configuration for the CPU's PCIe interface based on the plugged PCIe device.
[0046] In an exemplary embodiment, determining the channel splitting configuration information of the PCIe interface 108b based on obtaining the identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b includes:
[0047] The BMC 106 determines the maximum link width (e.g., x8) supported by the PCIe device 102a connected to the backplane 103a based on the acquired backplane identifier (e.g., 0) of the backplane 103a. Based on the acquired transmission bus number (e.g., 1a) and the preset correspondence between the transmission bus number and the PCIe 108b interface, the BMC 106 determines that the PCIe interface connected to the PCIe device 102a is PCIe 108b. Similarly, the BMC 106 determines the maximum link width (e.g., x4) supported by the PCIe device 102b connected to the backplane 103b based on the acquired backplane identifier (e.g., 1) of the backplane 103b. Based on the acquired transmission bus number (e.g., 1b) and the preset correspondence between the transmission bus number and the PCIe 108b interface, the BMC 106 determines that the PCIe interface connected to the PCIe device 102b is PCIe interface 108b.
[0048] Based on the maximum link width (e.g., x8, x4) supported by the PCIe devices 102a and 102b connected to the PCIe interface 108, determine the channel splitting configuration information (x8+x4+x4) of the PCIe interface 108.
[0049] In one exemplary embodiment, the memory 109 is used to store the channel splitting information of the PCIe interfaces 108a and 108b configured by the BMC 106. That is, the BMC 106 outputs different PCIe bridging codes and stores them in the memory 109 for use by the BIOS, eliminating the need for the BIOS to retrieve the PCIe bridging codes from the mapping table, and reducing the possibility of configuration errors causing PCIe devices to become unusable or operate at reduced speed.
[0050] In an exemplary embodiment, the BIOS 107 is connected to the processor 101 and is used to read the channel splitting information in the memory 109 and set the branch mode of the PCIe interface in the processor 101 according to the channel splitting information.
[0051] In one exemplary embodiment, the processor 101 may be a central processing unit (CPU), a data processing unit (DPU), or a graphics processing unit (GPU).
[0052] In one exemplary embodiment, the transmission buses 104a and 104b may be, for example, an Inter-Integrated Circuit (I2C), a Serial Peripheral Interface (SPI), or a Universal Asynchronous Receiver Transmitter (URAT).
[0053] Example 2
[0054] According to another embodiment of the present invention, an automatic branching method for the PCIe peripheral interconnect expansion bus is provided, applicable to any of the above-described automatic branching system embodiments. Figure 2 This is a flowchart of an automatic branching method for the PCIe peripheral interconnect expansion bus according to an embodiment of the present invention, as shown below. Figure 2 As shown, the process includes the following steps:
[0055] In step S202, when the BMC 106 detects that it is connected to the backplanes 103a and 103b to which the PCIe devices 102a and 102b are plugged, it obtains the backplane identifiers of the backplanes 103a and 103b to which the PCIe devices 102a and 102b are located, as well as the numbers of the transmission buses 104a and 104b connecting the PCIe devices 102a and 102b.
[0056] When the BMC106 detects a connection with the backplanes 103a and 103b, the BMC acquires signals from the backplanes 103a and 103b via the transmission buses 104a and 104b.
[0057] In step S204, BMC 106 sets the channel splitting information of the PCIe interface 108b according to the obtained identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b.
[0058] Specifically, the maximum link width supported by the PCIe devices 102a and 102b is determined according to the identifiers of the backplanes 103a and 103b, respectively, and the PCIe interface 108b to which the PCIe devices 102a and 102b are connected is determined according to the numbers of the transmission buses 104a and 104b, respectively.
[0059] For example, BMC 106 can determine the maximum link widths supported by PCIe devices 102a and 102b as x8 and x4 respectively based on the backplane identification, and determine that PCIe devices 102a and 102b are both plugged into PCIe interface 108b based on the transmission bus number. Therefore, BMC 106 can configure the channel splitting information of PCIe interface 108b as x8+x4+x4.
[0060] The relationship between the maximum link width supported by 102a and 102b and the channel splitting configuration information of the PCIe interface 108b is shown in Table 1:
[0061]
[0062] Table 1
[0063] Step S206: The channel splitting information is stored in memory 109 for use by BIOS 107. Memory 109 is connected to both BMC 106 and BIOS 107. For example, the channel splitting information x8+x4+x4 of PCIe interface 108b is saved to memory 109, thus eliminating the need for BIOS to retrieve PCIe Bifurcation from the mapping table and reducing configuration errors.
[0064] In one exemplary embodiment, step 208 is also included:
[0065] Step S208: After the processor is powered on, the BIOS 107 reads the channel splitting information from the memory 109 and sets the PCIe branch mode in the processor 101 according to the channel splitting information, so that the PCIe devices plugged into the PCIe interface can work normally. For example, the BIOS can set the branch mode of the PCIe interface 108b to x8+x4+x4 during processing based on the channel splitting information x8+x4+x4 stored in the memory 109.
[0066] In this embodiment, before executing step S202, the correspondence between the PCIe interface and the transmission bus number can be preset, as can the correspondence between the maximum link width supported by the PCIe device and the backplane identifier.
[0067] Figure 3This is a flowchart illustrating the specific execution process of an automatic branching system for a peripheral device interconnect expansion bus (PCIe) according to an embodiment of the present invention. Figure 3 As shown, it includes:
[0068] Step S300: Set the correspondence between the PCIe interface and the transmission bus number. This correspondence can be that the transmission bus of PCIe108a is set to 0a / 0b / 0c / 0d, and the transmission bus number of PCIe108b is set to 1a / 1b / 1c / 1d, corresponding to lane0-lane3, lane4-lane7, lane8-lane11, and lane12-lane15 of PCIe108a / b respectively.
[0069] Set the correspondence between the maximum link width supported by the PCIe device and the backplane identifier. This correspondence can be that the maximum link width supported by the PCIe device x8 corresponds to the backplane number 1 when plugged into the device, and the maximum link width supported by the PCIe device x4 corresponds to the backplane number 0 when plugged into the device.
[0070] In this embodiment, when two PCIe devices 102a and 102b (with maximum link widths of x8 and x4 respectively) are connected to the processor, different backplane numbers are selected according to the maximum link width of the PCIe devices. PCIe device 102a is plugged into backplane number 1, and PCIe device 102b is plugged into backplane number 0. Different transmission buses are selected according to the connected PCIe interfaces. The two PCIe devices are connected to PCIe interface 108b, and two transmission buses numbered 1a and 1b are selected to connect the two PCIe devices to BMC 106. When BMC 106 detects connection to backplanes 103a and 103b, it receives signals from backplanes 103a and 103b through transmission buses 104a and 104b.
[0071] Step S302: Based on the identifiers (1 and 0) of the backplanes 103a and 103b, determine that the maximum link width supported by the PCIe devices 102a and 102b is x8 and x4, respectively; and based on the numbers (1a and 1b) of the transmission buses 104a and 104b, determine that the PCIe interface connected to the PCIe devices 102a and 102b is PCIe interface 108b.
[0072] Step S304: Based on the maximum link widths x8 and x4 supported by the PCIe devices 102a and 102b and the PCIe interface 108b, set the channel splitting information of the PCIe interface 108b to x8+x4+x4.
[0073] Step S306: The channel splitting information is stored in memory 109 for use by BIOS 107. Memory 109 is connected to BMC 106 and BIOS 107.
[0074] Step S308: After the processor is powered on, the BIOS 107 retrieves the channel splitting information from the memory 109 and sets the branch mode of the PCIe interface in the processor.
[0075] In the above embodiments of the present invention, each peripheral is plugged into a backplane, each backplane has a different ID, each backplane communicates with the BMC via I2C, the BMC can determine whether it is an X4 / X8 / X16 device based on the backplane ID, the BMC can determine which group of X16 interfaces the backplane is plugged into based on the I2C number, and finally each group of standard PCIe interfaces is set to the correct branch mode in the BIOS stage.
[0076] The correspondence between the number of PCIe interfaces and the number of PCIe devices is shown in Table 2:
[0077]
[0078]
[0079] Table 2
[0080] As shown in Table 2, in this embodiment, N=2, and the maximum link width supported by the N PCI devices is (x8, x4). From the table, the transmission bus numbers are (1a, 1b), indicating that the connected PCIe interface is PCIe108b. Therefore, the channel splitting information of the PCIe108b interface is (x8+x4+x4). Compared with the prior art, the technical solution provided by this invention is very flexible in use. It does not require releasing a new version of the BIOS to adapt to changes in PCIe Bifurcation due to changes in the external PCIe devices connected to the server CPU. In addition, the BMC outputs different PCIe Bifurcations according to changes in the external devices connected to the CPU, stores them in the CPLD's RAM, and provides them to the BIOS for use. This eliminates the need for the BIOS to retrieve the PCIe Bifurcation from the mapping table, reducing the possibility of configuration errors causing PCIe devices to become unusable or run at reduced speed.
[0081] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.
[0082] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.
[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An automatic branching system for the PCIe peripheral device interconnect expansion bus, characterized in that, include: The processor is provided with one or more PCIe interfaces, through which it is connected to one or more PCIe devices; One or more backplanes, each backplane being configured with a backplane identifier and used to identify the maximum link width supported by a PCIe device plugged into the backplane, each PCIe device being plugged into a corresponding backplane; The Baseboard Management Controller (BMC) is connected to the backplane to which the PCIe devices are plugged in via a transmission bus. Each transmission bus is assigned a number and connected to a corresponding backplane. There is a preset correspondence between the number of each transmission bus and the PCIe interface to which the PCIe device plugged into the corresponding backplane is connected. The BMC obtains the backplane identifier of the backplane to which the PCIe devices are plugged in and the number of the transmission bus used. Based on the obtained backplane identifier and the number of the transmission bus, it determines the channel splitting configuration (Bifurcation) information for each PCIe interface for use by the Basic Input / Output System (BIOS). For each backplane connected to the BMC and the transmission bus used, the BMC determines the maximum link width supported by the PCIe device plugged into the backplane based on the obtained backplane identifier, and determines the PCIe interface to which the PCIe device is connected based on the obtained transmission bus number and the preset correspondence between the transmission bus number and the PCIe interface. The bridging information for each PCIe interface is determined based on the maximum link width supported by each PCIe device connected to each PCIe interface.
2. The system according to claim 1, characterized in that, The system also includes: A memory for storing the bridging information of each PCIe interface configured by the BMC; The BIOS, connected to the processor, is used to read the Bifurcation information from the memory and set the branch mode of the PCIe interface in the processor according to the Bifurcation information.
3. The system according to claim 1, characterized in that, The processor is one of the following: a central processing unit (CPU), a data processing unit (DPU), or a graphics processing unit (GPU).
4. The system according to claim 1, characterized in that, The transmission bus is one of the following: serial bidirectional communication interface bus I2C, serial peripheral interface bus SPI, or universal asynchronous transceiver bus UART.
5. An automatic branching method for a PCIe peripheral interconnect expansion bus, characterized in that, The method is performed by the automatic branching system according to any one of claims 1 to 4, and the method includes: For each backplane connected to the BMC and the transmission bus used, obtain the backplane identifier of the backplane where each PCIe device is located and the number of the transmission bus used. The BIOS determines the BIOS bifurcation information for each PCIe interface based on the obtained backplane identifier and the transmission bus number.
6. The method according to claim 5, characterized in that, After determining the bridging information for each PCIe interface based on the obtained backplane identifier and the transmission bus number, the method further includes: Store the Bifurcation information in a memory; The BIOS reads the Bifurcation information from the memory and sets the branch mode of each PCIe interface in the processor according to the Bifurcation information.
7. The method according to claim 5, characterized in that, The bridging information for each PCIe interface is determined based on the obtained backplane identifier and the transmission bus number, including: The maximum link width supported by the PCIe device plugged into each backplane is determined based on the obtained backplane identifier. The PCIe interface to which the PCIe device is connected is determined based on the obtained transmission bus number and the preset correspondence between the transmission bus number and each PCIe interface. The bridging information for each PCIe interface is determined based on the maximum link width supported by each PCIe device connected to each PCIe interface.
8. The method according to claim 6, characterized in that, Before obtaining the number of the transmission bus used, the following steps are also included: Establish the correspondence between the PCIe interface and the number of the transmission bus.
9. The method according to claim 6, characterized in that, Before obtaining the backplane identifier of each PCIe device's backplane, the following steps are also included: Configure the correspondence between the maximum link width supported by the PCIe device and the backplane identifier.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method as described in any one of claims 5 to 9 when it is run.